JP2007235152A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory cell that can be rewritten without applying a high voltage between a source region and a drain region. <P>SOLUTION: A part of a floating gate 15a formed on a control gate region 9a via a silicon oxide film 11 is extended on a tunnel oxide film 13b on a control gate region 9b. A part of a floating gate 15b formed on the control gate region 9b via the silicon oxide film 11 is extended on a tunnel oxide film 13a on the control gate region 9a. When applying a high voltage to the control gate region 9a and a low voltage to the control gate region 9b, electrons are injected into the floating gate 15a from a part extended on the control gate region 9b via the tunnel oxide film 13b and electrons are drawn out from a part extended on the control gate region 9a via the tunnel oxide film 13a in the floating gate 15b. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a nonvolatile memory and a manufacturing method thereof.
In this specification, the first conductivity type is P-type or N-type, and the second conductivity type is N-type or P-type opposite to the first conductivity type.

  As a use of a nonvolatile memory cell called an EEPROM (Electrically Erasable Programmable Random Access Memory), the most common use is for a memory device. The most important condition in a memory device is the degree of integration. Therefore, a large number of memory cells are arranged in a matrix, and the decoding circuit and sense circuit, which are cell driving parts, are shared by the many memory cells, thereby reducing the area on the chip and increasing the degree of integration. Yes.

FIG. 7 shows a plan view of a conventional nonvolatile memory cell. Such nonvolatile memory cells are described in, for example, Patent Document 1 and Patent Document 2 .

  On the P-type semiconductor substrate 101, N-type diffusion layers 103, 105, 107 and a control gate 109 made of the N-type diffusion layer are formed. N-type diffusion layers 103 and 105 are formed with a gap, and N-type diffusion layers 105 and 107 are formed with a gap.

  On the P-type semiconductor substrate 101 including the region between the N-type diffusion layers 103 and 105, a polysilicon film partially overlaps with the N-type diffusion layers 103 and 105 through a gate oxide film (not shown). A select gate 111 is formed. N-type diffusion layers 103 and 105 and select gate 111 constitute select transistor 115. The N-type diffusion layer 103 is electrically connected to a common source line 117 common to a plurality of nonvolatile memory cells.

  A floating gate 113 made of a polysilicon film is formed continuously on the P-type semiconductor substrate 101 including the region between the N-type diffusion layers 105 and 107 and on the control gate 109 via a silicon oxide film (not shown). Has been. In the region near the N-type diffusion layers 105 and 107, the floating gate 113 is partially overlapped with the N-type diffusion layers 105 and 107 via the memory gate oxide film. N-type diffusion layers 105 and 107 and floating gate 113 constitute sense transistor 119. The N-type diffusion layer 107 is electrically connected to a common bit line 121 common to a plurality of nonvolatile memory cells.

  A tunnel oxide film 123 is formed on a part of the surface of the N-type diffusion layer 105. A part of the floating gate 113 is also formed on the tunnel oxide film 123. The tunnel oxide film 123 is formed thinner than the gate oxide film of the sense transistor 119, and writing and erasing of the memory are performed through the tunnel oxide film 123.

  When this nonvolatile memory is erased, that is, when electrons are injected into the floating gate 113, the N-type diffusion layer 103 is set to 0 V (volt), the N-type diffusion layer 107 is set to a predetermined potential Vpp, for example, 15 V, and the control gate 109 and the select gate 111 are applied by applying a predetermined potential Vpp, for example, 15V. As a result, the select transistor 115 is turned on, and electrons are injected from the N-type diffusion layer 105 into the floating gate 113 through the tunnel oxide film 123.

  When writing to the nonvolatile memory, that is, when electrons are extracted from the floating gate 113, the control gate 109 is set to 0 V, the N-type diffusion layer 107 is set to open, and a predetermined potential Vpp is applied to the N-type diffusion layer 103 and the select gate 111. Is applied. As a result, the select transistor 115 is turned on, and electrons injected into the floating gate 113 are extracted to the N-type diffusion layer 105 through the tunnel oxide film 123 by the tunnel effect.

  This nonvolatile memory cell has a select transistor 115 in the cell, a plurality of nonvolatile memory cells are connected to one common source line 117 and one common bit line 121, and only a specific select transistor 115 is turned on. Thus, a method of selecting one nonvolatile memory cell is adopted. As a result, the peripheral decoding circuit and the like need only be provided for each common bit line 121, so that the area efficiency is improved.

  However, since a high voltage is applied between the N-type diffusion layer 103 and the N-type diffusion layer 105 and between the N-type diffusion layer 105 and the N-type diffusion layer 107 at the time of erasing, the select transistor 115 and the sense transistor 119 are set to the high voltage. There is a problem that the on-current of the select transistor 115 and the sense transistor 119 is reduced because it is necessary to use a transistor.

  Further, the normal select transistor 115 is the same N channel type transistor as the sense transistor 119, but at the time of erasing, between the N type diffusion layer 103 and the N type diffusion layer 105 and between the N type diffusion layer 105 and the N type diffusion layer 107. When a high voltage is applied between them, the voltage applied to the tunnel oxide film 123 causes a voltage loss corresponding to the threshold voltage of the select transistor 115, resulting in a decrease in erasing efficiency.

By the way, as another use of the EEPROM memory cell, it may be used for a purpose of switching the setting or configuration of a circuit block in an integrated circuit. Specifically, an address switching circuit for repairing defective bits in a memory device or the like, a switching circuit for setting circuit conditions in an analog device, or the like. In the use of such a switching circuit, the nonvolatile memory cells are not arranged in a matrix, but one or two nonvolatile memory cells are separately arranged. A nonvolatile memory cell used as a switching circuit is described in Patent Document 3 , for example.

In the case of a non-volatile memory cell used as a switching circuit, it is not necessary to arrange cells at high density, so there is no need to provide a select transistor in the cell unlike the conventional non-volatile memory cell shown in FIG. In addition, when a conventional nonvolatile memory cell is used as it is in a switching circuit, it is necessary to apply a high voltage between the source region and the drain region when rewriting the nonvolatile memory cell. There were also disadvantages that made it complicated.
JP-A-6-85275 Japanese National Patent Publication No. 8-506669 JP-A-10-303719

  The present invention has been made in view of the above problems, and provides a semiconductor device including a nonvolatile memory cell that can be rewritten without applying a high voltage between a source region and a drain region. It is intended.

  A semiconductor device according to the present invention includes a second conductivity type control gate region, a source region and a drain region which are separately formed on a first conductivity type semiconductor substrate, and a channel between the source region and the drain region. Two sense transistors each having a floating gate formed by extending from the channel region to the control gate region through the gate oxide film and the semiconductor substrate and the control gate region through the insulating film. In other words, a part of the floating gate of both sense transistors extends on the control gate region of the other sense transistor and overlaps with the control gate region via an oxide film, and at least a part of the oxide film is Non-volatile memory cell comprising tunnel oxide film is provided Is shall.

  In the nonvolatile memory cell of the present invention, by applying a predetermined voltage between one control gate region and the other control gate region, electrons are injected into or extracted from one floating gate and to the other floating gate. The electrons can be extracted or injected simultaneously.

  For example, when a high voltage is applied to one control gate region and a low voltage is applied to the other control gate region, the floating gate on one control gate region is tunnel oxidized from the part extending on the other control gate region. Electrons are injected through the film to enter the erased state, and the floating gate on the other control gate region is drawn out from the portion extending on the one control gate region through the tunnel oxide film to the written state. Become.

In the nonvolatile memory cell of the present invention, rewriting is performed without applying a high voltage between the source region and the drain region by applying a predetermined voltage between one control gate region and the other control gate region. be able to.
Furthermore, since there is no need to provide a select transistor as in the case of a conventional nonvolatile memory cell, a predetermined voltage can be directly applied to both control gate regions, thereby eliminating a decrease in erasing efficiency due to the select transistor. Can do.

  Usually, when a high voltage is applied to a transistor, special measures such as making a source region and a drain region formed of a diffusion layer into a double diffusion structure for high breakdown voltage are necessary. In this case, the channel length of the transistor becomes long and a parasitic resistance is formed between the source region and the drain region, so that the capability of the transistor is lowered, and the cell current (transistor on-current) as a nonvolatile memory cell is lowered.

  Therefore, in the semiconductor device of the present invention, the sense transistor is preferably a low breakdown voltage transistor. According to the nonvolatile memory cell constituting the present invention, since it is not necessary to apply a high voltage to the source region and the drain region at the time of rewriting, the sense transistor is a low withstand voltage transistor having a source region and a drain region for low withstand voltage. Can be. Thereby, the cell current as a nonvolatile memory cell can be increased.

In the semiconductor device of the present invention, the source region and the drain region are provided for each sense transistor, and two sets of the source region and the drain region have the same arrangement direction of the drain region with respect to the source region. It is preferable. As a result, the two sense transistors can be made less susceptible to variations in the manufacturing process, and the pairing can be improved.

  In the semiconductor device of the present invention, it is preferable that a conductor formed on the floating gate via an insulating film and electrically connected to the control gate region is provided for each sense transistor. As a result, the coupling ratio between the control gate region containing the conductor and the floating gate can be increased, and the write and erase characteristics can be improved.

  As an example of a circuit to which the nonvolatile memory cell constituting the present invention is applied, a switching circuit comprising the nonvolatile memory cell of the present invention and an output circuit that outputs an output signal according to the storage state of the nonvolatile memory cell Can be mentioned. When the nonvolatile memory cell constituting the present invention is applied to a rewrite circuit, it is not necessary to apply a high voltage between the source region and the drain region when rewriting the nonvolatile memory cell, so that the configuration of the peripheral write circuit can be simplified. Can be.

As another example of a circuit to which the nonvolatile memory cell constituting the present invention is applied, a dividing resistor for dividing the input voltage and supplying the divided voltage, a reference voltage generating circuit for supplying the reference voltage, A voltage detection circuit including a comparison circuit for comparing the divided voltage from the divided resistor and the reference voltage from the reference voltage generation circuit can be given.
In the voltage detection circuit, the divided resistor includes a plurality of resistance value adjusting resistance elements connected in series, and transistors connected in parallel corresponding to the resistance value adjusting resistance elements. It is preferable that the switching circuit for switching on and off of the transistor is provided.
As a result, the resistance value of the dividing resistor can be adjusted by switching on and off of the transistor under the control of the switching circuit, and the resistance value of the dividing resistor can be reset. As a result, the output voltage setting of the voltage detection circuit can be changed.

As still another example of a circuit to which the nonvolatile memory cell constituting the present invention is applied, an output driver for controlling the output of the input voltage, a dividing resistor for dividing the output voltage and supplying a divided voltage, and a reference A reference voltage generating circuit for supplying a voltage, and a comparison circuit for comparing the divided voltage from the dividing resistor with the reference voltage from the reference voltage generating circuit and controlling the operation of the output driver according to the comparison result There may be mentioned a constant voltage generating circuit comprising
In the constant voltage generation circuit, the divided resistor includes a plurality of resistance value adjusting resistance elements connected in series, and transistors connected in parallel corresponding to the resistance value adjusting resistance elements. It is preferable that the switching circuit for switching on and off the transistor is provided.
As a result, the resistance value of the dividing resistor can be adjusted by switching on and off of the transistor under the control of the switching circuit, and the resistance value of the dividing resistor can be reset. As a result, the output voltage setting of the constant voltage generation circuit can be changed.

  The semiconductor device according to claim 1, wherein the second conductivity type control gate region, the source region and the drain region, and the source region and the drain region formed separately from each other on the first conductivity type semiconductor substrate are formed. The channel region has a gate oxide film, and the semiconductor substrate and the control gate region have two sense transistors each having a floating gate extending from the channel region to the control gate region through an insulating film. In addition, a part of the floating gate of both sense transistors extends on the control gate region of the other sense transistor and overlaps with the control gate region through an oxide film, and at least a part of this oxide film forms a tunnel oxide film So that it has a non-volatile memory cell It can be rewritten without applying a high voltage between the region and the drain region. Furthermore, since there is no need to provide a select transistor as in the case of a conventional nonvolatile memory cell, a predetermined voltage can be directly applied to both control gate regions, thereby eliminating a decrease in erasing efficiency due to the select transistor. Can do.

In the semiconductor device according to claim 2 , the source region and the drain region are provided for each sense transistor, and the arrangement direction of the drain region with respect to the source region is the same in the two sets of the source region and the drain region. As a result, the two sense transistors can be made less susceptible to variations in the manufacturing process, and the pairing can be improved.

According to a third aspect of the present invention, the present invention is configured as a nonvolatile memory cell in a switching circuit including a nonvolatile memory cell and an output circuit that outputs an output signal in accordance with a storage state of the nonvolatile memory cell. Since the nonvolatile memory cell is provided, it is not necessary to apply a high voltage between the source region and the drain region when rewriting the nonvolatile memory cell, so that the configuration of the peripheral write circuit can be simplified. it can.

In the semiconductor device according to claim 4 is the voltage detection circuit, dividing resistors, a plurality of resistance value adjusting resistor elements are connected in series, the transistors corresponds is connected in parallel with the resistance value adjusting resistor element Since each transistor has a switching circuit for switching the transistor on and off, the resistance value of the dividing resistor can be adjusted by switching the transistor on and off by controlling the switching circuit. In addition, the resistance value of the dividing resistor can be reset. As a result, the output voltage setting of the voltage detection circuit can be changed.

In the semiconductor device according to claim 5, in the constant voltage generating circuit, dividing resistors are connected to the plurality of resistance value adjusting resistor elements are connected in series, transistors in parallel in correspondence to the resistance value adjusting resistor element Since each transistor has a switching circuit for switching the transistor on and off, the resistance value of the dividing resistor is adjusted by switching the transistor on and off by controlling the switching circuit. In addition, the resistance value of the dividing resistor can be reset. As a result, the output voltage setting of the constant voltage generation circuit can be changed.

1A and 1B are diagrams showing a nonvolatile memory cell portion of an embodiment of a semiconductor device, in which FIG. 1A is a plan view, FIG. 1B is a cross-sectional view taken along the line A-A in FIG. ) Is a cross-sectional view at the BB position, and (D) is a cross-sectional view at the CC position in (A).
A field oxide film 3 (illustration is omitted in (A)) for element isolation is formed on the surface of the P-type semiconductor substrate 1 with a film thickness of, for example, 4500 to 7000 mm, here 5000 mm.

  In the region of the P-type semiconductor substrate 1 surrounded by the field oxide film 3, drain regions 5a and 5b made of an N-type diffusion layer, a common source region 7, and control gate regions 9a and 9b are formed. The drain region 5a and the common source region 7 are formed with an interval, the drain region 5b and the common source region 7 are formed with an interval, and the drain region 5a, the common source region 7 and the drain region 5b are arranged in a line.

  In the vicinity of the surface of the P-type semiconductor substrate 1 between the drain region 5a and the common source region 7, a channel region 1a having an adjusted impurity concentration is formed, and the surface of the P-type semiconductor substrate 1 between the drain region 5b and the common source region 7 is formed. A channel region 1b whose impurity concentration is adjusted is formed in the vicinity. The drain regions 5a and 5b and the common source region 7 are not designed for high breakdown voltage such as a double diffusion structure, and the channel length of the channel regions 1a and 1b is, for example, 1.0 μm (micrometer).

  The control gate region 9a is formed with a distance from the drain regions 5a and 5b and the common source region 7, and the control gate region 9b is opposite to the control gate region 9a with respect to the drain regions 5a, 5b and the common source region 7. In the region, the drain regions 5 a and 5 b and the common source region 7 are formed with an interval.

  The surface of the P-type semiconductor substrate 1 surrounded by the field oxide film 3 including the region where the drain regions 5a and 5b, the common source region 7 and the control gate regions 9a and 9b are formed is, for example, 80 to 110 mm, here 100 mm. A silicon oxide film 11 (not shown in (A)) is formed. A tunnel oxide film having a thickness smaller than that of the silicon oxide film 11, for example, 90 to 100 mm, here 90 mm, is formed in a part of the surface of the control gate regions 9a and 9b. A tunnel oxide film 13a is formed in the control gate region 9a, and a tunnel oxide film 13b is formed in the control gate region 9b.

  On the silicon oxide film 11 and the tunnel oxide films 13a and 13b, floating gates 15a and 15b made of a polysilicon film having a thickness of 2500 to 4500 mm, for example, 3500 mm are formed. The floating gate 15a is formed on the control gate region 9a. A part of the floating gate 15a is formed to extend on the tunnel oxide film 13b on the control gate region 9b via the channel region 1a between the drain region 5a and the common source region 7, and the portion is Work as a program gate. The floating gate 15b is formed on the control gate region 9b. A part of the floating gate 15b is formed to extend on the tunnel oxide film 13a on the control gate region 9a via the channel region 1b between the drain region 5b and the common source region 7, and the portion is Work as a program gate.

  The channel region 1a, the drain region 5a, the common source region 7, the silicon oxide film 11 on the channel region 1a and the floating gate 15a on the channel region 1a constitute an N-channel type sense transistor 17a. The channel region 1b, the drain region 5b, the common source region 7, the silicon oxide film 11 on the channel region 1b, and the floating gate 15b on the channel region 1b constitute an N-channel type sense transistor 17b.

  A contact 19a is formed on the drain region 5a, a contact 19b is formed on the drain region 5b, a contact 21 is formed on the common source region 7, and a contact 23a is formed on the control gate region 9a. A contact 23b is formed on the control gate region 9b.

  FIG. 2 is a circuit diagram showing an embodiment including a switching circuit including the nonvolatile memory cell shown in FIG. 1 and a write control circuit for controlling the operation of the switching circuit. This embodiment will be described with reference to FIGS.

  In the switching circuit 24, the control gate regions 9a and 9b of the nonvolatile memory element 25 are electrically connected to the write control circuit 27 through contacts 23a and 23b. The write control circuit 27 is connected to a high voltage power supply VPP to be applied to the control gate region 9a or 9b at the time of writing and erasing of the floating gates 15a and 15b of the nonvolatile memory cell 25, and a ground potential GND.

  The common source region 7 of the sense transistors 17a and 17b is connected to the ground potential GND through a contact 21. The drain region 5 a of the sense transistor 17 a is connected to the drain of the P-channel type read transistor 31 through the connection point 29. The drain region 5 b of the sense transistor 17 b is connected to the drain of the P-channel type read transistor 35 through the connection point 33.

The sources of the read transistors 31 and 35 are connected to the read power supply VCC. The gate of the reading transistor 31 is connected to the connection point 33. The gate of the reading transistor 35 is connected to the connection point 29.
The connection point 33 is also connected to the inverter 37. The output (OUT) of the inverter 37 is the output of the switching circuit.
The read transistors 31 and 35 and the inverter 37 constitute an output circuit that outputs an output signal in accordance with the storage state of the nonvolatile memory cell 25.
In the switching circuit 25, when the output of the inverter 37 is a logical value 1, it is turned on, and when it is a logical value 0, it is turned off.

  When the switching circuit 24 is turned on (the output logical value is 1), the write control circuit 27 applies, for example, a high voltage of 11V to the control gate region 9a and 0V to the control gate region 9b.

  In the tunnel oxide film 13a on the control gate region 9a, electrons are extracted from the floating gate 15b on the control gate region 9a to the control gate region 9a by the tunnel phenomenon, and the entire floating gate 15b is positively charged. As a result, the sense transistor 17b becomes a depletion transistor having a negative threshold voltage (written state).

  On the other hand, in the tunnel oxide film 13b on the control gate region 9b, electrons are injected from the control gate region 9b to the floating gate 15a on the control gate region 9b by the tunnel phenomenon, and the entire floating gate 15a is negatively charged. As a result, the sense transistor 17a becomes an enhancement transistor having a high threshold voltage (erase state).

  With the sense transistor 17a in the erased state and the sense transistor 17b in the written state, the write control circuit 27 applies a constant voltage of, for example, 2V to the control gate regions 9a and 9b. At this time, the sense transistor 17a is turned off because it has a high threshold voltage, and the sense transistor 17b is turned on because the threshold voltage has a negative value.

  The voltage at the connection point 33 becomes a potential level of 0 V, that is, a logical value 0 by the ON state of the sense transistor 17b. As a result, the reading transistor 31 is turned on, the voltage at the connection point 29 becomes VCC, and the reading transistor 35 is turned off. The logical value 0 at the connection point 33 is inverted by the inverter 37 to be a logical value 1 and output.

  When the switching circuit 24 is turned off (the logic value of the output is 0), contrary to the on state, the write control circuit 27 causes the control gate region 9a to have a high voltage of 0V and the control gate region 9b of 11V, for example. Apply voltage. As a result, contrary to the ON state, electrons are injected from the control gate region 9a to the floating gate 15b through the tunnel oxide film 13a, the floating gate 15b is negatively charged, and the sense transistor 17b becomes an enhancement transistor. (Erased state), electrons are extracted from the floating gate 15a to the control gate region 9b through the tunnel oxide film 13b, the floating gate 15a is positively charged, and the sense transistor 17a becomes a depletion transistor (written state). ).

  With the sense transistor 17a in the write state and the sense transistor 17b in the erase state, the write control circuit 27 applies a constant voltage of, for example, 2V to the control gate regions 9a and 9b. At this time, the sense transistor 17a is turned on because the threshold voltage has a negative value, and the sense transistor 17b is turned off because it has a high threshold voltage.

  The voltage at the connection point 29 becomes 0V due to the ON state of the sense transistor 17a. As a result, the reading transistor 35 is turned on, the voltage at the node 33 becomes the potential level of VCC, that is, the logical value 1, and the reading transistor 31 is turned off. The logical value 1 at the connection point 33 is inverted by the inverter 37 to be a logical value 0 and output.

Thus, the nonvolatile memory cell 24 can be rewritten without applying a high voltage between the source region and the drain region.
Further, since it is not necessary to provide a select transistor as in the case of a conventional nonvolatile memory cell, a predetermined voltage can be directly applied to the control gate regions 9a and 9b, and the erasing efficiency is reduced due to the select transistor. Can be eliminated.

  Further, in this embodiment, since it is not necessary to apply a high voltage to the drain regions 5a and 5b and the common source region 7, the drain regions 5a and 5b and the common source region 7 are for high breakdown voltage such as a double diffusion structure. However, the channel length of the channel regions 1a and 1b is, for example, 1.0 μm, and the sense transistors 17a and 17b are composed of low breakdown voltage transistors. As a result, the ON current (cell current) of the sense transistors 17a and 17b can be increased.

FIG. 3 is a plan view showing a nonvolatile memory cell portion of another embodiment of the semiconductor device. Parts having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
The difference from the nonvolatile memory cell shown in FIG. 1 is that the sense transistor 17a is provided with a drain region 5a and a source region 7a, and the sense transistor 17b is provided with a drain region 5b and a source region 7b. It is. A set of the drain region 5a and the source region 7a and a set of the drain region 5b and the source region 7b are formed in the same direction on the P-type semiconductor substrate.

  The drain region 5a is electrically connected to the wiring layer 39a via a contact 19a, and the drain region 5b is electrically connected to the wiring layer 39b via a contact 19b. The source region 7a is electrically connected to the common wiring layer 41 via the contact 21a, and the source region 7b is electrically connected to the common wiring layer 41 via the contact 21b.

  In this embodiment, the source region and the drain region are provided for each of the sense transistors 17a and 17b, and the set of the drain region 5a and the source region 7a and the set of the drain region 5b and the source region 7b are the same on the P-type semiconductor substrate. Since it is formed in the direction, the sense transistors 17a and 17b can be made less susceptible to variations in the manufacturing process, and the pairing can be improved.

  4A and 4B are diagrams showing a nonvolatile memory cell portion of still another embodiment of the semiconductor device, wherein FIG. 4A is a plan view, FIG. 4B is a cross-sectional view taken along the line A-A in FIG. (A) is a cross-sectional view at the BB position, (D) is a cross-sectional view at the CC position of (A). Parts having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  A field oxide film 3 is formed on the surface of the P-type semiconductor substrate 1, and channel regions 1 a and 1 b, drain regions 5 a and 5 b, a common source region 7 are formed in the region of the P-type semiconductor substrate 1 surrounded by the field oxide film 3. Control gate regions 9a and 9b are formed. A silicon oxide film 11 and tunnel oxide films 13a and 13b are formed on the surface of the P-type semiconductor substrate 1 surrounded by the field oxide film 3. Floating gates 15a and 15b are formed on the silicon oxide film 11 and the tunnel oxide films 13a and 13b, and sense transistors 17a and 17b are formed.

  An insulating film 43 is formed on the field oxide film 3, the silicon oxide film 11, and the floating gates 15a and 15b. The insulating film 43 is, for example, a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film in order from the lower layer side. The film thickness of the lower silicon oxide film is 100 mm, the film thickness of the silicon nitride film is 100 mm, and the upper silicon film The thickness of the oxide film is 30 mm.

  On the insulating film 43, for example, conductors 45a and 45b made of a polysilicon film having a film thickness of 1500 to 4000 mm, here 3500 mm are formed. The conductor 45a is formed to cover the floating gate 15a on the control gate region 9a, and is electrically connected to the control gate region 9a through a contact 47a. The conductor 45b is formed to cover the floating gate 15b on the control gate region 9b, and is electrically connected to the control gate region 9b through a contact 47b. Here, a polysilicon film is used as the conductor, but the present invention is not limited to this, and a conductor made of a metal material may be formed.

  In the silicon oxide film 11 and the insulating film 43, a contact 19a is formed on the drain region 5a, a contact 19b is formed on the drain region 5b, a contact 21 is formed on the common source region 7, and on the control gate region 9a. A contact 23a is formed on the control gate region 9b, and a contact 23b is formed on the control gate region 9b.

  In this embodiment, there are provided conductors 45a and 45b formed on the floating gates 15a and 15b through an insulating film 43 and electrically connected to the control gate regions 9a and 9b through contacts 47a and 47b. Therefore, the coupling ratio between the control gate region 9a including the conductor 45a and the floating gate 15a, and the control gate region 9b including the conductor 45b and the floating gate 15b can be increased, thereby improving the write and erase characteristics. Can be made.

FIG. 5 is a circuit diagram showing an embodiment including the switching circuit and the constant voltage generation circuit shown in FIG.
A constant voltage generation circuit 49 is provided to stably supply power from the DC power supply 51. The constant voltage generation circuit 49 includes an input terminal (Vbat) 53 to which the DC power source 51 is connected, a reference voltage generation circuit (Vref) 55, an operational amplifier 57, and a P-channel MOS transistor (hereinafter abbreviated as PMOS) constituting an output driver. 59), dividing resistors 61 and 63, and an output terminal (Vout) 65.

The dividing resistor 63 is configured by R0. The dividing resistor 61 includes a plurality of resistance value adjusting resistor elements R1, R2,... Ri-1, Ri connected in series. Transistors SW1, SW2,... SWi-1, SWi are connected in parallel corresponding to resistance elements R1, R2,.
Corresponding to the transistors SW1, SW2,... SWi-1, SWi, a plurality of switching circuits 24 for switching the transistors SW1, SW2,. The outputs of the plurality of switching circuits 24 are connected to the gates of the corresponding transistors SW1, SW2,... SWi-1, SWi.

  In the operational amplifier 57 of the constant voltage generating circuit 49, the output terminal is connected to the gate electrode of the PMOS 59, the reference voltage Vref is applied from the reference voltage generating circuit 55 to the inverting input terminal, and the output voltage Vout is applied to the non-inverting input terminal. And the voltage divided by resistors 63 and 63 are applied, and the divided voltages of the resistors 61 and 63 are controlled to be equal to the reference voltage Vref.

FIG. 6 is a circuit diagram showing an embodiment including the switching circuit and the voltage detection circuit shown in FIG.
In the voltage detection circuit 73, the dividing resistors 61 and 63 and the oscillation preventing resistance element RH are connected in series between the input terminal 67 to which the voltage of the terminal to be measured (input voltage Vsens) is input and the ground potential. . The configuration of the dividing resistors 61 and 63 is the same as that in FIG. The transistors SW1, SW2,... SWi-1, SWi are connected in parallel corresponding to the resistance elements R1, R2,... Ri-1, Ri, and correspond to the transistors SW1, SW2,. Thus, a plurality of switching circuits 24 are provided. An N-channel oscillation prevention transistor SWH is connected in parallel with the oscillation prevention resistance element RH. The gate of the oscillation preventing transistor SWH is connected to the output of the operational amplifier 57.

  The inverting input terminal of the operational amplifier 57 is connected to the connection point between the dividing resistors 61 and 63. The reference voltage generating circuit 55 is connected to the non-inverting input terminal of the operational amplifier 57, and the reference voltage Vref is applied. The output of the operational amplifier 57 is output to the outside through an inverter 69 and an output terminal (DTout) 71.

In the voltage detection circuit 73, in the high voltage detection state, the oscillation preventing resistance element RH is in the OFF state, the voltage of the terminal to be measured input from the input terminal 67 is high, and the division resistor 61, the division resistor 63, and the oscillation prevention resistor. When the voltage divided by the resistance element RH is higher than the reference voltage Vref, the output of the operational amplifier 57 maintains the logical value 0, and the output is inverted by the inverter 69 to the logical value 1 and output from the output terminal 71. The At this time, the divided voltage input to the inverting input terminal of the operational amplifier 57 is:
{(R0) + (RH)} / {(R1) + (R2) ... + (Ri-1) + (Ri) + (R0) + (RH)} × (Vsens)
It is.

  When the voltage of the terminal to be measured drops and the voltage divided by the dividing resistor 61, the dividing resistor 63, and the oscillation preventing resistance element RH63 becomes equal to or lower than the reference voltage Vref, the output of the operational amplifier 57 becomes the logical value 1, and the output Is inverted by an inverter 69 to have a logical value of 0 and output from an output terminal 71.

  When the output of the operational amplifier 57 becomes a logical value 1, the oscillation preventing transistor SWH is turned on, the dividing resistor 63 is connected to the ground potential via the oscillation preventing transistor SWH, and the voltage between the dividing resistors 61 and 63 Decreases. As a result, the output of the operational amplifier 57 maintains the logical value 1, and the voltage detection circuit 73 enters the low voltage detection state. As described above, the oscillation preventing resistance element RH and the oscillation preventing transistor SWH prevent the output of the voltage detection circuit 73 from oscillating when the input voltage Vsens decreases.

The divided voltage input to the inverting input terminal of the operational amplifier 57 in the low voltage detection state of the voltage detection circuit 73 is:
(R0) / {(R1) + (R2) ... + (Ri-1) + (Ri) + (R0)} × (Vsens)
It is. The release voltage for setting the voltage detection circuit 73 to the high voltage detection state is the input voltage Vsens at which the divided voltage input to the inverting input terminal of the operational amplifier 57 in the low voltage detection state is larger than the reference voltage Vref.

  In the embodiment shown in FIGS. 5 and 6, the switching circuit 24 controls the transistors SW1, SW2,... SWi-1, SWi to be turned on and off to adjust the resistance value of the dividing resistor 61. it can. Thereby, the set voltage can be adjusted for the output voltage of the constant voltage generation circuit 53 and the output voltage of the voltage detection circuit 73.

  In the conventional constant voltage generation circuit and voltage detection circuit, instead of the transistors SW1, SW2,... SWi-1, SWi and the switching circuit 24, the resistance value adjusting resistance elements R1, R2,. A fuse made of silicon or a metal material is connected in parallel, and the resistance value of the dividing resistor is adjusted by cutting the fuse.

  In the embodiment shown in FIGS. 5 and 6, the switches (transistors SW1, SW2,... SWi-1, SWi) once turned off, which was difficult with the fuse, are turned on again by the control of the switching circuit 24. Therefore, the set voltage can be freely changed for the output voltage of the constant voltage generation circuit 53 and the output voltage of the voltage detection circuit 73.

  Furthermore, since the switching circuit 24 can be switched between the on state and the off state by writing to the nonvolatile memory cell, the output voltage of the constant voltage generation circuit 53 and the voltage detection circuit 73 can be changed even after the semiconductor device is accommodated in the package. The set voltage can be adjusted and changed for the output voltage.

  As mentioned above, although the Example of this invention was described, this invention is not limited to these, A various change is possible within the range of this invention described in the claim.

It is a figure which shows the non-volatile memory cell part of the Example of a semiconductor device, (A) is a top view, (B) is sectional drawing in the AA position of (A), (C) is B of (A). Sectional view at position -B, (D) is a sectional view at position CC in (A). FIG. 2 is a circuit diagram illustrating an embodiment including a switching circuit including the nonvolatile memory cell illustrated in FIG. 1 and a write control circuit for controlling the operation of the switching circuit. It is a top view which shows the non-volatile memory cell part of the other Example of a semiconductor device. It is a figure which shows the non-volatile memory cell part of other Example of a semiconductor device, (A) is a top view, (B) is sectional drawing in the AA position of (A), (C) is (A) ) Is a cross-sectional view at the BB position, and (D) is a cross-sectional view at the CC position in (A). FIG. 3 is a circuit diagram showing an embodiment including the switching circuit and the constant voltage generation circuit shown in FIG. 2. It is a circuit diagram which shows one Example provided with the switching circuit and voltage detection circuit which were shown in FIG. It is a top view which shows the non-volatile memory cell of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 P-type semiconductor substrate 3 Field oxide film 5a, 5b Drain region 7 Common source region 9a, 9b Control gate region 11 Silicon oxide film 13a, 13b Tunnel oxide film 15a, 15b Floating gate 17a, 17b Sense transistor 19a, 19b, 21 Contact

Claims (5)

  A control gate region, a source region and a drain region of a second conductivity type formed separately from each other on a semiconductor substrate of the first conductivity type, and a channel region between the source region and the drain region through a gate oxide film. The semiconductor substrate and the control gate region have two sense transistors each having a floating gate formed by extending from the channel region to the control gate region through an insulating film, Part of the floating gate extends on the control gate region of the other sense transistor and overlaps with the control gate region through an oxide film, and at least a part of the oxide film is a non-volatile that forms a tunnel oxide film A semiconductor device comprising a memory cell. The source region and the drain region is provided for each of the sense transistors, two pairs of the source region and the drain region according to claim 1, arrangement direction of the drain region with respect to the source region have the same Semiconductor device. The semiconductor device according to claim 1 , further comprising a switching circuit including an output circuit that outputs an output signal according to a storage state of the nonvolatile memory cell. A dividing resistor for dividing an input voltage to supply a divided voltage, a reference voltage generating circuit for supplying a reference voltage, a divided voltage from the dividing resistor, and a reference voltage from the reference voltage generating circuit are compared. In a semiconductor device comprising a voltage detection circuit comprising a comparison circuit for
In the divided resistor, a plurality of resistance value adjusting resistance elements are connected in series, and a transistor is connected in parallel corresponding to the resistance value adjusting resistance element, and the transistor is turned on and off for each transistor. A semiconductor device comprising the switching circuit according to claim 3 for switching. An output driver for controlling the output of the input voltage; a dividing resistor for dividing the output voltage to supply a divided voltage; a reference voltage generating circuit for supplying a reference voltage; a divided voltage from the dividing resistor; In a semiconductor device including a constant voltage generation circuit including a comparison circuit for comparing a reference voltage from a reference voltage generation circuit and controlling an operation of the output driver according to a comparison result.
In the divided resistor, a plurality of resistance value adjusting resistance elements are connected in series, and a transistor is connected in parallel corresponding to the resistance value adjusting resistance element, and the transistor is turned on and off for each transistor. A semiconductor device comprising the switching circuit according to claim 3 for switching.

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