JP2021082372A - Non-volatile storage device and program method of non-volatile storage device - Google Patents

Abstract

To reduce a circuit area of a non-volatile storage device.SOLUTION: A non-volatile storage device 10 comprises memory transistors 11, 12. The memory transistor 11 is turned on based on a first voltage supplied to a gate, and outputs an output voltage which is based on a power source voltage VSS supplied to one of the source and the drain from the other source and the drains. The memory transistor 12 is a conductive type same as that of the memory transistor 11, and one of the source and drain is connected to the other of the source and the drain of the memory transistor 11. The memory transistor 12 is programmed to be turned off when a power source voltage VDD is supplied to the other of the source and the drain and the first voltage is supplied to the gate.SELECTED DRAWING: Figure 1

Description

The present invention relates to a non-volatile storage device and a method for programming a non-volatile storage device.

As one of the non-volatile storage devices, there is a non-volatile storage device using an electric fuse (sometimes called a fuse ROM (Read Only Memory) or the like). A non-volatile storage device using an electric fuse is a type of OTP (One Time Programmable) memory that can be written only once. In the non-volatile storage device using an electric fuse, a sense circuit for detecting whether or not the electric fuse is blown and a holding circuit for holding the storage content (0 or 1) corresponding to the detection result are used.

A memory transistor that stores information by accumulating carriers (holes (holes) and electrons) in a side wall insulating film provided in contact with the side wall of the gate electrode has been proposed.

Japanese Unexamined Patent Publication No. 2004-335027

The non-volatile storage device using an electric fuse includes a sense circuit and a holding circuit as described above, and has a problem that the circuit area becomes large.

In one embodiment, the non-volatile storage device comprises a first memory transistor and a second memory transistor. The first memory transistor is turned on based on the first voltage supplied to the first gate. Then, the first memory transistor applies an output voltage based on one of the first power supply voltage supplied to one of the first source and the first drain and the second power supply voltage smaller than the first power supply voltage. , Output from the other of the first source and the first drain. The second memory transistor is of the same conductive type as the first memory transistor, and one of the second source and the second drain is connected to the other of the first source and the first drain. Then, in the second memory transistor, the other of the first power supply voltage and the second power supply voltage is supplied to the other of the second source and the second drain, and the first voltage is supplied to the second gate. It is programmed to turn off when

Also, in one embodiment, a method of programming a non-volatile storage device is provided. The non-volatile storage device is of the same conductive type as the first memory transistor and the first memory transistor, and has a second source and a second drain on one of the first source and the first drain of the first memory transistor. It includes a second memory transistor to which one of the drains is connected. Then, in the method of programming the non-volatile storage device, when the control circuit programs the first value in the non-volatile storage device, the other of the first source and the first drain, and the first of the first memory transistors. A first voltage is supplied to the gate of. Then, the control circuit supplies one of the first source and the first drain with a second voltage smaller than the first voltage to perform the program. Also, when the control circuit programs the non-volatile storage device with a second value, it supplies a first voltage to one of the second source and the second drain, and to the second gate of the second memory transistor. To do. Then, the control circuit supplies a second voltage to the other of the first source and the first drain to perform the program.

The circuit area of the non-volatile storage device can be reduced.

It is a figure which shows an example of the non-volatile storage device of 1st Embodiment. It is a figure which shows an example of the non-volatile storage device of "1" data read state. It is a figure which shows an example of the non-volatile storage device of 2nd Embodiment. It is sectional drawing which shows an example of a memory transistor. It is a figure which shows the relationship of an example of a drain current of a memory transistor, and a gate voltage. It is a figure which shows an example of the voltage supplied at the time of programming of a memory transistor (the 1). It is a figure which shows an example of the voltage supplied at the time of programming of a memory transistor (the 2). It is a figure which shows an example of a control circuit. It is a figure which shows an example of a switch circuit. It is a figure which shows another example of the voltage supplied at the time of programming a memory transistor. It is a figure which shows another example of a control circuit. It is a flowchart which shows the flow of an example of the programming method of a non-volatile storage device. It is a figure which shows an example of a fuse ROM.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First Embodiment)
FIG. 1 is a diagram showing an example of a non-volatile storage device according to the first embodiment.

The non-volatile storage device 10 has two memory transistors 11 and 12 of the same conductive type (n-channel type or p-channel type). Hereinafter, the memory transistors 11 and 12 will be described as being n-channel type memory transistors in which the side wall insulating films are the storage areas 11a and 12a.

Further, in the example of FIG. 1, the memory transistor 12 is in a state in which a drain current does not flow when a read control voltage (hereinafter referred to as a read control voltage) supplied at the time of reading is applied to the gate, that is, in an off state. It is programmed to be (blocked). In order to program the memory transistor 12 so as to be in the off state, the storage area 12a may be in a state in which electrons as carriers are injected (programmed state). By injecting carriers into the storage area 12a, the threshold voltage (threshold value for turning on) of the memory transistor 12 rises. Therefore, by making the read control voltage smaller than the threshold voltage of the memory transistor 12 and larger than the threshold voltage of the memory transistor 11, the memory transistor 12 is turned on even if the memory transistor 11 is turned on by the read control voltage. do not. For example, the read control voltage is 1.0 to 1.5 V (but not limited to this value).

The memory transistors 11 and 12 are connected in series. That is, one of the source and drain of the memory transistor 11 is connected to one of the source and drain of the memory transistor 12. In FIG. 1, the node 13 is shown as a connection point for the memory transistors 11 and 12.

When reading data from the non-volatile storage device 10, the memory transistor 11 is turned on based on the read control voltage supplied to the gate. Then, the memory transistor 11 outputs an output voltage based on the power supply voltage VSS supplied from the source from the drain.

When the memory transistor 11 is turned on, the potential of the node 13, which is the drain potential of the memory transistor 11, becomes substantially the power supply voltage VSS. Therefore, in the example of FIG. 1, the output voltage output from the drain of the memory transistor 11 is assumed to be the power supply voltage VSS. The power supply voltage VSS is a reference power supply voltage, for example, 0V (but not limited to this value). Hereinafter, the state in which the output voltage, which is the power supply voltage VSS, is output is referred to as a “0” data read state.

On the other hand, in the memory transistor 12, the read control voltage is supplied to the gate and the power supply voltage VDD is supplied to the drain, but the memory transistor 12 is in the off state for the reason described above.
The power supply voltage VDD, the power supply voltage VSS, and the lead control voltage are supplied from, for example, a control circuit (not shown). An example of the control circuit will be described later.

When the memory transistor 11 is programmed in the off state instead of the memory transistor 12, an output voltage that is approximately the power supply voltage VDD is obtained when reading data from the non-volatile storage device 10 (hereinafter, the power supply voltage VDD). It will be explained as being). Hereinafter, the state in which the output voltage, which is the power supply voltage VDD, is output is referred to as the “1” data read state, as opposed to the “0” data read state, which is the state in which the output voltage which is the power supply voltage VSS is output.

FIG. 2 is a diagram showing an example of a non-volatile storage device in the “1” data read state.
In FIG. 2, the memory transistor 11 is programmed so that when the read control voltage is applied to the gate, the drain current does not flow, that is, it is in the off state (cutoff state). In order to program the memory transistor 11 so as to be in the off state, the storage area 11a may be in a state in which electrons as carriers are injected (programmed state). By injecting carriers into the storage area 11a, the threshold voltage of the memory transistor 11 rises. Therefore, by making the read control voltage smaller than the threshold voltage of the memory transistor 11 and larger than the threshold voltage of the memory transistor 12, the memory transistor 11 is turned on even if the memory transistor 12 is turned on by the read control voltage. do not.

If the threshold voltage of the memory transistors 11 and 12 in the programmed state is set to the same level and the threshold voltage of the memory transistors 11 and 12 in the non-programmed state is set to the same level, the read control voltage becomes “0” and “1”. It can be the same in both data read states.

When reading data from the non-volatile storage device 10, the power supply voltage VDD, the power supply voltage VSS, and the read control voltage are supplied as described above. At this time, the memory transistor 12 is turned on based on the read control voltage supplied to the gate. Then, the memory transistor 12 outputs an output voltage based on the power supply voltage VDD supplied from the drain from the source. In the memory transistor 11, the read control voltage is supplied to the gate and the power supply voltage VSS is supplied to the source, but the memory transistor 11 is in the off state for the reason described above.

When the memory transistor 12 is turned on, the potential of the node 13, which is the source potential of the memory transistor 12, becomes substantially the power supply voltage VDD. Therefore, in the example of FIG. 2, the output voltage output from the source of the memory transistor 12 is assumed to be the power supply voltage VDD. That is, the non-volatile storage device 10 is in the “1” data read state. The power supply voltage VDD is a voltage larger than the power supply voltage VSS, for example, 0.5 V (but is not limited to this value).

As described above, in the non-volatile storage device 10 of the first embodiment, one of the two memory transistors 11 and 12 of the same conductive type connected in series is programmed in the off state. Therefore, at the time of reading, the read control voltage is supplied to the gates of the memory transistors 11 and 12, so that one is turned on and the other is turned off. Then, the output voltage based on the power supply voltage (VDD or VSS) supplied to one end (one of the source or drain) of the memory transistor to be turned on is read data from the other end of the memory transistor (the other of the source or drain). It is output. Therefore, the sense circuit and the holding circuit included in the non-volatile storage device using the electric fuse are not required, and the circuit area of the non-volatile storage device 10 can be reduced. Moreover, since the sense circuit and the holding circuit are not required, the power consumption can be reduced.

Although the memory transistors 11 and 12 have been described above as being of the n-channel type, they may be of the p-channel type. In that case, holes are used as carriers to be injected into the storage areas 11a, 12a.

Further, the memory transistors 11 and 12 may be flash memories. In that case, as the storage areas 11a and 12a, a floating gate of the flash memory is used instead of the side wall insulating film.

(Second Embodiment)
FIG. 3 is a diagram showing an example of the non-volatile storage device of the second embodiment. In FIG. 3, the same elements as those included in the non-volatile storage device 10 of the first embodiment shown in FIGS. 1 and 2 are designated by the same reference numerals.

The non-volatile storage device 20 of the second embodiment includes a control circuit 21, a program control voltage generation circuit 22, and a read control voltage generation circuit 23 in addition to the memory transistors 11 and 12.

The control circuit 21 supplies the memory transistors 11 and 12 with a voltage for programming or reading based on a mode instruction signal supplied from the outside (for example, a control device such as a processor). At the time of reading, the control circuit 21 propagates the output voltage (read data) output from the source of the memory transistor 11 (or the drain of the memory transistor 12) to the terminal 24.

The program control voltage generation circuit 22 generates a program control voltage used at the time of programming. The read control voltage generation circuit 23 generates a read control voltage used at the time of reading. Examples of the program control voltage and the lead control voltage will be described later.

Hereinafter, examples of the memory transistors 11 and 12 used in the non-volatile storage device 20 of the second embodiment will be described.
(Examples of memory transistors 11 and 12)
FIG. 4 is a cross-sectional view showing an example of a memory transistor. In FIG. 4, a cross section of a main part of an example of the memory transistor 11 is schematically shown.

The memory transistor 11 is formed on a p-type or n-type semiconductor substrate 30. As the semiconductor substrate 30, various semiconductor substrates such as a silicon substrate are used. The region (element region) in which the memory transistor 11 is formed is defined by the element separation region 31 formed on the semiconductor substrate 30 by using the STI (Shallow Trench Isolation) method or the like.

As shown in FIG. 4, the memory transistor 11 includes a gate insulating film 32 provided above the semiconductor substrate 30, a gate electrode 33 provided above the gate insulating film 32, a side wall of the gate electrode 33, and the semiconductor substrate 30. It has a side wall insulating film 34 provided above. The memory transistor 11 is further provided in the semiconductor substrate 30 on both sides of the gate electrode 33 (both sides in the gate length direction), and has an impurity region 35a and an impurity region 35b that function as a source region or a drain region, respectively.

Further, the memory transistor 11 may have an LDD (Lightly Doped Drain) region 36a and an LDD region 36b inside the impurity region 35a and the impurity region 35b in the semiconductor substrate 30 below the side wall insulating film 34.

The memory transistor 11 has a channel region 37 provided in a region between the impurity region 35a and the impurity region 35b (or between the LDD region 36a and the LDD region 36b) below the gate electrode 33, and an impurity provided below the channel region 37. It further has a region 38.

Here, various insulating materials such as silicon oxide can be used as the gate insulating film 32. The film thickness of the gate insulating film 32 is set based on, for example, the threshold voltage and the program control voltage set for the memory transistor 11.

As the gate electrode 33, various conductor materials such as polysilicon can be used.
The side wall insulating film 34 includes a structure in which an oxide film 34a such as silicon oxide and a nitride film 34b such as silicon nitride are laminated. For example, an oxide film 34a is provided on the side wall of the gate electrode 33 and the semiconductor substrate 30 in an L-shaped cross section, and the nitride film 34b is provided on the oxide film 34a. The side wall insulating film 34 may have a three-layer structure in which an oxide film and a nitride film having an L-shaped cross section are further provided, or a laminated structure of four or more layers of insulating films. In addition, the side wall insulating film 34 can have a single-layer structure of an oxide film or a nitride film.

The impurity region 35a and the impurity region 35b contain n-type or p-type conductive impurities at a predetermined concentration. When the memory transistor 11 is an n-channel type, the impurity region 35a and the impurity region 35b contain n-type conductive impurities. When the memory transistor 11 is of the p-channel type, the impurity region 35a and the impurity region 35b contain p-type conductive impurities.

The LDD region 36a and the LDD region 36b contain the same conductive type impurities as the impurities contained in the impurity region 35a and the impurity region 35b at a lower concentration than the impurity region 35a and the impurity region 35b.

The channel region 37 is a non-doped region in which impurities are not intentionally added, or a region in which impurities contained are extremely low in concentration. The impurity concentration in the channel region 37 is, for example, 1 × 10 ¹⁷ cm ^-3 or less.

The impurity region 38 is provided below the channel region 37 and contains a higher concentration of impurities than the channel region 37. The impurity region 38 is also referred to as a screen layer. The impurity region 38 contains conductive impurities different from the impurities contained in the impurity region 35a and the impurity region 35b that function as the source region or the drain region at a predetermined concentration. The threshold voltage of the memory transistor 11 is controlled by the impurity concentration in the impurity region 38.

Further, the impurity region 38 suppresses punch-through between the impurity region 35a and the impurity region 35b, which function as a source region or a drain region. The impurity region 38 is provided at a position embedded inside the semiconductor substrate 30 by the thickness of the channel region 37 from the interface between the semiconductor substrate 30 and the gate insulating film 32, and the threshold voltage is adjusted by the impurity concentration. For example, it has a relatively high impurity concentration of about ^{1 × 10 19} cm ^-3.

The memory transistor 11 stores information by accumulating charges (electrons or holes) in the side wall insulating film 34. That is, the side wall insulating film 34 functions as the storage area 11a in FIG.

When programming the memory transistor 11, the control circuit 21 as shown in FIG. 3 generates hot carriers by setting each node of the gate electrode 33, the impurity region 35a and the impurity region 35b, and the semiconductor substrate 30 to a predetermined potential. The hot carriers are injected into the side wall insulating film 34 and accumulated.

In the memory transistor 11, the threshold voltage is controlled by the impurity concentration of the impurity region 38 embedded inside the semiconductor substrate 30, and the channel region 37 above the impurity concentration is set to have a low impurity concentration. In the memory transistor 11, since the impurity concentration in the channel region 37 is low and the impurity concentration in the impurity region 38 below it is high, the generation of hot carriers during programming is increased. Since the impurity region 38 is located at a position separated from the interface between the semiconductor substrate 30 and the gate insulating film 32, the threshold voltage of the memory transistor 11 does not become significantly high even if the impurity concentration is increased.

That is, in a memory transistor that does not provide such an impurity region 38, if the impurity concentration in the channel region is increased in order to increase the generation of hot carriers, the threshold voltage may increase and the read current may decrease. .. On the other hand, in the memory transistor 11 in which the impurity region 38 having a relatively high concentration is provided below the channel region 37 as described above, the generation of hot carriers is increased and the threshold voltage is increased without causing such inconvenience. Can be controlled.

The impurity region 38 is in contact with the impurity region 35a and the impurity region 35b that function as a source region or a drain region in order to effectively realize functions such as increasing hot carrier generation, controlling the threshold voltage, and suppressing punch-through. It is provided as follows.

In the memory transistor 11, the program speed can be improved by adopting the impurity region 38 as described above.
The memory transistor 12 has the same structure. For example, the same structure as in FIG. 4 may be provided in the left direction of the paper surface or the right direction of the paper surface in FIG. Since the memory transistors 11 and 12 are of the same conductive type, they may share a source region or a drain region. For example, the memory transistors 11 and 12 may be provided adjacent to each other so as to share the impurity region 35a or the impurity region 35b without passing through the element separation region 31.

FIG. 5 is a diagram showing an example relationship between the drain current of the memory transistor and the gate voltage. The vertical axis represents the drain current Id (A / μm), and the horizontal axis represents the gate voltage Vg (V).

Note that FIG. 5 shows the relationship between the drain current Id of the memory transistor 11 having a gate width of 0.1 μm and a gate length of 0.16 μm and the gate voltage Vg. The characteristic 40 shows the relationship between the drain current Id before the program and the gate voltage Vg, and the characteristic 41 shows the relationship between the drain current Id after the program and the gate voltage Vg. The program is performed, for example, by setting the gate voltage Vg and the drain voltage Vd to 4V for 10 μsec.

As can be seen from the characteristic 40, before the program, when the gate voltage Vg is 1.0 to 1.5 V, a large amount of drain current Id flows and the memory transistor 11 is turned on. On the other hand, as can be seen from the characteristic 41, after the program, the drain current (leakage current) Id is 100 fA or less even when the gate voltage Vg is 1.0 to 1.5 V, and the state is off.

Assuming that the memory transistors 12 have the same characteristics, when the gate voltage Vg of the memory transistors 11 and 12 is 1.0 to 1.5 V, the programmed memory transistors 11 and 12 are in the off state, and the other is in the off state. Turns on.

Hereinafter, a programming method for the memory transistors 11 and 12 having a structure as shown in FIG. 4 will be described. In the following, the memory transistors 11 and 12 will be described as being of the n-channel type, but the memory transistors 11 and 12 may be of the p-channel type. In that case, the voltage supplied to the memory transistors 11 and 12 may be changed as appropriate.

Further, in the following, as shown in FIGS. 1 and 2, it is assumed that the power supply voltage VSS is supplied to the source or drain of the memory transistor 11 which is not connected to the memory transistor 12 at the time of reading. .. Further, it is assumed that the power supply voltage VDD is supplied to the source or drain of the memory transistor 12 that is not connected to the memory transistor 11 at the time of reading.

Further, in the following, programming the memory transistor 12 in the off state may mean programming “0” in the non-volatile storage device 20. Further, programming the memory transistor 11 to the off state may mean programming "1" in the non-volatile storage device 20.

(Programming method (1))
6 and 7 are diagrams showing an example of the voltage supplied when the memory transistor is programmed. FIG. 6 shows an example of the voltage supplied when programming “1” in the non-volatile storage device 20.

For example, 0.0V (power supply voltage VSS) is supplied to the drain of the memory transistor 11 and the source, drain, and gate of the memory transistor 12. A program control voltage (pulse signal) of, for example, 3.5 to 4.5 V, which is larger than the power supply voltage VDD or the read control voltage, is supplied to the drain and gate of the memory transistor 11 for a predetermined period. For example, when a 3.5 V program control voltage is used, the pulse width is 1 msec, when a 4.0 V program control voltage is used, the pulse width is 100 μsec, when a 4.5 V program control voltage is used, the pulse width is 10 μsec, and the like. And.

The lower limit of the program control voltage is set so that hot carrier injection occurs, for example. The upper limit of the program control voltage is set in consideration of, for example, the withstand voltage of the memory transistor 11.

The terminal 24 from which the read data is output is in an open state.
By supplying the program control voltage as described above to the memory transistor 11, the control circuit 21 injects hot carriers into the storage area 11a, and the memory transistor 11 is programmed in the off state.

FIG. 7 shows an example of the voltage supplied when programming “0” in the non-volatile storage device 20.
For example, 0.0V (power supply voltage VSS) is supplied to the source of the memory transistor 12. A program control voltage (pulse signal) of, for example, 3.5 to 4.5 V is supplied to the gate and drain of the memory transistor 12 and the drain, source and gate of the memory transistor 11 for a predetermined period. For example, when a 3.5 V program control voltage is used, the pulse width is 1 msec, when a 4.0 V program control voltage is used, the pulse width is 100 μsec, when a 4.5 V program control voltage is used, the pulse width is 10 μsec, and the like. And.

The terminal 24 from which the read data is output is in an open state.
By supplying the program control voltage as described above to the memory transistor 12, the control circuit 21 injects hot carriers into the storage area 12a, and the memory transistor 12 is programmed in the off state.

Next, an example of the control circuit 21 that supplies the voltage shown in FIGS. 6 and 7 to the memory transistors 11 and 12 is shown.
FIG. 8 is a diagram showing an example of a control circuit.

The control circuit 21 includes switch circuits 51, 52, 53, 54, 55 and a switch control circuit 56.
The switch circuit 51 supplies the power supply voltage VDD or the power supply voltage VSS to one of the source and drain of the memory transistor 12 based on the control signal supplied from the switch control circuit 56.

The switch circuit 52 supplies a program control voltage, a read control voltage, or a power supply voltage VSS to the gate of the memory transistor 12 based on the control signal supplied from the switch control circuit 56.

The switch circuit 53 switches whether to supply the program control voltage or the power supply voltage VSS to the node 13 or to electrically connect the terminal 24 based on the control signal supplied from the switch control circuit 56.

The switch circuit 54 supplies a program control voltage, a read control voltage, or a power supply voltage VSS to the gate of the memory transistor 11 based on the control signal supplied from the switch control circuit 56.

The switch circuit 55 supplies a program control voltage or a power supply voltage VSS to one of the source and drain of the memory transistor 11 based on the control signal supplied from the switch control circuit 56.

The switch control circuit 56 outputs a control signal for controlling the switch circuits 51 to 55 based on the mode instruction signal.
For example, when the switch control circuit 56 receives a mode instruction signal instructing the non-volatile storage device 20 to program “1”, the voltage shown in FIG. 6 is supplied to the memory transistors 11 and 12. Controls the switch circuits 51 to 55. When the switch control circuit 56 receives a mode instruction signal instructing the non-volatile storage device 20 to program "0", the switch control circuit 56 switches so that the voltage shown in FIG. 7 is supplied to the memory transistors 11 and 12. It controls circuits 51 to 55.

When the switch control circuit 56 receives the mode instruction signal instructing to read the stored contents, the switch control circuit 56 causes the switch circuit 51 to supply the power supply voltage VDD to the drain of the memory transistor 12. Further, the switch control circuit 56 causes the switch circuits 52 and 54 to supply the read control voltage to the gates of the memory transistors 11 and 12, and causes the switch circuit 55 to supply the power supply voltage VSS to the source of the memory transistors 11. Further, the switch control circuit 56 electrically connects the node 13 and the terminal 24 to the switch circuit 53. The read control voltage is a gate voltage in which the unprogrammed memory transistor of the memory transistors 11 and 12 is turned on and the programmed memory transistor is turned off, and is, for example, 1.0 to 1.5 V.

FIG. 9 is a diagram showing an example of a switch circuit. FIG. 9 shows an example of the switch circuit 52 shown in FIG.
The switch circuit 52 has level conversion circuits 60, 61, 62 and p-channel MOSFETs ((Metal-Oxide Semiconductor Field Effect Transistor) (hereinafter abbreviated as pMOS) 63, 64, 65. Further, the switch circuit 52 has n channels. It has type MOSFETs (hereinafter abbreviated as nMOS) 66, 67, 68.

As shown in FIG. 9, the switch control circuit 56 supplies the control signals ct1, ct2, and ct3 to the switch circuit 52.
When it is instructed to program "0" by the mode instruction signal, the switch control circuit 56 sets the logic level of the control signal ct1 to the H (High) level (for example, the control signal ct1 is 0.5V). When the reading of the stored contents is instructed by the mode instruction signal, the switch control circuit 56 sets the logic level of the control signal ct2 to H level (for example, the control signal ct2 is 0.5V). When it is instructed to program "1" by the mode instruction signal, the switch control circuit 56 sets the logic level of the control signal ct3 to H level (for example, the control signal ct3 is 0.5V).

The level conversion circuit 60 outputs two gate voltages having complementary logic levels for turning both pMOS63 and nMOS66 on and off based on the control signal ct1.
The level conversion circuit 61 outputs two gate voltages having complementary logic levels for turning both pMOS64 and nMOS67 on and off based on the control signal cnt2.

The level conversion circuit 62 outputs two gate voltages having complementary logic levels for turning both pMOS65 and nMOS68 on and off based on the control signal ct3.
The level conversion circuits 60 to 62 boost the control signals ct1 to ct3 to generate a gate voltage such that pMOSs 63 to 65 and nMOSs 66 to 68 are sufficiently turned on or off as described above.

pMOS63 and nMOS66 form a transfer gate. A program control voltage is supplied to one of the source or drain of the pMOS 63 and one of the source or drain of the nMOS 66. The gate of the memory transistor 12 is connected to the other of the source or drain of the pMOS 63 and the other of the source or drain of the nMOS 66. Therefore, when both pMOS 63 and nMOS 66 are turned on based on the two gate voltages supplied from the level conversion circuit 60, the program control voltage is supplied to the gate of the memory transistor 12. On the other hand, when both pMOS 63 and nMOS 66 are turned off based on the two gate voltages supplied from the level conversion circuit 60, the supply of the program control voltage to the gate of the memory transistor 12 is cut off.

pMOS64 and nMOS67 form a transfer gate. A read control voltage is supplied to one of the source or drain of the pMOS 64 and one of the source or drain of the nMOS 67. The gate of the memory transistor 12 is connected to the other of the source or drain of the pMOS 64 and the other of the source or drain of the nMOS 67. Therefore, when both pMOS 64 and nMOS 67 are turned on based on the two gate voltages supplied from the level conversion circuit 60, the read control voltage is supplied to the gate of the memory transistor 12. On the other hand, when both pMOS64 and nMOS67 are turned off based on the two gate voltages supplied from the level conversion circuit 60, the supply of the read control voltage to the gate of the memory transistor 12 is cut off.

pMOS65 and nMOS68 form a transfer gate. A power supply voltage VSS (for example, 0V) is supplied to one of the source or drain of pMOS65 and one of the source or drain of nMOS68. The gate of the memory transistor 12 is connected to the other of the source or drain of the pMOS 65 and the other of the source or drain of the nMOS 68. Therefore, when both pMOS65 and nMOS68 are turned on based on the two gate voltages supplied from the level conversion circuit 60, the power supply voltage VSS is supplied to the gate of the memory transistor 12. On the other hand, when both pMOS65 and nMOS68 are turned off based on the two gate voltages supplied from the level conversion circuit 62, the supply of the power supply voltage VSS to the gate of the memory transistor 12 is cut off.

In such a switch circuit 52, both the pMOS 63 and the nMOS 66 are turned on by the two gate voltages output from the level conversion circuit 60 based on the control signal cnt1 when the program is “0”. Further, both pMOS64 and nMOS67 are turned off by the two gate voltages output from the level conversion circuit 61 based on the control signal ct2. Further, both pMOS65 and nMOS68 are turned off by the two gate voltages output from the level conversion circuit 62 based on the control signal cnt3. As a result, the program control voltage is supplied to the gate of the memory transistor 12.

At the time of programming "1", both pMOS63 and nMOS66 are turned off by the two gate voltages output from the level conversion circuit 60 based on the control signal ct1. Further, both pMOS64 and nMOS67 are turned off by the two gate voltages output from the level conversion circuit 61 based on the control signal ct2. Further, both pMOS65 and nMOS68 are turned on by the two gate voltages output from the level conversion circuit 62 based on the control signal ct3. As a result, the power supply voltage VSS is supplied to the gate of the memory transistor 12.

Similar to the switch circuit 52, the switch circuits 53 and 54 can also be realized by a circuit including three transfer gates and three level conversion circuits. The switch circuits 51 and 55 can be realized by a circuit including two transfer gates and two level conversion circuits.

(Programming method (2))
FIG. 10 is a diagram showing another example of the voltage supplied when the memory transistor is programmed. FIG. 10 shows another example of the voltage supplied to the memory transistors 11 and 12 when "1" is programmed, that is, when the memory transistors 11 are programmed in the off state.

Unlike the programming method shown in FIG. 6, in the programming method shown in FIG. 10, a program control voltage of, for example, 3.5 to 4.5V is supplied to the gate of the unprogrammed memory transistor 12.

The voltage supplied when programming “0” is the same as the example shown in FIG.
Next, an example of a control circuit that supplies the voltage shown in FIG. 10 to the memory transistors 11 and 12 will be shown.

FIG. 11 is a diagram showing another example of the control circuit. In FIG. 11, the same elements as those shown in FIG. 8 are designated by the same reference numerals.
The control circuit 21a of the non-volatile storage device 20a shown in FIG. 11 does not have a switch circuit 54 unlike the control circuit 21 of the non-volatile storage device 20 shown in FIG. Instead, the gates of the memory transistors 11 and 12 are connected to each other, and the same voltage (program control voltage, read control voltage or power supply voltage VSS) is supplied to the gates of the memory transistors 11 and 12 from the switch circuit 52. To.

Even in such a control circuit 21a, the programs of the memory transistors 11 and 12 and the reading from the memory transistors 11 and 12 can be performed. Further, since the control circuit 21a can eliminate the switch circuit 54 of the control circuit 21 shown in FIG. 8, the circuit area of the non-volatile storage device 20a can be made smaller.

The flow of the programming method of the non-volatile storage devices 20 and 20a by the control circuits 21 and 21a will be summarized below.
FIG. 12 is a flowchart showing a flow of an example of a programming method for the non-volatile storage device.

When the control circuits 21 and 21a receive an instruction indicating that "0" or "1" is programmed by the mode instruction signal (step S1), the control circuits 21 and 21a determine whether or not to program "0" (step S2). .. When programming "0", the control circuits 21 and 21a supply the voltage shown in FIG. 7 to the memory transistors 11 and 12 to execute the program (step S3), and then end the program. When programming "1", the control circuits 21 and 21a supply the voltage shown in FIG. 6 or 10 to the memory transistors 11 and 12 to execute the program (step S4), and then execute the program. finish.

By the above programming method, it is possible to provide the non-volatile storage devices 20 and 20a in which one of the memory transistors 11 and 12 is programmed in the off state. The non-volatile storage devices 20 and 20a provided by the above programming method have the following effects as compared with, for example, a fuse ROM using an electric fuse, which is one of the non-volatile storage devices.

Hereinafter, an example of the fuse ROM will be shown in order to compare the non-volatile storage devices 20 and 20a of the second embodiment with the fuse ROM using the electric fuse which is one of the non-volatile storage devices.

FIG. 13 is a diagram showing an example of the fuse ROM.
The fuse ROM 70 includes an electric fuse 71, a writing circuit 72, a sense circuit 73, and a flip-flop 74.

One end of the electric fuse 71 is connected to the writing circuit 72 and the sense circuit 73. A predetermined voltage VBLOW is supplied to the other end of the electric fuse 71. As the electric fuse 71, a fuse using a silicide layer formed on a polysilicon layer, a metal fuse, or the like is used.

The writing circuit 72 has a level conversion circuit 72a and an nMOS 72b. When the logic level of the write enable signal WE (pulse signal) is H level (during writing), the level conversion circuit 72a boosts the write enable signal WE and outputs the gate voltage of nMOS72b. The drain of the nMOS 72 is connected to one end of the electric fuse 71, and the power supply voltage VSS is supplied to the source of the nMOS 72.

The sense circuit 73 has pMOS73a, nMOS73b, and a buffer circuit 73c. The power supply voltage VSS is supplied to the gate of the pMOS73a, and the power supply voltage VDD is supplied to the source of the pMOS73a. The drain of the pMOS 73a is connected to the drain of the nMOS 73b and the input terminal of the buffer circuit 73c. The source of the nMOS73b is connected to one end of the electric fuse 71 and the drain of the nMOS72b. A sense signal SENSE is supplied to the gate of the nMOS73b. The output terminal of the buffer circuit 73c is connected to the input terminal of the flip-flop 74.

The flip-flop 74 holds the output signal (read data) of the buffer circuit 73c of the sense circuit 73 in synchronization with the clock signal ck.
In such a fuse ROM 70, at the time of writing, the logic level of the sense signal SENSE becomes the L (Low) level, the nMOS73b is turned off, the logic level of the write enable signal WE becomes the H level, and the nMOS72b is turned on. Then, as a write voltage, a relatively large voltage VBLOW is applied to the electric fuse 71, a current flows through the electric fuse 71, and the electric fuse 71 is cut. When the resistance value of the electric fuse 71 is 120Ω and the fuse 71 is cut off when a current of 10 mA flows, for example, 2.4V is applied as the voltage VBLOW.

At the time of reading, the logic level of the sense signal SENSE becomes the H level, the nMOS73b turns on, the logic level of the write enable signal WE becomes the L level, and the nMOS72b turns off. Further, a predetermined voltage VBLOW (for example, 0V) is supplied to the electric fuse 71. When the electric fuse 71 is blown, the potential of the input terminal of the buffer circuit 73c becomes H level, and the buffer circuit 73c outputs "1" as read data. When the electric fuse 71 is not blown, the potential of the input terminal of the buffer circuit 73c becomes L level, and the buffer circuit 73c outputs "0" as read data.

The flip-flop 74 holds the read data output from the buffer circuit 73c in synchronization with the clock signal ck, and supplies the read data to the output terminal 75 of the fuse ROM 70.
Compared with the fuse ROM 70 as described above, the non-volatile storage devices 20 and 20a of the second embodiment only supply the read control voltage to the gates of the memory transistors 11 and 12 at the time of reading, and the read data can be obtained. Be done. That is, when the memory transistor 11 is programmed in the off state, it is in the “1” data read state, and when the memory transistor 12 is programmed in the off state, it is in the “0” data read state.

This eliminates the need for the sense circuit 73 and the holding circuit (flip-flop 74) as shown in FIG. 13, and can reduce the circuit area of the non-volatile storage devices 20 and 20a. Further, since the sense circuit 73 and the holding circuit are not required, the power consumption can be reduced.

Further, by using the memory transistor 11 having the structure shown in FIG. 4 (the memory transistor 12 can also have the same structure), as shown in FIG. 5, when programmed in the off state. Leakage current can be reduced. Therefore, the power consumption can be further reduced.

The memory transistors 11 and 12 may be flash memories. However, in the case of a flash memory, it is necessary to form a floating gate or the like, but in the case of a memory using a side wall insulating film, it is not necessary to form a floating gate or the like, and an increase in the number of steps can be suppressed.

Although one aspect of the non-volatile storage device and the programming method of the non-volatile storage device of the present invention has been described above based on the embodiment, these are merely examples and are not limited to the above description.

10 Non-volatile storage device 11, 12 Memory transistor 11a, 12a Storage area 13 nodes VDD, VSS power supply voltage

Claims (7)

A second power supply voltage that is turned on based on the first voltage supplied to the first gate and is smaller than the first power supply voltage and the first power supply voltage supplied to one of the first source and the first drain. A first memory transistor that outputs an output voltage based on one of the power supply voltages from the first source and the other of the first drain.
It is the same conductive type as the first memory transistor, and one of the second source and the second drain is connected to the other of the first source and the first drain, and the second source And the other of the second drain is supplied with the other of the first power supply voltage and the second power supply voltage, and is programmed to be turned off when the first voltage is supplied to the second gate. The second memory transistor that has been
Have,
The first memory transistor and the second memory transistor are
A source region and a drain region provided in the semiconductor substrate and containing first conductive type impurities, and
A channel region provided in the semiconductor substrate between the source region and the drain region,
A first impurity containing the first conductive type impurity provided in the semiconductor substrate between the source region and the drain region, with a part of the upper surface in contact with the channel region. It is in contact with the lower surface of the region and is perpendicular to the surface of the semiconductor substrate with respect to the entire lower portion of the channel region, the first storage region of the first memory transistor, and the second storage region of the second memory transistor. A second conductive type impurity different from the first conductive type, which is continuously provided between the source region and the drain region in the semiconductor substrate below in the above direction and has a higher concentration than the channel region. Has a second impurity region containing,
A non-volatile storage device characterized by this. The second power supply voltage is supplied to one of the second source and the second drain, and the first is supplied to the other of the second source and the second drain and the second gate. The first aspect of claim 1, wherein the control circuit further includes a control circuit for programming the second memory transistor to the off state by supplying a power supply voltage and a second voltage larger than the first voltage. Non-volatile storage device. The control circuit is characterized in that when the second memory transistor is programmed to the off state, the second voltage is further supplied to the first gate of the first memory transistor. The non-volatile storage device according to claim 2. The first storage area is a first side wall insulating film provided on the first side wall of the first gate electrode of the first memory transistor, and the second storage area is the second side wall. The non-volatile storage device according to any one of claims 1 to 3, wherein the second side wall insulating film is provided on the second side wall of the second gate electrode of the memory transistor. Claims 1 to 4, wherein the first memory transistor and the second memory transistor are provided adjacent to each other so as to share the source region or the drain region with each other without interposing the element separation region. The non-volatile storage device according to any one of the above. One of the second source and the second drain is provided on the first memory transistor and one of the first source and the first drain of the first memory transistor which is the same conductive type as the first memory transistor. The first memory transistor and the second memory transistor including the connected second memory transistor are provided in the semiconductor substrate, and the source region and the drain region containing the first conductive type impurities and the source. A channel region provided in the semiconductor substrate between the region and the drain region, a part of the upper surface is in contact with the channel region, and another part of the upper surface is in the semiconductor substrate with the source region and the drain. It is in contact with the lower surface of the first impurity region containing the first conductive type impurity provided between the regions, and is in contact with the entire lower portion of the channel region, the first storage region of the first memory transistor, and the said. The channel is continuously provided between the source region and the drain region in the semiconductor substrate below the surface of the semiconductor substrate in a direction perpendicular to the surface of the semiconductor substrate with respect to the second storage region of the second memory transistor. When the control circuit programs a first value in a non-volatile storage device having a second impurity region containing a second conductive type impurity different from the first conductive type, which has a higher concentration than the region.
The control circuit supplies a first voltage to the other of the first source and the first drain, and the first gate of the first memory transistor, and supplies the first source and the first. A second voltage smaller than the first voltage is supplied to one of the drains for programming.
When the control circuit programs the non-volatile storage device with a second value,
The control circuit supplies the first voltage to one of the second source and the second drain, and the second gate of the second memory transistor, and supplies the second source and the second. The second voltage is supplied to the other side of the drain to perform the program.
A method of programming a non-volatile storage device. When the control circuit programs the first value in the non-volatile storage device, it also supplies the first voltage to the second gate of the second memory transistor.
When the control circuit programs the second value in the non-volatile storage device, it also supplies the first voltage to the first gate of the first memory transistor.
The method for programming a non-volatile storage device according to claim 6.

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