JPH0757468A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain technology for writing initial data at high speed. CONSTITUTION:The device is provided with MOS transistors M5 and M6 and a control system for controlling them-as an initial data writing means for writing initial data in the lump in plural memory cells, and the initial data are written in the lump in the plural memory cells MS. By this method, high speed writing of the initial data is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to an initial data write technique for a semiconductor memory device having static memory cells arranged in an array.

[0002]

2. Description of the Related Art As a semiconductor memory device, a mask ROM (read only memory) whose holding data is determined in a manufacturing process, an electrically writable EPROM (electrically programmable read only memory),
EEPROM (Electrical Erasable and Programmable Read Only Memory), S that allows program changes while installed in the system, S
RAM (Static Random Access Memory)
Etc.

As an example of a document describing a semiconductor memory device, "LSI Handbook (485th Edition), published by Ohmsha Co., Ltd. on November 30, 1984, is available.
Page) ”.

[0004]

It is necessary to load initial environment data (initial data) at the time of system startup in a workstation or the like, and the present inventor examined such a load destination memory (main memory). However, as such a main memory, EEPR
SRAM that can operate at high speed is more suitable than OM etc.,
When this SRAM is applied, SRA is used for writing.
Since it is necessary to scan all the addresses of M, the write time of the initial data (day write cycle width or write pulse width) is inevitably long, which impedes high-speed system startup. Was found.

An object of the present invention is to provide a technique for writing initial data at high speed.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, the semiconductor memory device is provided with initial data writing means for collectively writing initial data to a plurality of memory cells. At this time, the initial data write means controls the initial data write element in a state in which the initial data write element coupled to the memory cell and the word line coupled to the memory cell are at the non-selection level. And a control means for determining the logic state of the memory cell. A cell power supply for erasing the data held in the memory cell by temporarily interrupting the power supply to the memory cell immediately before the control of the initial data writing element to determine the logic state of the memory cell. Parts may be included in the control means.

[0009]

According to the above-mentioned means, the initial data writing means collectively writes the initial data to the plurality of memory cells, which achieves the speedup of the initial data writing.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an SRAM according to an embodiment of the present invention.
Is shown.

Although not particularly limited, the SRAM shown in FIG. 1 is used as a main memory to which initial data is loaded in a workstation or the like, and one semiconductor substrate such as single crystal silicon is manufactured by a known semiconductor integrated circuit manufacturing technique. Is formed in.

In FIG. 1, reference numeral 6 denotes a memory cell array in which a plurality of static memory cells are arranged in a matrix. Select terminals of the memory cells are connected to word lines in each row direction and data input / output terminals of the memory cells are column columns. Each direction is coupled to a complementary data line (also called a complementary bit line). 1 for each complementary data line
Y including a plurality of column selection switches connected in pair 1
It is commonly connected to the complementary common data line via the selection switch circuit 9.

Address signals A0-A input from the outside
A0 to Am among n are transmitted to the X decoder 4 via the address buffers 1-0 to 1-m arranged corresponding to them, and the address signals Am + 1 to An are corresponding to the address buffers arranged corresponding to them. It is transmitted to the Y decoder 8 via 1-m + 1 to 1-n. Word driver 5 is X
Based on the decoded output of the decoder 4, the word line corresponding to the input address signal is driven to the selection level. When a predetermined word line is driven, the memory cell coupled to this word line is selected. Further, the Y decoder 8 turns on the column selection switch corresponding to the address signal supplied thereto, so that the column decoder switch is electrically connected to the selected complementary common data line. At this time, the potential of the complementary common data line is amplified by the sense amplifier included in the data input / output circuit 10,
Further, it can be output to the outside through the output buffer.
When write data is externally applied to the input buffer included in the data input / output circuit 10, the complementary common data line is driven according to the write data, whereby a predetermined memory is provided via the complementary data line selected by the address signal. Charge information corresponding to the data is stored in the cell. Here, although not particularly limited, the data input / output circuit 10 has a 4-bit structure and includes four input buffers and four output buffers corresponding thereto. In such a configuration, the same data external terminal is shared by the input buffer and the corresponding output buffer in the same bit because of the reduction in the number of external terminals.

Further, in the present embodiment, the address signals A0 to A0.
An address change detection circuit (also referred to as an ATD circuit) 11 that detects a change in An is provided, and the detection result of this address change detection circuit 11 is transmitted to the control unit 7. Then, a chip select signal CS * (* indicates low active or signal inversion) as a control signal given from the outside, a write enable signal WE *, and a reset signal RS * are CS * buffer 2 and WE *, respectively.
It is taken in by the control unit 7 via the buffer 3 and the RS * buffer 12, and the control unit 7 generates the operation control signals for the respective units of this embodiment. When the chip select signal CS * is asserted to the low level, the operation is selectively enabled. Further, in such a selected state, when the write enable signal WE * is asserted to the low level, the data is written to the memory cell, and when it is negated to the high level, the memory cell data is read. To be in a state. Further, when the reset signal RS * is asserted to the low level, the SRAM of this embodiment is returned to the initial state, and the state of the chip select signal CS *, the write enable signal WE *, and the address signals A0 to An are obtained. Regardless of this, predetermined initial data is written in the memory cell array 6. In order to write the initial data at high speed, in this embodiment, the cell power supply unit 13 and the delay circuit 14 arranged at the subsequent stage thereof are provided, and the initial data write cycle is controlled under the control of the control unit 7. It is supposed to be started. In the initial data write cycle, after the energization of the SRAM of this embodiment is started,
The RAM is activated immediately before the normal operation of the RAM is started.

Reference numeral 13 is a cell power supply unit, and this cell power supply unit 13 forms a cell power supply voltage VC1 supplied to the memory cell array 6. The cell power supply voltage VC1 is not particularly limited, but as shown in FIG. 3, is set to a low level at times t1 to t3 of the initial data write cycle, and then set to a high level. Such control is performed by the control unit 87. Also, when the reset signal RS * from the outside is asserted, the cell power supply voltage VC1 whose rising edge is delayed is similarly generated. That is, when the energization of the SRAM of this embodiment is started and the reset signal RS * is asserted, the cell power supply voltage VC1 output from the cell power supply unit 13 rises as shown in FIG. Is delayed so that energization to the memory cell is stopped for a short time. The reason for controlling the voltage level in this way is to erase the stored data of all memory cells immediately before writing the initial data, as will be described later.

As shown in FIG. 3, a delay circuit 14 for generating the initial data write signal IDW by delaying the cell power supply voltage VC1 is arranged at the subsequent stage of the cell power supply unit 13. As shown in FIG. 3, the initial data write signal IDW is delayed from the falling edge of the cell power supply voltage VC1 and is set to high level at time t2, and is set to low level at the end of the initial data write cycle, that is, time t4. It

FIG. 2 representatively shows one of the plurality of memory cells MS included in the memory cell array.

Although not particularly limited, the memory cell MS is
n-channel type MOS transistors M3, M4, and p
It includes a flip-flop formed by coupling channel type MOS transistors M7 and M8. p-channel type MOS
A cell power supply voltage VC1 as a memory cell power supply is supplied to the transistors M7 and M8. n
The channel type MOS transistors M3 and M4 are coupled to the low potential side power source Vss. This n-channel MOS transistor M is used for writing initial data.
N-channel MOS transistors M5 and M6 are connected in parallel to 3 and M4, respectively. The gate electrode of the n-channel MOS transistor M5 has a contact C
By being coupled to the initial data write line 17 via T1, the initial data write signal IDW is applied. Also, n-channel type M
The gate electrode of the OS transistor M6 has a contact CT
It is coupled to the low potential side power source Vss via 2. The complementary data lines d and d * are coupled to flip-flops via n-channel MOS transistors M1 and M2, respectively. The n-channel MOS transistors M1 and M2
Has its gate electrode coupled to a word line 16, and when this word line 16 is driven to a high level, n
By turning on the channel-type MOS transistors M1 and M2, it is possible to read data from the memory cell MS and write data to the memory cell MS.
Although not shown, the complementary data lines d and d * are selectively coupled to the complementary common data line via the Y selection switch circuit 9 of FIG. Although not particularly limited, the complementary data lines d and d * have p-channel MOS transistors M9 and M1 as their loads.
0 is coupled to the MOS transistors M9 and M
The complementary data lines d and d * are precharged via 10.

The other memory cells are also constructed in the same manner as above.

Writing of the initial data is performed as follows.

The cell power supply voltage V which is the output of the cell power supply unit 13 when the energization of the SRAM of this embodiment is started or the reset signal RS * is asserted to the low level.
By setting C1 to the low level, the stored data in all the memory cells MS is lost (t1). Word line 1
Due to the non-selected state of 6, the initial data write signal IDW is changed from the low level to the high level with the n-channel type MOS transistors M1 and M2 turned off (t2). In this state, when the cell power supply voltage VC1 is boosted (t3), the n-channel MOS transistor M5
Side storage node N1 is set to the low potential side power supply Vss level, and storage node N2 on the n-channel MOS transistor M6 side is set to the high potential side power supply Vcc level. That is, since the MOS transistor M5 is turned on by applying the high level of the initial data write signal IDW to the gate electrode of the n-channel MOS transistor M5, the node N1 is connected to the low-potential-side power supply V
Although it is set to the ss level, since the gate electrode of the n-channel type MOS transistor M6 is set to the low potential side power source Vss level, it is turned off.

The state of the write data to the memory cell is determined by whether the gate electrodes of the MOS transistors M5 and M6 for writing the initial data are connected to the initial data writing line 17 or the low potential side power source Vss. It That is, in this embodiment, the node N1 is set to the low level when the initial data write signal IDW is set to the high level.
, "0" is written in, but conversely, the gate electrode of the n-channel type MOS transistor M5 is coupled to the low potential side power source Vss, and the gate electrode of the n-channel type MOS transistor M6 is written with initial data. By connecting to the line 17, the n-channel MOS transistor M5 is turned off and the n-channel MOS transistor M6 is turned on, so that "1" is written in the memory cell MS. That is, the n-channel MOS transistor M5 or the n-channel MOS transistor
The logic of data to be written in the memory cell MS is determined depending on which one of the transistors M6 is coupled to the initial data write line 17.

The state of such initial data is determined in the manufacturing process of the SRAM of this embodiment, that is, in the line contact process in the wafer forming process.

The initial data writing as described above is performed simultaneously for all memory cells. for that reason,
R by scanning all addresses as before
As compared with the case of loading the initial data from the OM or the fixed disk, the writing time of the initial data can be significantly shortened.

The initial data write line cycle is ended by negating the initial data write signal IDW to the low level (t4), and thereafter, the normal SRAM operation cycle is started. For example, normal S
In the RAM operation cycle, one of the plurality of word lines is driven to the selection level according to the address signals A0 to Am, and the Y selection switch is controlled according to the address signals Am + 1 to An, so that the complementary data lines are Is selectively coupled to the complementary common data line, so that data can be read from or written in the specified memory cell.

According to the above embodiment, the following operational effects can be obtained.

(1) Initialization is performed by the cell power supply unit 13 and the delay unit 14 controlled by the control unit 7, and the n-channel type MOS transistors M5 and M6 as initial data writing elements coupled to the memory cell MS. Since the data writing means is formed to write the initial data to all the memory cells in a lump, it is not necessary to scan all addresses when loading the initial data from the ROM or the fixed disk, and the writing of the initial data is performed. Can be done at high speed. Therefore, in a workstation or the like that uses the SRAM of this embodiment as a main memory, the system can be started up faster. For example, in the prior art, SRA with a maximum access time of 20 ns and a 128K × 8 bit configuration is used.
Considering the case of performing initial data write to M and 2, the initial data write cycle is (this SRA
It is 20 ns × 128 K × 2 = 5.12 ms, assuming that the write time is controlled by M). However, according to the above embodiment, it depends on the capability of the p-channel type MOS transistors M7 and M8.
It is also possible to set the initial data write cycle to 50 ns or less.

(2) The initial data write means is an n-channel MOS transistor M as an initial data write element coupled to the memory cell MS.
5, M6 and the delay unit 14 as a control means for controlling the n-channel MOS transistor M5 to determine the logic state of the memory cell with the word line 16 at the non-selection level. Can be configured to.

(3) Immediately before determining the logic state of the memory cell MS, a cell power supply unit 13 for erasing the data held in the memory cell by temporarily interrupting the power supply to the memory cell MS is provided. By providing, it is possible to achieve accurate writing of the initial data.

FIG. 4 representatively shows one of the plurality of memory cells MS included in the memory cell array 6 in another embodiment.

In the above embodiment, the initial data written in one memory cell is fixed, but in this embodiment, a desired pattern can be selected from a plurality of initial data patterns. That is, the initial data write lines 21 to 26 are provided and selectively driven by the delay circuit 14 shown in FIG. 1 to write "1" or "0" in the memory cell. . Although not particularly limited, the initial data write lines 21 and 22 are connected to the initial data write signal IDW1 and the initial data write signal IDW1.
* Indicates that the initial data write signal 23, 24 has the initial data write signal IDW2, the initial data write signal IDW2 * has the initial data write line 2
5 and 26, initial data write signal IDW3,
The initial data write signal IDW3 * is supplied respectively. The gate electrode of the n-channel MOS transistor M5 is coupled to the initial data write line 21 by the contact CT21, coupled to the initial data write line 24 by the contact CT24, and further coupled to the initial data write line 26 by the contact CT26. . Similarly, the gate electrode of the n-channel MOS transistor M6 is coupled to the initial data write line 22 by the contact CT22, coupled to the initial data write line 23 by the contact CT23, and further contact CT2.
5 is coupled to the initial data write line 25. In such a configuration, for example, as shown in FIG. 5, the initial data write signal IDW1 is asserted at a high level, and the initial data write signal ID
When W1 * is asserted to low level, the other initial data write signals are set to high impedance to prevent signal destruction. At this time, initial data "0" is written in the memory cell. When the initial data write signal IDW2 is asserted to the high level and the initial data write signal IDW2 * is asserted to the low level, the initial data "1" is written in the memory cell. Therefore, in the manufacturing process, a plurality of patterns are prepared as the initial data if the initial data write lines to be connected to the gate electrodes of the n-channel MOS transistors M5 and M6 by contacts are selected in memory cell units. That is, it can be arbitrarily selected.
Such a configuration is effective when there are a plurality of types of initial data and it is necessary to switch them depending on the conditions.

FIG. 6 representatively shows one of the plurality of memory cells MS included in the memory cell array 6 in another embodiment.

Although the memory cell having the load of the p-channel type MOS transistor is used in the above-mentioned embodiment, the memory cell is not limited to this. For example, as shown in FIG. 6, the high resistances R1 and R2 are used as the memory. A cell can be configured, and in that case, the present invention can be applied. Although the values of the high resistances R1 and R2 are not particularly limited, they are equal to each other. Even when the memory cell is configured by such a high resistance load, the same effect as that of the above-described embodiment can be obtained. Note that the time required for the potential difference between the storage node N1 and the storage node N2 to become stable for storing data after the cell power supply voltage VC1 is set to the high level is the high resistance values R1 and R2 and the storage node N1. , N2
Of the p-channel type MOS as in the above-described embodiment. Therefore, the actual value of the initial data write cycle may be several ms.
The time required to write the initial data is slightly longer than when the transistors M7 and M8 are used as the memory cell load.

FIG. 7 representatively shows one of a plurality of memory cells MS included in the memory cell array 6 in another embodiment.

In the above embodiment, the n-channel MOS transistors M5 and M6 have been described, but they may be omitted. For example, in the embodiment shown in FIG. 7, the initial data is written in the memory cell MS via the complementary data lines d and d *.
In the normal SRAM operation, the column selection switch circuit 9
Although a plurality of complementary data lines are selectively coupled to the complementary common data line by (see FIG. 1), in the initial data write cycle, although not particularly limited, all complementary data lines have the corresponding complementary common data line. By being coupled to the lines, write data input from the outside can be simultaneously transmitted to all complementary data lines. The operation in this case is as shown in FIG.
Almost at the same time when the cell power supply voltage VC1 is set to low level, the load control voltage VC2 becomes high level. The load control voltage VC2 is applied to the gate electrodes of the p-channel MOS transistors M9 and M10, and is kept at the high level until the initial data write cycle ends. As a result, the p-channel MOS transistors M9 and M10 are kept in the off state until the end of the initial data write cycle. By turning off the p-channel type MOS transistors M9 and M10 at the time of writing the initial data in this way, useless current is prevented from flowing through the complementary data lines d and d *.

In the case of this embodiment, all word lines in the memory cell array are driven to a high level in the initial data write cycle. At this time, externally applied initial data is written in the memory cell via the corresponding complementary data lines d and d *. Data line d
Is high level, initial data "1" is written in the memory cell. Even with such a configuration, the initial data can be collectively written into the plurality of memory cells MS, and therefore the same effect as that of the above-described embodiment can be obtained.

In this embodiment, the cell power supply voltage VC1,
Although not particularly limited, the level control of the load control voltage VC2 and the simultaneous drive control of all word lines can be performed by the control unit 7 (see FIG. 1).

FIG. 9 representatively shows one of the plurality of memory cells MS included in the memory cell array 6 in another embodiment.

In FIGS. 2 and 4, an n-channel type MOS is used.
N-channel type M is used for each of the transistors M3 and M4.
Although the initial data is written by connecting the OS transistors M5 and M6 in parallel, as shown in FIG. 9, the p-channel MOS transistor M7 which is a load of the n-channel MOS transistors M3 and M4 is used. , M8 are p-channel type MOS
Even if the transistors M11 and M12 are connected in parallel, the initial data can be written. In that case, although not particularly limited, the gate electrode of the p-channel MOS transistor M11 has a contact C.
It is connected to the initial data write line 27 by T3,
The gate electrode of the p-channel MOS transistor M12 is coupled to the cell power supply voltage (VC1) line 28 by the contact CT4. Here, the initial data write line 27 is supplied with an inverted version of the initial data write signal IDW in the above embodiment (initial data write signal IDW *). Even with this configuration, by asserting the initial data write signal IDW * at a low level, it is possible to write the initial data to the memory cell MS, so that the same effect as the above embodiment can be obtained. .

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes.

For example, although the MOS transistor is applied in the above embodiment, a bipolar transistor may be applied. Further, the initial data write signal IDW may be supplied from outside the SRAM.

In the above description, the case where the invention made by the present inventor is applied to a workstation which is a field of application which is the background of the invention has been mainly described, but the present invention is not limited to this, and image data is not limited thereto. It can be widely applied to various control systems and display systems that require high-speed loading of initial environment data including.

The present invention can be applied on condition that it includes at least a plurality of memory cells.

[0044]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by providing the initial data writing means and collectively writing the initial data to the plurality of memory cells, the initial data writing time can be shortened.

[Brief description of drawings]

FIG. 1 is an overall configuration block diagram of an SRAM which is an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of a memory cell portion in the SRAM.

FIG. 3 is an operation timing chart of a main part of the SRAM.

FIG. 4 is a detailed circuit diagram of a memory cell portion in an SRAM which is another embodiment of the present invention.

5 is an operation timing of a main part in the circuit shown in FIG.

FIG. 6 is a detailed circuit diagram of a memory cell portion in an SRAM which is another embodiment of the present invention.

FIG. 7 is a detailed circuit diagram of a memory cell portion in an SRAM which is another embodiment of the present invention.

8 is an operation timing of a main part in the circuit shown in FIG.

FIG. 9 is a detailed circuit diagram of a memory cell portion in an SRAM which is another embodiment of the present invention.

[Explanation of symbols]

 1-0 to 1-n address buffer 2 CS * buffer 3 WE * buffer 4 X decoder 5 word driver 6 memory cell array 7 control unit 8 Y decoder 9 Y selection switch circuit 10 data input / output circuit 12 RS * buffer 13 cell power supply unit 14 Delay section

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ryo Saeki 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Division

Claims (3)

[Claims] 1. A semiconductor memory device including a plurality of static memory cells, wherein the plurality of memory cells include initial data writing means for collectively writing initial data. Storage device. 2. The initial data writing means is for writing the initial data in a state where an initial data writing element coupled to the memory cell and a word line coupled to the memory cell are at a non-selection level. 2. The semiconductor memory device according to claim 1, further comprising control means for controlling an element to determine a logic state of said memory cell. 3. The memory cell, wherein the control means temporarily interrupts power supply to the memory cell immediately before controlling the initial data write element to determine the logic state of the memory cell. 3. The semiconductor memory device according to claim 1, further comprising a cell power supply unit for erasing the held data of the cell.