JP2006191122A - Nonvolatile storage device and semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive nonvolatile memory which will not be affected by gate oxide film thickness, without ever changing the manufacturing processes of ordinary CMOS processes. <P>SOLUTION: In a source of an MOS transistor or in a longitudinal bipolar transistor constituted of a well and a substrate or a deep well, a forward bias is applied using the well as a base, minority carriers, injected from the substrate or from the deep well, are accelerated to be made into hot carriers, then are injected and trapped into a side spacer in the vicinity of a source that becomes a collector, to conduct writing. Since the insulating film side spacer of a transistor is used as a charge accumulating region so that retention performance or the like does not depend on the gate oxide film thickness, even in a microfabricated CMOS transistor process of 100 nm or smaller, the transistor can be manufactured without ever changing the manufacturing steps. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electrically erasable and writable nonvolatile memory device and a semiconductor integrated circuit device including the same.

  As a nonvolatile storage device capable of electrically erasing data to be stored in batches in a predetermined unit and electrically writing data, flash EEPROM (Electrically Erasable and Programmable Read Only Memory, hereinafter referred to as flash memory) Is provided). In flash memory, memory cells are composed of electrically erasable and writable nonvolatile memory elements. Data and programs once written in the memory cells are erased, and new data and programs are rewritten in the memory cells. (Programming) is possible.

  Therefore, if this flash memory or a macro computer with a built-in flash memory is incorporated into an application system and data changes, program bug corrections, or program updates are required, the data stored in the flash memory Since the application program can be changed on the application system, the development period of the application system can be shortened, and the program development of the application system can be flexible.

  On the other hand, in recent years, the application fields of IC (Integrated Circuits) cards are expanding dramatically, and authentication methods called radio tags or RFID (Radio Frequency Identification) are used in place of conventional barcode reading methods. I'm starting. In an RFID system, a high frequency of about 10 MHz to 3 GHz transmitted from a reader device is received by an RFID chip existing within a range of several mm to 1 m, and a DC voltage is received from the high frequency received by an antenna provided in the chip. To generate and operate the internal circuit. The RFID chip stores authentication data in a non-volatile memory. This data is modulated into an RF signal, transmitted, and received by the reader device to authenticate the RFID chip. A nonvolatile memory mounted on an RFID chip has two major requirements. The first is ultra-low cost, which is inevitable because the market price of RFID chips is 50 yen or less. The second is to operate with low voltage and low power consumption. This requirement is because the RFID chip receives high frequency and the power that can be generated inside the chip is extremely small. In addition to the non-volatile memory, it is necessary to simultaneously operate a logic circuit, an oscillation circuit, etc. Because there is.

  After completing the present invention, the present inventors investigated known documents from the following viewpoints.

  The viewpoint of the investigation is a nonvolatile memory transistor that can be manufactured without adding a new process to the manufacturing process of the CMOS transistor, and is a viewpoint that does not have a special floating gate for storing information.

As a result, Patent Literatures 1 to 3 and Non-Patent Literature 1 were discovered.
US Pat. No. 5,408,115 US Pat. No. 5,969,383 JP 2001-156188 A Fukuda et al., “New Nonvolatile Memory With Charge-Trapping Sidewall”, IEEE ElectronDevice Letters, Vol.24, No.8, July 2003, pp490-492

  As a first problem, the memory cell structure is complicated in a vertically stacked memory cell of a floating gate and a control gate, that is, a stacked gate type memory cell, which has been generally used in NOR flash memory products. It has been clarified by the present inventors that there is a problem that the manufacturing cost is increased due to the fact that In particular, in an RFID chip whose market is rapidly expanding in recent years, adopting a stacked gate type memory cell as a nonvolatile memory leads to an increase in manufacturing cost. According to the study of the present inventor, this is considered to be caused by an increase in the following photomask and manufacturing process. That is, since the tunnel oxide film of the flash memory is thicker than the gate oxide film of the logic circuit transistor or the DRAM cell transistor, the mask for forming the tunnel oxide film, the polysilicon film for the floating gate of the flash memory, Addition / processing mask, mask for processing word line of flash memory, mask for impurity implantation for forming drain region of flash memory, and low-concentration N type source / drain of high breakdown voltage transistor constituting write / erase circuit An impurity implantation mask for forming the region and the low-concentration P-type source / drain region is required, and the number of masks to be added is at least six. For this reason, it is difficult in terms of cost to provide an RFID chip equipped with a nonvolatile memory using stacked gate type memory cells. In order to solve this problem, a non-volatile memory transistor that can be manufactured without adding a new process to the CMOS transistor manufacturing process may be employed, and a structure that does not have a special floating gate for storing information. do it.

  According to the results of investigation and examination of the prior art by the present inventors, the following points have been clarified. First, U.S. Pat. No. 5,408,115 and U.S. Pat. No. 5,969,383 disclose splitting using side spacers, as shown in FIG. There is disclosed a memory cell system in which a gate is provided, a side spacer is composed of an oxide film / silicon nitride film / oxide film (Oxide Nitride Oxide, hereinafter referred to as ONO), and charges are accumulated in the ONO film. In this conventional first memory cell, as shown in FIG. 22, a select gate 143 is arranged via a gate oxide film 142 on the surface of the substrate 141, and a lower oxide film 145 and silicon nitride are formed around the select gate 143. After the film 146 and the upper oxide film 147 are stacked, a side spacer-shaped control gate 148 is disposed. Since the source 144 of the conventional first memory cell is formed immediately after the processing of the select gate 143 and the drain 149 is formed after the processing of the control gate 148, only the control gate 148 on the drain 149 side is used as the gate electrode. Function.

  In this conventional write operation to the first memory cell, 5V is applied to the drain 149, 1V is applied to the select gate 143, and 10V is applied to the control gate 148 to turn on the channel, and the electrons 150 traveling from the source 144 are selected. Accelerating in a strong horizontal electric field generated in the channel region below the boundary between the gate 143 and the control gate 148 to form hot electrons, penetrating the lower oxide film 145 and injecting it into the silicon nitride film 146 for trapping. Is done. This operation is generally called a source-side injection (SSI) method because the hot electron injection position is not near the drain. The threshold voltage measured from the control gate 148 is increased by the electrons 151 trapped in the silicon nitride film 146 to obtain a written state.

  In the first conventional memory cell, it is necessary to add a manufacturing process for forming a side spacer having an ONO structure and a control gate 148, and a circuit for controlling an operating voltage 10V necessary for writing. Therefore, there is a second problem that a large process is required to be added to a normal CMOS transistor manufacturing process. As a result, an increase in manufacturing cost is inevitable.

  In addition, the conventional electrically writable second nonvolatile memory cell disclosed in Japanese Patent Application Laid-Open No. 2001-156188 has a gate oxide film 162 on the surface of the substrate 161 as shown in a cross-sectional structure in FIG. The gate 163 is disposed through the gate electrode 163. After the lower oxide film 164, the silicon nitride film 165, and the upper oxide film 166 are stacked on the periphery of the gate 163, the side spacer-shaped side gate 167 and the low concentration source / drain 168 are formed. , The drain 170 and the source 171 are arranged, the gate 163 and the side gate 167 are connected by the salicide film 172, and the salicide film 172 is also formed on the source 171 and the drain 170 outside the oxide film side spacer 169. Has been.

  In the conventional second memory cell, an appropriate voltage is applied to the gate 163 and the drain 170 to turn on the transistor, and hot electrons 174 generated near the drain 170 are injected into the silicon nitride film 165. Write by trapping. By performing a write operation with the source and drain switched, hot electrons 173 can be injected and trapped into the silicon nitride film 165 on the source 171 side, so that 2-bit information can be stored in one cell.

  Also in the conventional second memory cell, it is necessary to change the manufacturing process of a normal CMOS transistor in order to form the side spacer and the side gate 167 having the ONO structure. As a result, an increase in manufacturing cost is inevitable.

  Furthermore, Fukuda et al., “New Nonvolatile Memory With Charge-Trapping Sidewall”, IEEE Electron Device Letters, Vol.24, No.8, July 2003, pp490-492 In the nonvolatile memory cell, a gate 183 having a length of 0.4 μm is arranged on the surface of a P-type substrate 181 with a gate oxide film 182 having a thickness of 7.6 nm as shown in a cross-sectional structure in FIG. A lower oxide film 184 having a film thickness of 4.5 nm is formed on the periphery of the silicon oxide film, and then a silicon nitride film 185 having a film thickness of 20 nm and an upper oxide film 186 having a film thickness of 50 nm are formed in a side spacer shape. A source 187 and a drain 188 are disposed on the substrate surface immediately below 185.

  In writing to the conventional third memory cell, a channel hot electron 189 generated in the vicinity of the drain 188 is applied by applying a programming voltage of 4.3 V to the gate 183 and the drain 188 for a programming time of 1 ms, Implanting into the silicon nitride film 185 is performed. The read operation is performed by applying a positive voltage of 1.2 V to the source 187 side and determining the threshold voltage of the memory cell. Under the above write conditions, a change in threshold voltage of about 1V is obtained.

  In the conventional third memory cell, the gates corresponding to the control gate 148 and the side gate 167, which are necessary for the conventional first and second memory cells, are unnecessary. However, in order to form an electric field distribution in the direction in which the channel hot electrons 189 are injected into the silicon nitride film 185, the lower oxide film 184 is made thinner than the gate oxide film 182 to increase the fringe electric field strength. There is a need. Further, the fringe electric field strength is very sensitively influenced by the junction position of the drain 188 immediately below the silicon nitride film 185 having a width of 20 nm. Accordingly, in order to obtain stable and uniform writing characteristics, the ion implantation amount for forming the drain 188 and the subsequent formation conditions such as heat treatment are optimized, and the length of the side spacer-like upper oxide film 186 is precise. Control is necessary. Therefore, the manufacturing process peculiar to the above-mentioned conventional third memory cell is unlikely to match the manufacturing process of the existing CMOS transistor as it is, and it is necessary to change the manufacturing conditions. As a result, the performance of the existing CMOS transistor is changed. Reaches a third problem of degradation or fluctuations.

  Accordingly, the object of the present invention is to provide a flip-flop memory cell structure capable of performing a highly reliable read operation without using any floating gate without changing the normal CMOS transistor manufacturing process, that is, inexpensive and practical. It is an object of the present invention to provide a non-volatile memory device that can withstand the above.

  Another object of the present invention is to provide a semiconductor integrated circuit device equipped with an inexpensive nonvolatile memory device without adding a completely new process to a normal logic circuit process, analog circuit process, or general-purpose DRAM process. It is in.

  Another object of the present invention is to provide a semiconductor integrated circuit device using a nonvolatile memory cell formed without changing the manufacturing process of a normal CMOS transistor as a memory module, an analog circuit relief circuit, or a trimming circuit. It is to provide.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

[1] A first aspect is to form a flip-flop having a pair of series circuits of a first conductivity type load transistor and a second conductivity type memory transistor and connecting them in the form of a static latch. Is a MOS transistor formed by a normal CMOS process.

[2] A second aspect is that the nonvolatile memory device, a write control circuit for writing data to the nonvolatile memory device, data to be written to the nonvolatile memory device, and reading from the nonvolatile memory device The present invention intends to provide a semiconductor integrated circuit device provided with a data latch circuit for holding the read data.

[3] A third aspect considers an RFID chip authentication information storage circuit and a relief information storage circuit as applications of the semiconductor integrated circuit device. At this time, the semiconductor device includes a repair target circuit and a repair circuit that replaces the repair target circuit on a semiconductor substrate, and the semiconductor integrated circuit device specifies a repair circuit to be replaced by the repair circuit. Used as an information storage circuit.
The circuit to be rescued may be a memory cell array with a built-in RAM.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  [1] The characteristics of a nonvolatile element obtained by making an offset structure on only one side of a transistor formed by a normal CMOS process are poor in stability and reproducibility and are likely to cause malfunction. According to this, the operational stability is drastically improved by the flip-flop operation / structure of four transistors.

  [2] By enclosing the second conductivity type well in which the nonvolatile element is formed with the first conductivity type deep well (bottom well), the memory transistor is electrically isolated from the semiconductor substrate, and the nonvolatile memory It becomes possible to apply a potential to the second conductivity type well in the write / erase operation of the element, and the operation characteristics are improved.

  [3] By making the offset structure only on one side, the performance of the transistor can be improved, and for example, the reading performance can be improved.

  FIG. 1 shows an example of a cross-sectional structure of a memory cell for explaining the best mode for implementing a nonvolatile memory included in a semiconductor device according to the present invention. In the figure, an element isolation 2, a deep N-type well 3, and a P-type well 4 are disposed in a surface region of a P-type silicon substrate 1, and a gate insulating film 5, a gate 6, a low concentration are formed in the surface region of the P-type well 4. A source / drain 7, a side spacer 8, and a source / drain 9 are formed, and an N-type diffusion layer 10 for connection to the deep n-type well 3 and a connection to the P-type well 4 are formed. A P-type diffusion layer 11 is provided.

  In FIG. 1, writing to the nonvolatile memory included in the semiconductor device according to the present invention includes writing a source voltage (VS) below the junction breakdown voltage to the source 9, a forward well voltage (VP) to the P-type well 4, and This is performed by applying a ground potential (VDN = 0 V) to the deep N-type well 3. According to the above voltage condition, when electrons 12 as minority carriers are injected from the deep N-type well 3 into the P-type well 4, and the source voltage (VS) of the source 9 acting as a collector is sufficiently high. The injected electrons 12 become hot electrons, are accelerated in the P-type well 4, and travel toward the source 9. A part of the hot electrons 12 is also injected into the side spacers 8 and trapped, and the trapped electrons 13 are modulated by the lower concentration source / drain 7 as a result of which the resistance is increased. For example, VD = 1 When reading is performed by applying .2 V, the writing state is confirmed as a decrease in drain current. In the write operation, if a gate voltage (VG) equal to or lower than the gate breakdown voltage is applied to the gate 6, the hot electrons 12 are also accelerated in the direction of the gate 6, and the side spacer 8 and the gate insulation A larger amount is injected and trapped in the film 5.

  FIG. 2 shows an example of a nonvolatile memory cell circuit included in the semiconductor device according to the present invention. In the figure, two P-channel transistors (MPL, MPR) which are load transistors and two N-channel transistors (MNL, MNR) constitute a flip-flop, and the N-channel transistors (MNL, MNR). ) Is a storage transistor having the structure shown in FIG. 1, and the P-type well (PW) in which each storage transistor is arranged is electrically isolated, and each P-type well is connected to the P-type well lines VPL and VPR. It is connected. The two P-type wells (PW) are formed in a common deep N-type well and connected to a deep N-type well line VDN. The sources of the storage transistors are both connected to the common source line (VS), and the sources of the two P-channel transistors (MPL and MPR) are both connected to the power supply line (VCC).

  FIG. 3 shows an outline of a planar structure of the nonvolatile memory cell circuit included in the semiconductor device according to the present invention shown in FIG. In the figure, a deep N-type well 24, a P-type well 26, and an N-type well 25 are disposed in a desired region, an active region 22 for defining a P-channel transistor, and an activity for defining an N-channel transistor. An active region 23 for connection to the region 21 and the P-type well 26 is provided, the right gate 27 is a right P-channel transistor and an N-channel transistor, and the left gate 28 is a left P-channel transistor and an N-channel transistor. A channel type transistor is formed. The active region 21 for defining the N channel type transistor has an N type source / drain 31, the active region 22 for defining the P channel type transistor has a P type source / drain 33, and the P type well 26. A P-type diffusion layer 32 is formed in the active region 23 for connection. The right gate 27 is connected to a left node line (VL) 37 made of a first metal wiring through a contact hole 35, and the left node line (VL) 37 is a drain of the left P-channel transistor and the N-channel transistor. The left gate 28 is connected to the right node line (VR) 36 made of the first metal wiring through the contact hole 35, and the right node line (VR) 36 is connected to the right P line through the contact hole 35. A flip-flop is configured by connecting the drains of the channel type transistor and the N channel type transistor via the contact hole 35. The sources of the two P-channel transistors are connected to a power supply line (VCC) 38 made of a first metal wiring through a contact hole 35, and the sources of the two N-channel transistors are first through a contact hole 35. Connected to the metal wiring 39, the two first metal wirings 39 are connected to a common source line (VS) composed of the second metal wiring 42 through a through hole 41. The two P-type diffusion layers 32 are connected to the left P-type well line (VPL) and the right P-type well line (VPR) made of the first metal wiring 40 through contact holes 35, and are controlled independently. Is done.

  FIG. 4 shows operating voltage conditions of the nonvolatile memory cell of the present invention shown in FIGS. First, when performing a write operation (Program) to the left N-channel transistor, the deep N-type well line (VDN) is grounded, and the N-type well line (VN) and the power supply line (VCC) are both powered. After fixing the voltage (Vcc) to the common source line (VS), a positive voltage equal to or lower than the junction breakdown voltage <BVj, for example, 5V is applied, and only to the left P-type well line (VPL) for writing, in the order of 1V. A bias voltage (> Vbe) is applied for the write time period, and substrate hot electrons are injected into the side spacer near the source of the left N-channel transistor to increase its threshold voltage by 0.4 to 0.6V. . The writing time is 10 ms to 100 ms.

  In the erase operation (Erase), after fixing the power supply line (VCC) to the floating potential and the N-type well line (VN) to the ground potential, the left and right P-type well lines (VPL, VPR), the common source line (VS), Further, a positive voltage lower than the breakdown voltage (BVox) of the gate insulating film is applied to the deep N-type well line (VDN), and electrons trapped in the side spacer are tunneled into the P-type well.

  In the read operation (Read), a power supply voltage (Vcc) is gradually applied to the power supply line (VCC) and the N-type well (VN), and the left and right gates are electrostatically coupled to the N-type well 25. In the process of increasing the potentials 27 and 28, the right N-channel transistor having a low threshold voltage starts to turn on, while the left N-channel transistor having a high threshold voltage remains turned off, and the power supply voltage is further reduced. When rising, the right N-channel transistor is completely turned on, the right node (VR) is set to the Low state, the left N-channel transistor is turned off, and the left node (VL) is fixed to the High state. The left P-channel transistor is turned on, the right P-channel transistor is turned off, and the latch is fixed. That. The potential states of the left and right node lines (VL, VR) are output via the inverter (INV) (VOL, VOR) and read out.

  In order to stably perform the read operation of the nonvolatile memory cell of the present invention, the gate capacitance Cgp of the P-channel transistor is defined as follows. In the process of gradually applying the power supply voltage (Vcc) to the power supply line (VCC) and the N-type well line (VN), the gate potential Vg changes as Vg = Cgp / CtVcc. Here, Ct is the total capacitance between the left and right node lines (VL, VR) and the ground potential, and Ct = Cgp + Cgn + Cii. Cgn is the gate capacitance of the N-channel transistor, and Cii is the input gate capacitance of the inverter (INV). When the N-channel transistor constituting the inverter (INV) has the same size as that of the memory cell, the channel width of the P-channel transistor constituting the inverter (INV) is usually twice that of the N-channel transistor. Since it is designed, Cii = 3Cgn. Therefore, Ct = Cgp + 4Cgn and Vg = Cgp / (Cgp + 4Cgn) Vcc. Assuming that the threshold voltage in the erase state of the N-channel transistor constituting the memory cell is Vthi, Vg> Vthi is a necessary condition for fixing the latch in the read operation. This is because Vthi <Cgp / It can be written as (Cgp + 4Cgn) Vcc. Further, in order to fix the latch when the power supply voltage rises to Vcc / 2, Vthi <Cgp / (Cgp + 4Cgn) Vcc / 2, and the stable operation condition is Cgp / Cgn> 8Vthi / (Vcc-2Vthi). It becomes. For example, when Vthi = 0.4V and power supply voltage Vcc = 1.8V, Cgp / Cgn> 3.2, that is, the channel width of the P-channel transistor of the memory cell is 3.2 times or more that of the N-channel transistor. Must be designed.

<< Source line split type non-volatile memory >>
FIG. 5 shows a cross-sectional structure of a source line division type nonvolatile memory cell included in the semiconductor device according to the present invention. In the figure, in the surface region of the P-type silicon substrate 1 having a resistivity of 10 Ωcm, the depth is 2 μm, the deep N-type well 3 having an average phosphorus concentration of 1 × 10 ¹⁷ cm ⁻³ , and the depth inside the deep N-type well 3. A P-type well 4 having an average boron concentration of 2 × 10 ¹⁷ cm ⁻³ of 0.8 μm and an N-channel transistor of a memory cell separated by an element isolation 2 having a depth of 250 nm is a gate oxide film having a thickness of 5 nm. 5. Gate 6 made of polysilicon film having a thickness of 200 nm and a phosphorus concentration of 2 × 10 ²⁰ cm ⁻³ , a length of 0.3 μm, a low concentration source / drain 7 having an average arsenic concentration of 5 × 10 ¹⁸ cm ⁻³ , and an average arsenic The deep N-type well includes a source / drain 9 having a concentration of 1 × 10 ²⁰ cm ⁻³ , an oxide film 50 having a thickness of 10 nm, a nitride film 51 having a thickness of 20 nm, and an oxide film side spacer 8 having a thickness of 30 nm. Connect to 3 N-type diffusion layer 10 of the average order of arsenic concentration 1 × 10 ²⁰ cm ^-3, and P-type diffusion layer 11 having an average boron concentration of 1 × 10 ²⁰ cm ^-3 for connection to the P-type well 4 is arranged Yes.

  FIG. 6 shows an equivalent circuit of the source line division type nonvolatile memory cell included in the semiconductor device according to the present invention shown in FIG. In the figure, two P-channel transistors (MPL, MPR) which are load transistors and two N-channel transistors (MNL, MNR) constitute a flip-flop, and the N-channel transistors (MNL, MNR). ) Are storage transistors having the structure shown in FIG. 5, each storage transistor being disposed in a P-type well (PW) existing in a common deep N-type well, each source being a source line VSL, and Connected to VSR. The deep N-type well is connected to a deep N-type well line VDN, and the sources of the two P-channel transistors (MPL and MPR) are both connected to a power supply line (VCC).

  FIG. 7 shows an outline of a planar structure of a source line division type nonvolatile memory cell circuit included in the semiconductor device according to the present invention shown in FIG. In the figure, a deep N-type well 24, a P-type well 26, and an N-type well 25 are disposed in a desired region, an active region 22 for defining a P-channel transistor, and an activity for defining an N-channel transistor. An active region 23 for connection to the region 21 and the P-type well 26 is provided, the right gate 27 is a right P-channel transistor and an N-channel transistor, and the left gate 28 is a left P-channel transistor and an N-channel transistor. A channel type transistor is formed. The active region 21 for defining the N channel type transistor has an N type source / drain 31, the active region 22 for defining the P channel type transistor has a P type source / drain 33, and the P type well 26. A P-type diffusion layer 32 is formed in the active region 23 for connection. The right gate 27 is connected to a left node line (VL) including a first metal wiring 37 through a contact hole 35, and the left node line (VL) is connected to the drains of the left P-channel transistor and the N-channel transistor. Connected via a contact hole 35, the left gate 28 is connected via a contact hole 35 to a right node line (VR) comprising a first metal wiring 36, and the right node line (VR) is a right P-channel type. A flip-flop is formed by connecting the transistor and the drain of the N-channel transistor via a contact hole 35. The sources of the two P-channel transistors are connected to a power supply line (VCC) including a first metal wiring 38 through a contact hole 35, and the sources of the two N-channel transistors are first through a contact hole 35. The P-type diffusion layer 32 is connected to the common P-type well line VP consisting of the first metal wiring 54 through the contact hole 35, connected to the source lines VSR and VSL consisting of the metal wirings 52 and 53. .

  FIG. 8 shows the operating voltage conditions of the source line division type nonvolatile memory cell of the present invention shown in FIGS. First, when performing a write operation (Program) to the left N-channel transistor, the deep N-type well (VDN) is connected to the ground potential, and the N-type well (VN) and the power supply line (VCC) are both supplied to the power supply voltage ( Vcc), a positive voltage <BVj, for example, 5 V, which is equal to or lower than the junction breakdown voltage, is applied only to the left source line (VCL) of the left N-channel transistor to be written, and then the common P-type well line (VP) A forward bias voltage (> Vbe), such as 1V, is applied to inject substrate hot electrons into the side spacer near the source of the left N-channel transistor. The writing time is 10 ms to 100 ms. The initial threshold voltage of the N-channel transistor was 0.4V, but the threshold voltage after writing was 0.7 to 0.9V.

  In the erase operation (Erase), after fixing the power supply line (VCC) to the floating potential and the N-type well line (VN) to the ground potential, the common P-type well line (VP), the left and right source lines (VSL, VSR), By applying a positive voltage, for example, 6 V, lower than the breakdown voltage (BVox) of the gate insulating film to the deep N-type well line (VDN), the electrons trapped in the side spacer are tunneled into the P-type well. Do.

  In the read operation (Read), the power supply voltage (Vcc) is applied to the power supply line (VCC) and the N-type well line (VN) to fix the latch, and the potential states (VL, VR) of the left and right nodes are changed. Then, the signal is output through the inverter (INV) (VOL, VOR) and read out.

<< P-channel nonvolatile memory >>
FIG. 9 shows a cross-sectional structure of a P-channel nonvolatile memory cell included in the semiconductor device according to the present invention. In the figure, an N-type well 63 having a depth of 1 μm and an average phosphorus concentration of 1 × 10 ¹⁷ cm ⁻³ , a depth of 1 μm and an average boron concentration of 2 × 10 ¹⁷ cm is formed on the surface region of a P-type silicon substrate 61 having a resistivity of 10 Ωcm. ^-3 P-type well 64 is disposed, and the P-channel transistor of the memory cell separated by the element isolation 62 having a depth of 250 nm includes a gate oxide film 5 having a thickness of 5 nm, a boron concentration of 2 × 10 ²⁰ with a thickness of 200 nm. a gate 66 made of a polysilicon film of cm ⁻³ and having a length of 0.3 μm, a drain extension 67 having an average boron concentration of 5 × 10 ¹⁸ cm ⁻³ , a source / drain 69 having an average boron concentration of 1 × 10 ²⁰ cm ⁻³ , It is composed of an oxide film side spacers 68 width 80 nm, N-type diffusion layer 71 of the average arsenic concentration for connection to the N-type well 63 1 × 10 ²⁰ cm ^-3, said P-type well 64 P-type diffusion layer 70 having an average boron concentration of 1 × 10 ²⁰ cm ^-3 for connection are disposed.

  FIG. 10 shows an equivalent circuit of a P-channel nonvolatile memory cell included in the semiconductor device according to the present invention shown in FIG. In the figure, two P-channel transistors (MPL, MPR) as load transistors and two N-channel transistors (MNL, MNR) constitute a flip-flop, and the P-channel transistors (MPL, MPR). ) Is a storage transistor having the structure shown in FIG. 9, and each storage transistor is arranged in a separate N-type well NW, and each N-type well is connected to the left and right N-type well lines VNL and VNR. Yes. The sources of the two N-channel transistors (MNL, MNR) are both connected to a common source line (VS).

  FIG. 11 shows an outline of a planar structure of a P-channel type nonvolatile memory cell circuit included in the semiconductor device according to the present invention shown in FIG. In the figure, a P-type well 84 and an N-type well 85 are arranged in a desired region, an active region 82 for defining a P-channel transistor, an active region 81 for defining an N-channel transistor, and the N-type An active region 83 for connection to the well 85 is provided, and a P-type drain 89, a P-type source 90, an N-type drain 87, an N-type source 88, and an N-type diffusion layer 91 are formed in each region. Yes. The left and right gates 27 constitute two inverters composed of left and right P-channel transistors and N-channel transistors, and the contact hole 92 and the first metal wires 95 and 96 constitute a flip-flop. The P-type sources of the two P-channel transistors are connected to a power supply line (VCC) made of the first metal wiring 93 through a contact hole 92, and the two N-type wells 85 are connected to the first through the contact hole 92. Connected to the two N-type well lines VNL and VNR made of the metal wiring 94, and the N-type source 88 of the two N-channel transistors are connected to the common source line VS made of the first metal wiring 97 through the contact hole 92. ing.

  FIG. 12 shows the operating voltage conditions of the P-channel type nonvolatile memory cell of the present invention shown in FIGS. In order to perform a write operation (Program) to the left P-channel transistor, the P-type well (Vsub) and the common source line (VS) are fixed to the ground potential, and the P-type transistor is connected to the power line (VCC). After applying a negative voltage equal to or lower than the junction breakdown voltage (BVj) of the source, a forward bias voltage (<-Vbe) such as -1 V is applied only to the left N-type well line (VNL) of the left P-channel transistor to be written. A substrate hot hole is injected into a side spacer in the vicinity of the source of the left P-channel transistor by applying a period of writing time. The writing time is 50 ms to 100 ms. The initial threshold voltage of the P-channel transistor was −0.5V, but the threshold voltage after writing was −0.7 to −0.9V.

  In the read operation (Read), the power supply voltage (Vcc) is applied to the power supply line (VCC) and the N-type well line (VN) to fix the latch, and the potential states (VL, VR) of the left and right node lines Are output via an inverter (INV) (VOL, VOR) and read out.

<< Source line split P-channel nonvolatile memory >>
FIG. 13 shows an equivalent circuit of a source line division P-channel nonvolatile memory cell included in the semiconductor device according to the present invention. In the figure, two P-channel transistors (MPL, MPR) as load transistors and two N-channel transistors (MNL, MNR) constitute a flip-flop, and the P-channel transistors (MPL, MPR). ) Is a storage transistor having the structure shown in FIG. 9. Each storage transistor is arranged in a common N-type well (NW), and each P-type source is connected to the left and right power supply lines VCCL and VCCR. ing. The sources of the two N-channel transistors (MNL, MNR) are both connected to a common source line (VS).

  FIG. 14 shows an outline of a planar structure of a source line divided P-channel type nonvolatile memory cell circuit included in the semiconductor device according to the present invention shown in FIG. In the figure, a P-type well 84 and an N-type well 85 are arranged in a desired region, an active region 82 for defining a P-channel transistor, an active region 81 for defining an N-channel transistor, and the N-type An active region 83 for connection to the well 85 is provided, and a P-type drain 89, a P-type source 90, an N-type drain 87, an N-type source 88, and an N-type diffusion layer 91 are formed in each region. Yes. The left and right gates 27 constitute two inverters composed of left and right P-channel transistors and N-channel transistors, and the contact hole 92 and the first metal wires 95 and 96 constitute a flip-flop. The P-type sources of the two P-channel transistors are connected to the two power supply lines VCCL and VCCR including the first metal wires 98 and 99 through the contact holes 92, and the two N-type wells 85 are connected to the contact holes 92. The N-type source 88 of the two N-channel transistors is connected to the common source line VS consisting of the first metal wiring 97 through the contact hole 92. Has been.

  FIG. 15 shows operating voltage conditions of the source line division P-channel type nonvolatile memory cell of the present invention shown in FIGS. In order to perform a write operation (Program) to the left P-channel transistor, the P-type well line (Vsub) and the common source line (VS) are fixed to the ground potential, and the left P-channel transistor for writing is performed. After applying a negative voltage equal to or lower than the junction breakdown voltage (BVj) only to the left power line (VCCL), a forward bias voltage (<-Vbe) such as -1 V is written to the common N-type well line (VN). The substrate hot hole is injected into the side spacer near the source of the left P-channel transistor. The writing time is 100 ms to 200 ms. The initial threshold voltage of the P-channel transistor was −0.5V, but the threshold voltage after writing was −0.7 to −0.9V.

  In the read operation (Read), the power supply voltage (Vcc) is applied to the power supply line (VCC) and the N-type well line (VN) to fix the latch, and the potential states (VL, VR) of the left and right node lines Are output via an inverter (INV) (VOL, VOR) and read out.

<Source offset nonvolatile memory>
FIG. 16 shows a cross-sectional structure of a source offset type nonvolatile memory cell included in a semiconductor device according to the present invention. In the figure, a deep N-type well 103 having a depth of 2 μm and an average phosphorus concentration of 1 × 10 ¹⁷ cm ⁻³ is formed in a surface region of a P-type silicon substrate 101 having a resistivity of 10 Ωcm, and a depth of 0 is provided inside the deep N-type well 103. An N-channel transistor of a memory cell in which a P-type well 104 having an average boron concentration of 2 × 10 ¹⁷ cm ⁻³ is disposed and is separated by an element isolation 102 having a depth of 250 nm is a gate oxide film 105 having a thickness of 5 nm. A gate 106 made of a polysilicon film having a thickness of 200 nm and a phosphorus concentration of 2 × 10 ²⁰ cm ⁻³ , a drain extension 107 having an average arsenic concentration of 5 × 10 ¹⁸ cm ⁻³ , and an average arsenic concentration of 1 × 10 ²⁰ drain 109 cm ^-3, is composed of an oxide film side spacer 108 having a thickness of 50 nm, average砒for connecting to said deep N-type well 103 N-type diffusion layer 110 at a concentration 1 × 10 ²⁰ cm ^-3, P-type diffusion layer 111 of the average boron concentration for connection to the P-type well 104 1 × 10 ²⁰ cm ^-3 is disposed.

  In the N-channel transistor that constitutes the source offset nonvolatile memory cell, no extension is formed on the source side, and the initial threshold voltage is 1.2V. In the write operation, a positive voltage equal to or lower than the junction breakdown voltage is applied to the N-type source line VS to inject an avalanche hot hole 112 generated in the depletion layer of the junction into the oxide film side spacer 108, and the threshold is set by the trap hole 113. This is done by reducing the voltage.

  FIG. 17 shows a second cross-sectional structure of a source offset type nonvolatile memory cell included in the semiconductor device according to the present invention. This figure explains the erase operation. By injecting the substrate hot electrons 114 described in FIG. 1 or FIG. 5, the trap hole 113 is neutralized and the threshold voltage is increased. Erase.

  FIG. 18 shows the operating voltage conditions of the source offset type nonvolatile memory cell of the present invention shown in FIGS. The circuit configuration of the source offset type nonvolatile memory cell is the same as that of the source line division type nonvolatile memory cell circuit shown in FIG. When writing to the left N-channel transistor (Program), the deep N-type well line (VDN) is connected to the ground potential, and the N-type well line (VN) and the power supply line (VCC) are both supplied to the power supply voltage (Vcc ), And a positive voltage <BVj, for example, 5 V, which is equal to or lower than the junction breakdown voltage is applied only to the left source line (VCL) of the left N-channel transistor to be written, and the depletion layer of the N-type source junction is applied. An avalanche hot hole generated inside is injected into the oxide film side spacer. The writing time is 300 ms to 500 ms. The initial threshold voltage of the N-channel transistor was 1.2V, but the threshold voltage after writing was 0.7 to 0.9V.

  In the erase operation (Erase), the deep N-type well line (VDN) is fixed to the ground potential, the N-type well line (VN) and the power supply line (VCC) are both fixed to the power supply voltage (Vcc), and then the left and right source lines (VSL) are fixed. , VSR) is applied with a positive voltage (<BVj) equal to or lower than the N-type source junction breakdown voltage, and a forward bias such as 1 V is applied to the common P-type well line (VP) during the erasing time, and the substrate hot electrons are left Implanted into the side spacer in the vicinity of the source of the N-channel transistor. The erase time is 50 ms to 100 ms. The threshold voltage after writing of the N-channel transistor was 0.8V, but the threshold voltage after erasing was 1.3V.

<< Source division type non-volatile memory module >>
FIG. 19 shows an outline of a circuit block of a source offset type nonvolatile memory module included in a semiconductor device according to the present invention. In this figure, the memory cell used is the source line division type non-volatile memory shown in FIGS. 5 to 7, and the flip-flop type memory cell has 64 bits (n = 64) arranged in a horizontal row. . The operation of the memory module is controlled by a state control circuit (Program, Erase, Read Status Controller), and a data latch circuit (Data Latch Circuit) for holding data to be written and read data is provided. . The data latch circuit operates at the power supply voltage Vcc, and when the write data is transferred to the memory cell, it is converted from the power supply voltage Vcc to the high voltage Vpp for writing by a level shifter. In the write and read operations, either the transfer gate signal VGP or VGR is selected by the state control circuit, and input / output to / from the data latch circuit is performed. In the write operation, the transfer gate signal VGP is selected, and the data held in the data latch circuit is supplied to the two left and right source lines (VSL, VSR) of each memory cell via the level shifter. After Vpp) or (Vpp, Vss) is applied, a forward bias voltage is applied to the common P-type well line VP, and substrate hot electrons are injected into a desired region.

  In the read operation of the source offset type nonvolatile memory module, the power supply line VCC is applied by the state control circuit to fix the latch of the memory cell, and then the transfer gate signal VGR is selected and read. Is output to the data latch circuit. After the data holding in the data latch circuit is completed, the power supply line VCC may be cut off to avoid disturbing the memory cells.

  In the erase operation of the present source offset type nonvolatile memory module, the state control circuit outputs the equalize signal VEQ of the source lines (VSL, VSR), the erase source line voltage VE, the deep N-type well line VDN, and the common Erase is performed by applying erase voltage Vpp to P-type well line VP.

<< RFID chip >>
FIG. 20 shows a circuit block of an RFID chip on which a source offset type nonvolatile memory module included in a semiconductor device according to the present invention is mounted. An antenna L arranged outside the chip is connected to the pads P1 and P2 to receive an RF signal transmitted from an external reader, and a power capacitor CT having a capacity of 120 pF and a voltage clamp are connected between the pads P1 and P2. A circuit (Voltage Clamp), a power supply modulator (Modulator), and a bridge rectifier (Bridge Rectifier) are connected to generate an internal power supply voltage (Vcc) and a high voltage (Vpp) from the output of the bridge rectifier (Vcc Detector). ), A Vpp booster circuit (Vpp Generator) is connected. In addition, the bridge rectifier uses a circuit (Mode Selector) for detecting an operation mode included in the received RF signal, a clock detection circuit (Clock Extractor), and a circuit for extracting write data to the nonvolatile memory module (EEPROM) (Data Modulator) is connected and the operation mode is sent to the controller to control the operation of the nonvolatile memory module. Writing The internal power supply voltage Vcc and the high voltage Vpp are supplied to the nonvolatile memory, and writing and reading operations are performed. A power supply stabilization capacitor CF is connected to the output of the bridge rectifier, and a control signal of a voltage regulator (Regulator) for detecting the output voltage is fed back to the voltage clamp circuit to stabilize the power supply voltage. Yes.

  This RFID chip operates at an RF frequency of 2.45 GHz, and the total power that can be generated inside the chip is about 10 mW at maximum. In the write operation, a forward bias current of 1 V and 3 mA is required for the common P-type well line VP, but there is no problem in operation.

  The source offset nonvolatile memory module of the semiconductor device according to the present invention mounted on the RFID chip has an ID number for chip authentication, an address for home delivery, and product information (price, Production date, place of production, producer, component information, etc.), necessary information of air cargo tag (flight name, owner name, boarding place, destination, etc.), etc. are written.

<< Restoring nonvolatile memory for system LSI >>
FIG. 21 schematically shows a chip plan view of a system LSI which is an example of a semiconductor device according to the present invention. The system LSI shown in the figure is not particularly limited, but a large number of external connection electrodes 120 such as bonding pads are arranged on the periphery of the semiconductor substrate, and an external input / output circuit 121 and an analog input / output circuit 122 are provided on the inside thereof. ing. The external input / output circuit 121 and the analog input / output circuit 122 use an external power supply having a relatively high level such as 3.3V as an operation power supply. The level shift circuit 123 steps down the external power supply to an internal power supply voltage such as 1.8V. Inside the level shift circuit 123, there are a static random access memory (SRAM) 124, a central processing unit (CPU) 125, a cache memory (CACH) 126, a logic circuit (Logic) 127, and a phase locked loop circuit ( PLL) 128, an analog / digital conversion circuit (ADC) 129, a digital / analog conversion circuit (DAC) 130, and a system controller (SYSC) 131. Reference numerals 132, 133, and 134 denote electrically erasable and writable nonvolatile memories (EPROMs), respectively, which have a memory capacity changed based on the nonvolatile memory cell module described in FIG.

  The SRAM 124, CPU 125, LOG 127, CACH 126, and SYSC 131 are operated using an internal power supply voltage such as 1.8 V supplied from the level shift circuit 123 as an operation power supply. However, the SRAM 304 boosts the internal power supply voltage to form a word line select level, which is used as an operation power supply such as a word driver. Nonvolatile memories (EPROM) 132, 133, and 134 operate using an internal power supply voltage in a data read operation, but a high voltage is required for an erase / write operation. The high voltage is formed by an internal booster circuit. Alternatively, it may be supplied from the outside via a predetermined external connection electrode in a predetermined operation mode such as the EPROM writer mode of the system LSI.

  The nonvolatile memory (EPROM) 132 is used for storing relief information (control information for replacing defective memory cells with redundant memory cells) in the SRAM 124, and the nonvolatile memory (EPROM) 133 is trimming data of the oscillation frequency of the analog circuit. Is used in place of the fuse, and is mounted in place of the fuse relief circuit.

  The nonvolatile memory (EPROM) 134 has a memory capacity of 256 bits and is used for storing chip ID information, chip operation mode information, and desired data.

  Since the nonvolatile memory included in the semiconductor device according to the present invention is a method in which programming / erasing is performed by injecting substrate hot carriers into an insulating film near the source of a transistor, a normal logic circuit process or a general-purpose DRAM process is used. An inexpensive semiconductor device equipped with a non-volatile memory can be provided without adding a completely new process. In addition, since the nonvolatile memory included in the semiconductor device according to the present invention does not use a floating gate for storing electric charge, it does not require a tunnel insulating film that is essential in a conventional nonvolatile memory, and even in a fine CMOS process. It can be easily formed. The non-volatile memory of the present invention is a low-cost microcomputer (1) for storing color gradation trimming data that is performed after a liquid crystal display driver (LCD) built-in microcomputer is mounted on a liquid crystal panel substrate, and for household appliances. Trimming data of the oscillation frequency of the internal oscillator (called a dollar microcomputer), trimming data of the internal resistance and circuit constant of the microcomputer equipped with the analog circuit, storage of SRAM relief information in a high performance microcomputer equipped with a large capacity SRAM, It is most suitable for non-contact IC cards, especially for storing ID information in low-cost RFID, etc., and is mounted on a semiconductor device that requires a low-cost non-volatile memory even though it has a small capacity. effective.

It is explanatory drawing which shows roughly the cross-section of the memory cell explaining the best form for implementing the non-volatile memory which the semiconductor device which concerns on this invention has. 3 is an example of a nonvolatile memory cell circuit included in a semiconductor device according to the present invention. FIG. 3 is an explanatory diagram schematically showing a planar structure of a nonvolatile memory cell circuit included in the semiconductor device according to the present invention shown in FIG. 2. FIG. 4 is an explanatory diagram illustrating operating voltage conditions of the nonvolatile memory cell of the present invention shown in FIGS. 1 to 3; It is explanatory drawing which shows roughly the cross-section of the source line division | segmentation non-volatile memory cell which the semiconductor device which concerns on this invention has. 6 is an equivalent circuit of a source line division type nonvolatile memory cell included in the semiconductor device according to the present invention shown in FIG. FIG. 6 is an explanatory diagram schematically showing a planar structure of a source line division type nonvolatile memory cell circuit included in the semiconductor device according to the present invention shown in FIG. 5; It is explanatory drawing which shows an example of the operating voltage conditions of the source line division | segmentation non-volatile memory cell of this invention shown by FIGS. FIG. 3 is an explanatory diagram schematically showing a cross-sectional structure diagram of a P-channel type nonvolatile memory cell included in a semiconductor device according to the present invention. 10 is an equivalent circuit of a P-channel type nonvolatile memory cell included in the semiconductor device according to the present invention shown in FIG. FIG. 11 is an explanatory diagram schematically showing a planar structure of a P-channel type nonvolatile memory cell circuit included in the semiconductor device according to the present invention shown in FIG. 10; FIG. 12 is an explanatory diagram showing an example of an operating voltage condition of the P-channel type nonvolatile memory cell of the present invention shown in FIGS. 9 to 11. 3 is an equivalent circuit of a source line division P-channel nonvolatile memory cell included in the semiconductor device according to the present invention. It is explanatory drawing which shows roughly the planar structure of the source line division | segmentation P channel type non-volatile memory cell circuit which the semiconductor device based on this invention shown by FIG. 13 has. FIG. 15 is an explanatory diagram showing an example of an operating voltage condition of the source line division P-channel nonvolatile memory cell of the present invention shown in FIGS. 13 and 14. It is explanatory drawing which shows roughly the cross-section of the source offset type non-volatile memory cell which the semiconductor device which concerns on this invention has. It is explanatory drawing which shows roughly the 2nd cross-sectional structure of the source offset type non-volatile memory cell which the semiconductor device concerning this invention has. FIG. 18 is an explanatory diagram showing an example of an operating voltage condition of the source offset nonvolatile memory cell of the present invention shown in FIGS. 16 and 17. It is explanatory drawing which shows schematically the circuit block of the source offset type non-volatile memory module which the semiconductor device which concerns on this invention has. It is explanatory drawing which shows schematically the circuit block of the RFID chip | tip which mounts the source offset type non-volatile memory module which the semiconductor device which concerns on this invention has. It is explanatory drawing which shows roughly the chip | tip plan view of system LSI which is an example of the semiconductor device which concerns on this invention. It is sectional drawing for demonstrating the 1st prior art. It is sectional drawing for demonstrating the 2nd prior art. It is sectional drawing for demonstrating the 3rd prior art.

Explanation of symbols

1,61,101,141,161,181-P-type silicon substrate 2,62,102-element isolation 4,26,64,84,104-P-type well 3,24,103-deep N-type well 25,63 85-N type well 5,65,105,142,162,182-gate insulating film 6,27,28,66,86,106,143,163,183-gate, select gate 7,168-low concentration source -Drain 8, 68, 108-Side spacer 9, 109-Source-Drain 10, 71, 91, 110-N type diffusion layer 11, 32, 70, 111-P type diffusion layer 12, 150, 173-electron, hot Electron 13-trap electron 21, 22, 23, 81, 82, 83-active region 31-N type source / drain 34, 69-P type source / drain 35 92-contact hole 36, 37, 38, 39, 40, 54, 93, 94, 95, 96, 97, 98, 99-first metal wiring 41-through hole 42-second metal wiring 50, 145, 164 184-lower oxide film 51,146,165,185-silicon nitride film 67,107-drain extension 72,112-hot hole 73,113-trap hole 87-N type drain 88-N type source 89-P type drain 90-P type source 120-external connection electrode 122-analog input / output circuit 123-level shift circuit 124-static random access memory SRAM
125-Central processing unit CPU
126-cache memory CACH
127-logic circuit LOG
128-phase locked loop circuit PLL
129-Analog / Digital Converter ADC
120-digital-analog converter circuit DAC
131-System Controller SYSC
132,133,134-nonvolatile memory EPROM
144,171,187-source 147,166,186-upper oxide film 148-control gate 149,170,188-drain 167-side gate 172-salicide film MPL, MPR-P channel type transistor MNL, MNR-N channel type Transistor PW-P type well VPL, VPR, VP, Vsub-P type well line VDN-Deep N type well line VNL, VNR, VN-N type well line VCC-Power supply line VSL, VSR, VS-Source line VL, VR -Node line Vcc-Power supply voltage Vpp-High voltage for programming / erasing Vss-Ground potential INV-Inverter

Claims (10)

  A non-volatile memory device in which a non-volatile memory is provided on a semiconductor substrate, wherein the non-volatile memory has a pair of series circuits of a first conductivity type load transistor and a second conductivity type memory transistor, which are statically connected. A non-volatile memory device, which is a flip-flop connected in a latch form, wherein the memory transistor is a MOS transistor formed by a normal CMOS process.   The storage transistor includes a second conductivity type well in a first conductivity type deep well, a first conductivity type source and drain in the second conductivity type well, and a gap between the source and drain. 2. The non-volatile memory device according to claim 1, further comprising: a channel, and a gate provided above the channel with a gate insulating film interposed therebetween, wherein transistors other than the memory transistor are configured outside the deep well. .   The junction with the second conductivity type well on the drain side of the memory transistor has an LDD structure having a low concentration region with a low impurity concentration, and the junction with the second conductivity type well on the source side has the LDD structure. The nonvolatile memory device according to claim 1, wherein a part of the low concentration region is not formed.   The nonvolatile memory device according to claim 1, a write control circuit for writing data to the nonvolatile memory device, data to be written to the nonvolatile memory device, and the nonvolatile memory device A semiconductor integrated circuit device comprising a data latch circuit for holding read data.   5. The repair information and a repair circuit that replaces the repair target circuit, wherein the nonvolatile memory device is a repair information storage circuit that specifies a repair target circuit to be replaced by the repair circuit. Semiconductor integrated circuit device.   6. The semiconductor integrated circuit device according to claim 5, wherein the circuit to be relieved is a memory cell array built in a RAM.   5. The semiconductor according to claim 4, further comprising an analog circuit and a constant trimming circuit that adjusts a circuit constant thereof, wherein the nonvolatile memory circuit is an information storage circuit for specifying the circuit constant of the constant trimming circuit. Integrated circuit device.   5. The semiconductor according to claim 4, further comprising: an oscillation circuit; and a frequency trimming circuit that adjusts the oscillation frequency, wherein the nonvolatile memory circuit is an information memory circuit for specifying the oscillation frequency of the frequency trimming circuit. Integrated circuit device.   5. A reference voltage generation circuit and a voltage trimming circuit for adjusting the generated reference voltage, wherein the nonvolatile storage circuit is an information storage circuit for specifying the reference voltage of the voltage trimming circuit. A semiconductor integrated circuit device according to 1.   5. The semiconductor integrated circuit device according to claim 4, further comprising a security circuit for specifying a chip, wherein the nonvolatile memory circuit is an information storage circuit for specifying a chip of the security circuit.

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