JP2008042870A - Leak current reduction circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a leak current during the stoppage of operation (during standby mode) of a logic circuit which operates intermittently, and further to sufficiently supply a driving current to the logic circuit during the operation of the logic circuit. <P>SOLUTION: In a configuration where a power switch connected between the logic circuit and a power source is controlled in accordance with the intermittent operation of the logic circuit, the power switch is configured by cascading an nMOS transistor and a pMOS transistor in this order from a high potential side between a positive power supply potential and a power supply terminal of the logic circuit. A gate potential control circuit is provided which performs control not to conduct the nMOS transistor and the pMOS transistor during operation stop of the logic circuit by bringing a gate terminal of the nMOS transistor to a ground potential and bringing a gate terminal of the pMOS transistor to the positive power supply potential, respectively, and to conduct the transistors during operation of the logic circuit by making the potential of the gate terminal of the nMOS transistor equal with or higher than the positive power supply potential and bringing the gate terminal of the pMOS transistor to the ground potential, respectively. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for reducing power consumption of a logic circuit that operates intermittently, and more particularly, to a leakage current reduction circuit that reduces the average power consumption by reducing the leakage current when the logic circuit is stopped (standby). Note that the intermittently operating logic circuit is assumed to be a high-frequency analog circuit used in, for example, a wireless tag (RFID) or a portable wireless terminal, but generally includes a logic circuit or an arithmetic circuit in an integrated circuit.

  Conventionally, MT-CMOS (Muiti-Threshold CMOS) technology is used as a method of reducing the leakage current of a CMOS circuit (logic circuit) when operation is stopped (standby) (Patent Document 1). This is a technique for reducing leakage current during standby of a logic circuit composed of low threshold voltage transistors by a power switch that is a high threshold voltage transistor.

  FIG. 16 shows a configuration of a leakage current reduction circuit using MT-CMOS technology. In the figure, a pMOS transistor 92 serving as a power switch with a high threshold voltage transistor is inserted between a logic circuit 91 composed of a low threshold voltage transistor and a power supply potential (Vdd), and a control terminal is connected to the gate terminal of the pMOS transistor 92. 1 is connected. The control terminal 1 is a terminal for controlling the gate voltage of the pMOS transistor 92. As shown in FIG. 17, the control terminal 1 becomes the ground potential (0V) when the logic circuit 91 is operated, and when the logic circuit 91 is stopped (standby). It becomes the power supply potential (Vdd). By setting the gate voltage of the pMOS transistor 92 to the power supply potential (source potential) Vdd, the pMOS transistor 92 is turned off and the leakage current can be reduced.

  In addition, a method has been proposed in which leakage current is reduced by setting the gate voltage of the power switch to an overshoot voltage, thereby further reducing the power consumption of the MT-CMOS circuit (Patent Document 2).

  On the other hand, as an application of the MT-CMOS technology, as shown in FIG. 18, a pMOS transistor 92 is connected between the logic circuit 91 and the power supply potential (Vdd), and further, between the logic circuit 91 and the ground potential (0 V). NMOS transistor 93 is connected to each other, and each transistor is complementarily turned on / off in accordance with on / off of logic circuit 91.

  When the logic circuit 91 shown in FIG. 18A is stopped (off), the switches 94 and 97 are turned off and the switches 95 and 96 are turned on, so that the gate potential of the nMOS transistor 93 is controlled to the ground potential (0 V). Then, the gate potential of the pMOS transistor 92 is controlled to the positive power supply potential (Vdd), and both transistors are turned off.

On the other hand, when the logic circuit 91 shown in FIG. 18B is in operation (on), the switches 94 and 97 are on, the switches 95 and 96 are off, and the gate potential of the nMOS transistor 93 is positive power supply potential (Vdd). ), The gate potential of the pMOS transistor 92 is controlled to the ground potential (0 V), both transistors are turned on, and a current is supplied to the logic circuit 91.
Japanese Patent No. 2631335 Japanese Patent No. 3314185

  In the MT-CMOS circuit shown in FIGS. 16 and 18, the power switch (92, 93) must supply a current of several tens mA to several hundred mA when the logic circuit 91 operates. For this reason, the gate width becomes as large as several tens of mm. Further, the gate-source voltage during standby is 0 V, and the leakage current is not minimum. As a result, there is a problem that the leakage current during standby flows about several tens of μA.

  In Patent Document 2, a leakage current during standby is set by using a voltage converter (DC / DC converter) or the like to make the gate voltage of the power switch higher than the power supply voltage, that is, by making the gate / source reversely biased. There is also a method for reducing this. However, in this method, since the charge pump circuit and the like are moved, there is a problem that the power consumption is large during standby and the average power consumption cannot be reduced.

  Furthermore, in the MT-CMOS technology of Patent Documents 1 and 2, since the power switch is connected to only one of the positive power supply side or the ground side, the potential in the logic circuit varies greatly between operation and standby. End up. For this reason, in a logic circuit including a large RC time constant due to a capacitance or the like in the circuit, there is a problem that the start-up time for switching from the standby mode to the operation mode becomes long.

  In consideration of the above-described problems, the present invention reduces the leakage current when the operation of the logic circuit that operates intermittently is stopped (standby), and can further supply the drive current when the logic circuit operates. An object is to provide a reduction circuit.

  The first invention controls the power switch connected between the logic circuit and the power supply in accordance with the intermittent operation of the logic circuit, and conducts the power switch to supply power to the logic circuit. In a leakage current reduction circuit that reduces leakage current when power supply to a logic circuit is stopped by making it non-conductive, a power switch is connected between a positive power supply potential and a power supply terminal of the logic circuit from the high potential side by an nMOS A configuration in which transistors and pMOS transistors are connected in series, and when the operation of the logic circuit is stopped, the gate terminal of the nMOS transistor is set to the ground potential, and the gate terminal of the pMOS transistor is set to the positive power supply potential to perform non-conduction, When the logic circuit operates, the gate terminal of the nMOS transistor is set to a positive power supply potential or higher, and the gate of the pMOS transistor is A gate potential control circuit for controlling to conduct each preparative potential as the ground potential.

  The second invention controls the power switch connected between the logic circuit and the power supply in accordance with the intermittent operation of the logic circuit, and conducts the power switch to supply power to the logic circuit. In a leakage current reduction circuit that reduces leakage current when power supply to a logic circuit is stopped by making it non-conductive, a power switch is connected between a ground potential and a power supply terminal of the logic circuit between an nMOS transistor and a high potential side. A configuration in which pMOS transistors are vertically connected in order, and when the operation of the logic circuit is stopped, the gate terminal of the nMOS transistor is set to the ground potential, and the gate terminal of the pMOS transistor is set to the positive power supply potential so as to be non-conductive. During the operation, the gate terminal of the nMOS transistor is set to a positive power supply potential and the gate potential of the pMOS transistor A gate potential control circuit for controlling to conduct respectively as follows ground potential.

  According to a third invention, as a gate potential control circuit according to the first invention, a complementary switch that complementarily turns on / off the connection between each gate terminal of an nMOS transistor and a pMOS transistor and a positive power supply potential or ground potential is used. When the operation is stopped, the gate terminal of the nMOS transistor is set to the ground potential, the gate terminal of the pMOS transistor is set to the positive power supply potential, and the gate terminal of the nMOS transistor is set to the positive power supply potential. The electric potential is set as a ground electric potential and each is made conductive.

  According to a fourth invention, as a gate potential control circuit according to the second invention, a complementary switch that complementarily turns on / off the connection between each gate terminal of the nMOS transistor and the pMOS transistor and a positive power supply potential or ground potential is used. When the operation is stopped, the gate terminal of the nMOS transistor is set to the ground potential, the gate terminal of the pMOS transistor is set to the positive power supply potential, and the gate terminal of the nMOS transistor is set to the positive power supply potential. The electric potential is set as a ground electric potential and each is made conductive.

  In the fifth invention, instead of the complementary switch connected to the gate terminal of the nMOS transistor in the third invention, one power supply terminal is connected to the positive power supply potential via the switch, and the other power supply terminal is connected to the ground potential. The voltage converter is turned off when the operation of the logic circuit is stopped, the switch is turned off and the gate terminal of the nMOS transistor is made nonconductive with the ground potential, and the switch is turned on when the logic circuit is operated. In this configuration, the gate terminal of the nMOS transistor is made conductive with a positive power supply potential or higher.

  In the sixth invention, instead of the complementary switch connected to the gate terminal of the pMOS transistor in the fourth invention, one power supply terminal is connected to the positive power supply potential, and the other power supply terminal is connected to the ground potential via the switch. The voltage converter is turned off when the operation of the logic circuit is stopped, the switch is turned off to make the gate terminal of the pMOS transistor a positive power supply potential, and the switch is turned on when the logic circuit is operated. Thus, the gate terminal of the pMOS transistor is made to be conductive below the ground potential.

  In the seventh invention, instead of the complementary switch connected to the gate terminal of the nMOS transistor in the third invention, one power supply terminal is connected to the positive power supply potential through the switch, and the other power supply terminal is connected to the ground potential. Is connected to the voltage control circuit, and the voltage control circuit turns off the switch when the operation of the logic circuit stops, turns off the gate terminal of the nMOS transistor as a ground potential, and turns on the switch when the logic circuit operates. In this configuration, the potential of the gate terminal of the nMOS transistor is controlled in accordance with the potential of the power supply terminal of the logic circuit.

  In the eighth invention, instead of the complementary switch connected to the gate terminal of the pMOS transistor in the fourth invention, one power supply terminal is connected to the positive power supply potential, and the other power supply terminal is connected to the ground potential via the switch. The voltage control circuit is connected to the voltage control circuit. The voltage control circuit turns off the switch when the logic circuit stops operating, makes the gate terminal of the pMOS transistor a non-conductive with the positive power supply potential, and turns on the switch when the logic circuit operates. Thus, the potential of the gate terminal of the pMOS transistor is controlled in accordance with the potential of the power supply terminal of the logic circuit to conduct.

  In the ninth invention, instead of the complementary switch connected to the gate terminal of the nMOS transistor in the third invention, one power supply terminal is connected to the positive power supply potential via the switch, and the other power supply terminal is connected to the ground potential. And a voltage control circuit in which one power supply terminal is connected to the voltage converter and the other power supply terminal is connected to the ground potential. When the operation of the logic circuit is stopped, the voltage converter is connected to the voltage converter. The switch is turned off and one power supply terminal of the voltage control circuit is set to the ground potential, and the switch is turned on when the logic circuit is operated to set one power supply terminal of the voltage control circuit to the positive power supply potential or more. The circuit is non-conductive with the gate terminal of the nMOS transistor as the ground potential when the operation of the logic circuit is stopped, and a power supply potential higher than the positive power supply potential is supplied from the voltage converter during operation of the logic circuit A control conducting and thereby configured in accordance with the potential of the gate terminal of the nMOS transistor to the potential of the power supply terminal of the logic circuit.

  In the tenth invention, instead of the complementary switch connected to the gate terminal of the pMOS transistor in the fourth invention, one power supply terminal is connected to a positive power supply potential, and the other power supply terminal is connected to the ground potential via the switch. Connect the voltage converter connected to the voltage control circuit, one power supply terminal is connected to the positive power supply potential, the other power supply terminal is connected to the voltage converter, the voltage converter operates the logic circuit The power supply terminal of the voltage control circuit is set to a positive power supply potential by turning off the switch at the time of stop, and the power supply terminal of the voltage control circuit is set to a ground potential or less by turning on the switch during the operation of the logic circuit. The voltage control circuit turns off the gate terminal of the pMOS transistor as a positive power supply potential when the operation of the logic circuit is stopped, and a power supply potential lower than the ground potential from the voltage converter during operation of the logic circuit. Is fed is controlled by conducting the cell configuration in accordance with the potential of the gate terminal of the pMOS transistor to the potential of the power supply terminal of the logic circuit.

  In an eleventh aspect of the invention, two power switches connected between the logic circuit and the positive power supply potential and between the logic circuit and the ground potential are controlled in accordance with the intermittent operation of the logic circuit, and the power switch is turned on. In the leakage current reduction circuit that reduces the leakage current when the power supply is turned off and the power supply to the logic circuit is stopped by supplying power to the logic circuit, the two power switches are the logic circuit and An nMOS transistor is connected between the positive power supply potential and a pMOS transistor is connected between the logic circuit and the ground potential. When the operation of the logic circuit is stopped, the gate terminal of the nMOS transistor is set to the ground potential. The gate terminal is controlled to be non-conducting with a positive power supply potential, and the nMOS transistor is operated during the operation of the logic circuit. The gate terminal is a positive power supply potential above a gate potential control circuit for controlling to conduct each gate potential of the pMOS transistor as below ground potential.

  According to a twelfth aspect of the invention, the gate potential control circuit according to the eleventh aspect of the present invention includes a complementary switch that complementarily turns on and off the connection between each gate terminal of the nMOS transistor and the pMOS transistor and a positive power supply potential or ground potential. When the operation is stopped, the gate terminal of the nMOS transistor is set to the ground potential, the gate terminal of the pMOS transistor is set to the positive power supply potential, and the gate terminal of the nMOS transistor is set to the positive power supply potential. The electric potential is set as a ground electric potential and each is made conductive.

  In the thirteenth invention, instead of the complementary switch connected to the gate terminal of the nMOS transistor in the twelfth invention, one power supply terminal is connected to the positive power supply potential via the switch, and the other power supply terminal is connected to the ground potential. The voltage converter is turned off when the operation of the logic circuit is stopped, the switch is turned off and the gate terminal of the nMOS transistor is made nonconductive with the ground potential, and the switch is turned on when the logic circuit is operated. In this configuration, the gate terminal of the nMOS transistor is made conductive with a positive power supply potential or higher.

  In the fourteenth invention, instead of the complementary switch connected to the gate terminal of the pMOS transistor in the twelfth invention, one power supply terminal is connected to the positive power supply potential, and the other power supply terminal is connected to the ground potential via the switch. The voltage converter is turned off when the operation of the logic circuit is stopped, the switch is turned off to make the gate terminal of the pMOS transistor a positive power supply potential, and the switch is turned on when the logic circuit is operated. Thus, the gate terminal of the pMOS transistor is made to be conductive below the ground potential.

  In the fifteenth aspect of the invention, instead of the complementary switch connected to the gate terminal of the nMOS transistor in the twelfth aspect of the invention, one power supply terminal is connected to the positive power supply potential via the first switch, and the other power supply terminal Is connected to the first voltage converter connected to the ground potential, and instead of the complementary switch connected to the gate terminal of the pMOS transistor, one power supply terminal is connected to the positive power supply potential and the other power supply terminal is connected The second voltage converter is connected to the ground potential via the second switch, the first and second switches are turned off when the operation of the logic circuit is stopped, the gate terminal of the nMOS transistor is set to the ground potential, and the pMOS An nMOS transistor in which the gate terminal of the transistor is made non-conductive with a positive power supply potential and the first and second switches are turned on during the operation of the logic circuit. The gate terminal is a positive power supply potential or a structure in which to conduct each of the gate terminal of the pMOS transistor as below ground potential.

  The leakage current reduction circuits of the first to fourth inventions use nMOS transistors and pMOS transistors connected in cascade as power switches, and reverse bias between the gates / sources of the two transistors as power switches when the operation of the logic circuit is stopped By setting the state, the leakage current can be greatly reduced. As a result, power consumption when the operation of the device including the logic circuit is stopped (standby) can be greatly suppressed, and in particular, in a device (for example, a wireless tag) that uses the battery as a power source and operates intermittently, the life of the battery can be extended. Can be planned.

  According to a fifth aspect of the present invention, a leakage current reducing circuit uses a voltage converter that makes the gate potential of the nMOS transistor higher than the power supply potential during operation of the logic circuit, in addition to the effect of reducing the leakage current when the operation of the logic circuit stops. Even when the power supply potential is low, a sufficient current can be supplied to the logic circuit.

  According to a sixth aspect of the present invention, in addition to the effect of reducing the leakage current when the operation of the logic circuit is stopped, the leakage current reduction circuit uses a voltage converter that lowers the gate potential of the pMOS transistor below the power supply potential during the operation of the logic circuit. Even when the power supply potential is low, a sufficient current can be supplied to the logic circuit.

  According to a seventh aspect of the present invention, in addition to the effect of reducing the leakage current when the operation of the logic circuit is stopped, the leakage current reduction circuit controls the gate potential of the nMOS transistor according to the power supply terminal voltage of the logic circuit during the operation of the logic circuit. By using the circuit, it can function as a voltage regulator for the logic circuit.

  According to an eighth aspect of the present invention, there is provided a leakage current reducing circuit for controlling a gate potential of a pMOS transistor according to a power supply terminal voltage of a logic circuit during operation of the logic circuit, in addition to an effect of reducing a leakage current when the operation of the logic circuit is stopped. By using the circuit, it can function as a voltage regulator for the logic circuit.

  According to a ninth aspect of the present invention, there is provided a leakage current reducing circuit for controlling a gate potential of an nMOS transistor in accordance with a power supply terminal voltage of a logic circuit during operation of the logic circuit, in addition to a leakage current reducing effect when the operation of the logic circuit is stopped By using the circuit and further boosting the power supply of the voltage control circuit with a voltage converter, the voltage control circuit can function as a voltage regulator for the logic circuit even when the power supply potential is low.

  According to a tenth aspect of the present invention, there is provided a leakage current reducing circuit for controlling the gate potential of a pMOS transistor in accordance with a power supply terminal voltage of the logic circuit during operation of the logic circuit, in addition to the effect of reducing the leakage current when the operation of the logic circuit is stopped. By using the circuit and further supplying the voltage control circuit with the voltage converter stepped down, it can function as a voltage regulator for the logic circuit even when the power supply potential is low.

  In the leakage current reduction circuits of the fifth to tenth inventions shown above, a sufficient current can be supplied to the logic circuit even when the power supply potential is low, and the device including the logic circuit is driven at a low voltage. Can also respond sufficiently. In addition, voltage converters and voltage control circuits are used only to supply potential to the gate, so they operate with very low power, and operate only when the logic circuit operates. There is no increase.

  In the eleventh to twelfth inventions, the logic circuit and the positive power supply potential are connected by an nMOS transistor, the logic circuit and the ground potential are connected by a pMOS transistor, and used as a power switch when operation of the logic circuit is stopped. By setting the gate / source between the two transistors in a reverse bias state, the leakage current can be greatly reduced. As a result, power consumption when the operation of the device including the logic circuit is stopped (standby) can be greatly suppressed, and in particular, in a device (for example, a wireless tag) that uses the battery as a power source and operates intermittently, the life of the battery can be extended. Can be planned.

  In addition, since the potential in the logic circuit can be held at an intermediate potential between the positive power supply potential and the ground potential, the startup time for changing from the standby mode to the operation mode can be shortened.

  In the thirteenth to fifteenth inventions, in addition to the effect of reducing the leakage current when the operation of the logic circuit is stopped, a voltage converter that makes the gate potential of the nMOS transistor higher than the power supply potential during the operation of the logic circuit is used. Thus, even when the power supply potential is low, a sufficient current can be supplied to the logic circuit. Further, by using a voltage converter that lowers the gate potential of the pMOS transistor below the power supply potential during operation of the logic circuit, a sufficient current can be supplied to the logic circuit even when the power supply potential is low.

  Furthermore, the voltage converter is used only to supply the potential to the gate, so it operates at very low power, and it operates only during the operation of the logic circuit. Absent.

(First basic configuration of the present invention)
FIG. 1 shows a first basic configuration of a leakage current reducing circuit of the present invention.
FIG. 1 (a) is vertically connected so that the nMOS transistor 12 and the pMOS transistor 13 constituting the power switch are on the high potential side and the low potential side, respectively, between the logic circuit 11 and the positive power supply potential (Vdd). In this configuration, the gate potential control circuit 10 controls the gate potential of each transistor. The gate potential control circuit 10 sets the gate terminal of the nMOS transistor 12 to the ground potential (0V) and the gate terminal of the pMOS transistor 13 to the positive power supply potential (Vdd) when the operation of the logic circuit 11 is stopped (off). When the logic circuit 11 is operated (ON), the gate terminal of the nMOS transistor 12 is set to a positive power supply potential or higher (≧ Vdd), and the gate potential of the pMOS transistor 13 is set to the ground potential (0 V). Control to turn on. This basic configuration corresponds to a first configuration example of each embodiment shown in FIGS.

  In FIG. 1 (b), the nMOS transistor 12 and the pMOS transistor 13 constituting the power switch are connected vertically between the logic circuit 11 and the ground potential (0V) so that they are on the high potential side and the low potential side, respectively. The gate potential control circuit 10 controls the gate potential of each transistor. The gate potential control circuit 10 sets the gate terminal of the nMOS transistor 12 to the ground potential (0V) and the gate terminal of the pMOS transistor 13 to the positive power supply potential (Vdd) when the operation of the logic circuit 11 is stopped (off). When the logic circuit 11 is operated (ON), the gate terminal of the nMOS transistor 12 is set to a positive power supply potential (Vdd) and the gate potential of the pMOS transistor 13 is set to a ground potential or less (≦ 0 V). Control to turn on. This basic configuration corresponds to a second configuration example of each embodiment shown in FIGS.

  The logic circuit 11 is a low threshold voltage transistor circuit mounted on a device that operates intermittently. However, the logic circuit 11 is not limited to a high-frequency analog circuit used in a wireless tag (RFID) or a portable wireless terminal as described above, and is generally integrated. It may be a logic circuit or an arithmetic circuit in the circuit. In addition, the timing control unit (not shown) controls the timing of the intermittent operation of the logic circuit 11 and also controls the gate potential set by the gate potential control circuit 10 in synchronization. The same applies to the configuration of each embodiment described below.

(Second basic configuration of the present invention)
FIG. 2 shows a second basic configuration of the leakage current reducing circuit of the present invention.
In this configuration, an nMOS transistor 12 constituting a power switch is connected between the logic circuit 11 and the positive power supply potential (Vdd), and a power switch is constituted between the logic circuit 11 and the ground potential (0 V). The pMOS transistor 13 is connected, and the gate potential control circuit 40 controls the gate potential of each transistor. The gate potential control circuit 40 sets the gate terminal of the nMOS transistor 12 to the ground potential (0V) and the gate terminal of the pMOS transistor 13 to the positive power supply potential (Vdd) when the operation of the logic circuit 11 is stopped (off). Control to turn on. Further, when the logic circuit 11 is operated (ON), the gate terminal of the nMOS transistor 12 is set to a positive power supply potential or higher (≧ Vdd), and the gate potential of the pMOS transistor 13 is set to a ground potential or lower (≦ 0 V). Take control. This basic configuration corresponds to a configuration example of each embodiment shown in FIGS.

(First embodiment)
FIG. 3 shows a first configuration example of the first embodiment of the leakage current reduction circuit of the present invention. 3A shows a connection state when the logic circuit 11 is stopped (when off), and FIG. 3B shows a connection state when the logic circuit 11 is in operation (when on).

  In the figure, the nMOS transistor 12 and the pMOS transistor 13 constituting the power switch are connected in series so as to be on the high potential side and the low potential side, respectively, between the logic circuit 11 and the positive power supply potential (Vdd). That is, the drain of the nMOS transistor 12 is connected to the positive power supply potential (Vdd), the source of the nMOS transistor 12 and the source of the pMOS transistor 13 are connected, and the drain of the pMOS transistor 13 and the first power supply terminal of the logic circuit 11 are connected. Connected. A ground potential (0 V) is connected to the second power supply terminal of the logic circuit 11. A positive power supply potential (Vdd) or a ground potential (0 V) is connected to the gate of the nMOS transistor 12 through switches 14 and 15 that are complementarily turned on and off. A positive power supply potential (Vdd) or a ground potential (0 V) is connected to the gate of the pMOS transistor 13 through switches 16 and 17 that are complementarily turned on and off. The switches 14, 16 and the switches 15, 17 are also turned on and off in a complementary manner.

  When the logic circuit 11 shown in FIG. 3A is stopped (off), the switches 14 and 17 are turned off, the switches 15 and 16 are turned on, and the gate potential of the nMOS transistor 12 is controlled to the ground potential (0 V). Then, the gate potential of the pMOS transistor 13 is controlled to the positive power supply potential (Vdd), and both transistors are turned off. At this time, the source potential of both transistors becomes an intermediate potential (˜Vdd / 2). For this reason, both transistors are in a reverse bias state between the gate and the source, and the leakage current is greatly reduced.

  On the other hand, when the logic circuit 11 shown in FIG. 3B is operating (on), the switches 14 and 17 are on and the switches 15 and 16 are off, and the gate potential of the nMOS transistor 12 is positive power supply potential (Vdd). ), The gate potential of the pMOS transistor 13 is controlled to the ground potential (0 V), both transistors are turned on, and a current is supplied to the logic circuit 11.

  In the leakage current reduction circuit of this embodiment, other switches 14 to 17 are used for switching the gate potential of the power switch (nMOS transistor 12 and pMOS transistor 13). For these four switches, a transistor similar to the power switch in this embodiment can be used, but a transistor with a small gate size (a gate width of 1 μm or less) is sufficient because it is used only for holding the gate potential. For this reason, the leakage current in the switches 14 to 17 is very small.

  FIG. 4 shows a second configuration example of the first embodiment of the leakage current reduction circuit of the present invention. 4A shows a connection state when the logic circuit 11 is stopped (when off), and FIG. 4B shows a connection state when the logic circuit 11 is in operation (when on).

  In this configuration example, a positive power supply potential (Vdd) is connected to the first power supply terminal of the logic circuit 11, and the nMOS transistor 12 constituting a power switch is connected between the second power supply terminal and the ground potential (0V). And pMOS transistor 13 are connected in series so as to be on the high potential side and the low potential side, respectively, but the operation mechanism of switches 14 to 17 connected to the gates of the transistors is the first configuration shown in FIG. Same as example.

(Second Embodiment)
FIG. 5 shows a first configuration example of the second embodiment of the leakage current reduction circuit of the present invention. FIG. 5A shows a connection state when the logic circuit 11 is stopped (when off), and FIG. 5B shows a connection state when the logic circuit 11 is in operation (when on).

  This configuration example is characterized in that a voltage converter (DC / DC converter) 21 is used to supply a potential to the gate of the nMOS transistor 12 in the first configuration example of the first embodiment shown in FIG. The voltage converter 21 has a positive power supply potential (Vdd) connected to one of the power supply terminals via the switch 14 and a ground potential (0 V) connected to the other, and when the switch 14 is off, the operation is stopped and the grounding is performed. A potential (0 V) is output, and when the switch 14 is on, a potential higher than the power supply potential (Vdd) is output by the boosting operation.

  When the logic circuit 11 shown in FIG. 5B is in operation (on), the switches 14 and 17 are turned on and the switch 16 is turned off, and the gate potential of the nMOS transistor 12 becomes positive by the boost operation of the voltage converter 21. Control is made to be higher than the power supply potential (Vdd), the gate potential of the pMOS transistor 13 is controlled to the ground potential (0 V), both transistors are turned on, and current is supplied to the logic circuit 11. At this time, since the gate potential of the nMOS transistor 12 becomes higher than the power supply potential (Vdd), a sufficient current can be supplied to the logic circuit 11 even when the power supply potential (Vdd) is low.

  On the other hand, when the operation of the logic circuit 11 shown in FIG. 5A is stopped (off), the switches 14 and 17 are turned off and the switch 16 is turned on, the operation of the voltage converter 21 is stopped and the nMOS transistor 12 is turned off. The gate potential becomes the ground potential (0 V), the gate potential of the pMOS transistor 13 is controlled to the positive power supply potential (Vdd), and both transistors become non-conductive. At this time, the source potential of both transistors becomes an intermediate potential (˜Vdd / 2). For this reason, both transistors are in a reverse bias state between the gate and the source, and the leakage current is greatly reduced.

  Since the voltage converter (DC / DC converter) 21 in this embodiment is used only for supplying a potential to the gate of the nMOS transistor 12, it operates with very low power. The voltage converter 21 is set to operate only when the logic circuit 11 operates. For this reason, in applications with a high intermittent ratio such as RFID, the average power consumption by the voltage converter 21 is only slightly increased.

  FIG. 6 shows a second configuration example of the second embodiment of the leakage current reduction circuit of the present invention. 6A shows a connection state when the logic circuit 11 is stopped (when off), and FIG. 6B shows a connection state when the logic circuit 11 is in operation (when on).

  This configuration example is characterized in that a voltage converter (DC / DC converter) 22 is used to supply a potential to the gate of the pMOS transistor 13 in the second configuration example of the first embodiment shown in FIG. The voltage converter 22 has a positive power supply potential (Vdd) connected to one of the power supply terminals and a ground potential (0 V) connected to the other via the switch 17. When the switch 17 is off, the operation is stopped and the power supply is turned off. A potential (Vdd) is output, and when the switch 17 is on, a potential lower than the ground potential (0 V) is output by the step-down operation.

  When the logic circuit 11 shown in FIG. 6B is operating (on), the switches 14 and 17 are turned on and the switch 15 is turned off. The gate potential of the pMOS transistor 13 is reduced to the ground potential by the step-down operation of the voltage converter 22. The gate potential of the nMOS transistor 12 is controlled to a positive power supply potential (Vdd), and both transistors are turned on to supply current to the logic circuit 11. At this time, since the gate potential of the pMOS transistor 13 becomes lower than the ground potential (0 V), a sufficient current can be supplied to the logic circuit 11 even when the power supply potential (Vdd) is low. The increase in average power consumption in the voltage converter 22 is slight as in the first configuration example of the present embodiment.

  On the other hand, when the logic circuit 11 shown in FIG. 6 (a) is stopped (off), the switches 14 and 17 are turned off and the switch 15 is turned on, and the voltage converter 22 stops operating and the pMOS transistor 13 is turned off. The gate potential becomes a positive power supply potential (Vdd), the gate potential of the nMOS transistor 12 is controlled to the ground potential (0 V), and both transistors become non-conductive. At this time, the source potential of both transistors becomes an intermediate potential (˜Vdd / 2). For this reason, both transistors are in a reverse bias state between the gate and the source, and the leakage current is greatly reduced.

(Third embodiment)
FIG. 7 shows a first configuration example of the third embodiment of the leakage current reduction circuit of the present invention. FIG. 7A shows a connection state when the logic circuit 11 is stopped (when off), and FIG. 7B shows a connection state when the logic circuit 11 is in operation (when on).

  This configuration example is characterized in that a voltage control circuit 31 is used to supply a potential to the gate of the nMOS transistor 12 in the first configuration example of the first embodiment shown in FIG. The voltage control circuit 31 has a positive power supply potential (Vdd) connected to one of the power supply terminals via the switch 14 and a ground potential (0 V) connected to the other, and when the switch 14 is off, the operation is stopped and grounding is performed. When the potential (0 V) is output and the switch 14 is on, the potential of the first power supply terminal (the drain of the pMOS transistor 13) of the logic circuit 11 is monitored so that this potential becomes the optimum operating potential of the logic circuit 11. In addition, the gate potential of the nMOS transistor 12 is controlled. That is, when the logic circuit 11 shown in FIG. 7B is operating (on), the switch 14 is turned on, so that the voltage control circuit 31 functions as a voltage regulator for the logic circuit 11.

  On the other hand, when the operation of the logic circuit 11 shown in FIG. 7A is stopped (off), the switches 14 and 17 are turned off and the switch 16 is turned on, the operation of the voltage control circuit 31 is stopped and the nMOS transistor 12 is turned off. The gate potential becomes the ground potential (0 V), the gate potential of the pMOS transistor 13 is controlled to the positive power supply potential (Vdd), and both transistors become non-conductive. At this time, the source potential of both transistors becomes an intermediate potential (˜Vdd / 2). For this reason, both transistors are in a reverse bias state between the gate and the source, and the leakage current is greatly reduced.

  FIG. 8 shows a second configuration example of the third embodiment of the leakage current reduction circuit of the present invention. FIG. 8A shows a connection state when the logic circuit 11 is stopped (when off), and FIG. 8B shows a connection state when the logic circuit 11 is in operation (when on).

  This configuration example is characterized in that a voltage control circuit 32 is used to supply a potential to the gate of the pMOS transistor 13 in the second configuration example of the first embodiment shown in FIG. The voltage control circuit 32 connects a positive power supply potential (Vdd) to one of the power supply terminals, and connects the ground potential (0 V) to the other via the switch 17. When the potential (Vdd) is output and the switch 17 is on, the potential of the second power supply terminal (the drain of the nMOS transistor 12) of the logic circuit 11 is monitored so that this potential becomes the optimum operating potential of the logic circuit 11. In addition, the gate potential of the pMOS transistor 13 is controlled. That is, when the logic circuit 11 shown in FIG. 8B is operating (on), the switch 17 is turned on, so that the voltage control circuit 32 functions as a voltage regulator for the logic circuit 11.

  On the other hand, when the operation of the logic circuit 11 shown in FIG. 8A is stopped (off), the switches 14 and 17 are turned off and the switch 15 is turned on, and the gate potential of the pMOS transistor 13 becomes the power supply potential (Vdd). The gate potential of the nMOS transistor 12 is controlled to the ground potential (0 V), and both transistors are turned off. At this time, the source potential of both transistors becomes an intermediate potential (˜Vdd / 2). For this reason, both transistors are in a reverse bias state between the gate and the source, and the leakage current is greatly reduced.

(Fourth embodiment)
FIG. 9 shows a first configuration example of the fourth embodiment of the leakage current reduction circuit of the present invention. FIG. 9A shows a connection state when the logic circuit 11 is stopped (when off), and FIG. 9B shows a connection state when the logic circuit 11 is in operation (when on).

  This configuration example is characterized in that a voltage converter (DC / DC converter) 21 is used to supply power to the voltage control circuit 31 in the first configuration example of the third embodiment shown in FIG. The voltage converter 21 has a positive power supply potential (Vdd) connected to one of the power supply terminals via the switch 14 and a ground potential (0 V) connected to the other, and when the switch 14 is off, the operation is stopped and the grounding is performed. A potential (0 V) is output, and when the switch 14 is on, a potential higher than the power supply potential (Vdd) is output by the boosting operation.

  When the logic circuit 11 shown in FIG. 9B is operating (on), the switches 14 and 17 are turned on and the switch 16 is turned off. The power supply potential of the voltage control circuit 31 is positive by the voltage converter 21 boosting operation. It is controlled to be higher than the power supply potential (Vdd). At this time, the voltage control circuit 31 monitors the potential of the first power supply terminal (the drain of the pMOS transistor 13) of the logic circuit 11, and the nMOS transistor 12 has an optimal operating potential for the logic circuit 11. Control the gate potential. In this way, when the logic circuit 11 is in operation (on), a power supply potential higher than the power supply potential (Vdd) is supplied to the voltage control circuit 31, so that even when the power supply potential (Vdd) is low, Function.

  On the other hand, when the logic circuit 11 shown in FIG. 9 (a) is stopped (off), the switches 14 and 17 are turned off and the switch 16 is turned on, and both the voltage converter 21 and the voltage control circuit 31 are stopped. The gate potential of the nMOS transistor 12 becomes the ground potential (0 V), the gate potential of the pMOS transistor 13 is controlled to the positive power supply potential (Vdd), and both transistors become non-conductive. At this time, the source potential of both transistors becomes an intermediate potential (˜Vdd / 2). For this reason, both transistors are in a reverse bias state between the gate and the source, and the leakage current is greatly reduced.

  FIG. 10 shows a second configuration example of the fourth embodiment of the leakage current reduction circuit of the present invention. FIG. 10A shows a connection state when the logic circuit 11 is stopped (when off), and FIG. 10B shows a connection state when the logic circuit 11 is in operation (when on).

  This configuration example is characterized in that a voltage converter (DC / DC converter) 22 is used for power supply to the voltage control circuit 32 in the second configuration example of the third embodiment shown in FIG. The voltage converter 22 has a positive power supply potential (Vdd) connected to one of the power supply terminals and a ground potential (0 V) connected to the other via the switch 17. When the switch 17 is off, the operation is stopped and the power supply is turned off. A potential (Vdd) is output, and when the switch 17 is on, a potential lower than the ground potential (0 V) is output by the step-down operation.

  When the logic circuit 11 shown in FIG. 10B is in operation (on), the switches 14 and 17 are on and the switch 15 is off, and the power supply potential of the voltage control circuit 32 is grounded by the voltage converter 22 step-down operation. It is controlled to be lower than the potential (0 V). At this time, the voltage control circuit 32 monitors the potential of the first power supply terminal (the drain of the pMOS transistor 13) of the logic circuit 11, and the nMOS transistor 12 has an optimum operating potential for the logic circuit 11. Control the gate potential. Thus, when the logic circuit 11 is in operation (on), a power supply potential lower than the ground potential (0 V) is supplied to the voltage control circuit 32. Therefore, even when the power supply potential (Vdd) is low, Function.

  On the other hand, when the logic circuit 11 shown in FIG. 10 (a) is stopped (off), the switches 14 and 17 are turned off and the switch 15 is turned on, and both the voltage converter 22 and the voltage control circuit 32 are stopped. The gate potential of the pMOS transistor 13 becomes the power supply potential (Vdd), the gate potential of the nMOS transistor 12 is controlled to the ground potential (0 V), and both transistors become non-conductive. At this time, the source potential of both transistors becomes an intermediate potential (˜Vdd / 2). For this reason, both transistors are in a reverse bias state between the gate and the source, and the leakage current is greatly reduced.

  Since the voltage converter (DC / DC converter) 22 in this embodiment is used only for supplying a potential to the voltage control circuit 32, it operates with very low power. The voltage converter 22 is set to operate only when the logic circuit 11 operates. For this reason, in applications with a high intermittent ratio such as RFID, the average power consumption by the voltage converter 22 is only slightly increased.

(Fifth embodiment)
FIG. 11 shows a fifth embodiment of the leakage current reduction circuit of the present invention. FIG. 11A shows a connection state when the logic circuit 11 is stopped (when off), and FIG. 11B shows a connection state when the logic circuit 11 is in operation (when on).

  In this embodiment, an nMOS transistor 12 constituting a power switch is connected between the logic circuit 11 and the positive power supply potential (Vdd), and the power switch is connected between the logic circuit 11 and the ground potential (0 V). The pMOS transistor 13 to be configured is connected. That is, the drain of the nMOS transistor 12 is connected to the positive power supply potential (Vdd), the source of the nMOS transistor 12 is connected to the first power supply terminal of the logic circuit 11, and the drain of the pMOS transistor 13 and the ground potential (0V) are connected. The source of the pMOS transistor 13 and the second power supply terminal of the logic circuit 11 are connected. The logic circuit 11 is assumed to be, for example, an LC filter described later, and includes such a capacitor C. In this configuration, the arrangement of the nMOS transistor 12 and the pMOS transistor 13 is reversed from the conventional configuration shown in FIG.

  A positive power supply potential (Vdd) or a ground potential (0 V) is connected to the gate of the nMOS transistor 12 through switches 14 and 15 that are complementarily turned on and off. A positive power supply potential (Vdd) or a ground potential (0 V) is connected to the gate of the pMOS transistor 13 through switches 16 and 17 that are complementarily turned on and off. The switches 14, 16 and the switches 15, 17 are also turned on and off in a complementary manner.

  When the logic circuit 11 shown in FIG. 11B is in operation (on), the switches 14 and 17 are turned on, the switches 15 and 16 are turned off, and the gate potential of the nMOS transistor 12 becomes a positive power supply potential (Vdd). As a result, the gate potential of the pMOS transistor 13 is controlled to the ground potential (0 V), both transistors are turned on, and a current is supplied to the logic circuit 11. At this time, the potential of the capacitor C in the logic circuit 11 can be an intermediate potential Va (˜Vdd / 2) between the positive power supply potential and the ground potential.

  When the logic circuit 11 shown in FIG. 11A is stopped (off), the switches 14 and 17 are turned off, the switches 15 and 16 are turned on, and the gate potential of the nMOS transistor 12 is controlled to the ground potential (0 V). Then, the gate potential of the pMOS transistor 13 is controlled to the positive power supply potential (Vdd), and both transistors are turned off. At this time, the source potential of both transistors and the potential of the capacitor C in the logic circuit 11 are held at a substantially intermediate potential (˜Va) between the positive power supply potential and the ground potential. For this reason, both transistors are in a reverse bias state between the gate and the source, and the leakage current is greatly reduced.

  In the leakage current reduction circuit of this embodiment, other switches 14 to 17 are used for switching the gate potential of the power switch (nMOS transistor 12 and pMOS transistor 13). For these four switches, a transistor similar to the power switch in this embodiment can be used, but a transistor with a small gate size (a gate width of 1 μm or less) is sufficient because it is used only for holding the gate potential. For this reason, the leakage current in the switches 14 to 17 is very small.

  FIG. 12 shows an example of the logic circuit 11. Here, a gm-C filter having the same characteristics as the LC filter and formed on-chip is shown. Capacitors C1, C2, and C3 are connected between the connection points of the four gm-Cells that are bridge-connected between the input terminal and the output terminal and the ground, and four gm-Cells and two capacitors C2 are connected. Functions as an inductor L. These capacitors hold potentials for adjusting the pass band of a band pass filter, for example, as logic circuit characteristics.

  When such a logic circuit 11 is applied to the leakage current reduction circuit of FIG. 11, the potentials of the capacitors C1 to C3 are also set to the intermediate potential Va when the logic circuit 11 is operated (on). When the operation of the logic circuit 11 is stopped (off), the gate potential of the nMOS transistor 12 is 0 V, the gate potential of the pMOS transistor 13 is Vdd, and the source potentials of both transistors and the potentials of the capacitors C1 to C3 operate. It is maintained at the intermediate potential (~ Va) which is almost the same as the time. As a result, the change in the internal potential (capacitance potential) between the operation and the operation stop (standby) of the logic circuit 11 becomes small, so that the rise time for changing from the standby mode to the operation mode can be shortened.

(Sixth embodiment)
FIG. 13 shows a first configuration example of the sixth embodiment of the leakage current reduction circuit of the present invention. FIG. 13A shows a connection state when the logic circuit 11 is stopped (when off), and FIG. 13B shows a connection state when the logic circuit 11 is in operation (when on).

  This configuration example is characterized in that a voltage converter (DC / DC converter) 21 is used to supply a potential to the gate of the nMOS transistor 12 in the fifth embodiment shown in FIG. The voltage converter 21 has a positive power supply potential (Vdd) connected to one of the power supply terminals via the switch 14 and a ground potential (0 V) connected to the other, and when the switch 14 is off, the operation is stopped and the grounding is performed. A potential (0 V) is output, and when the switch 14 is on, a potential higher than the power supply potential (Vdd) is output by the boosting operation.

  When the logic circuit 11 shown in FIG. 13B is operating (on), the switches 14 and 17 are turned on and the switch 16 is turned off, and the gate potential of the nMOS transistor 12 is positive by the boosting operation of the voltage converter 21. Control is made to be higher than the power supply potential (Vdd), the gate potential of the pMOS transistor 13 is controlled to the ground potential (0 V), both transistors are turned on, and current is supplied to the logic circuit 11. At this time, since the gate potential of the nMOS transistor 12 becomes higher than the power supply potential (Vdd), a sufficient current can be supplied to the logic circuit 11 even when the power supply potential (Vdd) is low.

  On the other hand, when the operation of the logic circuit 11 shown in FIG. 13A is stopped (off), the switches 14 and 17 are turned off and the switch 16 is turned on, the operation of the voltage converter 21 is stopped and the nMOS transistor 12 is turned off. The gate potential becomes the ground potential (0 V), the gate potential of the pMOS transistor 13 is controlled to the positive power supply potential (Vdd), and both transistors become non-conductive. At this time, the source potential of both transistors becomes the intermediate potential Va. For this reason, both transistors are in a reverse bias state between the gate and the source, and the leakage current is greatly reduced.

  FIG. 14 shows a second configuration example of the sixth embodiment of the leakage current reduction circuit of the present invention. FIG. 14A shows a connection state when the logic circuit 11 is stopped (when off), and FIG. 14B shows a connection state when the logic circuit 11 is in operation (when on).

  This configuration example is characterized in that a voltage converter (DC / DC converter) 22 is used to supply a potential to the gate of the pMOS transistor 13 in the fifth embodiment shown in FIG. The voltage converter 22 has a positive power supply potential (Vdd) connected to one of the power supply terminals and a ground potential (0 V) connected to the other via the switch 17. When the switch 17 is off, the operation is stopped and the power supply is turned off. A potential (Vdd) is output, and when the switch 17 is on, a potential lower than the ground potential (0 V) is output by the step-down operation.

  When the logic circuit 11 shown in FIG. 14B is operating (on), the switches 14 and 17 are turned on and the switch 15 is turned off. The gate potential of the pMOS transistor 13 is reduced to the ground potential by the step-down operation of the voltage converter 22. The gate potential of the nMOS transistor 12 is controlled to a positive power supply potential (Vdd), and both transistors are turned on to supply current to the logic circuit 11. At this time, since the gate potential of the pMOS transistor 13 becomes lower than the ground potential (0 V), a sufficient current can be supplied to the logic circuit 11 even when the power supply potential (Vdd) is low.

  On the other hand, when the logic circuit 11 shown in FIG. 14 (a) is stopped (off), the switches 14 and 17 are turned off and the switch 15 is turned on, and the voltage converter 22 stops operating and the pMOS transistor 13 is turned off. The gate potential becomes a positive power supply potential (Vdd), the gate potential of the nMOS transistor 12 is controlled to the ground potential (0 V), and both transistors become non-conductive. At this time, the source potential of both transistors becomes the intermediate potential Va. For this reason, both transistors are in a reverse bias state between the gate and the source, and the leakage current is greatly reduced.

  FIG. 15 shows a third configuration example of the sixth embodiment of the leakage current reduction circuit of the present invention. FIG. 15A shows a connection state when the logic circuit 11 is stopped (when off), and FIG. 15B shows a connection state when the logic circuit 11 is in operation (when on).

  This configuration example is characterized in that voltage converters (DC / DC converters) 21 and 22 are used to supply potentials to the gates of the nMOS transistor 12 and the pMOS transistor 13 in the fifth embodiment shown in FIG. The voltage converter 21 has a positive power supply potential (Vdd) connected to one of the power supply terminals via the switch 14 and a ground potential (0 V) connected to the other, and when the switch 14 is off, the operation is stopped and the grounding is performed. A potential (0 V) is output, and when the switch 14 is on, a potential higher than the power supply potential (Vdd) is output by the boosting operation. The voltage converter 22 connects a positive power supply potential (Vdd) to one of the power supply terminals, and connects the ground potential (0 V) to the other via the switch 17, and stops operating when the switch 17 is off. The power supply potential (Vdd) is output, and when the switch 17 is on, a potential lower than the ground potential (0 V) is output by the step-down operation.

  Thus, when the logic circuit 11 is in operation (on), the gate potential of the nMOS transistor 12 becomes higher than the power supply potential (Vdd) and the gate potential of the pMOS transistor 13 becomes lower than the ground potential (0 V). Even when the power supply potential (Vdd) is low, a sufficient current can be supplied to the logic circuit 11.

  Since the voltage converters (DC / DC converters) 21 and 22 in this embodiment are used only for supplying potentials to the gates of the nMOS transistor 12 and the pMOS transistor 13, they operate with very low power. The voltage converters 21 and 22 are set to operate only when the logic circuit 11 operates. For this reason, in applications with a high intermittent ratio such as RFID, the average power consumption by the voltage converters 21 and 22 is only slightly increased.

The figure which shows the 1st basic composition of this invention. The figure which shows the 2nd basic composition of this invention. The figure which shows the 1st structural example of the 1st Embodiment of this invention. The figure which shows the 2nd structural example of the 1st Embodiment of this invention. The figure which shows the 1st structural example of the 2nd Embodiment of this invention. The figure which shows the 2nd structural example of the 2nd Embodiment of this invention. The figure which shows the 1st structural example of the 3rd Embodiment of this invention. The figure which shows the 2nd structural example of the 3rd Embodiment of this invention. The figure which shows the 1st structural example of the 4th Embodiment of this invention. The figure which shows the 2nd structural example of the 4th Embodiment of this invention. The figure which shows the 5th Embodiment of this invention. 2 is a diagram illustrating an example of a logic circuit 11. FIG. The figure which shows the 1st structural example of the 6th Embodiment of this invention. The figure which shows the 2nd structural example of the 6th Embodiment of this invention. The figure which shows the 3rd structural example of the 6th Embodiment of this invention. The figure which shows the structural example of the conventional leakage current reduction circuit. The time chart which shows the control signal waveform of the control terminal in a conventional structure. The figure which shows the other structural example of MT-CMOS technology.

Explanation of symbols

10 gate potential control circuit 11 logic circuit 12 nMOS transistor 13 pMOS transistor 14, 15, 16, 17 switch 21, 22 voltage converter (DC / DC converter)
31, 32 Voltage control circuit 91 Logic circuit 92 pMOS transistor 93 nMOS transistor 94, 95, 96, 97 switch

Claims (15)

The power switch connected between the logic circuit and the power supply is controlled in accordance with the intermittent operation of the logic circuit, the power switch is turned on to supply power to the logic circuit, and the power switch is turned off to turn on the logic circuit. In the leakage current reduction circuit that reduces the leakage current when the power supply to is stopped,
The power switch has a configuration in which an nMOS transistor and a pMOS transistor are serially connected in order from a high potential side between a positive power supply potential and a power supply terminal of the logic circuit.
When the operation of the logic circuit is stopped, the gate terminal of the nMOS transistor is set to the ground potential, and the gate terminal of the pMOS transistor is controlled to be a non-conductive state by setting the gate terminal of the pMOS transistor as a positive power supply potential. A leakage current reduction circuit comprising: a gate potential control circuit that controls a terminal to have a positive power supply potential or more and conducts the gate potential of the pMOS transistor as a ground potential. The power switch connected between the logic circuit and the power supply is controlled in accordance with the intermittent operation of the logic circuit, the power switch is turned on to supply power to the logic circuit, and the power switch is turned off to turn on the logic circuit. In the leakage current reduction circuit that reduces the leakage current when the power supply to is stopped,
The power switch has a configuration in which an nMOS transistor and a pMOS transistor are serially connected in order from a high potential side between a ground potential and a power supply terminal of the logic circuit.
When the operation of the logic circuit is stopped, the gate terminal of the nMOS transistor is set to the ground potential, and the gate terminal of the pMOS transistor is controlled to be a non-conductive state by setting the gate terminal of the pMOS transistor as a positive power supply potential. A leakage current reduction circuit comprising: a gate potential control circuit that performs control such that a terminal is set to a positive power supply potential and the gate potential of the pMOS transistor is set to a ground potential or less. The power switch connected between the logic circuit and the power supply is controlled in accordance with the intermittent operation of the logic circuit, the power switch is turned on to supply power to the logic circuit, and the power switch is turned off to turn on the logic circuit. In the leakage current reduction circuit that reduces the leakage current when the power supply to is stopped,
The power switch has a configuration in which an nMOS transistor and a pMOS transistor are serially connected in order from a high potential side between a positive power supply potential and a power supply terminal of the logic circuit.
The gate terminal of the nMOS transistor is set to the ground potential when the operation of the logic circuit is stopped by a complementary switch that complementarily turns on and off the connection between each gate terminal of the nMOS transistor and the pMOS transistor and the positive power supply potential or the ground potential. The gate terminal of the pMOS transistor is made nonconductive as a positive power supply potential, and the gate terminal of the nMOS transistor is made positive power supply potential and the gate potential of the pMOS transistor is made conductive as the ground potential when the logic circuit is operated. A leakage current reduction circuit characterized by that. The power switch connected between the logic circuit and the power supply is controlled in accordance with the intermittent operation of the logic circuit, the power switch is turned on to supply power to the logic circuit, and the power switch is turned off to turn on the logic circuit. In the leakage current reduction circuit that reduces the leakage current when the power supply to is stopped,
The power switch has a configuration in which an nMOS transistor and a pMOS transistor are serially connected in order from a high potential side between a ground potential and a power supply terminal of the logic circuit.
The gate terminal of the nMOS transistor is set to the ground potential when the operation of the logic circuit is stopped by a complementary switch that complementarily turns on and off the connection between each gate terminal of the nMOS transistor and the pMOS transistor and the positive power supply potential or the ground potential. The gate terminal of the pMOS transistor is made nonconductive as a positive power supply potential, and the gate terminal of the nMOS transistor is made positive power supply potential and the gate potential of the pMOS transistor is made conductive as the ground potential when the logic circuit is operated. A leakage current reduction circuit characterized by that. In the leakage current reduction circuit according to claim 3,
Instead of a complementary switch connected to the gate terminal of the nMOS transistor, a voltage converter in which one power supply terminal is connected to the positive power supply potential via a switch and the other power supply terminal is connected to the ground potential. connection,
The voltage converter turns off the switch when the operation of the logic circuit is stopped to turn off the gate terminal of the nMOS transistor as the ground potential, and turns on the switch when the logic circuit operates to turn on the switch of the nMOS transistor. A leakage current reduction circuit characterized in that the gate terminal is made conductive when the positive power supply potential is exceeded. The leakage current reduction circuit according to claim 4,
Instead of a complementary switch connected to the gate terminal of the pMOS transistor, a voltage converter in which one power supply terminal is connected to the positive power supply potential and the other power supply terminal is connected to the ground potential via a switch. connection,
The voltage converter turns off the switch when the operation of the logic circuit is stopped to turn off the gate terminal of the pMOS transistor as the positive power supply potential, and turns on the switch when the logic circuit is operated. A leakage current reduction circuit characterized in that a gate terminal of a transistor is made to be conductive below the ground potential. In the leakage current reduction circuit according to claim 3,
Instead of a complementary switch connected to the gate terminal of the nMOS transistor, a voltage control circuit in which one power supply terminal is connected to the positive power supply potential via a switch and the other power supply terminal is connected to the ground potential. connection,
The voltage control circuit turns off the switch when operation of the logic circuit is stopped to turn off the gate terminal of the nMOS transistor as the ground potential, turns on the switch when the logic circuit operates, and turns on the nMOS transistor. A leakage current reduction circuit characterized in that the potential of the gate terminal of the logic circuit is controlled in accordance with the potential of the power supply terminal of the logic circuit. The leakage current reduction circuit according to claim 4,
Instead of a complementary switch connected to the gate terminal of the pMOS transistor, a voltage control circuit in which one power supply terminal is connected to the positive power supply potential and the other power supply terminal is connected to the ground potential via a switch. connection,
The voltage control circuit turns off the switch when operation of the logic circuit is stopped to turn off the gate terminal of the pMOS transistor as the positive power supply potential, turns on the switch when the logic circuit operates, A leakage current reduction circuit characterized in that the potential of the gate terminal of the pMOS transistor is controlled according to the potential of the power supply terminal of the logic circuit to conduct. In the leakage current reduction circuit according to claim 3,
Instead of a complementary switch connected to the gate terminal of the nMOS transistor, a voltage converter having one power supply terminal connected to the positive power supply potential via a switch and the other power supply terminal connected to the ground potential; A voltage control circuit having one power supply terminal connected to the voltage converter and the other power supply terminal connected to the ground potential;
The voltage converter turns off the switch when the operation of the logic circuit stops and sets one power supply terminal of the voltage control circuit to the ground potential, and turns on the switch when the logic circuit operates to turn on the voltage control circuit. The one power supply terminal is configured to be equal to or higher than the positive power supply potential,
The voltage control circuit turns off the gate terminal of the nMOS transistor as the ground potential when the operation of the logic circuit is stopped, and a power supply potential higher than the positive power supply potential is supplied from the voltage converter during the operation of the logic circuit. The leakage current reduction circuit is characterized in that the potential of the gate terminal of the nMOS transistor is controlled according to the potential of the power supply terminal of the logic circuit to conduct. The leakage current reduction circuit according to claim 4,
Instead of a complementary switch connected to the gate terminal of the pMOS transistor, a voltage converter having one power supply terminal connected to the positive power supply potential and the other power supply terminal connected to the ground potential via a switch; A voltage control circuit having one power supply terminal connected to the positive power supply potential and the other power supply terminal connected to the voltage converter;
The voltage converter turns off the switch when operation of the logic circuit is stopped to set one power supply terminal of the voltage control circuit to the positive power supply potential, and turns on the switch when the logic circuit is operated. One power supply terminal of the control circuit is configured to be below the ground potential,
The voltage control circuit turns off the gate terminal of the pMOS transistor as the positive power supply potential when the operation of the logic circuit is stopped, and supplies a power supply potential equal to or lower than the ground potential from the voltage converter during the operation of the logic circuit. A leakage current reduction circuit characterized in that the potential of the gate terminal of the pMOS transistor is controlled according to the potential of the power supply terminal of the logic circuit to conduct. Two power switches connected between the logic circuit and the positive power supply potential and between the logic circuit and the ground potential are controlled in accordance with the intermittent operation of the logic circuit, and the power switch is turned on to connect to the logic circuit. In the leakage current reduction circuit that reduces the leakage current when supplying power and turning off the power switch to stop power supply to the logic circuit,
The two power switches have a configuration in which an nMOS transistor is connected between the logic circuit and a positive power supply potential, and a pMOS transistor is connected between the logic circuit and a ground potential.
When the operation of the logic circuit is stopped, the gate terminal of the nMOS transistor is set to the ground potential, and the gate terminal of the pMOS transistor is controlled to be a non-conductive state by setting the gate terminal of the pMOS transistor as a positive power supply potential. A leakage current reduction circuit comprising: a gate potential control circuit that controls a terminal to have a positive power supply potential or higher and a gate potential of the pMOS transistor to be lower than a ground potential. Two power switches connected between the logic circuit and the positive power supply potential and between the logic circuit and the ground potential are controlled in accordance with the intermittent operation of the logic circuit, and the power switch is turned on to connect to the logic circuit. In the leakage current reduction circuit that reduces the leakage current when supplying power and turning off the power switch to stop power supply to the logic circuit,
The two power switches have a configuration in which an nMOS transistor is connected between the logic circuit and a positive power supply potential, and a pMOS transistor is connected between the logic circuit and a ground potential.
The gate terminal of the nMOS transistor is set to the ground potential when the operation of the logic circuit is stopped by a complementary switch that complementarily turns on and off the connection between each gate terminal of the nMOS transistor and the pMOS transistor and the positive power supply potential or the ground potential. The gate terminal of the pMOS transistor is made nonconductive as a positive power supply potential, and the gate terminal of the nMOS transistor is made positive power supply potential and the gate potential of the pMOS transistor is made conductive as the ground potential when the logic circuit is operated. A leakage current reduction circuit characterized by that. The leakage current reduction circuit according to claim 12,
Instead of a complementary switch connected to the gate terminal of the nMOS transistor, a voltage converter in which one power supply terminal is connected to the positive power supply potential via a switch and the other power supply terminal is connected to the ground potential. connection,
The voltage converter turns off the switch when the operation of the logic circuit stops and makes the gate terminal of the nMOS transistor non-conductive with the ground potential, and turns on the switch when the logic circuit operates to turn on the gate of the nMOS transistor. A leakage current reduction circuit characterized in that the terminal is made conductive when the positive power supply potential is exceeded. The leakage current reduction circuit according to claim 12,
Instead of a complementary switch connected to the gate terminal of the pMOS transistor, a voltage converter in which one power supply terminal is connected to the positive power supply potential and the other power supply terminal is connected to the ground potential via a switch. connection,
The voltage converter turns off the switch when the operation of the logic circuit is stopped to turn off the gate terminal of the pMOS transistor as the positive power supply potential, and turns on the switch when the logic circuit is operated. A leakage current reduction circuit characterized in that the transistor has a gate terminal connected to a ground potential or less to conduct. The leakage current reduction circuit according to claim 12,
Instead of a complementary switch connected to the gate terminal of the nMOS transistor, one power supply terminal is connected to the positive power supply potential via a first switch, and the other power supply terminal is connected to the ground potential. Connect 1 voltage converter,
Instead of a complementary switch connected to the gate terminal of the pMOS transistor, one power supply terminal is connected to the positive power supply potential, and the other power supply terminal is connected to the ground potential via a second switch. Connect the voltage converter
When the operation of the logic circuit is stopped, the first and second switches are turned off, the gate terminal of the nMOS transistor is set to the ground potential, the gate terminal of the pMOS transistor is set to the positive power supply potential, and the non-conduction is performed. The first and second switches are turned on at the time of the operation, the gate terminal of the nMOS transistor is set to a positive power supply potential or higher, and the gate terminal of the pMOS transistor is set to a ground potential or lower to conduct. Leakage current reduction circuit.

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