JP2008021703A - Semiconductor device, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress erosion and redeposition of wiring due to the solar cell effect of pn junction. <P>SOLUTION: The semiconductor device is provided with a shared contact 111 that electrically connects an n-type impurity diffusion layer 106 formed on a p well 103 with a p-type impurity diffusion layer 108 formed on an n well 104. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a method for preventing metal corrosion and redeposition due to the solar cell effect of a PN junction.

  In a semiconductor process, corrosion and redeposition of a metal used for wiring, such as copper, has a great impact on performance degradation and yield reduction of a semiconductor device. The corrosion and redeposition of this metal are caused by various steps in the semiconductor process.

  FIG. 24 is a cross-sectional view showing the structure of a conventional general semiconductor device. The device shown in FIG. 24 is separated from each other by a semiconductor substrate 301, an element isolation region (STI: Shallow Trench Isolation) 302 made of an insulating film provided in a part of the semiconductor substrate 301, and an element isolation region 302 of the semiconductor substrate 301. P well 303 and N well 304 provided in the regions 300a and 300b, an Nch transistor gate electrode 305 formed on the P well 303, and a Pch transistor gate electrode 306 formed on the N well 304, respectively. And diffusion layers (source / drain) 307 provided on both sides of the gate electrode 305 of the Nch transistor in the P well 303 and diffusion layers (source / drain) provided on both sides of the gate electrode 306 of the Pch transistor in the N well 304. 308 and gate electrodes 305 and 3 6, a plurality of contacts formed in the insulating film 309 for connecting the illustrated device (that is, Nch transistor and Pch transistor) and another device to the insulating film 309 provided on the semiconductor substrate 301. 310, an insulating film 311 provided on the insulating film 309, and a wiring 312 formed in the insulating film 311 so as to be connected to each contact 310. The gate electrodes 305 and 306 are respectively formed on the semiconductor substrate 301 via the gate insulating film 321, and insulating side walls 322 are formed on the side surfaces of the gate electrodes 305 and 306, respectively.

  In the manufacturing process of the device shown in FIG. 24, the junction between the P well 303 and the N well 304 is generally exposed to light at various stages. And irradiation of the light to a PN junction part causes the corrosion and redeposition of the metal by the solar cell effect (photocell effect).

FIG. 25 is a diagram showing an outline of metal corrosion and redeposition due to the solar cell effect at the PN junction. As shown in FIG. 25, when light is applied to the junction 401 between the P well 411 and the N well 412 in the semiconductor substrate 410, electron (e) / hole (hole) pairs are generated, and the electrons enter the N well 412. The holes diffuse into the P well 411, respectively. This separation of electrons and holes causes a voltage drop at the PN junction 401, and a photovoltaic force is generated. At this time, a copper wiring 402 connected to the P well 411 via the contact 405 and a copper wiring 403 connected to the N well 412 via the contact 406 are formed in the insulating film 413 on the semiconductor substrate 410. As a result, a potential difference is generated between the copper wiring 402 and the copper wiring 403. Further, when the electrolyte 404 exists between the copper wiring 402 and the copper wiring 403 on the insulating film 413, an electrochemical reaction occurs in the copper constituting the copper wirings 402 and 403. That is, in the copper wiring 402 connected to the P well 411, an oxidation reaction (Cu → Cu ²⁺ + 2e ⁻ ) occurs, and copper is dissolved in the electrolyte 404. Thereby, corrosion of the copper wiring 402 occurs. On the other hand, in the copper wiring 403 connected to the N well 412, a reduction reaction (Cu ²⁺ + 2e ⁻ → Cu) occurs, and copper redeposition occurs. As described above, corrosion occurs in one wiring and redeposition occurs in the other wiring.

  In the semiconductor process, there are many processes in which metal corrosion and redeposition occur due to the solar cell effect of the PN junction as described above. For example, in chemical mechanical polishing (CMP) of copper or cleaning after CMP, a chemical solution used in each step acts as the electrolyte. Also, when the wafer is stored in the air with the wiring exposed, moisture in the air acts as the electrolyte, causing metal corrosion and redeposition.

  In addition, the general light which exists in a semiconductor manufacturing facility has the spectrum of the visible light region of the range of 1.7-4.0 eV. Therefore, this light can easily generate a photovoltaic force on a silicon wafer having a band gap at room temperature of about 1.2 eV at most.

As a technique for suppressing metal corrosion and redeposition described above, Patent Document 1 discloses a method for suppressing light irradiation of a PN junction by forming a photon prevention layer.
JP 2004-172617 A

  However, according to the method of Patent Document 1, there is a problem that the process technique such as embedding of the interlayer insulating film and contact etching becomes complicated and the number of steps increases by adding a new photon prevention layer.

  In view of the above, an object of the present invention is to suppress corrosion and redeposition of wiring due to photovoltaic power of a PN junction without changing the structure of an interlayer insulating film and without increasing the number of steps.

  In order to achieve the above object, a semiconductor device according to the present invention includes a first conductive type semiconductor layer and a second conductive type semiconductor layer formed adjacent to each other so as to form a junction on a substrate, and the first conductive type. An element isolation region formed on the junction in the type semiconductor layer and the second conductivity type semiconductor layer, and the first conductivity type semiconductor layer, the second conductivity type semiconductor layer, and the element isolation region. A first insulating film and a shared contact formed in the first insulating film so as to electrically connect the first conductive semiconductor layer and the second conductive semiconductor layer. .

  According to the semiconductor device of the present invention, since the shared contact for electrically connecting the first conductive type semiconductor layer and the second conductive type semiconductor layer (hereinafter referred to as the shared contact of the present invention) is provided, the following is provided. Effects can be obtained. That is, the corrosion and redeposition of the metal that constitutes the wiring electrically connected to each well, that is, the first conductive type semiconductor layer and the second conductive type semiconductor layer, are caused by the photons generated at the PN junction between the wells. Although each well is charged by electric power, in the semiconductor device of the present invention, the wells are electrically connected by the shared contact of the present invention. And since the resistance of the circuit comprised by this (henceforth the circuit of this invention) is low compared with the resistance of the electrolyte (slurry, washing | cleaning liquid, etc.) which exists between the said wiring in a semiconductor process, a solar cell effect Is caused to flow through the circuit of the present invention. Therefore, even if electric charges are generated at the PN junction due to the solar cell effect, it is possible to prevent the wiring electrically connected to each well from being charged, so that corrosion of the wiring metal and occurrence of redeposition can be prevented. it can.

  The semiconductor device of the present invention further comprises a first impurity layer formed on the first conductivity type semiconductor layer, and a second impurity layer formed on the second conductivity type semiconductor layer. The first impurity layer and the second impurity layer are separated by the element isolation region, and the shared contact electrically connects the first impurity layer and the second impurity layer, and It may be formed so as to straddle the element isolation region between the first impurity layer and the second impurity layer.

  In this way, the shared contact of the present invention can be formed in the same process as the contact connected to the source / drain, for example, and the above-described effects can be achieved without changing the structure of the interlayer insulating film and without increasing the number of processes. Can do.

  In the semiconductor device of the present invention, the first impurity layer formed on the first conductivity type semiconductor layer, the second impurity layer formed on the second conductivity type semiconductor layer, and the element isolation region The first impurity layer and the second impurity layer are separated by the element isolation region, and the first insulating film covers the dummy gate electrode. A first shared contact that electrically connects the first impurity layer and one end of the dummy gate electrode, the second impurity layer, and the dummy gate as the shared contact. A second shared contact that electrically connects the other end of the electrode may be provided.

  Thus, the first conductivity type semiconductor layer and the second conductivity type semiconductor layer can be electrically connected by the shared contact and the dummy gate electrode of the present invention (hereinafter referred to as the dummy gate electrode of the present invention). Therefore, the above effects can be achieved. In addition, since the dummy gate electrode of the present invention can be formed in the same process as the gate electrode of the transistor, for example, and the shared contact of the present invention can be formed in the same process as the contact connected to the source / drain, for example, The above effects can be achieved without changing the structure and without increasing the number of steps. Further, even when the distance between the first impurity layer and the second impurity layer is long, in other words, even when the width of the element isolation region is large, the dummy gate electrode of the present invention is used to form a gap between the wells. It can be easily electrically connected.

  In the present application, the dummy gate electrode is formed of the same material as the gate electrode (that is, the same process), but is not electrically connected to the gate electrode (that is, does not constitute a transistor).

  The semiconductor device of the present invention further includes a first impurity layer formed on the first conductivity type semiconductor layer and a second impurity layer formed on the second conductivity type semiconductor layer. The first impurity layer may be a second conductivity type impurity layer, and the second impurity layer may be a first conductivity type impurity layer. Alternatively, each of the first impurity layer and the second impurity layer may be a first conductivity type impurity layer. Alternatively, each of the first impurity layer and the second impurity layer may be a second conductivity type impurity layer.

  In the semiconductor device of the present invention, the first conductive semiconductor layer may be a P-well, and the second conductive semiconductor layer may be an N-well.

  In the semiconductor device of the present invention, a silicide layer is formed on at least one of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and the shared contact may be connected to the silicide layer. Good.

  In the semiconductor device of the present invention, a third impurity layer formed on at least one of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer is electrically connected to the third impurity layer. As described above, the first contact formed in the first insulating film, the second insulating film formed on the first insulating film, and the first contact are electrically connected. A second contact formed in the second insulating film, and a wiring formed on the second insulating film so as to be electrically connected to the second contact. Good.

  The method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a first conductive semiconductor layer and a second conductive semiconductor layer adjacent to each other so as to form a junction on a substrate, and the first conductive semiconductor. A step (b) of forming an element isolation region on the junction in the layer and the second conductivity type semiconductor layer, and so as to cover the first conductivity type semiconductor layer, the second conductivity type semiconductor layer, and the element isolation region. A step (c) of forming a first insulating film, and forming a shared contact in the first insulating film so as to electrically connect the first conductive semiconductor layer and the second conductive semiconductor layer; Step (d).

  According to the method for manufacturing a semiconductor device of the present invention, since the semiconductor device of the present invention can be manufactured, the same effects as the semiconductor device of the present invention can be obtained.

  In the method for manufacturing a semiconductor device of the present invention, the execution timing of the step (b) is not particularly limited, and may be performed, for example, before the step (a).

  In the method for manufacturing a semiconductor device of the present invention, a step (e) of forming a first impurity layer on the first conductivity type semiconductor layer after the step (b) and before the step (c); A step (f) of forming a second impurity layer on the second conductivity type semiconductor layer, wherein in the step (d), the first impurity layer and the second impurity layer are electrically connected to each other. The shared contact may be formed so as to straddle the element isolation region between the first impurity layer and the second impurity layer.

  In this way, the shared contact of the present invention can be formed in the same process as the contact for connecting the transistor and the wiring, so that the above effect can be achieved without changing the structure of the interlayer insulating film and without increasing the number of processes. Can play.

  In the method for manufacturing a semiconductor device of the present invention, a step (e) of forming a first impurity layer on the first conductivity type semiconductor layer after the step (b) and before the step (c); A step (f) of forming a second impurity layer on the second conductivity type semiconductor layer, and a step (g) of forming a dummy gate electrode on the element isolation region, wherein the step (c) Forming the first insulating film so as to cover the dummy gate electrode, and electrically connecting the first impurity layer and one end of the dummy gate electrode as the shared contact in the step (d). A first shared contact to be connected and a second shared contact to electrically connect the second impurity layer and the other end of the dummy gate electrode may be formed.

  In this way, the dummy gate electrode of the present invention can be formed in the same process as the gate electrode of the transistor, and the shared contact of the present invention can be formed in the same process as the contact for connecting the transistor and the wiring. The above effects can be achieved without changing the structure of the interlayer insulating film and without increasing the number of steps. Here, the execution timing of the step (g) is not particularly limited as long as it is after the step (b) and before the step (c). For example, it is performed before the steps (e) and (f). May be.

  In the method for manufacturing a semiconductor device of the present invention, after the step (b) and before the step (c), a third layer is formed on at least one of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. A step (h) of forming a first impurity layer, wherein in the step (c), the first insulating film is formed so as to cover the third impurity, and in the step (d), the first insulating layer is formed. A first contact electrically connected to the third impurity layer may be formed in the insulating film. In this case, after the step (d), a second insulating film is formed on the first insulating film, and then electrically connected to the first contact in the second insulating film. The method may further comprise a step (i) of forming a second contact and then forming a wiring electrically connected to the second contact on the second insulating film.

  Another semiconductor device according to the present invention includes a first conductivity type semiconductor layer and a second conductivity type semiconductor layer, which are formed adjacent to each other so as to form a junction on a substrate, and the first conductivity type semiconductor layer and the second conductivity type. An impurity layer formed on the conductive semiconductor layer; and a silicide layer formed on the impurity layer, wherein the silicide layer includes the first conductive semiconductor layer and the second conductive semiconductor layer. It is formed across the junction so as to be electrically connected.

  According to another semiconductor device of the present invention, a silicide layer (hereinafter referred to as a silicide layer of the present invention) that electrically connects the first conductivity type semiconductor layer and the second conductivity type semiconductor layer is provided. The following effects can be obtained. That is, the corrosion and redeposition of the metal that constitutes the wiring electrically connected to each well, that is, the first conductive type semiconductor layer and the second conductive type semiconductor layer, are caused by the photons generated at the PN junction between the wells. Although each well is charged by electric power, in the semiconductor device of the present invention, the wells are electrically connected by the silicide layer of the present invention. And since the resistance of the circuit comprised by this (henceforth the circuit of this invention) is low compared with the resistance of the electrolyte (slurry, washing | cleaning liquid, etc.) which exists between the said wiring in a semiconductor process, a solar cell effect Is caused to flow through the circuit of the present invention. Therefore, even if electric charges are generated at the PN junction due to the solar cell effect, it is possible to prevent the wiring electrically connected to each well from being charged, so that corrosion of the wiring metal and occurrence of redeposition can be prevented. it can.

  According to the present invention, it is possible to suppress corrosion and redeposition of wiring due to the photovoltaic power of the PN junction without changing the structure of the interlayer insulating film and without increasing the number of processes.

(First embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings. 1 to 6 are cross-sectional views showing the respective steps of the semiconductor device manufacturing method according to the first embodiment.

  First, as shown in FIG. 1, an element isolation region (specifically, STI) 102 (102a, 102b, 102c) made of an insulating film is formed on a semiconductor substrate 101, whereby the first region 100a and the first region 100a are formed. The second region 100b, the third region 100c, and the fourth region 100d are formed. In the present embodiment, the third region 100c and the fourth region 100d having a narrower region width than the first region 100a and the second region 100b are provided between the first region 100a and the second region 100b. Provide. The element isolation region 102a is narrower than the element isolation region 102b and the element isolation region 102c, and is formed between the element isolation region 102b and the element isolation region 102c. That is, an element isolation region 102a is provided between the third region 100c and the fourth region 100d, and an element isolation region 102b is provided between the first region 100a and the third region 100c. The element isolation region 102c is provided between the second region 100b and the fourth region 100d. Therefore, the third region 100c is partitioned by element isolation regions 102a and 102b, and the fourth region 100d is partitioned by element isolation regions 102a and 102c.

Next, as shown in FIG. 2, a P-type impurity such as boron (B) is applied to the first region 100a and the third region 100c, for example, at an acceleration voltage of 200 KeV and a dose of 1 × 10 ¹³ cm ⁻² . Inject with. Further, a P-type impurity such as B is implanted into the first region 100a and the third region 100c, for example, under the conditions of an acceleration voltage of 100 eV and a dose of 1 × 10 ¹³ cm ⁻² . As a result, a P well 103 having a junction depth deeper than the element isolation region 102 is formed in the first region 100a and the third region 100c. At this time, the P well 103 is also formed below the element isolation region 102b and below a part of the element isolation region 102a in the semiconductor substrate 101. Next, an N-type impurity such as phosphorus (P) is implanted into the second region 100b and the fourth region 100d, for example, under the conditions of an acceleration voltage of 400 KeV and a dose of 1.5 × 10 ¹³ cm ⁻² . Further, an N-type impurity such as P is implanted into the second region 100b and the fourth region 100d, for example, under conditions of an acceleration voltage of 200 KeV and a dose of 1.5 × 10 ¹³ cm ⁻² . As a result, an N well 104 having a junction depth deeper than that of the element isolation region 102 is formed in the second region 100b and the fourth region 100d. At this time, the N well 104 is also formed below the element isolation region 102c and below a part of the element isolation region 102a in the semiconductor substrate 101. Next, for example, annealing is performed for a short time of about 30 seconds at a temperature of about 850 ° C., thereby activating the impurities introduced by ion implantation. As a result, the P well 103 and the N well 104 form a PN junction below the element isolation region 102a.

Next, as shown in FIG. 3, N-type impurities such as As are implanted into the first region 100a and the third region 100c, for example, under conditions of an acceleration voltage of 30 KeV and a dose of 5 × 10 ¹⁵ cm ^−2. Subsequently, an N-type impurity such as P is implanted under the conditions of an acceleration voltage of 10 KeV and a dose of 1 × 10 ¹⁵ cm ⁻² , for example. As a result, an N-type impurity diffusion layer 105 is formed on the P well 103 in the first region 100a, and an N-type impurity diffusion layer 106 is formed on the P well 103 in the third region 100c.

Next, as shown in FIG. 3, a P-type impurity such as B is implanted into the second region 100b and the fourth region 100d, for example, under conditions of an acceleration voltage of 2 KeV and a dose of 5 × 10 ¹⁵ cm ^−2. . As a result, the P-type impurity diffusion layer 107 is formed on the N well 104 in the second region 100b, and at the same time, the P-type impurity diffusion layer 108 is formed on the N well 104 in the fourth region 100d.

  Each of the impurity diffusion layers 105 to 108 is isolated by the element isolation region 102.

  Next, the impurity introduced by ion implantation is activated by performing short-time annealing for about 2 seconds at a temperature of about 1000 ° C., for example.

  Next, as shown in FIG. 4, the silicide layer 120 is formed on the surface portions of the impurity diffusion layers 105 to 108, and then the insulating film 109 is formed on the semiconductor substrate 101.

  Next, as shown in FIG. 5, a plurality of holes for electrically connecting each of the N-type impurity diffusion layer 105 and the P-type impurity diffusion layer 107 and the wiring are formed in the insulating film 109, and N One hole (one hole for electrically connecting the N-type impurity diffusion layer 106 and the P-type impurity diffusion layer 108) on a part of each of the type impurity diffusion layer 106 and the P-type impurity diffusion layer 108 Form. The plurality of holes and one hole are formed through the insulating film 109 so as to reach the silicide layer 120 formed on each impurity diffusion layer. Thereafter, a plurality of contacts 110 and one shared contact 111 are formed by embedding a conductive material such as metal, such as tungsten, in each of the holes. Shared contact 111 is formed so as to straddle element isolation region 102 between N-type impurity diffusion layer 106 and P-type impurity diffusion layer 108.

  Next, as shown in FIG. 6, after forming the insulating film 112 on the insulating film 109, a region to be a wiring in the insulating film 112 is removed by etching, and the insulating film 112 including the recess formed thereby is formed. A metal film such as a copper film is deposited over the entire surface. Thereafter, the copper film protruding from the concave portion is removed by polishing, for example, by CMP, and thereby the wiring 113 electrically connected to each of the N-type impurity diffusion layer 105 and the P-type impurity diffusion layer 107 via each contact 110. Form. At this time, no wiring is formed on the shared contact 111, and the shared contact 111 remains covered with the insulating film 112.

  FIG. 7 is a diagram showing a planar configuration of the semiconductor device of this embodiment. 6 is a cross-sectional view taken along line A-A ′ of FIG. In FIG. 7, for the sake of simplicity, the element isolation region 102, the insulating film 109, the insulating film 112, the wiring 113, and the silicide layer 120 are not shown. Further, as shown in FIG. 7, the N-type impurity diffusion layer 105 serves as a source region or a drain region of the Nch transistor, and is provided on both sides of the gate electrode 121 of the Nch transistor in the P well 103. Further, the P-type impurity diffusion layer 107 becomes a source region or a drain region of the Pch transistor, and is provided on both sides of the gate electrode 122 of the Pch transistor in the N well 103.

  In the semiconductor device of this embodiment manufactured by the manufacturing method described above, the N-type impurity diffusion layer 106 formed on the P well 103 and the P-type impurity diffusion layer 108 formed on the N well 104 are electrically connected. In this case, a shared contact 111 is provided, and the following effects can be obtained. That is, the corrosion and redeposition of the metal constituting the wiring electrically connected to each well occurs when each well is charged by the photovoltaic force generated at the PN junction between the wells. According to the form, the P well 103 and the N well 104 are electrically connected by the shared contact 111. And since the resistance of the circuit comprised by this (henceforth the circuit of this invention) is low compared with the resistance of the electrolyte (slurry, washing | cleaning liquid, etc.) which exists between wiring in a semiconductor process, it is by the solar cell effect. The resulting current flows through the circuit of the present invention. Therefore, even if electric charges are generated at the PN junction due to the solar cell effect, the wiring 113 electrically connected to the P well 103 and the N well 104 can be prevented from being charged, so that corrosion of the metal constituting the wiring 113 can be prevented. And the occurrence of redeposition can be prevented.

  Further, according to the first embodiment, the impurity diffusion layers 106 and 108 in the third region 100c and the fourth region 100d can be formed in the same process as the impurity diffusion layers 105 and 107 that become the source and drain of the transistor. In addition, since the shared contact 111 can be formed in the same process as the contact 110 connected to the source / drain of the transistor, the above effect can be achieved without changing the structure of the interlayer insulating film and without increasing the number of processes. it can.

  Further, according to the first embodiment, since the element for connecting the wells is formed in the shared contact 111 forming step performed simultaneously with the contact 110 forming step, the action of the electrolyte existing between the contacts 110 and the sun Corrosion and redeposition of the metal constituting the contact 110 can be prevented from occurring due to the battery effect.

  By the way, in general, when a circuit is operated, a positive bias is applied to the N well. Then, when the semiconductor device of the first embodiment is operated as a circuit, the circuit of the present invention is always applied with a reverse bias diode (that is, a diode composed of the P well 103 and the N-type impurity diffusion layer 106, and N The diode of the well 104 and the P-type impurity diffusion layer 108 exists, and the circuit of the present invention does not affect the normal device operation. That is, the circuit of the present invention contributes to the operation of suppressing corrosion and redeposition caused by the solar cell effect generated during the semiconductor process, but does not contribute to the device operation.

  In the first embodiment, an N-type impurity diffusion layer 106 is formed on the P-well 103 and a P-type impurity diffusion layer 108 is formed on the N-well 104. The P-type impurity diffusion layer 108 was electrically connected. However, instead of this, an N-type impurity diffusion layer 106 is formed on the P-well 103, but an N-type impurity diffusion layer is formed on the N-well 104 instead of the P-type impurity diffusion layer 108, and a shared contact is formed. Even if the N-type impurity diffusion layer 106 and the N-type impurity diffusion layer on the N well 104 are electrically connected by 111, the same effect as in this embodiment can be obtained. Alternatively, a P-type impurity diffusion layer is formed on the P well 103 instead of the N-type impurity diffusion layer 106, a P-type impurity diffusion layer 108 is formed on the N well 104, and the P contact 103 is formed on the P well 103 by the shared contact 111. Even if the P-type impurity diffusion layer and the P-type impurity diffusion layer 108 are electrically connected, the same effect as in the present embodiment can be obtained.

  In the first embodiment, the arrangement position of the N-type impurity diffusion layer 106, the P-type impurity diffusion layer 108, and the shared contact 111 that connects both is the boundary region between the P well 103 and the N well 104. It is not particularly limited. That is, as long as the shared contact 111 is arranged so as to bridge the P well 103 and the N well 104, the arrangement position of the shared contact 111 is not particularly limited.

  In the first embodiment, instead of the shared contact 111, a contact connected to the N-type impurity diffusion layer 106 via the silicide layer 120 and a contact connected to the P-type impurity diffusion layer 108 via the silicide layer 120. May be formed separately, and both contacts may be electrically connected by wiring.

(Modification of the first embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a modification of the first embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment. In FIG. 8, the same components as those in the first embodiment shown in FIG. 1 to FIG.

  As shown in FIG. 8, this modification is different from the first embodiment in that an insulating film 109 and a wiring 113 on which a contact (hereinafter referred to as a first contact) 110 and a shared contact 111 are formed are provided. An insulating film 114 is formed between the insulating film 112 to be formed, and a second contact 115 that electrically connects the first contact 110 and the wiring 113 is formed in the insulating film 114. It is that.

  That is, in this modification, the shared contact 111 is formed in the same layer as the first contact 110. Therefore, according to the present modification, in addition to the same effects as those of the first embodiment, the wiring 113 is not affected by the element of the present invention, in other words, not affected by the arrangement position of the shared contact 111. Can be laid out. Specifically, in the modification, for example, the wiring 113 can be formed above the arrangement position of the shared contact 111.

(Second Embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to the drawings. 9 to 14 are cross-sectional views showing the respective steps of the semiconductor device manufacturing method according to the second embodiment.

  First, as shown in FIG. 9, an element isolation region (specifically, STI) 202 (202a, 202b, 202c) made of an insulating film is formed on a semiconductor substrate 201, whereby the first region 200a and the first region are formed. The second region 200b, the third region 200c, and the fourth region 200d are formed. In the present embodiment, the third region 200c and the fourth region 200d having a narrower region width than the first region 200a and the second region 200b are provided between the first region 200a and the second region 200b. Provide. The element isolation region 202a is wider than the element isolation region 202b and the element isolation region 202c, and is formed between the element isolation region 202b and the element isolation region 202c. That is, an element isolation region 202a is provided between the third region 200c and the fourth region 200d, and an element isolation region 202b is provided between the first region 200a and the third region 200c. An element isolation region 202c is provided between the second region 200b and the fourth region 200d. Accordingly, the third region 200c is partitioned by element isolation regions 202a and 202b, and the fourth region 200d is partitioned by element isolation regions 202a and 202c.

Next, as shown in FIG. 9, a P-type impurity such as B is implanted into the first region 200a and the third region 200c under the conditions of, for example, an acceleration voltage of 200 KeV and a dose of 1 × 10 ¹³ cm ^−2. . Further, a P-type impurity such as B is implanted into the first region 200a and the third region 200c, for example, under the conditions of an acceleration voltage of 100 eV and a dose of 1 × 10 ¹³ cm ⁻² . Thereby, a P well 203 having a junction depth deeper than the element isolation region 202 is formed in the first region 200a and the third region 200c. At this time, the P well 203 is also formed below the element isolation region 202b and below a part of the element isolation region 202a in the semiconductor substrate 201. Next, an N-type impurity such as P is implanted into the second region 200b and the fourth region 200d, for example, under conditions of an acceleration voltage of 400 KeV and a dose of 1.5 × 10 ¹³ cm ⁻² . Further, an N-type impurity such as P is implanted into the second region 200b and the fourth region 200d, for example, under the conditions of an acceleration voltage of 200 KeV and a dose of 1.5 × 10 ¹³ cm ⁻² . As a result, an N well 204 having a junction depth deeper than that of the element isolation region 202 is formed in the second region 200b and the fourth region 200d. At this time, the N well 204 is also formed below the element isolation region 202c and below a part of the element isolation region 202a in the semiconductor substrate 201. Next, for example, annealing is performed for a short time of about 30 seconds at a temperature of about 850 ° C., thereby activating the impurities introduced by ion implantation. As a result, the P well 203 and the N well 204 form a PN junction below the element isolation region 202a.

  Next, as shown in FIG. 9, for example, a silicon oxide film 205 having a thickness of 2 nm and a polysilicon film 206 having a thickness of 120 nm, for example, are sequentially deposited on the semiconductor substrate 201. The silicon oxide film 205 is for forming a gate insulating film, and the polysilicon film 206 is for forming a gate electrode of a transistor.

Next, a P-type impurity such as B ions is implanted into the polysilicon film 206 on the second region 200b under the conditions of an acceleration voltage of 5 Kev and a dose of 2 × 10 ¹⁵ cm ⁻² , for example. Next, an N-type impurity such as P ion is applied to the polysilicon film 206 on the first region 200a, the third region 200c, the fourth region 200d, and the element isolation region 202a, for example, an acceleration voltage of 15 Kev and a dose amount. Implantation is performed under conditions of 5 × 10 ¹⁵ cm ⁻² . Note that a P-type impurity may be implanted into the polysilicon film 206 on the third region 200c, the fourth region 200d, and the element isolation region 202a in the same manner as the polysilicon film 206 in the second region 200b.

  Next, as shown in FIG. 10, the polysilicon film 206 is etched by, for example, a dry etching method. As a result, the gate electrode 207 of the Nch transistor is formed on the first region 200a (P well 203) in the semiconductor substrate 201, and the gate electrode of the Pch transistor is formed on the second region 200b (N well 204) in the semiconductor substrate 201. 208 is formed, and a dummy gate electrode 209 is formed on the element isolation region 202a between the third region 200c and the fourth region 200d. Here, a gate insulating film 231 made of a silicon oxide film 205 is formed below each of the gate electrodes 207 and 208 and the dummy gate electrode 209. Note that the gate insulating film 231 is not necessarily formed under the dummy gate electrode 209. Thereafter, a silicon nitride film having a thickness of, for example, 50 nm is formed on the semiconductor substrate 201 by, eg, CVD (chemical vapor deposition), and then the silicon nitride film is etched back by, eg, dry etching. An insulating sidewall 210 is formed on the side surfaces of the gate electrodes 207 and 208 and the dummy gate electrode 209.

Next, as shown in FIG. 11, N-type impurities such as As are implanted into the first region 200a and the third region 200c, for example, under the conditions of an acceleration voltage of 30 KeV and a dose of 5 × 10 ¹⁵ cm ^−2. Subsequently, an N-type impurity such as P is implanted under the conditions of an acceleration voltage of 10 KeV and a dose of 1 × 10 ¹⁵ cm ⁻² , for example. As a result, N-type source / drain regions 211 are formed on both sides of the gate electrode 207 in the first region 200 a of the semiconductor substrate 201, and at the same time, an N-type impurity diffusion layer 212 is formed in the third region 200 c of the semiconductor substrate 201. It is formed.

Next, as shown in FIG. 11, a P-type impurity such as B is implanted into the second region 200b and the fourth region 200d, for example, under the conditions of an acceleration voltage of 2 KeV and a dose of 5 × 10 ¹⁵ cm ^−2. . As a result, P-type source / drain regions 213 are formed on both sides of the gate electrode 208 in the second region 200b of the semiconductor substrate 201, and at the same time, a P-type impurity diffusion layer 214 is formed in the fourth region 200d of the semiconductor substrate 201. It is formed. The N-type impurity diffusion layer 212 and the P-type impurity diffusion layer 214 are separated by the element isolation region 202a, and the N-type source / drain region 211 and the N-type impurity diffusion layer 212 are separated by the element isolation region 202b. The source / drain region 213 and the P-type impurity diffusion layer 214 are separated by an element isolation region 202c.

  Next, the impurity introduced by ion implantation is activated by performing short-time annealing for about 2 seconds at a temperature of about 1000 ° C., for example.

  Next, as shown in FIG. 11, an N-type source / drain region 211 and a P-type source / drain region 213, an N-type impurity diffusion layer 212 and a P-type impurity diffusion layer 214, gate electrodes 207 and 208, and a dummy gate electrode A silicide layer 232 is formed on each surface portion of 209.

  Next, as illustrated in FIG. 12, an insulating film 215 is formed over the semiconductor substrate 201.

  Next, as shown in FIG. 13, in the insulating film 215, a plurality of contacts 216 that electrically connect each of the N-type source / drain region 211 and the P-type source / drain region 213 and the wiring, and the N-type A shared contact 217 that electrically connects the impurity diffusion layer 212 and the dummy gate electrode 209 and a shared contact 218 that electrically connects the P-type impurity diffusion layer 214 and the dummy gate electrode 209 are formed. The plurality of contacts 216 and shared contacts 217 and 218 are formed so as to penetrate the insulating film 215 so as to reach the silicide layer 232 formed on each impurity diffusion layer.

  Specifically, a plurality of holes reaching each of the silicide layer 232 on the N-type source / drain region 211 and the P-type source / drain region 213, a part of the silicide layer 232 on the N-type impurity diffusion layer 212, and a dummy gate electrode After forming one hole reaching a part of 209 and one hole reaching a part of the silicide layer 232 on the P-type impurity diffusion layer 214 and a part of the dummy gate electrode 209 in the insulating film 215, Contacts 216 and shared contacts 217 and 218 are formed by embedding a conductive material such as metal, for example, tungsten. Each of the shared contacts 217 and 218 is formed so as to straddle the insulating sidewall 210 formed on the side surface of the dummy gate electrode 209.

  Next, as shown in FIG. 14, after the insulating film 219 is formed on the insulating film 215, a region to be a wiring in the insulating film 219 is removed by etching, and the insulating film 219 including a recess formed thereby is formed. A metal film such as a copper film is deposited over the entire surface. Thereafter, the copper film protruding from the concave portion is removed by polishing, for example, by CMP, so that the N-type source / drain region 211 and the P-type source / drain region 213 are electrically connected to each other through the contacts 216 and the silicide layer 232. Wiring 220 to be connected is formed.

  FIG. 15 is a diagram showing a planar configuration of the semiconductor device of this embodiment. 14 is a cross-sectional view taken along line B-B ′ of FIG. In FIG. 15, for the sake of simplicity, the dimensions of some of the components are changed as compared with FIG. 14, and the element isolation region 202, the insulating sidewall 210, the insulating film 215, the insulating film 219, the wiring Illustration of 220 and the silicide layer 232 is omitted.

  The semiconductor device of this embodiment manufactured by the manufacturing method described above includes an N-type impurity diffusion layer 212 formed on the P well 203 and a P-type impurity diffusion layer 214 formed on the N well 204. A dummy gate electrode 209 is formed on the element isolation region 202a to be isolated, and a shared contact 217 that electrically connects the dummy gate electrode 209 and each of the N-type impurity diffusion layer 212 and the P-type impurity diffusion layer 214, and The following effects can be obtained. That is, the corrosion and redeposition of the metal constituting the wiring electrically connected to each well occurs when each well is charged by the photovoltaic force generated at the PN junction between the wells. According to the embodiment, the P well 203 and the N well 204 are electrically connected by the dummy gate electrode 209 and the shared contacts 217 and 218. And since the resistance of the circuit comprised by this (henceforth the circuit of this invention) is low compared with the resistance of the electrolyte (slurry, washing | cleaning liquid, etc.) which exists between wiring in a semiconductor process, it is by the solar cell effect. The resulting current flows through the circuit of the present invention. Therefore, even if electric charges are generated at the PN junction due to the solar cell effect, the wiring 220 electrically connected to the P well 203 and the N well 204 can be prevented from being charged. And the occurrence of redeposition can be prevented.

  Further, according to the second embodiment, even when the distance between the N-type impurity diffusion layer 212 and the P-type impurity diffusion layer 214 is long, in other words, the N-type impurity diffusion layer 212 and the P-type impurity diffusion layer 214. The P well 203 and the N well 204 can be easily electrically connected using the dummy gate electrode 209 even when the width of the element isolation region 202a that isolates the two is large.

  According to the second embodiment, the N-type impurity diffusion layer 212 in the third region 200c and the P-type impurity diffusion layer 214 in the fourth region 200d are respectively an N-type source / drain region 211 and a P-type source / drain region. The drain region 213 can be formed in the same process, the dummy gate electrode 209 can be formed in the same process as the gate electrodes 207 and 208, and the shared contacts 217 and 218 are contacts 216 connected to the source / drain regions 211 and 213. Therefore, the above-described effects can be obtained without changing the structure of the interlayer insulating film and without increasing the number of steps.

  In addition, according to the second embodiment, the element that connects the wells is formed in the formation process of the shared contacts 217 and 218 performed at the same time as the formation process of the contact 216, so that the action of the electrolyte existing between the contacts 216 is formed. Corrosion and redeposition of the metal constituting the contact 216 can be prevented due to the solar cell effect.

  By the way, in general, when a circuit is operated, a positive bias is applied to the N well. Then, when the semiconductor device of the second embodiment is operated as a circuit, a reverse bias is always applied to the circuit of the present invention (that is, a diode including the P well 203 and the N-type impurity diffusion layer 212, and N The diode of the well 204 and the P-type impurity diffusion layer 214 is present, and the circuit of the present invention does not affect the normal device operation. That is, the circuit of the present invention contributes to the operation of suppressing corrosion and redeposition caused by the solar cell effect generated during the semiconductor process, but does not contribute to the device operation.

  In the second embodiment, an N-type impurity diffusion layer 212 is formed on the P well 203 and a P-type impurity diffusion layer 214 is formed on the N well 204, and the shared contacts 217 and 218 and the dummy gate electrode 209 are used. The N-type impurity diffusion layer 212 and the P-type impurity diffusion layer 214 were electrically connected. However, instead of this, an N-type impurity diffusion layer 212 is formed on the P-well 203, but an N-type impurity diffusion layer is formed on the N-well 204 in place of the P-type impurity diffusion layer 214, and a shared contact is formed. Even if the dummy gate electrode 209 and the N-type impurity diffusion layer on the N well 204 are electrically connected by 218, the same effect as in the present embodiment can be obtained. Alternatively, a P-type impurity diffusion layer is formed on the P well 203 instead of the N-type impurity diffusion layer 212, a P-type impurity diffusion layer 214 is formed on the N well 204, and the P contact 203 is formed on the P well 203 by the shared contact 217. Even if the P-type impurity diffusion layer and the dummy gate electrode 209 are electrically connected, the same effect as in the present embodiment can be obtained.

  In the second embodiment, the N-type impurity diffusion layer 212 and the P-type impurity diffusion layer 214, the shared contacts 217 and 218, and the dummy gate electrode 209 are arranged at the boundary region between the P well 203 and the N well 204. If there is, it will not be specifically limited. That is, as long as the dummy gate electrode 209 is arranged so as to bridge the P well 203 and the N well 204, the arrangement position of the dummy gate electrode 209 is not particularly limited.

(Modification of the second embodiment)
Hereinafter, a semiconductor device and a method for manufacturing the same according to a modification of the second embodiment of the present invention will be described with reference to the drawings. FIG. 16 is a cross-sectional view of a semiconductor device according to a modification of the second embodiment. In FIG. 16, the same components as those of the second embodiment shown in FIGS.

  As shown in FIG. 16, this modification is different from the second embodiment in that the contact (hereinafter referred to as the first contact) 216 and the insulating film 215 on which the shared contacts 217 and 218 are formed, and the wiring The insulating film 221 is formed between the insulating film 219 and the second contact 222 that electrically connects the first contact 216 and the wiring 220 in the insulating film 221. It is formed.

  That is, in this modification, the shared contacts 217 and 218 are formed in the same layer as the first contact 216. Therefore, according to the present modification, in addition to the same effects as those of the second embodiment, the influence of the arrangement of the shared contacts 217 and 218 and the dummy gate electrode 209 is not affected by the element of the present invention. Thus, the effect that the wiring 220 can be laid out can be obtained. Specifically, in the modification, for example, the wiring 220 can be formed above the arrangement position of the dummy gate electrode 209.

(Third embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a third embodiment of the present invention will be described with reference to the drawings. 17 to 22 are cross-sectional views illustrating the steps of the method of manufacturing a semiconductor device according to the third embodiment.

  First, as shown in FIG. 17, an element isolation region (specifically, STI) 102 (102b, 102c) made of an insulating film is formed on a semiconductor substrate 101, whereby the first region 100a and the second region are formed. The region 100b and the third region 100c are formed. In the present embodiment, a third region 100c having a narrower region width than the first region 100a and the second region 100b is provided between the first region 100a and the second region 100b. That is, an element isolation region 102b is provided between the first region 100a and the third region 100c, and an element isolation region 102c is provided between the second region 100b and the third region 100c. It has been. Accordingly, the third region 100c is partitioned by the element isolation regions 102b and 102c.

Next, as shown in FIG. 18, a P-type impurity such as boron (B) is applied to a part of the first region 100a and the third region 100c, for example, an acceleration voltage of 200 KeV and a dose of 1 × 10 ¹³ cm ^−2. Inject under the conditions of Further, a P-type impurity such as B is implanted into a part of the first region 100a and the third region 100c, for example, under the conditions of an acceleration voltage of 100 eV and a dose of 1 × 10 ¹³ cm ⁻² . As a result, a P well 103 having a junction depth deeper than that of the element isolation region 102 is formed in a part of the first region 100a and the third region 100c. At this time, the P well 103 is also formed below the element isolation region 102 b in the semiconductor substrate 101. Next, an N-type impurity such as phosphorus (P) is applied to other portions of the second region 100b and the third region 100c under the conditions of, for example, an acceleration voltage of 400 KeV and a dose of 1.5 × 10 ¹³ cm ⁻² . inject. Further, N-type impurities such as P are implanted into other parts of the second region 100b and the third region 100c, for example, under the conditions of an acceleration voltage of 200 KeV and a dose of 1.5 × 10 ¹³ cm ⁻² . As a result, an N well 104 having a junction depth deeper than that of the element isolation region 102 is formed in other portions of the second region 100b and the third region 100c. At this time, the N well 104 is also formed below the element isolation region 102 c in the semiconductor substrate 101. Next, for example, annealing is performed for a short time of about 30 seconds at a temperature of about 850 ° C., thereby activating the impurities introduced by ion implantation. As a result, the P well 103 and the N well 104 are adjacent to each other in the third region 100c to form a PN junction.

Next, as shown in FIG. 19, an N-type impurity such as As is implanted into the first region 100a and the third region 100c, for example, under the conditions of an acceleration voltage of 30 KeV and a dose of 5 × 10 ¹⁵ cm ^−2. Subsequently, an N-type impurity such as P is implanted under the conditions of an acceleration voltage of 10 KeV and a dose of 1 × 10 ¹⁵ cm ⁻² , for example. As a result, an N-type impurity diffusion layer 105 is formed on the P well 103 in the first region 100a, and an N-type impurity diffusion layer 106 is formed on the P well 103 and the N well in the third region 100c. The

Next, as shown in FIG. 19, a P-type impurity such as B is implanted into the second region 100b under the conditions of, for example, an acceleration voltage of 2 KeV and a dose of 5 × 10 ¹⁵ cm ⁻² . As a result, a P-type impurity diffusion layer 107 is formed on the N well 104 in the second region 100b.

  Each of the impurity diffusion layers 105 to 107 is isolated by the element isolation region 102.

  Next, the impurity introduced by ion implantation is activated by performing short-time annealing for about 2 seconds at a temperature of about 1000 ° C., for example.

  Next, as shown in FIG. 20, silicide layers 120 (120 a, 120 b, 120 c) are formed on the respective surface portions of the impurity diffusion layers 105 to 107, and then an insulating film 109 is formed on the semiconductor substrate 101.

  Next, as shown in FIG. 21, a plurality of holes for electrically connecting each of the N-type impurity diffusion layer 105 and the P-type impurity diffusion layer 107 and the wiring are formed in the insulating film 109. The plurality of holes are formed through the insulating film 109 so as to reach the silicide layer 120a formed on the N-type impurity diffusion layer 105 and the silicide layer 120b formed on the P-type impurity diffusion layer 107. ing. Thereafter, a plurality of contacts 110 are formed by embedding a conductive material such as metal, for example, tungsten in each of the holes.

  Next, as shown in FIG. 22, after the insulating film 112 is formed on the insulating film 109, a region to be a wiring in the insulating film 112 is removed by etching, and the insulating film 112 including a recess formed thereby is formed. A metal film such as a copper film is deposited over the entire surface. Thereafter, the copper film protruding from the concave portion is removed by polishing, for example, by CMP, and thereby the wiring 113 electrically connected to each of the N-type impurity diffusion layer 105 and the P-type impurity diffusion layer 107 via each contact 110. Form.

  FIG. 23 is a diagram illustrating a planar configuration of the semiconductor device of the present embodiment. FIG. 22 is a sectional view taken along line C-C ′ of FIG. In FIG. 23, for simplicity, the element isolation region 102, the insulating film 109, the insulating film 112, the wiring 113, and the silicide layer 120 (except for the silicide layer 120c in the third region 100c) are not shown. . As shown in FIG. 23, the N-type impurity diffusion layer 105 serves as a source region or a drain region of the Nch transistor, and is provided on both sides of the gate electrode 121 of the Nch transistor in the P well 103. Further, the P-type impurity diffusion layer 107 becomes a source region or a drain region of the Pch transistor, and is provided on both sides of the gate electrode 122 of the Pch transistor in the N well 103.

  In the semiconductor device of this embodiment manufactured by the manufacturing method described above, the N-type impurity diffusion layer 106 formed on the P well 103 and the N-type impurity diffusion layer 106 formed on the N well 104 are electrically connected. The third region 100c is provided with a silicide layer 120c that is electrically connected, and the following effects can be obtained. That is, the corrosion and redeposition of the metal constituting the wiring electrically connected to each well occurs when each well is charged by the photovoltaic force generated at the PN junction between the wells. According to the form, the P well 103 and the N well 104 are electrically connected by the silicide layer 120c. And since the resistance of the circuit comprised by this (henceforth the circuit of this invention) is low compared with the resistance of the electrolyte (slurry, washing | cleaning liquid, etc.) which exists between wiring in a semiconductor process, it is by the solar cell effect. The resulting current flows through the circuit of the present invention. Therefore, even if electric charges are generated at the PN junction due to the solar cell effect, the wiring 113 electrically connected to the P well 103 and the N well 104 can be prevented from being charged, so that corrosion of the metal constituting the wiring 113 can be prevented. And the occurrence of redeposition can be prevented.

  Further, according to the third embodiment, the impurity diffusion layer 106 in the third region 100c can be formed in the same process as the impurity diffusion layer 105 serving as the source / drain of the transistor, and the silicide layer 120c is formed from the impurity of the transistor. Since it can be formed in the same process as the silicide layers 120a and 120b formed on the diffusion layers 105 and 107, the above-described effects can be achieved without changing the structure of the interlayer insulating film and without increasing the number of processes.

  Further, according to the third embodiment, since the element for connecting the wells is formed in the formation process of the silicide layer 120c performed simultaneously with the formation process of the silicide layers 120a and 120b before forming the contact 110, the contact is formed. Corrosion and redeposition of the metal constituting contact 110 can be prevented by the action of the electrolyte existing between 110 and the solar cell effect.

  By the way, in general, when a circuit is operated, a positive bias is applied to the N well. Then, when the semiconductor device of the third embodiment is operated as a circuit, the above-described circuit of the present invention always includes a diode to which a reverse bias is applied (that is, a diode composed of the P well 103 and the N-type impurity diffusion layer 106). Therefore, the circuit of the present invention does not affect normal device operation. That is, the circuit of the present invention contributes to the operation of suppressing corrosion and redeposition caused by the solar cell effect generated during the semiconductor process, but does not contribute to the device operation.

  In the third embodiment, the N-type impurity diffusion layer 106 is formed on the P well 103 and the N-type impurity diffusion layer 106 is formed on the N well 104 in the third region 100c. The N-type impurity diffusion layer 106 on the P well 103 and the N-type impurity diffusion layer 106 on the N well 104 were electrically connected. However, instead of this, in the third region 100c, a P-type impurity diffusion layer is formed in place of the N-type impurity diffusion layer 106 on each of the P well 103 and the N well 104, and the P well is formed by the silicide layer 120c. Even if the P-type impurity diffusion layer on 103 and the P-type impurity diffusion layer on the N well 104 are electrically connected, the same effect as in this embodiment can be obtained.

  Further, in the third embodiment, the arrangement position of the silicide layer 120 c that connects the N-type impurity diffusion layer 106 on the P well 103 and the N-type impurity diffusion layer 106 on the N well 104 is arranged as follows. Is not particularly limited. That is, the position of the silicide layer 120c is not particularly limited as long as the silicide layer 120c is disposed so as to straddle the junction between the P well 103 and the N well 104.

  As described above, the present invention relates to a semiconductor device and a manufacturing method thereof, and is particularly useful as a technique for preventing metal corrosion and redeposition due to the solar cell effect of a PN junction.

FIG. 1 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 7 is a plan view of the semiconductor device according to the first embodiment of the present invention. FIG. 8 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment of the present invention. FIG. 9 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 10 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 11 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 12 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 13 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 14 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 15 is a plan view of a semiconductor device according to the second embodiment of the present invention. FIG. 16 is a cross-sectional view of a semiconductor device according to a modification of the second embodiment of the present invention. FIG. 17 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 18 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 19 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 20 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 21 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 22 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 23 is a plan view of a semiconductor device according to the third embodiment of the present invention. FIG. 24 is a cross-sectional view of a conventional semiconductor device. FIG. 25 is a diagram showing an outline of metal corrosion and redeposition due to the solar cell effect at the PN junction.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100a 1st area | region 100b 2nd area | region 100c 3rd area | region 100d 4th area | region 101 Semiconductor substrate 102 (102a, 102b, 102c) Element isolation area 103 P well 104 N well 105 N type impurity diffusion layer 106 N type impurity Diffusion layer 107 P-type impurity diffusion layer 108 P-type impurity diffusion layer 109 Insulating film 110 Contact (first contact)
111 Shared contact 112 Insulating film 113 Wiring 114 Insulating film 115 Contact (second contact)
120 (120a, 120b, 120c) Silicide layer 121, 122 Gate electrode 200a First region 200b Second region 200c Third region 200d Fourth region 201 Semiconductor substrate 202 (202a, 202b, 202c) Element isolation region 203 P well 204 N well 205 Silicon oxide film 206 Polysilicon film 207, 208 Gate electrode 209 Dummy gate electrode 210 Insulating sidewall 211 N type source / drain region 212 N type impurity diffusion layer 213 P type source / drain region 214 P type Impurity diffusion layer 215 Insulating film 216 Contact (first contact)
217, 218 Shared contact 219 Insulating film 220 Wiring 221 Insulating film 222 Contact (second contact)
231 Gate insulating film 232 Silicide layer

Claims (16)

A first conductivity type semiconductor layer and a second conductivity type semiconductor layer formed adjacent to each other to form a bond on the substrate;
An element isolation region formed on the junction in the first conductivity type semiconductor layer and the second conductivity type semiconductor layer;
A first insulating film formed to cover the first conductive semiconductor layer, the second conductive semiconductor layer, and the element isolation region;
A semiconductor device comprising: a shared contact formed in the first insulating film so as to electrically connect the first conductive semiconductor layer and the second conductive semiconductor layer. The semiconductor device according to claim 1,
A first impurity layer formed on the first conductivity type semiconductor layer;
A second impurity layer formed on the second conductivity type semiconductor layer,
The first impurity layer and the second impurity layer are separated by the element isolation region;
The shared contact electrically connects the first impurity layer and the second impurity layer and straddles the element isolation region between the first impurity layer and the second impurity layer. A semiconductor device characterized in that the semiconductor device is formed. The semiconductor device according to claim 1,
A first impurity layer formed on the first conductivity type semiconductor layer;
A second impurity layer formed on the second conductivity type semiconductor layer;
A dummy gate electrode formed on the element isolation region;
The first impurity layer and the second impurity layer are separated by the element isolation region;
The first insulating film is formed so as to cover the dummy gate electrode,
As the shared contact, a first shared contact that electrically connects the first impurity layer and one end of the dummy gate electrode, and a second impurity layer and the other end of the dummy gate electrode, A semiconductor device, wherein a second shared contact for electrical connection is provided. The semiconductor device according to claim 2 or 3,
The first impurity layer is a second conductivity type impurity layer;
The semiconductor device, wherein the second impurity layer is a first conductivity type impurity layer. The semiconductor device according to claim 2 or 3,
The semiconductor device, wherein each of the first impurity layer and the second impurity layer is a first conductivity type impurity layer. The semiconductor device according to claim 2 or 3,
The semiconductor device, wherein each of the first impurity layer and the second impurity layer is a second conductivity type impurity layer. The semiconductor device according to any one of claims 1 to 6,
The semiconductor device according to claim 1, wherein the first conductivity type semiconductor layer is a P-well. In the semiconductor device according to claim 1,
The semiconductor device according to claim 2, wherein the second conductivity type semiconductor layer is an N well. The semiconductor device according to any one of claims 1 to 8,
A silicide layer is formed on at least one of the first conductive semiconductor layer and the second conductive semiconductor layer;
The semiconductor device according to claim 1, wherein the shared contact is connected to the silicide layer. The semiconductor device according to any one of claims 1 to 9,
A third impurity layer formed on at least one of the first conductive semiconductor layer and the second conductive semiconductor layer;
A first contact formed in the first insulating film so as to be electrically connected to the third impurity layer;
A second insulating film formed on the first insulating film;
A second contact formed in the second insulating film so as to be electrically connected to the first contact;
The semiconductor device further comprising: a wiring formed on the second insulating film so as to be electrically connected to the second contact. Forming a first conductive semiconductor layer and a second conductive semiconductor layer adjacent to each other so as to form a bond on the substrate;
Forming an element isolation region on the junction in the first conductivity type semiconductor layer and the second conductivity type semiconductor layer (b);
Forming a first insulating film so as to cover the first conductive semiconductor layer, the second conductive semiconductor layer, and the element isolation region;
And (d) forming a shared contact in the first insulating film so as to electrically connect the first conductive semiconductor layer and the second conductive semiconductor layer. Semiconductor device. In the manufacturing method of the semiconductor device according to claim 11,
After the step (b) and before the step (c), a step (e) of forming a first impurity layer on the first conductive type semiconductor layer, and a second step on the second conductive type semiconductor layer. A step (f) of forming an impurity layer of 2;
In the step (d), the element isolation region between the first impurity layer and the second impurity layer is electrically connected to the first impurity layer and the second impurity layer. The shared contact is formed so as to straddle the semiconductor device. In the manufacturing method of the semiconductor device according to claim 11,
After the step (b) and before the step (c), a step (e) of forming a first impurity layer on the first conductive type semiconductor layer, and a second step on the second conductive type semiconductor layer. A step (f) of forming a second impurity layer, and a step (g) of forming a dummy gate electrode on the element isolation region,
In the step (c), the first insulating film is formed so as to cover the dummy gate electrode,
In the step (d), as the shared contact, a first shared contact that electrically connects the first impurity layer and one end of the dummy gate electrode, the second impurity layer, and the dummy gate A method of manufacturing a semiconductor device, comprising: forming a second shared contact that electrically connects the other end of the electrode. In the manufacturing method of the semiconductor device of any one of Claims 11-13,
Step (h) of forming a third impurity layer on at least one of the first conductive type semiconductor layer and the second conductive type semiconductor layer after the step (b) and before the step (c). Further comprising
In the step (c), the first insulating film is formed so as to cover the third impurity,
In the step (d), a first contact that is electrically connected to the third impurity layer is formed in the first insulating film. In the manufacturing method of the semiconductor device according to claim 14,
After the step (d), a second insulating film is formed on the first insulating film, and then the second insulating film is electrically connected to the first contact in the second insulating film. A method of manufacturing a semiconductor device, further comprising a step (i) of forming a contact and then forming a wiring electrically connected to the second contact on the second insulating film . A first conductivity type semiconductor layer and a second conductivity type semiconductor layer formed adjacent to each other to form a bond on the substrate;
An impurity layer formed on the first conductive semiconductor layer and the second conductive semiconductor layer;
A silicide layer formed on the impurity layer,
The semiconductor device, wherein the silicide layer is formed across the junction so as to electrically connect the first conductivity type semiconductor layer and the second conductivity type semiconductor layer.

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