JP2008004696A - Interconnection structure for connection and its manufacturing method, solid-state imaging apparatus, method of manufacturing the same, and electronic information equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent defects such as disconnection by lowering the aspect ratio of a contact hole, and improving the embeddability of an interconnection layer for connection without forming an interlayer insulation film in a portion which needs no formation thereof by forming the interlayer insulation film again as in a conventional manner. <P>SOLUTION: In forming contact holes 33a-33c in the interlayer insulation film 6a above electrode interconnections 3a-3c, respectively, such portions that are expected to have a high aspect ratio are selected and etched in advance to make the interlayer insulation film in those portions thin. The portions that are expected to have a high aspect ratio are the contact hole above the electrode interconnection 3b which will become a reduced pattern and the contact hole above the electrode interconnection 3c, and nearby which will become a portion having a large difference in level. Thereafter, etching is conducted again to form the contact holes in the interlayer insulation film. In this case, the most upper layer of the interlayer insulation film consists of a melting material layer. Prior to melting of a BPSG film 6 as the melting material layer, the portion 3c having a large difference in level and the portion having a reduced pattern are etched in advance to make the interlayer insulation film in those portions thin. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a connection wiring structure in which a connection wiring for electrically connecting a device electrode and a peripheral circuit is provided on an interlayer insulation film through a contact hole provided in the interlayer insulation film, and manufacturing of the connection wiring structure Method, manufacturing method of solid-state imaging device using the same, solid-state imaging device manufactured by the manufacturing method of the solid-state imaging device, and, for example, a digital video camera and a digital still using the solid-state imaging device as an image input device in an imaging unit The present invention relates to an electronic information device such as a digital camera such as a camera, an image input camera, a scanner, a facsimile, and a camera-equipped mobile phone device.

  In this type of conventional solid-state imaging device, for example, as in Patent Document 1, an interlayer insulating film is provided on a light receiving portion and a charge readout portion that reads signal charges from the light receiving portion, and is provided on the interlayer insulating film. Via the contact hole, the gate electrode or drain region constituting the charge readout portion and its peripheral circuit are connected by a connection wiring.

  In the conventional method for manufacturing a solid-state imaging device disclosed in Patent Document 1, a portion where a contact hole is formed in an interlayer insulating film and a portion adjacent to a wiring are thinned by etching in advance. The processing start height is set at a low position. As a result, the etching amount of the contact hole can be reduced during the subsequent etching process, and the aspect ratio (for example, the ratio of width to height) of the contact hole can be reduced. This makes it difficult for defects such as disconnection to occur in the subsequent metal wiring formation process.

  Hereinafter, a method for manufacturing this type of conventional solid-state imaging device will be described in detail with reference to FIG.

  FIG. 4A to FIG. 4D are longitudinal sectional views of main parts for explaining a connection wiring process of the conventional solid-state imaging device.

  First, as shown in FIG. 4A, an electrode wiring 13 made of polysilicon is formed on a silicon (Si) substrate 11 via a gate insulating film 12, and the surface thereof is oxidized, for example, so that an interlayer insulating film 14 is formed. Form. After the interlayer insulating film 15 is formed by deposition so as to cover the silicon substrate 11, a resist pattern 21 having a predetermined shape with an opening 21a is formed in order to etch the interlayer insulating film 15 on the electrode wiring 13. To do.

  Next, as shown in FIG. 4B, the interlayer insulating film 15 on the electrode wiring 13 is partially removed by etching to leave only the side wall portion 15a of the electrode wiring 13, and the resist pattern 21 is stripped. An interlayer insulating film 16 made of another material is formed on the substrate portion.

  Further, as shown in FIG. 4C, a resist pattern 22 having a predetermined shape having an opening 22a is formed on the interlayer insulating film 16, and the interlayer insulating film 14 on the electrode wiring 3 is removed by etching. A contact hole 20 reaching the wiring 13 is formed.

  Thereafter, as shown in FIG. 4D, metal wirings 17 to 19 are formed in this order on the interlayer insulating film 16 in which the contact holes 20 are formed, and electrode wirings are formed via these metal wirings 17 to 19. 13 and its peripheral circuit (not shown) are connected.

  In this way, connection wiring layers (metal wirings 17 to 19) of the conventional solid-state imaging device 10 are formed.

According to the above connection wiring process, the portion of the contact hole 20 to be processed in advance is thinned by etching, and the interlayer insulating film 16 having an appropriate film thickness is formed again, thereby reducing the aspect ratio of the contact hole 20. can do. Thereby, the embedding property of the metal wirings 17 to 19 to be formed later can be improved, and disconnection in the middle of the wiring layer can be reduced.
Japanese Patent Laid-Open No. 7-169928

  However, the conventional method for manufacturing the solid-state imaging device 10 has the following problems.

  That is, as shown in FIG. 4C, after the interlayer insulating film 15 at the contact hole forming portion is removed by etching and partially thinned, and the interlayer insulating film 16 is formed again, the light receiving in the solid-state imaging device 10 is performed. There arises a problem that the interlayer insulating film 16 is also formed on the part.

  The present invention solves the above-described conventional problems, and reduces the aspect ratio of the contact hole without forming an interlayer insulating film again in an unnecessary portion by re-forming the interlayer insulating film as in the prior art. Connection wiring structure capable of improving the embedding property of the connection wiring layer and preventing problems such as disconnection, a method of manufacturing the connection wiring structure, a method of manufacturing a solid-state imaging device using the same, and a method of manufacturing the solid-state imaging device An object of the present invention is to provide a solid-state imaging device manufactured by the above and an electronic information device using the solid-state imaging device as an imaging unit.

  In the connection wiring structure of the present invention, an interlayer insulating film is provided so as to cover a substrate on which a plurality of electrode wirings are provided, and the electrode wiring is electrically connected via a contact hole provided in the interlayer insulating film. In the connection wiring structure in which the connection wiring layer to be connected is provided on the interlayer insulating film, the portion where the aspect ratio of the contact hole is expected to be higher than a predetermined value is higher than the other portions. The film is configured to have a thin thickness, thereby achieving the above object.

  Preferably, the predetermined value of the aspect ratio in the connection wiring structure of the present invention is a numerical value of 1.05 or less and not including 0.

  Further preferably, in the connection wiring structure of the present invention, the portion where the aspect ratio is expected to be higher than a predetermined value is a portion where the step is a predetermined value or more and a portion where the contact hole pattern size is smaller than the predetermined value. At least one.

  Still preferably, in the connection wiring structure of the present invention, the plurality of contact holes reaching the electrode wiring include at least one contact hole reaching the substrate.

  Further preferably, the uppermost layer of the interlayer insulating film in the connection wiring structure of the present invention is formed of a molten material layer made of a material that is melted by heat treatment.

  Further preferably, the molten material layer in the connection wiring structure of the present invention is configured such that the portion where the aspect ratio is expected to be high is configured thinner or removed than the other portions and subjected to the heat treatment. Yes.

  More preferably, the molten material layer in the connection wiring structure of the present invention is a BPSG (boron / phosphorus / silica gate / glass) film.

  Further preferably, in the connection wiring structure of the present invention, the BPSG film is selectively thinned by an etching process.

  The method for manufacturing a wiring structure for connection according to the present invention includes an interlayer insulating film forming step of forming an interlayer insulating film so as to cover a substrate provided with a plurality of electrode wirings, and an aspect ratio of the contact hole is higher than a predetermined value. An etching process for reducing the thickness of the interlayer insulating film by previously etching a portion expected to be formed, and forming a contact hole reaching the electrode wiring by performing an etching process on a predetermined portion of the thinned interlayer insulating film A contact hole forming step, a connection wiring layer forming step of forming a connection wiring layer on the interlayer insulating film, and electrically connecting the connection wiring layer and the electrode wiring through the contact hole; This achieves the above object.

  Preferably, the predetermined value of the aspect ratio in the method for manufacturing a connection wiring structure of the present invention is a numerical value that is 1.05 or less and does not include zero.

  Further preferably, in the method for manufacturing a connection wiring structure according to the present invention, the portion where the aspect ratio is expected to be higher than a predetermined value is a portion where the step is a predetermined value or more and the contact hole pattern size is larger than the predetermined value. It is at least one of the small places.

  Further preferably, in the method for manufacturing a connection wiring structure according to the present invention, the plurality of contact holes reaching the electrode wiring include at least one contact hole reaching the substrate.

  Still preferably, in the method for manufacturing a connection wiring structure according to the present invention, in the interlayer insulating film forming step, a molten material layer made of a material to be melted by heat treatment is formed on the uppermost layer of the interlayer insulating film.

  Further preferably, in the method for manufacturing a wiring structure for connection according to the present invention, the molten material layer is melted between the etching process step and the contact hole forming step to flow the material from a high position to a low position. The thickness of the interlayer insulating film at the portion where the aspect ratio is expected to be higher than a predetermined value is reduced.

  Further preferably, a BPSG (boron / phosphorus / silica gate / glass) film is formed as a molten material layer in the method for manufacturing a connection wiring structure of the present invention.

Further preferably, the BPSG film in the method for manufacturing a connection wiring structure of the present invention is etched using a mixed gas of CF ₄ , CHF ₃ and Ar.

  The solid-state imaging device manufacturing method of the present invention is a solid-state imaging device that manufactures a solid-state imaging device in which a plurality of light receiving units that perform photoelectric conversion and a charge readout unit that reads signal charges from each of the plurality of light receiving units are provided in a matrix. In an imaging device manufacturing method, an interlayer insulating film forming step of forming an interlayer insulating film so as to cover a substrate on which the light receiving unit and the charge reading unit are provided, and an aspect ratio of a contact hole is higher than a predetermined value An etching process for reducing the thickness of the interlayer insulating film by performing an etching process on an expected portion in advance, and an etching process is performed on a predetermined portion of the thinned interlayer insulating film to form the charge readout portion in the interlayer insulating film A contact hole forming step of forming a contact hole reaching at least one of the gate electrode and the drain region, and the interlayer insulation A connecting wiring layer forming step of forming a connecting wiring layer on the top and electrically connecting the connecting wiring layer to the gate electrode and the drain region through the contact hole, This achieves the above object.

  Preferably, the predetermined value of the aspect ratio in the method for manufacturing a solid-state imaging device of the present invention is a numerical value that is 1.05 or less and does not include 0.

  Further preferably, in the method of manufacturing a solid-state imaging device according to the present invention, the portion where the aspect ratio is expected to be higher than a predetermined value is a portion where the step is a predetermined value or more and the contact hole pattern size is smaller than the predetermined value. It is at least one of the places.

  Still preferably, in a method for manufacturing a solid-state imaging device according to the present invention, the plurality of contact holes reaching the electrode wiring include at least one contact hole reaching the substrate.

  Still preferably, in the method for manufacturing a solid-state imaging device of the present invention, in the interlayer insulating film forming step, a molten material layer made of a material to be melted by heat treatment is formed on the uppermost layer of the interlayer insulating film.

  Further preferably, in the solid-state imaging device manufacturing method of the present invention, by melting the molten material layer and flowing the material from a high position to a low position between the etching process step and the contact hole forming step, The thickness of the interlayer insulating film at a portion where the aspect ratio is expected to be higher than a predetermined value is reduced.

  Further preferably, a BPSG (boron, phosphorus, silica gate, glass) film is formed as a molten material layer in the method for manufacturing a solid-state imaging device of the present invention.

Further preferably, the BPSG film in the method for manufacturing a solid-state imaging device of the present invention is etched using a mixed gas of CF ₄ , CHF ₃ and Ar.

  The solid-state imaging device of the present invention is manufactured by the method for manufacturing a solid-state imaging device of the present invention, and thereby the above object is achieved.

  An electronic information device according to the present invention uses the solid-state imaging device according to the present invention as an imaging unit, thereby achieving the object.

  The operation of the present invention will be described below with the above configuration.

  In the present invention, when a contact hole is formed in the interlayer insulating film on the electrode wiring, it is expected that the aspect ratio of the contact hole becomes high, such as a high step portion and a reduced pattern portion (high pixel location, etc.). A portion is selected and etched in advance to reduce the thickness of the interlayer insulating film in that portion. Thereafter, etching is performed again to form a contact hole reaching at least the electrode wiring of the electrode wiring and the substrate in the interlayer insulating film. This makes it possible to form a contact hole with a low aspect ratio even at a high step portion or a reduced pattern portion, and to improve the embedding property of the connection wiring to be formed in the contact hole after that, disconnection, etc. Can be suppressed. In this case, the interlayer insulating film is formed again on the light receiving portion of the solid-state imaging device or the like, as in the prior art in which all the interlayer insulating film on the electrode wiring is removed by etching and the interlayer insulating film is formed again. There is no problem.

  In the solid-state imaging device, a molten material layer such as a BPSG film that is melted by heat treatment is used as the uppermost layer of the interlayer insulating film. This BPSG film is frequently used because its shape can be changed by performing a heat treatment such as a melting method and light can be efficiently taken in to improve the sensitivity of the solid-state imaging device. However, as the number of pixels of a solid-state image sensor increases and the size of the contact hole decreases, the contact hole tends to decrease, and the aspect ratio of the contact hole is expected to increase.

  Thus, before the molten material layer such as the BPSG film formed on the uppermost layer of the interlayer insulating film is melted by heat treatment, the high step portion and the reduced pattern portion are etched in advance to reduce the thickness of the portion. As a result, when the molten material layer is melted by the melting method or the like, the flowing amount can be reduced when the molten material flows from a high position to a low position. For this reason, when the etching process is performed again to form the contact hole, the aspect ratio can be lowered at a high step portion, a reduced pattern portion, or the like. Furthermore, when the molten material layer flows from a high position to a low position, an interlayer insulating film is formed between the electrode wirings and also on the electrode wiring, and the breakdown voltage of that portion can be ensured.

  As described above, according to the present invention, the etching process of the interlayer insulating film is performed twice in a portion where the aspect ratio of the contact hole is expected to be high, such as a high step portion and a reduced pattern portion. Without forming the interlayer insulating film again and forming it in an unnecessary part as in the technology, a contact hole with a low aspect ratio can be easily formed to improve the embedding property of the connection wiring with the peripheral circuit. It is possible to suppress problems such as disconnection.

  Hereinafter, a method for manufacturing a solid-state imaging device using the method for manufacturing a wiring layer for connection of the present invention and embodiments of the solid-state imaging device manufactured thereby will be described in detail with reference to the drawings.

  FIG. 1 is a longitudinal sectional view of a main part showing a connection wiring structure layer of a semiconductor device according to an embodiment of the present invention.

  As shown in FIG. 1, the connection wiring structure of the solid-state imaging device 30 of this embodiment includes three types of electrode wiring patterns 3a, 3b and 3c made of polysilicon on a silicon substrate 1 with a gate insulating film 2 interposed therebetween. The interlayer insulating film 4 is provided on the electrode wiring patterns 3a, 3b and 3c by surface oxidation. Interlayer insulating films 5 and 6a are provided in this order on the interlayer insulating film 4 and the silicon substrate 1. Contact holes 33a to 33c are provided in the interlayer insulating films 4, 5, and 6a on the electrode wiring patterns 3a, 3b, and 3c, respectively. Connection wirings 7 to 9 made of metal laminated films connected to the electrode wiring patterns 3a, 3b, and 3c are provided through the contact holes 33a to 33c, respectively.

  In this case, of the contact holes 33a to 33c, when the hole shape is a groove (or a diameter when the hole shape is circular), an aspect ratio that is a ratio of width to height is expected to be higher than a predetermined value. The portions (contact holes 33b and 33c) to be formed constitute the interlayer insulating films 4, 5, and 6a thinner than the other portions (contact holes 33a). The uppermost layer of the interlayer insulating films 4, 5, 6a is composed of a BPSG (boron / phosphorus / silica gate / glass) film 6a which is a molten material layer made of a material melted by heat treatment. The BPSG film 6a is selectively thinned by an etching process. As described above, the processing of the BPSG film 6a by the etching process can be selectively performed, so that it is effective in a place where the dimension is severe or a rear step. The BPSG film 6a is etched before melting, and the contact holes 33b and 33c can be easily processed by reducing the flow amount. The aspect ratio is a numerical value that is 1.05 or less and does not include 0 as the predetermined value.

  Here, the leftmost electrode wiring 3a has a wide line width, and the contact holes 33a of the interlayer insulating films 4, 5, 6a formed thereon are also formed widely. The center electrode wiring 3b has a narrow line width, and the contact holes 33b of the interlayer insulating films 4, 5, and 6a formed thereon are also formed with a narrow line width. The rightmost electrode wiring 3c is connected to an impurity implantation region (not shown) which is a semiconductor region (drain region) of the silicon substrate 1 provided in a part of the silicon substrate 1 adjacent to one side of the wiring and the electrode wiring 3c. Therefore, the contact hole 33c is formed, and both the line width and height of the contact hole 33c to be etched are the largest and highest (deep).

   Each manufacturing process of the connection wiring structure used in the manufacturing method of the solid-state imaging device 30 of the present embodiment configured as described above will be described in detail below with reference to FIGS.

  2 (a) to 2 (d) and FIGS. 3 (e) to 3 (g) show respective manufacturing steps of the connection wiring structure used in the method of manufacturing the solid-state imaging device according to the embodiment of the present invention. It is a principal part longitudinal cross-sectional view shown.

  First, as shown in FIG. 2 (a), electrode wirings 3a to 3c made of polysilicon are formed on a silicon substrate 1 with a gate insulating film 2 interposed therebetween, and reactive interlayer insulation is performed by oxidizing the surface thereof. A film 4 is formed. An interlayer insulating film 5 is formed by deposition so as to cover the substrate portion, and a BPSG film 6 is formed as a hot melt material layer on the uppermost layer of the interlayer insulating film. Thereafter, a resist pattern 31 is formed to etch the uppermost BPSG film 6 into a predetermined shape.

  Here, since the leftmost electrode wiring 3a can be formed with a wide line width, it is not necessary to form the opening of the resist pattern 31 as shown in FIG. On the other hand, in the portion where the opening 31a becomes narrow like the resist pattern 31 on the electrode wiring 3b shown in the center, the etching rate is lowered due to the microloading effect. For this reason, the portion on the central electrode wiring 3b needs to be etched in advance to reduce the film thickness. Since the left electrode wiring 3a has a wide line width, the microloading effect is small, so only one etching is performed. It is possible to form a contact hole. Further, the etching amount is insufficient even at a portion where a high step is formed by processing the BPSG film 6, the interlayer insulating film 4, and the interlayer insulating film 5, as in the portion on the rightmost electrode wiring 3c. Accordingly, it is necessary to reduce the film thickness by etching in advance also on the portion on the right electrode wiring 3c. Therefore, in the present embodiment, the etching process is performed twice in forming the contact hole in the central electrode wiring 3b portion and the right electrode wiring 3c portion.

  Next, as shown in FIG. 2B, the resist pattern 31 is stripped by etching the BPSG film 6 using the resist pattern 31 having a predetermined shape as a mask. The etching process at this time can be performed using, for example, a mixed gas of CF4, CHF3, and Ar. This etching process is intended to reduce the thickness of the BPSG film 6 on the electrode wiring 3b and the electrode wiring 3c, and it is not necessary to remove all of the BPSG film 6 as shown in FIG.

  Further, as shown in FIG. 2C, the BPSG film 6 is melted by heat treatment at a high temperature. Since the BPSG film 6 is melted at a high temperature of 900 ° C. to 1000 ° C., it can be heat-treated using a diffusion furnace or the like. As a result, as shown in FIG. 2 (c), the BPSG film 6 flows from a high position to a low position, and is formed as an interlayer insulating film between the electrode wirings and on the electrode wiring, and on each of the electrode wirings 3b and 3c. The BPSG film 6a is thin.

Further, as shown in FIG. 2 (d), a resist pattern 32 for forming a contact hole is formed on the BPSG film 6a, and the interlayer insulating films 4, 5 and 6a are etched as shown in FIG. 3 (e). Then, a contact hole 33a reaching the electrode wiring 3a, a contact hole 33b reaching the electrode wiring 3b, and a contact hole 33c reaching the electrode wiring 3c and the silicon substrate 1 are formed. The etching process at this time can also be performed using, for example, a mixed gas of CF ₄ , CHF ₃ and Ar, and the selection ratio between the electrode wirings _{3 a to 3} c and the interlayer insulating films 4, 5 and 6 a is about 15 to 20. I just need it.

  Thereafter, as shown in FIG. 3 (f), the resist pattern 32 is peeled off, and as shown in FIG. 3 (g), connection wirings 7 to 9 are formed in this order to form a metal laminated film. The film connects the electrode wirings 3a to 3c and the portion of the silicon substrate 1 adjacent to the electrode wiring 3c with the peripheral circuit.

  As described above, according to the present embodiment, when the contact holes 33a to 33c are formed in the interlayer insulating film 6a on the electrode wirings 3a to 3c, the contact holes on the electrode wiring 3b to be a reduced pattern and the electrodes to be a high step. A portion where the aspect ratio is expected to be high, such as a contact hole on and near the wiring 3c, is selected and etched in advance to reduce the thickness of the interlayer insulating film. Thereafter, etching is performed again to form a contact hole in the interlayer insulating film. Here, the uppermost layer of the interlayer insulating film is a molten material layer, and before the BPSG film 6 as the molten material layer is melted, the high step portion 3c, the reduced pattern portion, etc. are etched in advance and the interlayer insulating film of that portion is processed. When the BPSG film 6 is melted, the flow amount from the high position to the low position is reduced. As described above, by performing the etching process of the interlayer insulating film twice, the contact hole 33b having a low aspect ratio of the contact hole without forming the interlayer insulating film again and forming it in an unnecessary portion as in the prior art. 33c can be easily formed, the embedding property of the connection wiring with the peripheral circuit can be improved, and problems such as disconnection can be suppressed. A location where this etching process is performed twice can be selectively set, and a location where the area (or diameter or side) of the contact hole can be made sufficiently wide like a portion on the electrode wiring 3a, A contact hole can be formed by one etching process.

  In the above embodiment, the case where the interlayer insulating film includes the molten material layer has been described. However, the present invention is not limited to this, and the interlayer insulating film may not include the molten material layer. It is only necessary that the portion that is expected to be higher than the predetermined value has a smaller thickness of the interlayer insulating film than the other portions.

  In the above-described embodiment, the molten material layer is removed by the etching process, and the molten material layer is melted by a subsequent heat treatment to flow the material from a high position to a low position, whereby the aspect ratio is higher than a predetermined value. Although the case where the thickness of the interlayer insulating film at the place where it is expected to be reduced has been described, the present invention is not limited to this, and the molten material layer is processed thinly by the etching process, and the molten material layer is melted by the subsequent heat treatment to increase the position. The thickness of the interlayer insulating film at the location where the aspect ratio is expected to be higher than the predetermined value may be set so as to be smaller than the predetermined aspect ratio. Good.

  Further, although not particularly described in the above embodiment, the portion where the spectroscopic ratio is expected to be higher than the predetermined value is at least a portion where the step is greater than the predetermined value and a portion where the contact hole pattern size is smaller than the predetermined value. Either.

  Furthermore, although the said embodiment demonstrated the case where a molten material layer was a BPSG film | membrane, not only this but films other than a BPSG film | membrane may be sufficient. For example, there is a P—SiO (plasma SiO) film.

  Furthermore, in the above-described embodiment, an interlayer insulating film is provided so as to cover a substrate on which a plurality of electrode wirings are provided, and the connection is electrically connected to the electrode wirings through contact holes provided in the interlayer insulating film. A wiring structure for connection in which a wiring layer is provided on an interlayer insulating film and a method for manufacturing the same, in which a plurality of light receiving portions for photoelectric conversion and a charge reading portion for reading signal charges from each of the plurality of light receiving portions are arranged in a matrix The manufacturing method of the solid-state imaging device for manufacturing the provided solid-state imaging device and the case of applying to the solid-state imaging device manufactured thereby have been described, but not limited thereto, besides the solid-state imaging device and the manufacturing method thereof, The present invention can be applied to a semiconductor device such as a circuit device using a transistor and a manufacturing method thereof.

  Although not specifically described in the above embodiment, the aspect ratio (height / width) of the contact hole is an important factor in sputtering performed in a later process (for example, sputtering of Al—Cu or Al—Si). When this aspect ratio (height / width) is high, that is, in a hole with a narrow line width and a high height (depth), the film as shown above may be thinly formed on the side wall in the hole. In some cases (when the aspect is extremely high), it may not be sputtered. Therefore, it is necessary to reduce the aspect ratio of the contact hole as in the present invention.

  Specifically, spatter formation defects are likely to occur when the aspect ratio is 1.05 or 1 or more, so the predetermined value (height / width) of the aspect ratio is a predetermined value of 1.05 or less (for example, 1.05 or 1). In this case, the range of the predetermined value X of 1.05 or less is 0 <X ≦ 1.05 or 0.1 ≦ X ≦ 1.05. Note that when the predetermined value (height / width) of the aspect ratio is “0”, the height is “0” and no step is generated on the flat surface.

  Further, although not particularly described in the above embodiment, a digital camera such as a digital video camera or a digital still camera using the solid-state imaging device 30 of the above embodiment as an imaging unit, an image input camera, a scanner, a facsimile, An electronic information apparatus having an image input device such as a camera-equipped mobile phone device will be described. The electronic information device of the present invention is a memory such as a recording medium for recording data after performing predetermined signal processing for recording high-quality image data obtained by using the solid-state imaging device 30 of the above-described embodiment of the present invention as an imaging unit. A display means such as a liquid crystal display device for displaying the image data on a display screen such as a liquid crystal display screen after the image data is subjected to predetermined signal processing for display; and after the image data is subjected to predetermined signal processing for communication It has at least one of communication means such as a transmission / reception device for performing communication processing and image output means for printing (printing) and outputting (printing out) the image data.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to a connection wiring structure for connecting a connection wiring for connecting between an element electrode and a peripheral circuit via a contact hole provided in an interlayer insulating film, a method for manufacturing the connection wiring structure, and a solid-state imaging using the connection wiring structure Manufacturing method of apparatus, solid-state imaging apparatus manufactured by manufacturing method of this solid-state imaging apparatus, digital cameras such as digital video cameras and digital still cameras using this solid-state imaging apparatus as an image input device in an imaging unit, and images In the field of electronic information equipment such as input cameras, scanners, facsimiles, and camera-equipped mobile phone devices, interlayer insulation is used in places where the contact hole aspect ratio is expected to be high, such as high-stepped parts and reduced pattern parts. By performing the etching process of the film twice, the interlayer insulating film is again formed as in the prior art. Easily form contact holes with a low aspect ratio without forming them in unnecessary parts, improve the embedding of wiring for connecting to peripheral circuits, and suppress problems such as disconnection Can do.

It is a principal part longitudinal cross-sectional view which shows the wiring structure layer for a connection of the semiconductor device which concerns on embodiment of this invention. (A)-(d) is a principal part longitudinal cross-sectional view which shows each manufacturing process (the 1) of the wiring structure for a connection used for the manufacturing method of the solid-state imaging device which concerns on embodiment of this invention. (E)-(g) is a principal part longitudinal cross-sectional view which shows each manufacturing process (the 2) of the wiring structure for a connection used for the manufacturing method of the solid-state imaging device which concerns on embodiment of this invention. (A)-(d) is a principal part longitudinal cross-sectional view for demonstrating the wiring process for a connection of the conventional solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Gate insulating film 3a Electrode wiring with a large processing size when forming a contact hole 3b Electrode wiring with a small processing size when forming a contact hole 3c Electrode wiring with a high step when forming a contact hole 4 Reactive interlayer insulating film 5 Deposition 6 Interlayer insulation film made of BPSG 6a State after melting BPSG interlayer insulation film 7-9 Connection wiring 30 Solid-state imaging device 31, 32 Resist pattern 31a, 32a Opening 33a Contact with wide processing dimension Hole 33b Contact hole with small processing size 33c Contact hole with high step

Claims (26)

An interlayer insulating film is provided so as to cover a substrate on which a plurality of electrode wirings are provided, and a connection wiring layer electrically connected to the electrode wirings through a contact hole provided in the interlayer insulating film In the connection wiring structure provided on the interlayer insulating film,
A connection wiring structure in which a portion where the aspect ratio of the contact hole is expected to be higher than a predetermined value is configured to be thinner than the other portions.   The connection wiring structure according to claim 1, wherein the predetermined value of the aspect ratio is a numerical value of 1.05 or less and not including 0.   3. The connection according to claim 1, wherein the portion where the aspect ratio is expected to be higher than a predetermined value is at least one of a portion where the step is greater than the predetermined value and a portion where the contact hole pattern size is smaller than the predetermined value. Wiring structure.   The connection wiring structure according to claim 1, wherein the plurality of contact holes reaching the electrode wiring include at least one contact hole reaching the substrate.   2. The connection wiring structure according to claim 1, wherein the uppermost layer of the interlayer insulating film is formed of a molten material layer made of a material that is melted by heat treatment.   6. The connection wiring structure according to claim 5, wherein the molten material layer is configured such that a portion where the aspect ratio is expected to be higher is configured thinner than other portions or is removed and the heat treatment is performed.   7. The connection wiring structure according to claim 5, wherein the molten material layer is a BPSG (boron / phosphorus / silica gate / glass) film.   The connection wiring structure according to claim 7, wherein the BPSG film is selectively thinned by an etching process. An interlayer insulating film forming step of forming an interlayer insulating film so as to cover a substrate provided with a plurality of electrode wirings;
An etching process for reducing the thickness of the interlayer insulating film by previously etching a portion where the aspect ratio of the contact hole is expected to be higher than a predetermined value;
A contact hole forming step of forming the contact hole reaching the electrode wiring by performing an etching process on a predetermined portion of the thinned interlayer insulating film;
A connection wiring structure comprising a connection wiring layer forming step of forming a connection wiring layer on the interlayer insulating film and electrically connecting the connection wiring layer and the electrode wiring through the contact hole Manufacturing method.   The method for manufacturing a connection wiring structure according to claim 9, wherein the predetermined value of the aspect ratio is a numerical value of 1.05 or less and not including 0.   The connection according to claim 9 or 10, wherein the part where the aspect ratio is expected to be higher than a predetermined value is at least one of a part where the step is a predetermined value or more and a part where the contact hole pattern size is smaller than the predetermined value. Method for manufacturing a wiring structure.   The method for manufacturing a connection wiring structure according to claim 9, wherein the plurality of contact holes reaching the electrode wiring include at least one contact hole reaching the substrate.   The method for manufacturing a connection wiring structure according to claim 9, wherein in the interlayer insulating film forming step, a molten material layer made of a material melted by heat treatment is formed on the uppermost layer of the interlayer insulating film.   Between the etching process step and the contact hole forming step, the molten material layer is melted and the material is allowed to flow from a high position to a low position so that the aspect ratio is expected to be higher than a predetermined value. The method for manufacturing a connection wiring structure according to claim 9, wherein the thickness of the insulating film is reduced.   15. The method of manufacturing a connection wiring structure according to claim 13, wherein a BPSG (boron / phosphorus / silica gate / glass) film is formed as the molten material layer. The method of manufacturing a connection wiring structure according to claim 15, wherein the BPSG film is etched using a mixed gas of CF ₄ , CHF _3, and Ar. In a manufacturing method of a solid-state imaging device for manufacturing a solid-state imaging device in which a plurality of light-receiving units that perform photoelectric conversion and a charge reading unit that reads signal charges from each of the plurality of light-receiving units are provided in a matrix form,
An interlayer insulating film forming step of forming an interlayer insulating film so as to cover the substrate on which the light receiving unit and the charge reading unit are provided;
An etching process for reducing the thickness of the interlayer insulating film by previously etching a portion where the aspect ratio of the contact hole is expected to be higher than a predetermined value;
A contact hole forming step of forming a contact hole reaching at least one of a gate electrode and a drain region constituting the charge readout portion in the interlayer insulating film by performing an etching process on a predetermined portion of the thinned interlayer insulating film;
A solid having a connection wiring layer forming step of forming a connection wiring layer on the interlayer insulating film and electrically connecting the connection wiring layer, the gate electrode and the drain region through the contact hole Manufacturing method of imaging apparatus.   The method for manufacturing a solid-state imaging device according to claim 17, wherein the predetermined value of the aspect ratio is a numerical value of 1.05 or less and not including 0.   19. The solid according to claim 17, wherein the portion where the aspect ratio is expected to be higher than a predetermined value is at least one of a portion where the step is greater than the predetermined value and a portion where the contact hole pattern size is smaller than the predetermined value. Manufacturing method of imaging apparatus.   The solid-state imaging device manufacturing method according to claim 17, wherein the plurality of contact holes reaching the electrode wiring includes at least one contact hole reaching the substrate.   18. The method of manufacturing a solid-state imaging device according to claim 17, wherein in the interlayer insulating film forming step, a molten material layer made of a material that is melted by heat treatment is formed on the uppermost layer of the interlayer insulating film.   Between the etching process step and the contact hole forming step, the molten material layer is melted and the material is allowed to flow from a high position to a low position so that the aspect ratio is expected to be higher than a predetermined value. The method for manufacturing a solid-state imaging device according to claim 17, wherein the thickness of the insulating film is reduced.   23. The method of manufacturing a connection wiring structure according to claim 21, wherein a BPSG (boron / phosphorus / silica gate / glass) film is formed as the molten material layer. The method of manufacturing a connection wiring structure according to claim 23, wherein the BPSG film is etched using a mixed gas of CF ₄ , CHF ₃ and Ar.   The solid-state imaging device manufactured by the manufacturing method of the solid-state imaging device in any one of Claims 17-24.   An electronic information device using the solid-state imaging device according to claim 25 in an imaging unit.

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