JPH08236724A - Method of fabrication of semiconductor device - Google Patents

Abstract

PURPOSE: To provide a method of fabrication of a semiconductor device capable of easily achieving flattening on an insulating layer such as a BPSG layer and an SOG layer and of applying wiring and the like with high reliability and redundance in a later process. CONSTITUTION: There is provided a method of fabrication of a semiconductor device such as a dynamic RAM wherein upon flattening a layer (e.g. a BPSG layer 66) including a step (e.g. global step 62) formed with an upper part (e.g. a part on a memory cell array part MA) and a lower part (e.g. a part on a peripheral circuit part PC) a resist layer 70 is formed into a predetermined pattern such that an end part is located on a slope 62A forming the step part 62 after preannealing. A higher layer 66 than the resist layer is uniformly removed by etching by a predetermined thickness using the resist layer as a mask, and thereafter a protruded part (e.g. a protrusion 66A produced after the etching) existent on a lower side than the resist layer 70 is eliminated with a reflow processing in the state where the resist layer T670 is removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device (for example, a dynamic RAM: Random access memory) having a memory cell array section and a peripheral circuit section.

[0002]

2. Description of the Related Art Conventionally, as a structure for increasing the capacity of a capacitor in each memory cell, for example, a dynamic RAM having a memory cell structure of a stacked cell capacitor formed in a cylindrical shape as shown in FIG. 62 has been adopted. .

According to this memory cell structure, the gate oxide film 5 is formed in the element region separated by the field SiO ₂ film 2 on the P-type silicon substrate 1, and the word lines WL and SiO made of polysilicon are formed thereon. _Two layers 6 are formed, and N ⁺ type semiconductor regions 3 (source regions) and 4 (drain regions) are formed by a self-alignment method using the word lines WL as a mask.

Then, Si for passivation is formed on the entire surface.
O ₂ layer 7, Si ₃ N ₄ layer 8 for protecting underlayer, and Si
An O ₂ layer 9 is sequentially laminated, and a contact hole 10 is formed in a part of the passivation film on the N ⁺ type source region 3, and the contact hole 10 is included in the source region 3.
A polysilicon layer 11 (storage node) is formed so as to be connected to the above, and a cylindrical polysilicon layer 13 is formed on this polysilicon layer 11, and these polysilicon layers 11 and 13 form a lower capacitor electrode. . Further, a dielectric film such as a Si ₃ N ₄ film 15 is formed on the entire surface of the polysilicon layer 11.
Is deposited, and an upper capacitor electrode (plate electrode) made of the polysilicon layer 16 is formed on the Si ₃ N ₄ film.

Thus, the upper and lower capacitor electrodes 16 and 1
The partition-type polysilicon layer 1 is composed of 1, 13 and the dielectric film 15.
The capacitor Cap whose capacitance is expanded by 3 is connected to the source region 3.

Further, an interlayer insulating film, for example, a silicate glass layer (BPSG layer) 36 doped with boron and phosphorus is laminated on the upper electrode 16 by a CVD method, and N ⁺
A contact hole 49 reaching the mold drain region 4 is opened, and a bit line BL is deposited in the contact hole via the polysilicon layer 50, for example, 16
A memory cell M-CEL of a dynamic RAM for mega, and further for 64 mega is configured.

As shown in FIG. 55, such a dynamic RAM generally comprises a memory cell array section MA having a large number of memory cells M-CEL and a peripheral circuit section PC (however, the elements of each section are schematically shown. Shown). Then, the BPSG layer 36 is formed on the memory cell array unit MA and the peripheral circuit unit PC by the steps described below, and wirings such as the bit line BL are provided.

As shown in FIG. 55, on one main surface of the P-type silicon substrate 1, in the memory cell array portion MA, a memory cell M-CELL having a stack cell capacitor Cap as shown in FIG. Approximately 1.2 μm, word line spacing is approximately 0.4 μm, word line height is approximately 3500 Å), and many peripheral circuits PC
Each MOS transistor TR forming an input / output circuit is formed in the. These transistors TR have a structure in which a polysilicon gate electrode 20 is provided between the N ⁺ type source region 23 and the N ⁺ type drain region 24 with the gate oxide film 5 interposed therebetween.

Next, as shown in FIG. 56, a BPSG layer 36 is deposited on the entire surface of the substrate 1 by the CVD method to a thickness of about 0.6 μm. On the surface of the deposited layer 36, in the memory cell array portion MA, each memory cell M is determined by the partition height of the cell capacitor Cap and the thickness of the word line WL.
Since a gap is formed between the CELLs and a step 21 is formed, there is no high structure such as a partition structure outside the end of the memory cell array portion MA (the distance between the word line WL of the memory cell and the gate electrode 20 is about 4 μm). In addition, a step 22 which is steeper than the step 21 is formed between the memory cell array section MA and the peripheral circuit section PC.

Here, the step 21 of the memory cell array portion MA.
May be referred to as a "local step" in the present specification, but this is a step between a plurality of word lines WL (or cells) that are relatively close to each other, and usually the distance between word lines or wirings is It occurs when the thickness is 10 μm or less.

The step 22 between the memory cell array section MA and the peripheral circuit section PC is sometimes referred to as a "global step" in the present specification, but it is quite steep and is usually between word lines or. Distance between wires is 10 μm or more (However, in some cases, it is 10 μm or less.)
It occurs when.

In the peripheral circuit portion PC as well, a step 25 is formed between the gate electrodes 20-20 or on the side of the gate electrode 20, but this difference in height is smaller than that of the global step 22 (however, the local step 21 and The height difference may be equal or higher).

These steps 21, 22 (25 further) are BP
In order to provide the wiring on the SG layer 36 with high reliability, it disappears,
It needs to be flattened. For this purpose, the BPSG layer 36 is reflowed by annealing at 900 ° C. for 10 minutes in the state of FIG.

However, in reality, as shown in FIG. 57, the local step 21 disappears substantially, and the peripheral circuit portion PC
The step 25 becomes gentle like 35, and the global step
Although the steep shape of 22 is gentle, it is difficult to flatten it in the vicinity of the global step 22 having a large height difference.
That is, a step 32 (also a global step) having a height difference of about 1.2 μm remains between the memory cell array section MA and the peripheral circuit section PC.

In this state, as shown in FIG.
Forming a contact hole 49 at a predetermined position of the PSG layer 36,
When a predetermined wiring, particularly a bit line BL, is formed via the polysilicon layer 50, the wiring BL is likely to be broken or short-circuited in photolithography because the step is large at the above-mentioned global step 32. That is, if a thick photoresist is applied to the disconnection portion, for example, a positive photoresist is applied, the bottom of the photoresist cannot be exposed and a short circuit or a step is formed.
The non-exposed part of the photoresist is exposed due to irregular reflection of light by the slopes of 32, and the pattern width of the wiring formed by etching the photoresist with the pattern collapsed as a mask deforms, causing the wiring to break. There is also.

When aluminum is used for the wiring BL, even if the wire breakage does not occur during manufacturing, the wire breakage may occur at the step due to so-called electromigration during use.

In addition to the above method, a spin coating method using SOG (Spin on Glass) is adopted to eliminate the step for providing the wiring with high reliability. That is, as shown by the phantom line in FIG.
_{A second} insulating layer 166 is provided. The insulating layer 166 formed by the plasma CVD method has an advantage that it can be formed at a low temperature, is dense, and has excellent insulating properties, and is mainly used in a planarization process on a metal wiring, and by high temperature annealing such as BPSG. No reflow is done. Then the insulating layer 166
SOG167 is spin coated on top and the surface is flattened.
This structure is manufactured by the procedure shown in FIGS.

As shown in FIG. 59, an insulating layer 166 of SiO ₂ having a thickness of 0.6 is formed on the entire surface of the substrate 1 by the plasma CVD method.
Deposit to μm. On the surface of this deposited layer 166,
In the memory cell array portion MA, the partition height is formed between the memory cells M-CELL due to the partition height of the cell capacitor Cap, the thickness of the word line WL, etc., while the partition structure is formed outside the end portion of the memory cell array portion MA. Since there is no such a high structure as described above (the distance between the word line WL of the memory cell and the gate electrode 20 is about 4 μm), the global level difference 22 between the memory cell array section MA and the peripheral circuit section PC is steeper than the step 21. Occurs.

Next, as shown in FIG. 60, SGO167 is spin-coated on the entire surface of the insulating layer 166. In this state, the local step 21 is flattened by the insulating layer 167, but the global step 22 is 1.0 μm due to the difference in height on both sides.
A step 32 'of m or more is formed.

Next, as shown in FIG. 61, when the bit line BL is laminated on the SOG layer 167, the wiring BL is broken or short-circuited on the step 32 'for the same reason as described above with reference to FIG. easy.

As described above, by any of the above methods, the reliability of the wiring is deteriorated, and there is a limit in miniaturizing the wiring width and the pitch, which is extremely disadvantageous for manufacturing a highly integrated semiconductor device. Is.

[0022]

SUMMARY OF THE INVENTION An object of the present invention is to easily planarize an insulating layer such as the BPSG layer or the SOG layer described above, and to provide a reliable wiring with a margin in a subsequent process. It is to provide a method of manufacturing a semiconductor device that can be applied.

[0023]

That is, according to the present invention, when an insulating film is formed on a surface having unevenness and / or steps formed on a semiconductor substrate, the insulating film is formed on the surface having unevenness and / or steps. A step of forming an insulating film, and
On the surface excluding the high part protruding above a predetermined height,
A step of forming a resist, a step of removing the high-level portion of the insulating film using the resist as a mask, and a step of forming a predetermined film on the insulating film after removing the resist, The present invention relates to a method of manufacturing a semiconductor device, wherein the unevenness and / or the step is covered by the planarized insulating film.

The above-mentioned "high-level portion" mainly means a position on the higher side with a global step 62 described later as a boundary.

The present invention also includes at least the step when manufacturing a semiconductor device in which a global step exists between the memory cell array section and the peripheral circuit section due to the difference in the predetermined circuit configuration formed on the semiconductor substrate. A step of forming an insulating film over the surface over the memory cell array part and the peripheral circuit part, and a resist except a position on a higher side than an arbitrary position on a slope forming the step on the insulating film. A step of forming a predetermined film on the insulating film, a step of removing the high-order portion of the insulating film by a predetermined thickness using the resist as a mask, and a step of forming a predetermined film on the insulating film after removing the resist. The present invention also provides a method of manufacturing a semiconductor device including the above.

The present invention further includes a step of forming an insulating film on a surface including the convex portion when manufacturing a semiconductor device in which a local step exists due to the convex portion of a predetermined circuit formed on the semiconductor substrate. A step of forming a resist on the surface of the insulating film excluding the high-level portion forming the convex portion, a step of removing the high-level portion of the insulating film by a predetermined thickness using the resist as a mask, and the resist And a step of forming a predetermined film on the insulating film after the removal of the semiconductor film.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, it is desirable to form a silicate glass film as an insulating film.

In the above, it is preferable to further include a step of applying silicate glass on the surface having irregularities and / or steps and then performing a heat treatment to flatten the insulating film made of this silicate glass.

Further, in the present invention, a silicon dioxide film may be formed as the insulating film.

In the above, it is desirable to further include a step of spin-coating SOG on the planarized silicon dioxide film.

In the above, the SOG is etched back to leave the SOG in the concave portion of the insulating film made of silicon dioxide, and a second insulating film made of silicon dioxide is further formed on the insulating film where the SOG remains. It is desirable to form.

Further, in the present invention, the resist layer is formed in a predetermined pattern so that the resist end portion is located on the slope of the step and / or the convex portion, and this resist layer is used as a mask to form a higher side than the resist layer. It is more desirable to uniformly remove the insulating film by etching to a predetermined thickness.

In the above, it is more desirable to eliminate the protrusions remaining after etching.

In the present invention, it is more desirable to carry out both the process described in claim 9 and the process described in claim 10.

Further, in the above, it is desirable to use the materials or steps described in the above claims 2 to 8.

In the manufacturing method of the present invention, after removing the layer portion on the high-order side by a predetermined thickness as described above, heat treatment is used to eliminate the protruding portion existing on the lower-order side than an arbitrary position of the step. You can Furthermore, the surface of the layer can be flattened with the disappearance of the protruding portion.

According to the above, the step formed by the high-level portion and the low-level portion is not subjected to the reflow treatment as it is as described above, but is higher than the arbitrary position on the slope forming the step. Since the heat treatment is performed after removing the layer portion by a predetermined thickness, the subsequent heat treatment can be performed in a state where the layer thickness and the height of the step are reduced corresponding to the removed thickness.

Therefore, at the time of this heat treatment, the volume (height and height) of the projecting portion existing on the lower side of the step above the arbitrary position (that is, remaining after the layer portion is removed by a predetermined thickness). Since the volume (determined by the width and length) is small, this protruding part is easily eliminated by heat treatment, which makes it possible to significantly reduce the height difference between the high part and the low part. And it can be surely flattened.

As a result, the adherence of the wiring such as the bit line to the above layer, especially to the step portion is improved, and the wiring having no breakage and having high reliability can be formed. Also,
Since the photoresist can be exposed according to the design pattern when forming the wiring, it is possible to form a plurality of adjacent wirings with a predetermined width and interval (or pitch).

Therefore, the wiring can be finely and densely processed.
Moreover, it can be performed with a large margin. In particular, when the design rule becomes strict with the minimum line width or spacing (for example, 0.4 μm or less), the margin of the depth of focus of exposure during photolithography cannot be so large, but this is considerably reduced by the flattening of the step according to the present invention. Can be realized to the extent of, and the process margin can be expanded.

As a technique for flattening the step,
In recent years, a technique using so-called CMP (Chemical Mechanical Polish) has been proposed, but the flattening method according to the present invention requires only the addition of required steps to the conventional steps as compared with CMP, and dust generation. It is excellent in that there are few problems and that new equipment is not required.

In the manufacturing method of the present invention, when the above step is flattened, a resist layer is formed in a predetermined pattern so that the end portion is located on the slope forming the step, and this resist layer is used as a mask. The layer on the side higher than this resist layer is uniformly removed by etching by a predetermined thickness,
After that, it is desirable to perform a reflow process with the resist layer removed. In this case, it is preferable to uniformly remove the layer on the higher side of the intermediate height position on the slope of the step by a predetermined thickness.

Further, an insulating layer having a step (for example, a BPSG layer described later) is pre-annealed, and the step remaining after the pre-annealing is flattened by the above method (that is, from an arbitrary position on the slope of the step). (The high-side part is removed by a predetermined thickness, and the protruding part disappears by the subsequent heat treatment.)
Is desirable. At this time, for example, the preliminary annealing is 850
The heat treatment (reflow) can be performed at 900 ℃ for 10 minutes and at 900 ℃ for 10 minutes.
It can be reduced to m.

In the manufacturing method of the present invention, it is desirable to form the insulating layer (for example, the BPSG layer described later) by the CVD method. According to the CVD method, a highly pure insulating layer can be uniformly deposited and formed.

In the manufacturing method of the present invention, unlike the above, after removing the layer portion of the high-order portion by a predetermined thickness, the insulating material is applied to substantially fill the protrusion and the surface of the layer is covered. It can also be flattened.

In this case, an insulating layer (for example, SiO ₂ described later) is used.
It is desirable to form the insulating layer 166) by the plasma CVD method. According to the plasma CVD method, the above-mentioned CVD
In addition to the advantages of the method, the film can be formed at a low temperature of 300 to 400 ° C., which is convenient because the elements already formed are less damaged by heat.

Since the insulating layer formed by the plasma CVD method is dense, the surface cannot be flattened by the reflow by the heat treatment. Therefore, flattening is performed by applying an insulating material. For this application, SOG (Spi
It is desirable to spin coat (on glass) from the viewpoint of good planarization and efficiency. Spin coating is 3000-4500
It is desirable to perform the rpm and heat treatment under the conditions of 400 to 450 ° C. and 30 to 60 minutes from the viewpoints of film thickness uniformity, embedding property, film quality and the like.

When SOG is spin-coated, CVD
In order to prevent cracks and the like due to the difference in thermal contraction from the insulating layer formed of, for example, SiO ₂ and peeling off from the bit line formed thereabove, this SOG layer is formed into a predetermined layer by etching. It is desirable to remove only the thickness and then form an insulating layer on the SOG insulating layer having a predetermined thickness by the plasma CVD method.

The manufacturing method of the present invention is a dynamic RAM.
In such a memory device, a step existing between a memory cell array unit (for example, a memory cell array unit MA described later) and a non-memory cell array unit (for example, a peripheral circuit unit PC or a word strap unit WS described later) is flattened. It is suitable for this. Further, it can be applied to flattening the step existing in the non-memory cell array portion.

In this case as well, an insulating layer (for example, BPSG described later) is formed on the memory cell array section and the non-memory cell array section.
After forming the layer 66) and pre-annealing this insulating layer, it is desirable to flatten the step between the memory cell array section and the non-memory cell array section by the above-mentioned processing. Also here, the conditions of the preliminary annealing, the reflow and the spin coating may be the same as those described above.

Further, after forming the insulating layer on the memory cell array section and the non-memory cell array section and pre-annealing the insulating layer, the first layer between the memory cell array section and the non-memory cell array section is formed. The insulating layer on the side of the memory cell array portion with respect to an arbitrary position on the slope forming the step is removed by a predetermined thickness, and thereafter, on the slope forming the second step existing in the non-memory cell array part. Of the insulating layer on the side of the higher level than the above position by a predetermined thickness, and further, by heat treatment, the protruding portions existing on the side of the lower level than the arbitrary position of the first and second steps disappear. Is desirable. Here, the conditions of the preliminary annealing, the heat treatment (reflow) and the spin coating may be the same as those described above.

The present invention also includes, for example, ASIC (Applicati
on specific IC: an IC for specific use), an insulating layer (for example, a BPSG layer 66 described later) is formed on the surface including a plurality of gate electrode portions, and the insulating layer is pre-annealed, and then the plurality of gates are formed. It is also applicable to the case where the steps existing between the electrode parts and on the sides of the gate electrode parts are flattened by the above-mentioned processing. Again, pre-anneal,
The conditions for reflow and spin coating may be the same as those described above.

The present invention further includes, for example, in the above-mentioned ASIC, a layer (for example, an insulating layer) having a step formed by a wiring (for example, a metal wiring) is divided into two types described above. It can also be flattened. As a result, a device having a three-dimensional, multi-layered and complicated laminated structure can be easily manufactured with high reliability.

[0054]

EXAMPLES The present invention will be described below with reference to examples.

1 to 12 show the dynamic RA of the present invention.
1 shows a first embodiment applied to M.

The manufacturing process of the dynamic RAM according to this embodiment will be described with reference to FIGS.

First, FIG. 1 is a cross-sectional view taken along line AA of FIG. 9 which is an enlarged plan view showing a part of a dynamic RAM having a memory array unit MA and a peripheral circuit unit PC ( (Similar to the step described with reference to FIG. 55), the memory cell array portion MA is provided with a pattern on one main surface of the P-type silicon substrate 1.
A large number of memory cells M-CELL (cell height is about 1.2 μm, word line WL interval is about 0.4 μm, word line WL height is about 3500 Å) with a stack cell capacitor Cap as shown in 62 are formed in an array. Further, in the peripheral circuit portion PC, MOS transistors TR for separating each bit line-sense amplifier forming the input / output circuit are formed.
These transistors TR have N ⁺ type source regions 23 and N
^It has a structure in which the polysilicon gate electrode 20 is provided between the ⁺ type drain region 24 and the gate oxide film 5.

Then, as shown in FIG. 2 (similar to the step described with reference to FIG. 56), the entire surface of the substrate 1 is deposited by the CVD method.
A BPSG layer 66 of about 4 wt% boron and about 5 wt% phosphorus is deposited to a thickness of 1.0 μm. This thickness is set to 1 μm in consideration of etch back (etching amount is 0.5 μm) described later.

On the surface of the deposited layer 66, in the memory cell array portion MA, each memory cell M depends on the partition height of the cell capacitor Cap and the thickness of the word line WL.
While there is a local step 21 between the CEL and CEL, a high structure such as a partition structure does not exist in the peripheral circuit portion PC outside the end portion of the memory cell array portion MA (the word line WL of the memory cell and the gate electrode 20). (The distance is about 4 μm)
Therefore, a global step 22 is formed between the memory cell array section MA and the peripheral circuit section PC, which is steeper than the local step 21.

In the peripheral circuit section PC as well, a step 25 is formed between the gate electrodes 20-20 or on the side of the gate electrode 20, but this difference in height is smaller than that of the global step 22 (however, the local step 21 The height difference may be equal or higher).

Next, as shown in FIG. 3, pre-annealing is performed in N ₂ at 850 ° C. for 10 minutes to form the steps 21, 2 above.
2 and 25 are made smooth (smoothing) to make the BPSG layer dense and stable. The conditions of this preliminary annealing are determined so that the thermal history is minimized in consideration of the BPSG reflow process described later.

However, this pre-annealing substantially eliminates the local step 21 and the step 25 of the peripheral circuit portion PC.
As shown in FIG. 35, the global step 22 has a gentle steep shape, but it is difficult to flatten the global step 22 in the vicinity of the global step 22 having a large height difference. That is, a step 62 (also a global step) having a height difference of about 1.2 μm remains between the memory cell array section MA and the peripheral circuit section PC. This global step 62 is
Remove as follows.

First, as shown in FIG. 4, a photoresist 70 applied on the entire surface of the BPSG layer 66 is exposed and developed in a predetermined pattern to develop a global step 62 between the memory cell array portion MA and the peripheral circuit portion PC. The photoresist 70 is patterned so that the end portion 70A is located at an intermediate position on the inclined surface 62A. The position of this end portion 70A is also shown in FIG.

Next, as shown in FIG. 5, with the photoresist 70 as a mask, the global step 62 (specifically,
The memory cell array unit MA rather than the end position of the resist 70)
The exposed portion of the BPSG layer 66 on the side is uniformly etched back by CF ₄ gas by anisotropic dry etching (hereinafter referred to as PEB (patterned etch back)). This dry etching is referred to as "PEB1", in which the BPSG layer 66 is uniformly removed by a thickness of 0.5 .mu.m.

After that, the photoresist 70 is removed over the entire surface. As a result, as shown in FIG. 6, the thickness of the BPSG layer 66 on the memory cell array portion MA is reduced by half, and the slope of the global step 62 at the location where it existed.
A protruding portion 66A formed by a part of 62A remains. The volume and height of the protruding portion 66A are not so large.

Next, as shown in FIG. 7, annealing is performed in N ₂ at 900 ° C. for 10 minutes to reflow the BPSG layer 66. As a result, the above-mentioned protruding portion 66A is fluidized and collapsed, and the step of the peripheral circuit portion is also substantially disappeared like 35 ', and it is slight (the height difference is usually 0.3 ~ 0.8 μm, eg about 0.7 μm)
Although only the step 62 ′ remains as a global step, this step 62 ′ is very small, and the surface of the BPSG layer 66 is substantially flattened so that it does not affect the wiring described later.

Then, as shown in FIG. 8, a BPSG layer 66 is formed.
A contact hole 49 is opened at a predetermined position of the polysilicon layer, a polysilicon layer 50 is buried therein, and a bit line BL is further formed by
It is formed on the G layer 66 with a predetermined width and pitch.

In this case, the height difference of the global step 62 'is considerably small, and the step of the peripheral circuit portion PC is 35'.
As described above, since the surface of the BPSG layer 66 is substantially flat as a whole, the photoresist serving as a mask when patterning the bit lines BL can be processed with high accuracy, and There is no short circuit or disconnection.

FIG. 55 shows that such excellent results are obtained.
~ Instead of simply reflowing the BPSG layer as in the prior art shown in Fig. 58, as shown in Figs. 2 to 6, the intermediate position 70A (photo Since the layer portion on the higher side than the resist end portion) is removed by PEB by a predetermined thickness and then reflowed as shown in FIG. 7, the thickness of the BPSG layer 66 is corresponding to the removed thickness. Also, the height of the step 66 can be reduced, and the reflow process can be performed in a state where the remaining protruding portion 66A is also small, the height difference between the high portion and the low portion of the BPSG layer 66 can be significantly reduced, and the protruding portion 66A can also be formed. This is because it can be easily eliminated and the BPSG layer 66 can be planarized sufficiently and reliably.

Therefore, the bit line BL (and other wirings) can be formed without disconnection or short circuit, and at the same time, the exposure of the photoresist can be performed according to the design pattern when the wirings are formed. Can be formed with the width and the interval (or pitch).

As a result, the wiring can be finely and densely processed with a large margin. In particular, the design rule is that the minimum line width or spacing (eg 0.4 μm)
If the following becomes strict, the margin of the depth of focus of exposure during photolithography cannot be so large, but this is
This can be realized to a considerable extent by the flattening of the global level difference according to the present embodiment, and the process margin can be expanded. Further, it is possible to minimize disconnection at the step portion due to electromigration of the aluminum wiring during actual use.

Further, according to this embodiment, the global step
Since the flattening of 62 is performed only by adding the required steps (steps in FIGS. 3 to 6) to the conventional technique, it is sufficient to add the required steps to the conventional steps, and the introduction of a new device. It is excellent in that it is unnecessary.

Next, the influence of the pattern position of the photoresist 70 shown in FIGS. 4 and 5 in the above manufacturing process will be described with reference to FIGS.

In FIG. 10, the resist pattern end portion 70A is located between the memory cell array region and the peripheral circuit region (that is, a step).
It is located at the middle position on the slope 62A of 62),
Since the PBSG layer 66 is sufficiently etched back by the PEB1 and the remaining protruding portion 66A is also thin and small, the remaining step 62 ′ is as low as about 0.7 μm, and it can be seen that the surface can be sufficiently flattened by reflow. According to the design rule, the gate electrode of the peripheral circuit section is provided at a position 4 μm away from the outermost word line WL of the memory cell array section (hereinafter the same).

On the other hand, FIG. 11 shows the case where the resist pattern end portion 70A is located in the memory cell array region. PEB1 is used to form the BPSG layer of the memory cell array portion.
66 is etched back, but since the step 62 is not etched, a considerably thick residual portion 66A remains after PEB1, and this residual portion does not disappear even by reflow, leaving a very high step 62 ′ of about 1.0 μm. And
It is less effective than the example shown in FIG.

FIG. 12 shows the resist pattern end portion 70A.
Shows the case where it is located in the peripheral circuit area. However, because the resist pattern end 70A is out of the step 62, PEB
1 causes the BPSG layer 66 including the step 62 to be etched back uniformly, and even if reflow is performed,
The step 62 ′ of 1.0 μm remains, which is less effective than the example shown in FIG.

As shown in FIGS. 10 to 12, it is necessary to form the pattern of the resist pattern 70 in the PEB 1 such that the resist pattern end portion 70A exists on the slope 62A of the step 62 as shown in FIG. I know there is. However, the position of this resist pattern end portion 70A is the slope 62 of the step 62.
It does not matter if it is on A, but it is desirable that it exists in an intermediate height region corresponding to approximately 1/3 of its height. For example, the storage node of the cell capacitor at the outermost end of the memory cell array portion (see FIG. It is desirable to set it at a position (see FIG. 9) that is about 0.4 μm away from (see 62).

The PE shown in FIGS. 5 and 6 described above is used.
After the step B, the BPSG layer including the above-mentioned protruding portion 66A is also included.
Another BPSG layer (not shown) may be deposited on the 66 by CVD to a thickness of, for example, 0.25 μm, after which the reflow of FIG. 7 may be performed. Also in this case, it is expected that the surface of the BPSG layer can be further flattened by the reflow, and the influence of the protruding portion 66A described above at the time of flattening can be sufficiently eliminated.

After the reflow process shown in FIG. 7, B
The PSG layer 66 is wet-etched on the entire surface with, for example, a buffer hydrofluoric acid-based (buffered hydrofluoric acid-based solution such as HF + NH ₄ F) etching solution to form the BPSG layer 66 with, for example, 0.25 μm.
The thickness may be uniformly removed. By this, B
The thickness of the PSG layer 66 is reduced, and then the bit line BL
The contact hole 49 (see FIG. 8) can be easily opened during formation.

13 to 17 show the dynamic RA of the present invention.
It shows a second embodiment applied to M.

According to this embodiment, the steps before the step shown in FIG. 13 are carried out in the same manner as the steps shown in FIGS. 1 to 5 (however, the BPSG layer shown in FIGS. The thickness of 66
1.2 μm, the etching amount with PEB1 in FIG.
μm. ), Further, a step of flattening the step 35 of the peripheral circuit portion PC is added.

That is, after removing the resist 70, a new photoresist 80 is applied, and as shown in FIG. 13, each end portion 80A is positioned on the slope 35A of the step 35 in the peripheral circuit portion PC. The photoresist 80 is patterned.

Next, as shown in FIG. 14, using the photoresist 80 as a mask, the step 35 (specifically, the resist 80) is formed.
BP on the higher side (gate electrode 20 side) than the edge position)
The exposed portion of the SG layer 66 is uniformly etched back by anisotropic dry etching with CF ₄ gas. This dry etching is called "PEB2", in which the BPSG layer 66 on the gate electrode 20 is uniformly removed by a thickness of 0.3 .mu.m.

By this, as shown in FIG. 15 where the photoresist 80 is removed, the thickness of the BPSG layer 66 on the gate electrode 20 is reduced, and at the place where the step 35 exists, a part of the slope 35A thereof. The projecting portion 66B formed in 1. remains. The volume and height of this protruding portion 66B are quite small.

Then, as shown in FIG. 16, annealing is performed in N ₂ at 900 ° C. for 10 minutes to reflow the BPSG layer 66. As a result, the above-mentioned protruding portions 66A and 66B are fluidized and collapsed, and are slight at the location where the global step 62 existed (the height difference is usually 0.3 to 0.8 μm, for example, about 0.5 μm).
Although only the step 62 ′ (μm) remains as a global step, this step 62 ′ is very small, and the step 35 of the peripheral circuit portion disappears almost completely like 35 ′, and the surface of the BPSG layer 66 is substantially Is flattened and does not affect the wiring described later.

Next, as shown in FIG. 17, the BPSG layer 66
A contact hole 49 is opened at a predetermined position of the polysilicon layer, a polysilicon layer 50 is buried in the contact hole 49, and the bit line BL is formed by BPS.
It is formed on the G layer 66 with a predetermined width and pitch.

In this case, the height difference of the global step 62 'is considerably small, and the step of the peripheral circuit portion PC is 35'.
As described above, since the surface of the BPSG layer 66 is substantially flat as a whole, the photoresist serving as a mask when patterning the bit lines BL can be processed with high precision, and the space between the bit lines described above can be No short circuit or disconnection will occur. Besides, the same excellent effects as those of the first embodiment described above can be obtained.

In this embodiment, as shown in FIGS. 13 to 16, not only the global step 62 between the memory cell array section MA and the peripheral circuit section PC but also the step 35 existing in the peripheral circuit section PC is PEB2 and reflowed. The surface of the BPSG layer 66 can be made even flatter than in the first embodiment described above, since it has been treated to be almost completely eliminated.

18 to 20 show the dynamic RA of the present invention.
It shows a third embodiment applied to M.

FIG. 18 shows the chip layout of the entire 64 mega dynamic RAM device. In FIG.
The one marked "DRAM chip A" shows the layout of the entire chip, and is divided into B and C on the right side in the drawing, and the minimum structure is D. A partially enlarged layout diagram of the word strap portion WS and the memory array portion MA in D is shown in FIG. A partially enlarged layout diagram of the memory array unit MA and the sense amplifier circuit unit SA is shown in FIG.

Here, as shown by C and D in FIG. 18, a word strap section WS is connected between the memory array sections MA1 and MA2 or other memory array sections. The word strap portion WS is a portion lined with metal wiring in order to reduce the resistance of the word line,
Specifically, word lines are alternately alternated every 64 bits to the uppermost metal wiring through through holes.

Since the detailed plan view showing each formation pattern of the word strap portion WS is complicated, FIG. 19 mainly shows the pattern of the word lines WL, but FIG.
Inside the word strap section WS and the memory array section MA1,
The sectional view which follows the BB line of MA2 is shown. The central convex portion P of the word line WL in FIG. 19 is a word strap contact WSC.
Is a part to be provided.

That is, the lowermost word line WL in FIG. 20 is connected to the metal wiring I via the word strap contact WSC, and further connected to the metal wiring II via the through hole contact TH1, and then shown by a virtual line in FIG. A structure is formed to be connected to the uppermost metal wiring III via a through hole contact TH2. A control signal is input from the metal wiring III to each word line. Each contact is BP
This is performed through an insulating layer such as the SG layer 66. And the figure
Although a step is formed along the line marked PEB1 in FIG. 19, the steps described in FIGS. 1 to 8 are performed in the same manner so as to flatten the step, whereby the memory cell array section MA and the word strap section are formed. The steps between WS can be flattened.

In this flattening step, since the word strap portion has no storage node, the height difference (step) from the memory cell array portion is about 0.65 μm.
When EB is laid out as above, the difference in height is about
It has been confirmed that it can be reduced to 0.2 μm.

21 to 29 show the dynamic RA of the present invention.
4 shows a fourth embodiment applied to M, and
9 is a cross-sectional view of a main part showing a manufacturing process similar to FIGS. 1 to 8 in the embodiment of FIG.

In this embodiment, an insulating layer formed on the memory cell array portion and the peripheral circuit portion is formed by plasma CVD, and the surface irregularities formed on this insulating layer are spin-coated with an organic SOG. To flatten the surface and reduce local and global steps. Others are the same as those in the first embodiment described with reference to FIGS.

First, an insulating layer (SiO ₂ layer) 166 shown in FIG. 22 is formed on the entire surface of the silicon substrate 1 of FIG. 21 having the memory cell array section MA and the peripheral circuit section PC by the plasma CVD method under the following conditions. Deposit to a thickness of 1.0 μm. The conditions of plasma CVD are as follows. Temperature Approx. 350 ℃ Gas TEOS + O ₂ Power 480W Pressure 9.0Torr

On the surface of the insulating layer 166, recesses are formed by the local steps 21 and 25 in the region of the memory cell array portion MA and the region of the peripheral circuit portion PC, respectively.
A global step 162 is formed in the boundary area of the PC.

Next, as shown in FIG. 23, an insulating layer (SiO 2
_The photoresist 70 applied on the entire surface of the _second layer 166 is exposed to a predetermined pattern and developed to form a slope 162 of the global step 162 between the memory cell array section MA and the peripheral circuit section PC.
The photoresist 70 is patterned so that the end portion 70A is located at the intermediate position on A.

Next, as shown in FIG. 24, using the photoresist 70 as a mask, the global step 162 (specifically,
The memory cell array unit MA rather than the end position of the resist 70)
The exposed portion of the SiO ₂ layer 166 on the side is uniformly etched by CF ₄ gas by anisotropic dry etching (PE
B) This dry etching is called "PEB1",
Here, the SiO ₂ layer 166 is uniformly removed by a thickness of 0.5 μm.

As a result of removing the photoresist 70, as shown in FIG. 25, the Si on the memory cell array portion MA is
The thickness of the O ₂ layer 166 is reduced by almost half, and a protruding portion 166A formed by a part of the inclined surface 162A remains at the position where the global step 162 was present. This protruding part 1
The volume and height of 66A is not so large.

Then, as shown in FIG. 26, a SiO ₂ layer 16 is formed.
SOG167 is spin-coated on the 6 to a thickness of 0.32 μm, and then cured at 450 ° C. to be solidified. The composition of SOG and the conditions of spin coating are as follows. Composition of SOG: -Si-O-CH ₃ The organic conditions in unit coating: 3000～4500Rpm baking: 100 to 350 ° C., 5 to 10 minutes Cure: 400 to 450 ° C., 30 to 60 minutes

Due to the SOG spin coating, the recesses on the local step 121 in the memory cell array portion MA are SOG.
167 is filled and becomes flat, and the concave portion on the local step 25 in the peripheral circuit portion PC is also made nearly flat, and the protrusion 166A is filled with SOG167, and the global step 162 ′ is formed.
The slope that forms The level difference 162 'formed in this way is as small as 0.7 μm
The surface of the G layer 167 is substantially flattened, and does not affect the wiring described later.

Then, as shown in FIG. 27, the SOG layer 167 is formed.
Is etched back to leave the SOG 167 only on the local step 121 and the global step 22.

Next, as shown in FIG. 28, plasma CV
The SiO ₂ layer 266 is formed on the surface by the D method.

Then, as shown in FIG. 29, a SiO ₂ layer 16 is formed.
6, 266 (and a part of the SOG layer 167 partially remaining) is provided with a contact hole 49, and a polysilicon layer 50 is formed there.
, And bit lines BL are formed on the SiO ₂ layer 266 with a predetermined width and pitch.

In this case, the height difference of the global step 162 'is considerably small, and the step of the peripheral circuit portion PC is also 135'.
As described above, since the surface of the SiO ₂ layer 266 is substantially flat as a whole, the photoresist serving as a mask when patterning the bit line BL can be processed with high accuracy, and There is no short circuit or disconnection between them.

FIG. 59 shows that such excellent results can be obtained.
~ Instead of just spin coating the SOG layer as in the prior art shown in Fig. 61, the intermediate position 70A on the slope 162A forming the global step 162 as shown in Figs.
As shown in FIG. 26, after removing the layer portion on the higher side than the (photoresist edge portion) by PEB to a predetermined thickness, as shown in FIG.
Since the OG is spin-coated, the thickness of the SiO ₂ layer 166 and the height of the step are reduced corresponding to the removed thickness, and the remaining protruding portion 166A is also spin-coated in a small state. The height difference between the high-level portion and the low-level portion of the SOG layer 167 can be significantly reduced, and the protruding portion 166A
This is because the SOG layer 167 can be embedded in the SOG layer easily and the SOG layer 167 can be sufficiently and surely planarized.

Therefore, the bit line BL (and other wirings) can be formed without disconnection or short circuit, and at the same time, the exposure of the photoresist can be performed according to the design pattern when forming the wirings. Can be formed with the width and the interval (or pitch).

As a result, the wiring can be processed finely and densely and with a large margin. Especially the design rule is the minimum line width or space (eg 0.4 μm
If the following becomes strict, the margin of the depth of focus of exposure during photolithography cannot be so large, but this is
This can be realized to a considerable extent by the flattening of the global level difference according to the present embodiment, and the process margin can be expanded. Further, in the future, in the dynamic RAM, it is expected that the structure of the memory cell will become complicated and the height thereof will increase, and accordingly, the global step difference between the memory cell array section and the peripheral circuit section becomes large. Even so, the surface can be flattened by coping with this.

According to this embodiment, in addition to the above advantages,
Since the SiO ₂ layers 166 and 266 are formed by the plasma CVD method, they can be formed at a low temperature of 300 to 400 ° C., and the layers formed by the plasma CVD method are dense and do not undergo reflow due to heating. The advantage is that there is no risk of damage to the elements already formed prior to this film formation due to heat. Further, since the heat treatment is not performed, the diffusion region does not spread between the layers.
Furthermore, the spin coating of SOG for planarization has an advantage that the coating is performed quickly and the surface is surely smoothed.

As in this example, the use of an organic SOG has the advantage that its composition can be easily adjusted and that the viscosity can be easily adjusted during spin coating because a solvent is used.

FIG. 30 shows a fifth embodiment in which the present invention is applied to a dynamic RAM.

In this embodiment, an inorganic SOG (--Si) is used instead of the organic SOG 167 in the fourth embodiment.
Inorganic substance 267 having -OH unit is used. The inorganic SOG layer can be thinner than the organic SOG layer, and does not require etch back. Therefore, the SOG layer 26
A SiO ₂ layer 266 is formed on the surface 7 by plasma CVD. In addition, the etching amount by PEB1 in FIG.
0.7 μm.

31 to 37 show the dynamic RA of the present invention.
9 shows a sixth embodiment applied to M.

According to this embodiment, the steps before the step shown in FIG. 31 are carried out in the same manner as the steps shown in FIGS. 21 to 24 (however, the SiO ₂ layer 166 of FIG. Thickness is 1.2
and the etching amount with PEB1 in FIG. 24 is 0.7 μm.
And ), And the step of flattening the step 25 of the peripheral circuit portion PC is further added.

That is, after removing the resist 70, a new photoresist 80 is deposited, and as shown in FIG. 31, each end portion 80A is positioned on the slope 25A of the step 25 in the peripheral circuit portion PC. The photoresist 80 is patterned.

Next, as shown in FIG. 32, using the photoresist 80 as a mask, the step 25 (specifically, the resist 80) is formed.
Si on the higher side (gate electrode 20 side) than the edge position)
The exposed portion of the O ₂ layer 166 is uniformly etched back by CF ₄ gas by dry etching. This dry etching is referred to as "PEB2", and here, Si on the gate electrode 20 is used.
The O ₂ layer 166 is uniformly removed by a thickness of 0.3 μm.

As a result, the SiO ₂ layer 166 on the gate electrode 20 is removed as shown in FIG.
In addition to reducing the thickness of the step 25, a protruding portion 166B formed by a part of the slope 25A remains at the portion where the step 25 existed. The volume and height of this protruding portion 166B are quite small.

Then, as shown in FIG. 34, a SiO ₂ layer 16 is formed.
An organic SOG167 is spin-coated on the 6 to a thickness of 0.3 μm and then cured at 450 ° C. to be solidified. SOG
The composition and spin coating conditions are the same as those in the fourth embodiment.

By the SOG spin coating, the concave portion and the protruding portion 166A on the local step 121 in the memory cell array portion MA are filled with the SOG 167, and the plane of the memory cell array portion MA becomes flat. The concave portion and the protruding portion 166B on the local step 25 in the peripheral circuit portion PC are also filled with the SOG 167, and the surface of the peripheral circuit portion PC becomes flat. In addition, when the global step 162 was present, the SO
The global step 162 ′ of the G layer 167 is as small as 0.5 μm, the slope thereof is gentle, the surface of the SOG layer 166 is substantially flattened, and it does not affect the wiring described later.

Then, as shown in FIG. 35, the SOG layer 167 is formed.
Is etched back to leave the SOG layer 167 only on a part of the local step 121 and the global step 22.

Next, as shown in FIG. 36, plasma CV
The SiO ₂ layer 266 is formed on the surface by the D method.

Then, as shown in FIG. 37, the SiO ₂ layer 16
6, 266 (and a part of the SOG layer 167 partially remaining) is provided with a contact hole 49, and a polysilicon layer 50 is formed there.
, And bit lines BL are formed on the SiO ₂ layer 266 with a predetermined width and pitch.

According to this embodiment, the same effect as that of the fourth embodiment can be obtained. In addition to this, the surface of the SOG layer 167 in the peripheral circuit portion PC becomes flat, and the reliability of the wiring (bit line BL) thereon is further improved.

SiO ₂ layer deposition by the plasma CVD method and S in the fourth and fifth embodiments and this embodiment.
The OG spin coating is performed by the memory cell array units MA1 and MA2 according to the third embodiment described above with reference to FIGS.
And the structure of the word strap portion WS located between them.

FIG. 38 shows a seventh embodiment in which the present invention is applied to a dynamic RAM.

In this embodiment, an inorganic SOG267 is used in place of the organic SOG167 in the sixth embodiment. The inorganic SOG layer can be thinner than the organic SOG layer and does not require etch back. Therefore, Si is formed on the SOG layer 267 by the plasma CVD method.
An O ₂ layer 266 is formed. The etching amount by PEB1 in FIG. 24 is 0.7 μm.

39 to 46 show an eighth embodiment in which the present invention is applied to an ASIC (IC for a specific application).

According to this embodiment, in order to reduce the step difference between the gate electrodes in the ASIC, first, as shown in FIG. 39, a polysilicon gate electrode is formed on the P-type silicon substrate 1.
90 is formed with a predetermined width and interval. 2, 3, in the figure
Reference numerals 4 and 5 denote a field oxide film, an N ⁺ type source region, an N ⁺ type drain region, and a gate oxide film, respectively.

Then, as shown in FIG. 40, a BPSG layer 86 of about 4% by weight of boron and about 5% by weight of phosphorus is deposited on the entire surface of the substrate 1 by CVD to a thickness of 1.2 μm. This thickness is equivalent to the etch back (etching amount is 0.5μ
Considering m), it is set to 1.2 μm. On the surface of this deposition layer 86, the gate electrode 90
A step 85 is formed on the side of the.

Next, as shown in FIG. 41, pre-annealing is performed in N ₂ at 850 ° C. for 10 minutes to form each step 85 above.
Smooth (smooth) like. The conditions of this preliminary annealing are determined so that the thermal history is minimized in consideration of the BPSG reflow process described later.

Next, as shown in FIG. 42, the photoresist 100 applied to the entire surface is exposed and developed into a predetermined pattern so that the end portion 100A is located at an intermediate position on the slope 95A of the step 95. Pattern 100.

Next, as shown in FIG. 43, using the photoresist 100 as a mask, the step 95 (specifically, the resist
The exposed portion of the BPSG layer 86 on the higher side than the end position of 100) is uniformly anisotropically dry-etched (PEB) by CF ₄ gas to form the BPSG layer 86 of 0.3.
It is uniformly removed by a thickness of μm.

As a result, the photoresist 100 is removed, and as shown in FIG. 44, the protruding portion 86A formed by a part of the slope 95A remains at the portion where the step 95 was present.
The volume and height of the protruding portion 86A are not so large.

Next, as shown in FIG. 45, annealing is performed in N ₂ at 900 ° C. for 10 minutes to reflow the BPSG layer 86. As a result, the above-mentioned protruding portion 86A is fluidized and collapsed, and only a small step (height difference is usually 0.3 to 0.8 μm, for example, about 0.5 μm) 95 ′ remains as a step at the place where the step 95 existed. The step 95 ′ is very small, and the surface of the BPSG layer 86 is substantially flattened so that it does not affect the wiring described later.

Then, as shown in FIG. 46, the BPSG layer 86
The metal wiring MW is formed thereon with a predetermined width and pitch.

In this case, the step 95 ′ has a considerably small height difference, and the surface of the BPSG layer 86 is substantially flat as a whole. Therefore, it is necessary to process the photoresist serving as a mask when patterning the metal wiring MW. It can be performed with high accuracy, and the short-circuiting or disconnection between the metal wirings described above does not occur. Besides, the same excellent effects as those of the first embodiment described above can be obtained.

47 to 54 show a ninth embodiment in which the present invention is applied to an ASIC, in which an insulating layer is provided on a metal wiring and a step formed on the surface of the insulating layer by the metal wiring is flattened. It shows the procedure to convert. In these figures, only the metal wiring is shown as an element, and the elements on the lower layer side are not shown.

FIG. 47 is a sectional view showing a state in which metal wiring 367 is formed on insulating layer 366.

First, as shown in FIG. 48, a SiO ₂ layer 368 is deposited to a thickness of 1.0 μm by plasma CVD on the entire surface of the insulating layer 366 on which the metal wiring 367 is formed. This thickness is equivalent to the etch back (etching amount is 0.3μ
Considering m), it is set to 1.0 μm. The SiO ₂ layer 368 contains
A convex portion 368A is formed on the metal wiring 367.

Next, a photoresist is provided on the SiO ₂ layer 368, which is exposed and developed to be patterned as shown in FIG. The photoresist 370 is patterned so as to remain between the protrusions 368A of the SiO ₂ layer.

Next, as shown in FIG.
The convex portion 368A of the SiO ₂ layer is etched back by anisotropic dry etching using 370 as a mask. By this etch back, the thickness of the protrusion 368A is reduced by 0.3 μm, and the recess 368B having a wedge-shaped cross section is formed on both sides of the protrusion 368A.

Next, as shown in FIG. 51, a photoresist is used.
370 is removed, and then the SiO ₂ layer 36 is removed, as shown in FIG.
An organic SOG layer 369 is laminated on the above by spin coating and cured at 450 ° C. to be solidified. In this state, the recess 368B is filled with SOG, and the SOG layer 36
The surface of 9 is flattened. Therefore, the element to be laminated in the subsequent step has a shape and dimensions that are faithful to the design and has high reliability.

Next, as shown in FIG. 53, the SOG layer 369 is etched back to expose the SiO ₂ layer 368.

Next, as shown in FIG. 54, a SiO ₂ layer 368 is formed.
Further, the SiO ₂ layer 370 is formed on the SOG 369 that partially remains by a plasma CVD method.

The formation of the SiO ₂ layer by the plasma CVD method is sufficiently lower than the melting point of aluminum, 660 ° C. 3
Since it is performed at a temperature of 00 to 400 ° C., the metal wiring 367 can be aluminum wiring. Therefore, by forming the SiO ₂ layer by the plasma CVD method, it is possible to enjoy the merit that the degree of freedom in selecting the wiring material is increased.

Also in this example, when the projections 368A of the SiO ₂ layer are thinned and the insulation is insufficient in the etching back step of FIG. SiO ₂ by plasma CVD method on the SOG layer 369 as
The layer 370 is stacked to secure interlayer insulation between the metal wiring 367 and an element formed in a later step.

Although the embodiments of the present invention have been described above, the above embodiments can be further modified based on the technical idea of the present invention.

For example, the above-mentioned preliminary annealing, PEB,
The pattern shape of the photoresist and the end position thereof may be variously changed, including the conditions of reflow and plasma CVD. For PEB, dry etching is preferable because of the problem of undercut under the resist.

In addition to the steps shown in the above-described example, the planarization method according to the present invention is capable of forming steps existing at various places on the semiconductor device, particularly steps having a height difference of 1 μm or more from 0.3 to This is an effective method when flattening to 0.8 μm or less.

The layer to be flattened is the above-mentioned B.
The present invention is not limited to the PSG layer and SOG layer, and can be applied to other insulating layers and the like.

In addition to the dynamic RAM having the stack cell capacitor described above, the present invention can be applied to the case where the conductivity type of the semiconductor region is changed, or to other semiconductor memories or other devices. it can.

[0154]

According to the present invention, an insulating film is formed on the surface of a semiconductor substrate having irregularities and / or steps, and a resist is formed on the surface of the insulating film excluding the high-level portions. Is used as a mask to remove the high-level portion of the insulating film,
After removing the resist, a predetermined film is formed on the insulating film, and the unevenness and / or step is covered by the insulating film having a flattened surface, so that the surface is easily flattened,
Concavities and convexities are significantly reduced in the subsequent process.

Further, by removing the above-mentioned layer portion by the above-mentioned predetermined thickness and then eliminating the protruding portion existing on the lower side than the arbitrary position of the step by heat treatment, the unevenness of the surface can be flattened. It will be easier. This is because the protruding portion remains after removing the layer portion by a predetermined thickness, and the volume thereof is small.

Further, if the protruding portions are eliminated by heat treatment and the surface of the layer is flattened, the exposure of the photoresist can be performed according to the design pattern when forming the wiring on this layer. The wiring can be formed with a predetermined width and interval (or pitch).

Therefore, the wiring can be finely and densely processed.
Moreover, it can be performed with a large margin. In particular, the design rule is the minimum line width or spacing (for example, 0.4 μm or less)
However, the margin of the depth of focus of the exposure during photolithography cannot be so large, but this can be achieved to a considerable extent by the flattening of the step according to the present invention, and the process margin can be expanded. Further, when aluminum is used for the wiring, it is possible to minimize disconnection at the step portion due to so-called electromigration during use.

If, instead of the heat treatment, the insulating material is applied to substantially fill the protruding portion and the surface of the layer is flattened, the same effect as that of the heat treatment can be obtained. To be

In this case, in the above-mentioned layer as the insulating layer, the introduction of undesired impurities is prevented and the interlayer insulating property is further ensured. As a result, a highly reliable semiconductor device can be obtained.

Further, the method according to the present invention is excellent in that it is an extension technique in which the required steps are added to the conventional technique, there is little dust generation, and the introduction of a new device is unnecessary.

[Brief description of drawings]

FIG. 1 is a dynamic RA according to a first embodiment of the present invention.
FIG. 9 is a sectional view of an essential part showing one step of the manufacturing process of M
A cross-sectional view taken along the line: the same applies hereinafter).

FIG. 2 is a sectional view of an essential part showing another stage of the same.

FIG. 3 is a main-portion cross-sectional view showing another step of the same.

FIG. 4 is a sectional view of a key portion showing another step of the same.

FIG. 5 is a sectional view of an essential part showing another stage of the same.

FIG. 6 is a main-portion cross-sectional view showing another step of the same.

FIG. 7 is a main-portion cross-sectional view showing another step of the same.

FIG. 8 is a main-portion cross-sectional view showing still another step of the same.

FIG. 9 is a plan pattern view of a main part of the dynamic RAM.

FIG. 10 is a main-portion cross-sectional view showing a planarized state depending on a resist position in the manufacturing process.

FIG. 11 is a cross-sectional view of an essential part similar to FIG. 10 when the resist position is changed.

FIG. 12 is a cross-sectional view of an essential part similar to FIG. 10 when the resist position is further changed.

FIG. 13 is a dynamic RA according to the second embodiment of the present invention.
FIG. 9 is a main-portion cross-sectional view showing a step in the manufacturing process of M.

FIG. 14 is a main-portion cross-sectional view showing another step of the same.

FIG. 15 is a main-portion cross-sectional view showing another step of the same.

FIG. 16 is a sectional view of a key portion showing another step of the same.

FIG. 17 is a main-portion cross-sectional view showing another step of the same.

FIG. 18 is a dynamic RA according to a third embodiment of the present invention.
It is a schematic diagram showing a layout of M.

FIG. 19 is a plan pattern view of a main part of the same dynamic RAM.

20 is a cross-sectional view taken along the line BB of FIG.

FIG. 21 is a dynamic RA according to a fourth embodiment of the present invention.
FIG. 9 is a main-portion cross-sectional view showing a step in the manufacturing process of M.

FIG. 22 is a sectional view of a key portion showing another step of the same.

FIG. 23 is a main-portion cross-sectional view showing another step of the same.

FIG. 24 is a main-portion cross-sectional view showing another step of the same.

FIG. 25 is a main-portion cross-sectional view showing another step of the same.

FIG. 26 is a main-portion cross-sectional view showing another step of the same.

FIG. 27 is a main-portion cross-sectional view showing another step of the same.

FIG. 28 is a main-portion cross-sectional view showing another step of the same.

FIG. 29 is a sectional view of a key part showing a further step of the same.

FIG. 30 is a dynamic RA according to a fifth embodiment of the present invention.
FIG. 9 is a main-portion cross-sectional view showing a step in the manufacturing process of M.

FIG. 31 is a dynamic RA according to the sixth embodiment of the present invention.
FIG. 9 is a main-portion cross-sectional view showing a step in the manufacturing process of M.

FIG. 32 is a sectional view of a key portion showing another step of the same.

FIG. 33 is a main-portion cross-sectional view showing another step of the same.

FIG. 34 is a main-portion cross-sectional view showing another step of the same.

FIG. 35 is a main-portion cross-sectional view showing another step of the same.

FIG. 36 is a main-portion cross-sectional view showing another step of the same.

FIG. 37 is a main-portion cross-sectional view showing still another step of the same.

FIG. 38 is a dynamic RA according to the seventh embodiment of the present invention.
FIG. 9 is a main-portion cross-sectional view showing a step in the manufacturing process of M.

FIG. 39 is a dynamic RA according to the eighth embodiment of the present invention.
FIG. 9 is a main-portion cross-sectional view showing a step in the manufacturing process of M.

FIG. 40 is a main-portion cross-sectional view showing another step of the same.

FIG. 41 is a sectional view of a key portion showing another step of the same.

FIG. 42 is a sectional view of a key portion showing another step of the same.

FIG. 43 is a sectional view of a key portion showing another step of the same.

FIG. 44 is a main-portion cross-sectional view showing another step of the same.

FIG. 45 is a main-portion cross-sectional view showing another step of the same.

FIG. 46 is a main-portion cross-sectional view showing still another step of the same.

FIG. 47 is a main-portion cross-sectional view showing a step in the manufacturing process of the semiconductor device according to the ninth embodiment of the invention.

FIG. 48 is a main-portion cross-sectional view showing another step of the same.

FIG. 49 is a sectional view of a key portion showing another step of the same.

FIG. 50 is a sectional view of a key portion showing another step of the same.

FIG. 51 is a sectional view of a key portion showing another step of the same.

FIG. 52 is a sectional view of a key portion showing another step of the same.

FIG. 53 is a main-portion cross-sectional view showing another step of the same.

FIG. 54 is a cross-sectional view of main parts showing still another stage of the same.

FIG. 55 is a main-portion cross-sectional view showing a step in the manufacturing process of the conventional dynamic RAM.

FIG. 56 is a cross-sectional view of main parts showing another stage of the same.

FIG. 57 is a sectional view of a key portion showing another step of the same.

FIG. 58 is a main-portion cross-sectional view showing still another step of the same.

FIG. 59 is a main-portion cross-sectional view showing a step in the manufacturing process of the dynamic RAM according to another conventional example.

FIG. 60 is a main-portion cross-sectional view showing another step of the same.

FIG. 61 is a cross-sectional view of main parts showing still another stage of the same.

FIG. 62 is an enlarged cross-sectional view of a memory cell of a dynamic RAM according to a conventional example.

[Explanation of symbols]

1 ... Silicon substrate 3, 23 ... N ⁺ type source region 4, 24 ... N ⁺ type drain region 6 ... SiO ₂ layer 11 ... Polysilicon layer (storage node: lower electrode) 13 , 50 ・ ・ ・ Polysilicon layer 15 ・ ・ ・ Dielectric film 16 ・ ・ ・ Polysilicon layer (plate electrode: upper electrode) 20, 90 ・ ・ ・ Gate electrode 21, 121 ・ ・ ・ Local step 22 ・ ・ ・ Global Steps 25, 32, 35, 35 ', 62, 62', 95, 95 ', 162, 162' ・
..Steps 35A, 62A, 95A, 162A ... Slopes 36, 66, 86 ... BPSG layer 49 ... Contact holes 66A, 66B, 86A, 166A, 166B ... Protruding portions 70, 80, 100, 370 ・ ・ ・ Photoresist 70A, 80A, 100A ・ ・ ・ Edge of resist pattern 166, 266, 186, 266, 368, 370 ・ ・ ・ Plasma C
SiO ₂ layer by VD method 167, 369 ... Organic SOG layer 267 ... Inorganic SOG layer 367, MW ... Metal wiring WL ... Word line BL ... Bit line M-CELL ... Memory cell MA ・ ・ ・ Memory cell array section Cap ・ ・ ・ Cell capacitor PC ・ ・ ・ Peripheral circuit section TR ・ ・ ・ Transistor PEB ・ ・ ・ Patterned etch back BPSG ・ ・ ・ Boron and phosphorus-doped silicate glass SOG ・ ・ ・ Spin on Glass

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication location H01L 21/31 9276-4M H01L 27/10 621C 9276-4M 681F

Claims (12)

[Claims] 1. When forming an insulating film on a surface having unevenness and / or steps formed on a semiconductor substrate, forming an insulating film on the surface having unevenness and / or steps, A step of forming a resist on a surface of the film excluding a high part protruding above a predetermined height; a step of removing the high part of the insulating film using the resist as a mask; And a step of forming a predetermined film on the insulating film after the removal of the film, and the unevenness and / or the step is covered with the insulating film having a flattened surface. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a silicate glass film is formed as the insulating film. 3. The method according to claim 2, further comprising a step of applying a silicate glass on a surface having irregularities and / or steps and then performing a heat treatment to flatten the insulating film made of the silicate glass. Manufacturing method of semiconductor device. 4. A silicon dioxide film is formed as an insulating film,
The method for manufacturing a semiconductor device according to claim 1. 5. SOG on the planarized silicon dioxide film
The method for manufacturing a semiconductor device according to claim 4, further comprising a step of spin-coating (Spin on Glass). 6. The SOG is etched back to leave the SOG in the concave portion of the insulating film made of silicon dioxide.
The method for manufacturing a semiconductor device according to claim 5, wherein a second insulating film made of silicon dioxide is further formed on the insulating film where G remains. 7. A resist layer is formed in a predetermined pattern so that a resist end portion is located on a slope of a step and / or a convex portion, and this resist layer is used as a mask to form an insulating film on a side higher than the resist layer. The uniform removal by a predetermined thickness by etching is as set forth in any one of claims 1 to 6,
Manufacturing method of semiconductor device. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the protruding portion remaining after etching is eliminated. 9. When manufacturing a semiconductor device in which a global step exists between a memory cell array section and a peripheral circuit section due to a difference in a predetermined circuit configuration formed on a semiconductor substrate, at least a surface including the step is formed. Forming an insulating film over the memory cell array portion and the peripheral circuit portion; and forming a resist except for a position on a side higher than an arbitrary position on the slope forming the step on the insulating film. A semiconductor including a step, a step of removing the high-order portion of the insulating film by a predetermined thickness using the resist as a mask, and a step of forming a predetermined film on the insulating film after removing the resist Device manufacturing method. 10. When manufacturing a semiconductor device in which a local step exists due to a convex portion of a predetermined circuit formed on a semiconductor substrate, a step of forming an insulating film on a surface including the convex portion; A step of forming a resist on the surface excluding the high-level portion forming the convex portion, a step of removing the high-level portion of the insulating film by a predetermined thickness using the resist as a mask, and after removing the resist And a step of forming a predetermined film on the insulating film, the method for manufacturing a semiconductor device. 11. The manufacturing method according to claim 9 and claim 10.
A method of manufacturing a semiconductor device, which is carried out together with the method of manufacturing described in 1. 12. The method for manufacturing a semiconductor device according to claim 9, which comprises the material or the process according to any one of claims 2 to 8.