JP5019934B2 - Manufacturing method of solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device used in a mobile phone with a camera, a digital still camera, a surveillance camera, and the like, a manufacturing method thereof, and an electronic information device. A solid-state imaging device including a transistor having a gate electrode electrically connected to the diffusion region of the FD portion, and an output circuit that outputs a signal corresponding to the charge change of the FD portion through the transistor; The present invention relates to a manufacturing method and electronic information equipment.

  This type of conventional solid-state imaging device includes a CCD solid-state imaging device and a CMOS solid-state imaging device.

  FIG. 7 is a schematic diagram illustrating a CCD type solid-state imaging device.

  The CCD type solid-state imaging device 100 includes a plurality of photoelectric conversion elements 1 made of photodiodes arranged vertically and horizontally on a light receiving surface, a vertical CCD 10 arranged along a vertical arrangement of the elements, and the vertical CCD 10 The horizontal CCD 20 disposed at the end of the horizontal CCD 20 and the signal output unit A disposed at the end of the horizontal CCD 20 and converting the electric charge from the horizontal CCD 20 into a voltage signal and outputting the voltage signal are provided. In the figure, reference numeral 100a denotes a pixel portion in which the photoelectric conversion element 1 and the vertical CCD 10 are arranged.

  As the configuration of the signal output unit A of such a solid-state imaging device, an FDA (Floating Diffusion Amplifier) type is generally widely used.

  FIG. 8 is a plan view showing details of the signal output unit A. The signal output unit A will be described with reference to FIGS. 8 and 7. In FIG. 8, the same reference numerals as those in FIG. 7 denote the same components.

  The signal output unit A of the solid-state imaging device accumulates the charges transferred from the horizontal CCD 20, holds a potential corresponding to the charges, and then repeats the operation to become a reset potential by a reset operation, and the horizontal CCD 20 A horizontal output transistor 31 that controls the transfer of charge from the FD unit 30 to the FD unit 30, a reset transistor 32 that controls the reset operation thereof, an output circuit 40 that converts the displacement of the charge of the FD unit 30 into a signal, amplifies and outputs the signal, Consists of.

  The output circuit 40 includes a plurality of stages (2 to 3 stages) of source follower circuits. An initial stage transistor 41 constituting the output circuit 40 includes an impurity diffusion region 41b formed on a substrate, and the impurity diffusion region. A gate electrode 41a disposed on a gate insulating film (not shown). Further, a horizontal output transistor 31 for controlling the transfer of charges from the horizontal CCD 20 to the FD unit 30 is disposed at the end of the horizontal CCD 20, and the horizontal output transistor 31 is an impurity diffusion region constituting the horizontal CCD 20. An impurity diffusion region 31b connected to 20a, and a gate electrode 31a disposed on the impurity diffusion region 31b via a gate insulating film. Further, the reset transistor 32 is disposed on the opposite side of the horizontal CCD 20 with respect to the FD portion 30, and the reset transistor 32 includes an impurity diffusion region 32 b connected to the impurity diffusion region 30 a constituting the FD portion 30. And a gate electrode 32a disposed on the impurity diffusion region 32b via a gate insulating film (not shown).

  In the CCD type solid-state imaging device having such a configuration, the charge generated in the photoelectric conversion element 1 is transferred to the horizontal CCD 20 by the vertical CCD 10, and the charge transferred to the horizontal CCD 20 is further transferred to the horizontal output transistor by the horizontal CCD 20. The data is transferred to the FD unit 30 via 31 and stored in the FD unit 30. Then, the FD unit 30 holds a potential corresponding to the accumulated charge, and this potential is amplified by the output circuit 40 and output. The charge converted into the voltage signal is discharged from the FD unit 30 by the reset transistor 32.

  Next, a CMOS type solid-state imaging device will be briefly described.

  FIG. 9 is a schematic plan view for explaining a CMOS type solid-state imaging device, and shows a photoelectric conversion element and a signal output unit for converting charges from the photoelectric conversion element into a signal voltage.

  Also in this CMOS type solid-state imaging device, photodiodes as photoelectric conversion elements are arranged vertically and horizontally on the light receiving surface, but FIG. 9 shows only two adjacent photodiodes.

  In this CMOS type solid-state imaging device, the two adjacent photodiodes 1a share the signal output part B that converts the charge generated in the photodiode 1a into a voltage signal and outputs the voltage signal. The signal output unit B accumulates the charge from the photodiode 1a, holds the potential corresponding to the charge, and then repeats the operation to become the reset potential by the reset operation, and the FD unit 60 from the photodiode to the FD unit 60. A transfer transistor 61 that controls the transfer of charge to the output, a reset transistor 62 that controls the reset operation, and an output circuit 70 that converts the charge displacement of the FD section 60 into a signal, amplifies it, and outputs it.

  An output first stage transistor 71 constituting the output circuit 70 includes an impurity diffusion region 71b formed on the substrate, and a gate electrode 71a disposed on the impurity diffusion region 71b via a gate insulating film (not shown). have. The transfer transistor 61 includes an impurity diffusion region 61b located between the photodiode 1a and the FD portion 60, and a gate electrode 61a disposed on the impurity diffusion region 61b via a gate insulating film. ing. Further, the reset transistor 62 is disposed on the opposite side of the photodiode 1 a with respect to the FD portion 60, and the reset transistor 62 is an impurity diffusion region located between the FD portion 60 and the reset drain portion 63. 62b, and a gate electrode 62a disposed on the impurity diffusion region 62b via a gate insulating film (not shown).

  In the CMOS solid-state imaging device having such a configuration, charges generated in the photodiode unit 1a are accumulated in the FD unit 60 via the transfer transistor 61, and the FD unit 60 outputs a signal corresponding to the accumulated charge. appear. Then, the output circuit 70 including the first stage transistor 71 amplifies and outputs the voltage signal. The electric charge converted into the voltage signal is discharged to the reset drain 63 through the reset transistor 62.

  In the CCD solid-state imaging device, the FD portion 30 and the gate electrode 41b of the output circuit 40 are connected by a wiring layer 51 formed on the gate electrode 41b via an insulating film (not shown). ing. That is, one end portion of the wiring layer 51 is connected to the impurity diffusion region 30a constituting the FD portion 30 through the contact hole 33 formed in the insulating film, and the other end portion of the wiring layer 51 is formed in the insulating film. The contact hole 43 is connected to the gate electrode 41 a of the first stage transistor of the output circuit 41.

  Such a connection structure between the FD unit 30 and the gate electrode 41a of the output circuit 40 in the solid-state imaging device is disclosed in, for example, Patent Document 1 and Patent Document 2.

  First, the connection structure disclosed in Patent Document 1 will be described with reference to FIG.

  A p-well layer (p-well) 202 is formed in the surface region of the n-type silicon substrate (n-sub) 201, and a field oxide film 203 and an n + impurity diffusion region 204 are formed in the p-well layer 2. Yes. The diffusion region 204 becomes an FD portion. A gate electrode 206 is disposed on the field oxide film 203 through a gate oxide film 205. The gate electrode 206 is a gate electrode of the output circuit (see FIGS. 7 and 8). A conductive film 207 made of TiN or the like is formed on the gate electrode 206 and the diffusion region 204, and a conductive film made of a refractory metal such as tungsten is formed on the conductive film 207. A film 208 is formed.

  That is, in Patent Document 1, the gate electrode 206 is formed on the p well layer 202 of the silicon substrate 201 via the gate insulating film 205, the opening is formed in the gate insulating film 205, and the p of the silicon substrate 201 is formed. After the diffusion region of the FD portion formed in the well layer 202 is exposed, the conductive films 207 and 208 are selectively formed so as to span the gate electrode 206 and the exposed diffusion region of the FD portion. The electrode and the FD part are electrically connected.

  Next, a connection structure between the FD portion and the gate electrode of the output circuit disclosed in Patent Document 2 will be described with reference to FIG.

  A diffusion region 215 as the FD portion is formed in the surface region of the n-type semiconductor substrate 212. A wiring 210 is formed on the semiconductor substrate 212 via a silicon oxide film 213. The wiring 210 is extended from the gate electrode of the output circuit. A silicon oxide film 214 is further formed on the wiring 210 and the silicon oxide film 213, and a contact portion 211 is formed on a portion of the silicon oxide film 214 on the wiring 210, and the silicon oxide films 213 and 214 are formed. The contact portion 219 is formed on the FD portion. A wiring part 212 is formed on the silicon oxide film 214, one end of the wiring part 212 is connected to the FD part 215 via a contact part 219, and the other end of the wiring part 212 is connected via a contact part 211. Are connected to a wiring 210 extending from the gate electrode.

  That is, in Patent Document 2, after the wiring 210 as the gate electrode is formed, the insulating film 214 is formed thereon, and the insulating film 213 on the wiring 210 as the gate electrode and the insulating film 213 on the FD portion. After the openings are formed in 214 and 214, a metal wiring material is formed so as to straddle these openings, thereby electrically connecting the diffusion region of the FD portion and the gate electrode of the output circuit.

  Further, Patent Document 3 discloses another example of a connection structure between the FD portion 30 and the gate electrode 41a of the output circuit 41 shown in FIG. 8, and this connection structure will be described with reference to FIG.

An n ⁺ diffusion region (FD region) 226 constituting the FD portion is formed on the surface portion of the semiconductor substrate 223, and a gate electrode 221 is formed on the semiconductor substrate 223 via a gate insulating film 224. . Further, an interlayer insulating film 227 is formed over the gate electrode 221 and the gate insulating film 224, and a contact hole 228 is formed in the adjacent portion of the interlayer insulating film 227 between the gate electrode and the FD portion. A tungsten plug 220 is buried in the contact hole, and the gate electrode 221 and the FD region 226 are electrically connected by the plug 220.

Also in the CMOS type solid-state imaging device, the gate electrode 71a of the output transistor constituting the FD section 60 and the output circuit 70 is an insulating film (not shown) on the gate electrode 71a, like the CCD type solid-state imaging device. Are connected by a wiring layer 52 formed through the connection. That is, one end portion of the wiring layer 52 is connected to the impurity diffusion region 60a of the FD portion 60 through the contact hole 64 formed in the insulating film, and the other end portion of the wiring layer 52 is formed in the insulating film. The contact hole 74 is connected to the gate electrode 71 a of the output transistor 71 constituting the output circuit 70.
JP 2006-344654 A JP 2000-22122 A JP 2002-368203 A

  However, in Patent Document 1 and Patent Document 2, since the wiring connecting the FD portion and the gate electrode of the output transistor is formed by processing a metal wiring material, the substrate when processing the metal wiring material There is a problem that pixel characteristics are deteriorated (white scratches, etc.) due to damage to the metal and due to diffusion of constituent materials of the metal wiring material, for example, Ti diffusion from TiN.

  Further, in the case of performing the connection using the metal plug (tungsten material) disclosed in Patent Document 3, the interlayer insulating film is planarized before the tungsten is deposited, or the planarization is performed by a metal polishing method after the tungsten is deposited. It is necessary, and due to this flattening process, the distance between the substrate of the pixel portion and the condensing lens is enlarged, the condensing efficiency is lowered, and the pixel characteristics are deteriorated (sensitivity deterioration).

  Hereinafter, the point that the distance between the substrate of the pixel portion and the condensing lens increases due to the flattening process will be described with reference to FIGS.

  For example, as shown in FIG. 13A, contact holes 28a and 28b are formed in the interlayer insulating film 27a while the surface of the interlayer insulating film 27a formed on the semiconductor substrate 23 is not flat. When the metal material is deposited, the metal material is deposited thicker in the thin part of the interlayer insulating film 27a than in the thick part.

  For this reason, as shown in FIG. 13B, when the deposited metal material is etched back so that the opening of the contact hole 28a in the thin portion of the interlayer insulating film 27a is exposed, in the thick portion of the interlayer insulating film 27a, The metal material embedded in the contact hole 28b is etched, and a step portion is formed.

  If a wiring layer is formed in a portion where such a step portion is formed, disconnection of the wiring, poor connection between the wiring and the metal material in the contact hole, and the like are caused.

  Therefore, the interlayer insulating film needs to be planarized. However, the flattening of the interlayer insulating film causes an increase in the distance between the substrate of the pixel portion and the condenser lens.

  Briefly, in the pixel portion 10, as shown in FIG. 14 (a), vertical CCD diffusion regions 10a are disposed on both sides of the photodiode 1, and the vertical CCD gate electrode is disposed on the diffusion region 10a. 10b is arranged, when the interlayer insulating film 12 is not flattened, the interlayer insulating film 12 is recessed at the portion above the photodiode 1, and the microlens 13 is formed above the photodiode 1. Of the interlayer insulating film 12. FIG. 14A shows a cross-section corresponding to the A-A ′ line portion of FIG. 7, and the surface of the substrate 11 and the microlens 13 are separated by a distance L <b> 1.

  On the other hand, when the interlayer insulating film 12 is planarized, as shown in FIG. 14B, the distance between the surface of the substrate 11 and the microlens 13 increases to a distance L2.

  The reason is that when the interlayer insulating film 12 is planarized, as shown in FIG. 15A, the interlayer insulating film 12a is formed thick, and the interlayer insulating film 12a is formed as shown in FIG. As shown, since the surface is etched back so as to be flat, the thickness L2 of the interlayer insulating film 12a after the etch back is the thickness of the interlayer insulating film 12 in the photodiode 1 portion when flattening is not performed. This is because it becomes thicker than the thickness L1.

  In addition, in this way, not only when the interlayer insulating film is planarized before depositing a metal material such as tungsten on the interlayer insulating film, but also after the metal material such as tungsten is deposited on the interlayer insulating film. Even when the step is performed by a metal polishing method, since the interlayer insulating film needs to be formed thick, the distance between the surface of the substrate 11 and the microlens 13 increases.

  The present invention has been made in order to solve the above-described conventional problems, and does not cause deterioration of pixel characteristics due to a wiring process, and has a device structure that can ensure high reliability. The purpose is to obtain.

  An object of the present invention is to obtain a method for manufacturing a solid-state imaging device capable of manufacturing a solid-state imaging device with high reliability without causing deterioration of pixel characteristics due to a wiring process.

A method of manufacturing a solid-state imaging device according to the present invention is a method of manufacturing a solid-state imaging device, the step of forming an impurity diffusion region serving as a floating diffusion portion that accumulates signal charges on a semiconductor substrate, and the impurities A step of forming an opening in the gate insulating film formed on the diffusion region so that a part of the impurity diffusion region is exposed, a step of depositing a gate electrode material on the entire surface, and patterning the deposited gate electrode material Forming a gate electrode of a transistor that outputs a signal in accordance with a change in charge of the floating diffusion portion, and a part of the gate electrode of the transistor has an opening in the gate insulating film. through it, it is disposed so as to come in contact to the impurity diffusion region serving as the floating diffusion portion, to form the gate electrode In the step, the deposited gate electrode material is patterned so that the planar shape of the gate electrode includes the planar shape of the opening of the gate insulating film, and after the gate electrode is formed, a heat treatment exceeding 800 ° C. is performed. In addition, the impurity diffusion region and the gate electrode are electrically connected by diffusing phosphorus, which is an impurity in the gate electrode material, into the impurity diffusion region serving as the floating diffusion portion by the heat treatment. Therefore, the above object can be achieved.

  Preferably, a polysilicon wiring material is used as the gate electrode material in the method for manufacturing a solid-state imaging device of the present invention.

  Preferably, the method for manufacturing a solid-state imaging device according to the present invention further includes a step of forming an insulating film covering the gate electrode after the gate electrode is formed.

  Preferably, an SiO 2 material is used for the insulating film covering the gate electrode in the method for manufacturing a solid-state imaging device of the present invention, and the insulating film is formed by a thermal oxidation method or a CVD method.

  The operation of the present invention will be described below with the above configuration.

  In the present invention, the gate electrode of the transistor of the output circuit that outputs a signal corresponding to the accumulated charge in the floating diffusion portion (FD portion) is so that a part thereof is in contact with the impurity diffusion region constituting the FD portion. Therefore, it is possible to eliminate the step of forming a wiring for connecting the gate electrode of the transistor of the output circuit and the impurity diffusion region of the FD portion through the contact hole. Accordingly, damage to the silicon substrate can be reduced as compared with the case of forming a contact hole in the method of connecting the FD portion and the gate electrode of the output first stage transistor, thereby improving the reliability of the element.

  In addition, since the metal wiring is not used for the connection between the gate electrode of the transistor of the output circuit and the FD portion, there is no influence on the pixel portion such that the constituent material of the metal wiring material diffuses into the pixel portion. As a result, image quality deterioration can be avoided.

  Further, there is no increase in the distance between the substrate of the pixel portion and the condensing lens as in the case where a metal plug is used for connection between the gate electrode of the transistor of the output circuit and the FD portion, which is caused by a decrease in condensing efficiency. There is no deterioration of pixel characteristics.

  In the present invention, since the gate electrode is made of a polysilicon wiring material, the diffusion region constituting the FD portion is auto-doped with polysilicon from the polysilicon constituting the gate electrode. For this reason, it is possible to reduce the contact resistance while suppressing an increase in parasitic capacitance when a high concentration diffusion region for reducing the contact resistance between the gate electrode and the diffusion region of the FD portion is formed. Thereby, it is possible to avoid a decrease in the conversion rate for converting the accumulated charge in the FD portion into a voltage signal. As a result, it is possible to provide a solid-state imaging device that has no reduction in conversion rate and no deterioration in image quality.

  In the present invention, the gate electrode is formed by patterning the deposited gate electrode material so that the planar shape of the gate electrode includes the planar shape of the gate insulating film opening on the FD portion. When patterning a certain polysilicon film, etching of the substrate of the FD portion can be avoided.

  As described above, according to the present invention, the connection structure between the diffusion region of the FD portion and the gate electrode of the transistor of the output circuit that converts the electric charge from the FD portion into a signal voltage and outputs the signal, damage to the substrate, It is possible to form the pixel portion without increasing the distance between the substrate of the pixel portion and the condensing lens, and it is possible to provide a highly reliable solid-state imaging device that does not deteriorate pixel characteristics.

Hereinafter, embodiments of the present invention will be described.
(Embodiment 1)
FIG. 1 is a diagram for explaining a CCD type solid-state imaging device according to Embodiment 1 of the present invention. FIG. 1A is a plan view showing a signal output unit of the solid-state imaging device, and FIG. It is the Ib-Ib sectional view taken on the line of Fig.1 (a).

  The CCD solid-state imaging device according to the first embodiment is similar to the conventional CCD solid-state imaging device shown in FIG. 7, and includes a plurality of photoelectric conversion elements including photodiodes arranged vertically and horizontally on the light receiving surface, and the element. A vertical CCD arranged along the vertical arrangement of the horizontal CCD, a horizontal CCD arranged at the end of the vertical CCD, and arranged at the end of the horizontal CCD, and converts the charge from the horizontal CCD into a voltage signal. And a signal output unit for outputting. In addition, the signal output unit A1 in the solid-state imaging device of the first embodiment shown in FIG.

  The signal output unit A according to the first embodiment accumulates the charges transferred from the horizontal CCD 120, holds a potential corresponding to the charges, and then repeats an operation to become a reset potential by a reset operation (hereinafter referred to as FD). 114), a horizontal output transistor 125 that controls the transfer of charges from the horizontal CCD 120 to the FD unit 114, a reset transistor 126 that controls the reset operation thereof, and the displacement of charges in the FD unit 114 are converted into signals. It comprises an output circuit 140 that amplifies and outputs.

  The output circuit 140 is the same as the output circuit 40 in the conventional solid-state imaging device, and is configured by a plurality of (two to three stages) source follower circuits. The first-stage transistor 124 constituting the output circuit 140 includes an impurity diffusion region (hereinafter referred to as an activation region) 124b formed in the P well 115 on the surface of the substrate 110, and a gate insulating film 119 on the activation region 124b. And a gate electrode 124a disposed through the gate electrode 124a. Here, the activation region 124 b includes an impurity implantation region 116 for adjusting the threshold value of the first-stage transistor 124 obtained by implantation of P-type impurities into the surface of the P well 115.

  A horizontal output transistor 125 that controls the transfer of charges from the horizontal CCD to the FD unit 11 is disposed at the terminal end of the impurity diffusion region 120 a of the horizontal CCD 120. The horizontal output transistor 125 includes an impurity diffusion region (hereinafter referred to as a diffusion region) 125b connected to an impurity diffusion region (hereinafter referred to as a diffusion region) 120a of the horizontal CCD, and a gate insulating film on the diffusion region 125b. The gate electrode 125a is disposed. Further, the reset transistor 126 is disposed on the opposite side of the FD portion 114 from the horizontal CCD. The reset transistor 126 includes an impurity diffusion region (hereinafter referred to as a diffusion region) 126b connected to an impurity diffusion region (hereinafter referred to as a diffusion region) 117 constituting the FD portion 114, and a gate insulating film (see FIG. And a gate electrode 126a disposed through the gate electrode 126a. Note that the horizontal output transistor 125 and the reset transistor 126 in the solid-state imaging device of Embodiment 1 are the same as those in the conventional solid-state imaging device.

  In the CCD type solid-state imaging device according to the first embodiment, a part of the gate electrode 124 a of the output first stage transistor 124 is formed in the diffusion region 117 of the FD portion 114 and is formed on the diffusion region 117. It arrange | positions so that it may contact through the opening 103 of the film | membrane 118. FIG. That is, a portion 124 a 1 located on the diffusion region 117 of the FD portion 114 of the gate electrode 124 a is a portion where the opening 103 is formed in the gate insulating film 118 on the diffusion region 117 and is exposed in the opening 103. It is in contact with the diffusion region 117. As a result, the charges transferred from the horizontal CCD unit are accumulated, the FD unit 114 that holds a potential corresponding to the amount of accumulated charges, and the output that amplifies the potential held by the FD unit 114 and outputs a voltage signal. The gate electrode of the first stage transistor of the circuit 140 is electrically connected.

  Further, a portion 124 a 1 of the gate electrode 124 a located on the diffusion region 117 of the FD portion 114 has a larger planar shape including the planar shape of the opening 103 of the gate insulating film 118.

  Next, the operation will be briefly described with reference to FIGS.

  In the CCD type solid-state imaging device having such a configuration, the charges generated in the photoelectric conversion element 1 are transferred to the horizontal CCD 120 by the vertical CCD, and the charges transferred to the horizontal CCD 120 are further transferred to the horizontal output transistor by the horizontal CCD 120. The data is transferred to the FD unit 114 via 125 and stored in the FD unit 114. Then, the FD unit 114 holds a potential corresponding to the accumulated charge, and this potential is amplified by the output circuit 140 and output. The charge converted into the voltage signal is discharged from the FD unit 114 by the reset transistor 126.

  Next, a method for manufacturing the solid-state imaging device according to the first embodiment will be described with reference to FIGS. 2 (a) to 4 (a) are plan views showing the state of the signal output unit at a specific stage in the method of manufacturing the solid-state imaging device, and FIG. 2 (b) is a plan view of FIG. IIb-IIb sectional view, FIG. 3B is a sectional view taken along line IIIb-IIIb in FIG. 3A, and FIG. 4B is a sectional view taken along line IV-IV in FIG. 2 to 5, the same reference numerals as those in FIG. 1 denote the same components.

As shown in FIG. 4B, a P well region 115, a field oxide film 112, and a thermal oxide film 111 are formed on the silicon substrate 110. The field oxide film 112 may be a thermal oxide film formed by a LOCOS method or a CVD dioxide oxide film (SiO ₂ film) formed by using an STI method (Shallow Trench Isolation). Here, the thermal oxide film 111 is formed to a thickness of about 100 to 1000 angstroms, and the P well region 115 is generally formed by P-type implantation using boron as an ionic species. Further, as shown in FIG. 4A, the field oxide film 112 includes a portion that becomes the active region (diffusion region) 124b of the first stage transistor of the output circuit 140 and a portion that becomes the floating diffusion portion (FD portion) 114. It is separated by. FIG. 4A shows a portion that becomes an active region (diffusion region) 120a of a horizontal CCD, a portion that becomes an active region (diffusion region) 131b of a horizontal transfer transistor, and an active region (diffusion region) 132b of a reset transistor. This part is shown.

  Next, as shown in FIG. 3B, shallow P-type implantation for adjusting the threshold value of the first-stage transistor is performed on the portion that becomes the active region 124b of the first-stage transistor, thereby forming the channel implantation region 116. However, this P-type implantation is not necessarily performed. Further, an N-type impurity is introduced into a portion that becomes the active region 120a of the horizontal CCD 120, a portion that becomes the active region 131b of the horizontal transfer transistor, a portion that becomes the active region 117 of the FD portion 114, and a portion that becomes the active region 132b of the reset transistor. Diffusion forms these active regions. At this time, an active area of the vertical CCD is also formed in the pixel portion.

  Thereafter, the first gate insulating film 118 and the first gate electrode made of an ONO film or the like are formed, and the structure of the first gate transistor constituting the vertical CCD and the horizontal CCD is formed. At this time, as shown in FIG. 5A, on the pixel unit 10 (see FIG. 7) side, the first gate insulating film 118 and the first gate (1 Gate) G1 are formed on the P well 115, and the output circuit 114 is formed. On the side, only the first gate insulating film is formed. The first gate insulating film 118 is formed by stacking an upper oxide film 118c on a lower oxide film 118a via a nitride film 118b. Further, a polysilicon (PolySi) film is used for the first gate electrode. Thereafter, as shown in FIG. 5B, an oxide film 108a and a silicon nitride film (SiN film) 108b are formed by thermal oxidation on the pixel portion side. Through this process, in the pixel portion, the first gate electrode G1 is completely insulated from the second gate electrode (2Gate) G2 disposed later in the upper layer.

  Further, the ONO film 118 formed as the first gate insulating film is deleted in the portion (the output circuit 140 side) that becomes the active region 124 b of the output first stage transistor, and the second gate oxide film 119 is formed on the channel implantation region 116. (See FIG. 5 (c)).

  Thereafter, an opening 103 (see FIG. 4B) is formed in the ONO film 118 of the FD unit 114. The opening 103 serves as a contact portion for electrically connecting the second gate electrode, that is, the gate electrode 124a of the output first stage transistor 124 and the diffusion region 117 of the FD portion. As a method for forming the opening, an etching method using a known photoresist mask 121 may be used. That is, a photoresist mask 121 having an opening 121a is formed on the diffusion region 117 of the FD portion 114, the ONO film 118 is selectively etched, and the opening 103 is formed in a portion of the ONO film on the diffusion region 117. Form.

  In FIG. 3A, after the second gate oxide film 119 is formed on the channel implantation region 116, a photoresist mask 121 having an opening 121a is formed on the diffusion region 117 of the FD portion 114 on the entire surface. Is shown.

  Next, after removing the photoresist mask 121, as shown in FIG. 4B, a polysilicon film (PolySi film) 122 to be the second gate electrode is formed on the entire surface. As this PolySi film 122, a film containing N-type impurities 1E20 to 1E21 (atms / cm−3) is used. Generally, phosphorus (P31) is used as the N-type impurity, and the impurity is implanted by a method of adding to the gas during the deposition of PolySi or a method of doping by performing implantation and thermal diffusion after the formation of the PolySi film. Use it. Then, a photoresist mask 123 for patterning the PolySi film 122 by dry etching is formed.

  4A shows a state in which photoresist masks 123a, 123b, and 123c for pattern formation are formed on a polysilicon film (PolySi film) 122 that becomes the second gate electrode formed on the entire surface. . The photoresist mask 123a corresponds to the pattern of the gate electrode of the output first stage transistor, the photoresist mask 123b corresponds to the pattern of the gate electrode of the horizontal transfer transistor, and the photoresist mask 123c corresponds to the gate electrode of the reset transistor. It corresponds to a pattern.

  Then, using the photoresist mask, the polysilicon film (PolySi film) 122 is patterned by a dry etching method. At this time, on the output circuit 140 side, as shown in FIGS. 1A, 1B, and 5C, the gate electrode 124a of the output first stage transistor 124, which is the second gate electrode, is formed, and the FD As shown in FIGS. 1A and 1B, the gate electrode 125a of the horizontal output transistor 125 and the gate electrode 126a of the reset transistor 126 are formed on the pixel portion 10 side. ), A second gate electrode (2 Gate) G2 is formed on the nitride film 108b.

  At this time, a part of the gate electrode 124 a of the output first stage transistor 124 comes into contact with the diffusion region 117 of the FD portion 114 through the gate insulating film opening 103 disposed on the FD portion 144. The gate electrode 124a and the diffusion region 117 of the FD portion 114 are electrically connected.

  Further, the portion 124a1 of the gate electrode 124a located on the diffusion region 117 of the FD portion 114 has a planar shape larger than this planar shape so as to include the planar shape of the opening 103 of the gate insulating film 118. Yes. Therefore, the gate electrodes of the transistors 124, 125, and 126 are formed as the second gate electrode by etching the PolySi film when forming the gate electrode without etching the diffusion region on the Si substrate surface of the FD portion. Is possible.

  Thereafter, a high temperature annealing process exceeding 800 ° C. is performed, and N-type impurity diffusion is performed by heat treatment from the gate electrode 124a of the output first stage transistor 124, which is the second gate electrode, to the diffusion region 117 of the FD 114 part. The FD part is electrically connected.

  After that, an insulating film (not shown) is formed on the entire surface, a shielding film is disposed on the insulating film, an insulating film made of a BPSG (boron phosphorus silicate glass) film or the like is formed, and reflow treatment is performed. Thereafter, a planarizing film made of a transparent resin or the like is formed, a color filter is formed thereon, and a microlens is formed through the planarizing film. Thereby, a solid-state image sensor is completed.

  As described above, in the first embodiment, the gate electrode 124a of the transistor 124 of the output circuit 140 that outputs a signal corresponding to the accumulated charge in the floating diffusion portion (FD portion) 114, a part of which constitutes the FD portion 114. Since the impurity diffusion region 117 is in contact with the gate electrode 124a, the step of forming a wiring for connecting the gate electrode 124a of the transistor of the output circuit and the impurity diffusion region 117 of the FD portion through the contact hole can be eliminated. it can. Accordingly, damage to the silicon substrate can be reduced as compared with the case of forming a contact hole in the method of connecting the FD portion and the gate electrode of the output first stage transistor, thereby improving the reliability of the element.

  In addition, since metal wiring is not used for connection between the gate electrode 124a of the transistor of the output circuit and the FD portion 114, there is no influence on the pixel portion such that the constituent material of the metal wiring material diffuses to the pixel portion, thereby degrading image quality. Can be avoided.

  Further, there is no increase in the distance between the substrate of the pixel portion and the condensing lens as in the case where a metal plug is used for connection between the gate electrode 124a of the transistor of the output circuit and the FD portion 114. The pixel characteristics are not deteriorated due to the decrease.

  Further, since the gate electrode 124a is made of a polysilicon wiring material, the diffusion region 117 constituting the FD portion is auto-doped with an impurity from polysilicon which is a constituent material of the gate electrode. For this reason, it is possible to reduce the contact resistance while suppressing an increase in parasitic capacitance when a high concentration diffusion region for reducing the contact resistance between the gate electrode 124a and the diffusion region 117 of the FD portion is formed. Thereby, it is possible to avoid a decrease in the conversion rate for converting the accumulated charge in the FD portion into a voltage signal. As a result, it is possible to provide a solid-state imaging device that has no reduction in conversion rate and no deterioration in image quality.

Furthermore, the portion 124a1 of the gate electrode 124a located on the diffusion region 117 of the FD portion 114 has a planar shape larger than this planar shape so that the planar shape includes the planar shape of the opening 103 of the gate insulating film 118. Therefore, it is possible to avoid etching the diffusion region on the Si substrate surface of the FD portion by etching the PolySi film when forming the gate electrode.
(Embodiment 2)
FIG. 6 is a schematic plan view for explaining a CMOS type solid-state imaging device according to Embodiment 2 of the present invention, showing a photoelectric conversion element and a signal output unit for converting charges from the photoelectric conversion element into a signal voltage. ing.

  In the CMOS type solid-state imaging device of the second embodiment as well as the CCD solid-state imaging device of the first embodiment, photodiodes as photoelectric conversion elements are arranged vertically and horizontally on the light receiving surface, but in FIG. Only two adjacent photodiodes are shown.

  In this CMOS type solid-state imaging device, the signal output unit B1 that converts the electric charge generated in the photodiode 101a into a voltage signal and outputs it is the two adjacent photodiodes 101a as in the conventional CMOS type solid-state imaging device. Shared. The signal output unit B1 includes an FD unit 160, a transfer transistor 161, a reset transistor 162, and an output circuit 170 as in the conventional example shown in FIG. Here, the FD unit 160, the transfer transistor 161, and the reset transistor 162 are the same as the FD unit 60, the transfer transistor 61, and the reset transistor 62 in the conventional solid-state imaging device, respectively. That is, the transfer transistor 161 includes an impurity diffusion region 161b located between the photodiode 101a and the diffusion region 160a of the FD portion 160, and a gate electrode 161a disposed on the impurity diffusion region 161a via a gate insulating film. have. The reset transistor 162 includes an impurity diffusion region 162b located between the diffusion region 160a of the FD portion 160 and the reset drain portion 163, and a gate insulating film (not shown) on the impurity diffusion region 162b. The gate electrode 162a is disposed.

  In the second embodiment, the output first stage transistor 171 constituting the output circuit 170 includes an impurity diffusion region 171b formed on the substrate and a gate insulating film (not shown) on the impurity diffusion region 171b. The gate electrode 171a is disposed.

  In the second embodiment, a part of the gate electrode 171a of the output first stage transistor 171 is formed in the diffusion region 160a of the FD portion 160 via the contact opening 164 of the gate oxide film formed in the diffusion region 160a. Are placed in contact with each other. That is, a portion 171a1 of the gate electrode 172a located on the diffusion region 160a of the FD portion 160 is a portion where the contact opening 164 is formed in the gate insulating film on the diffusion region 160a. It is in contact with the exposed diffusion region 160a. As a result, the charges transferred from the horizontal CCD unit are accumulated, the FD unit 160 that holds a potential corresponding to the accumulated amount of the charges, and the output that amplifies the potential held by the FD unit 160 and outputs a voltage signal. The gate electrode 171a of the first stage transistor of the circuit 170 is electrically connected.

  In the CMOS solid-state imaging device, a polysilicon wiring material is used as the gate electrode material.

  In the CMOS solid-state imaging device, the portion 171a1 of the gate electrode 171a located on the diffusion region 160a of the FD portion 160 includes the planar shape of the opening 164 of the gate insulating film. The planar shape is larger than this planar shape.

  In the CMOS solid-state imaging device having such a configuration, charges generated in the photodiode portion 101a are accumulated in the FD portion 160 via the transfer transistor 161, and the FD portion 160 outputs a signal corresponding to the accumulated charges. appear. Then, the output circuit 170 including the first stage transistor 171 amplifies and outputs the voltage signal. Note that the charge converted into the voltage signal is discharged to the reset drain 163 through the reset transistor 162.

  Further, in this CMOS type solid-state imaging device manufacturing method, the connection structure between the gate electrode 171a of the output first stage transistor and the diffusion region 160a of the FD portion 160 is formed by the following steps.

  That is, the impurity diffusion region 160a that becomes the FD portion 160 for accumulating signal charges is formed on the semiconductor substrate. Next, a contact opening 164 is formed in the gate insulating film formed on the impurity diffusion region 160a so that a part of the impurity diffusion region is exposed. Subsequently, a gate electrode material is deposited on the entire surface, and the deposited gate electrode material is patterned to form the gate electrode 171a of the output first stage transistor 171. Thereby, the gate electrode 171a of the output first stage transistor 171 is arranged so that a part thereof is in contact with the impurity diffusion region serving as the FD portion through the opening of the gate insulating film.

  In the method for manufacturing a CMOS solid-state imaging device, a heat treatment exceeding 800 ° C. is performed after the gate electrode 171a is formed. Due to the heat treatment, impurities in the gate electrode material are diffused into the impurity diffusion region 160a serving as the FD portion, and the resistance of the connection portion of the impurity diffusion region 160a with the gate electrode 171a is reduced.

Further, in the method for manufacturing a CMOS solid-state imaging device, after forming the gate electrode 171a, an insulating film covering the gate electrode is formed. An SiO ₂ material is used for the insulating film covering the gate electrode, and the insulating film is formed by a thermal oxidation method or a CVD method.

  In the second embodiment, as in the first embodiment, the damage to the silicon substrate is reduced as compared with the case where the contact hole is formed in the connection method between the FD portion 160 and the gate electrode 171a of the output first stage transistor 171. This can improve the reliability of the device.

  In addition, since metal wiring is not used for connection between the gate electrode 171a of the transistor of the output circuit and the FD portion 160, there is no influence on the pixel portion such that the constituent material of the metal wiring material diffuses to the pixel portion, thereby degrading image quality. Can be avoided.

  Further, there is no increase in the distance between the substrate of the pixel portion and the condensing lens as in the case where a metal plug is used for the connection between the gate electrode 171a of the transistor of the output circuit and the FD portion 160. The pixel characteristics are not deteriorated due to the decrease.

  Further, since the gate electrode 171a is made of a polysilicon wiring material, the diffusion region 160a constituting the FD portion is auto-doped with polysilicon from the polysilicon constituting the gate electrode. Therefore, it is possible to reduce the contact resistance while suppressing an increase in parasitic capacitance when a high concentration diffusion region for reducing the contact resistance between the gate electrode 171a and the diffusion region 160a of the FD portion is formed. Thereby, it is possible to avoid a decrease in the conversion rate for converting the accumulated charge in the FD portion into a voltage signal. As a result, it is possible to provide a solid-state imaging device that has no reduction in conversion rate and no deterioration in image quality.

  Furthermore, the portion 171a1 of the gate electrode 171a located on the diffusion region 160a of the FD portion 160 has a planar shape larger than this planar shape so as to include the planar shape of the opening 164 of the gate insulating film. Therefore, it is possible to avoid etching the diffusion region on the Si substrate surface of the FD portion by etching the PolySi film when forming the gate electrode.

  Although not particularly described in Embodiments 1 and 2, for example, a digital camera such as a digital video camera or a digital still camera using at least one of the solid-state imaging devices of Embodiments 1 and 2 as an imaging unit, An electronic information device having an image input device such as an image input camera, a scanner, a facsimile, a camera-equipped mobile phone device, and the like will be described.

  The electronic information device according to the present invention performs high-quality image data obtained by using at least one of the solid-state imaging devices according to Embodiments 1 and 2 of the present invention as an imaging unit, and performs data recording after performing predetermined signal processing for recording. A memory unit such as a recording medium, a display unit such as a liquid crystal display device that displays the image data on a display screen such as a liquid crystal display screen after performing predetermined signal processing for display, and the image data for communication At least one of communication means such as a transmission / reception device that performs communication processing after the signal processing and image output means for printing (printing) and outputting (printing out) the image data.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention is a solid-state imaging device used for a camera-equipped mobile phone, a digital still camera, a surveillance camera, or the like, and in particular, a floating diffusion unit (FD unit) that accumulates signal charges and a diffusion region of the FD unit. In the field of a solid-state imaging device including an output circuit that includes a transistor having an electrically connected gate electrode and outputs a signal corresponding to a change in charge of the FD portion through the transistor, The connection structure between the diffusion region of the portion and the gate electrode of the transistor of the output circuit that converts the electric charge from the FD portion into a signal voltage and outputs the signal, and damage between the substrate and the substrate of the pixel portion and the condenser lens It is possible to provide a highly reliable solid-state imaging device that can be formed without causing an increase in the distance between them and that has no deterioration in pixel characteristics. Kill.

1A and 1B are diagrams for explaining a CCD type solid-state imaging device according to Embodiment 1 of the present invention. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line Ib-Ib in FIG. . 2A and 2B are diagrams for explaining a method of manufacturing a solid-state imaging device according to Embodiment 1 of the present invention. FIG. 2A is a plan view, and FIG. 2B is a cross-sectional view taken along the line IIb-IIb in FIG. . 3A and 3B are diagrams for explaining a method of manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIG. 3A is a plan view, and FIG. 3B is a sectional view taken along line IIIb-IIIb in FIG. . 4A and 4B are diagrams for explaining a method of manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIG. 4A is a plan view, and FIG. 4B is a sectional view taken along line IVb-IVb in FIG. . FIG. 5 is a diagram for explaining the method of manufacturing the solid-state imaging device according to the first embodiment of the present invention, and shows etching of the gate insulating film (FIGS. (A) to (c)). FIG. 6 is a plan view for explaining a CMOS type solid-state imaging device according to Embodiment 2 of the present invention. FIG. 7 is a plan view schematically showing a conventional CCD type solid-state imaging device. FIG. 8 is a plan view for explaining a signal output unit of a conventional CCD solid-state imaging device. FIG. 9 is a plan view for explaining a signal output unit of a conventional CMOS type solid-state imaging device. FIG. 10 is a cross-sectional view illustrating a connection structure between the FD portion and the gate electrode of the output transistor described in Patent Document 1. FIG. 11 is a cross-sectional view illustrating a connection structure between the FD portion and the gate electrode of the output transistor described in Patent Document 2. FIG. 12 is a cross-sectional view illustrating a connection structure between the FD portion and the gate electrode of the output transistor described in Patent Document 3. FIG. 13 is a cross-sectional view for explaining the problem of the connection structure between the FD portion and the gate electrode of the output transistor described in Patent Document 3. FIG. 13 is a cross-sectional view for explaining the problem of the connection structure between the FD portion and the gate electrode of the output transistor described in Patent Document 3. FIG. 13 is a cross-sectional view for explaining the problem of the connection structure between the FD portion and the gate electrode of the output transistor described in Patent Document 3.

Explanation of symbols

103,164 FD portion first gate insulating film opening 110 Silicon substrate (Si substrate)
111 Oxide Film 112 Field Oxide Film 114,160 FD Part 115 P-Well Impurity Diffusion Area 116 Output First Stage Transistor Channel Injection Area 118 First Gate Insulation Film 119 Second Gate Insulation Film 120 Horizontal CCD
120a Horizontal CCD N-type diffusion region 121 Photoresist 122 Second gate electrode material (PolySi film)
123 Photoresist 124, 171 Output first stage transistor 124a, 171a Output first stage transistor gate electrode 124b, 171b Output first stage transistor activation region 125, 161 Horizontal output transistor 125a, 161a Horizontal output transistor gate electrode 125b, 161b Horizontal output transistor activation region 126 , 162 Reset transistor 126a, 162a Reset transistor gate electrode 126b, 162b Reset transistor activation region 140, 170 Output circuit A1, B1 Signal output unit

Claims (4)

A method of manufacturing a solid-state imaging device,
Forming an impurity diffusion region serving as a floating diffusion portion for accumulating signal charges on a semiconductor substrate;
Forming an opening in the gate insulating film formed on the impurity diffusion region so that a part of the impurity diffusion region is exposed;
Depositing a gate electrode material on the entire surface;
Patterning the deposited gate electrode material to form a gate electrode of a transistor that outputs a signal corresponding to a change in charge of the floating diffusion portion, and
A part of the gate electrode of the transistor is disposed so as to be in contact with the impurity diffusion region serving as the floating diffusion portion through the opening of the gate insulating film .
In the step of forming the gate electrode, the deposited gate electrode material is patterned so that the planar shape of the gate electrode includes the planar shape of the opening of the gate insulating film,
The method further includes a step of performing a heat treatment exceeding 800 ° C. after forming the gate electrode,
A solid-state imaging device for electrically connecting the impurity diffusion region and the gate electrode by diffusing phosphorus, which is an impurity in the gate electrode material, into the impurity diffusion region serving as the floating diffusion portion by the heat treatment Manufacturing method. The method for manufacturing a solid-state imaging device according to claim 1 , wherein a polysilicon wiring material is used as the gate electrode material. After forming the gate electrode, forming an insulating film covering the gate electrode, further comprising, a method for manufacturing a solid-state imaging device according to claim 1. The method for manufacturing a solid-state imaging device according to claim 3 , wherein an SiO ₂ material is used for the insulating film covering the gate electrode, and the insulating film is formed by a thermal oxidation method or a CVD method.

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