JP2006351787A - Solid-state imaging device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device that is high in accuracy and reliability regarding high-level microfabrication. <P>SOLUTION: The solid-state imaging device is provided with an optical conversion section, and a charge transfer section provided with a charge transfer electrode for transferring charges generated in the optical conversion section. The device is characterized in that at least one of insulation films is constituted of a double-layer structure of a radical oxide film having low-temperature plasma and a CVD film. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof, and more particularly to a manufacturing method of a solid-state imaging device having a structure capable of withstanding miniaturization.

  A solid-state imaging device using a CCD used for an area sensor or the like includes a photoelectric conversion unit such as a photodiode and a charge transfer unit including a charge transfer electrode for transferring a signal charge from the photoelectric conversion unit. A plurality of charge transfer electrodes are arranged adjacent to each other on a charge transfer path formed on the semiconductor substrate, and are sequentially driven.

  In recent years, demands for higher resolution and higher sensitivity have been increasing in solid-state imaging devices, and the number of imaging pixels has been increasing to more than gigapixels. Under such circumstances, in order to obtain high resolution without increasing the chip size, it is necessary to reduce the area per unit pixel and achieve high integration.

  On the other hand, if the area of the photodiode that constitutes the photoelectric conversion unit is reduced, the sensitivity is lowered. Therefore, the area of the photodiode region must be ensured. Therefore, various studies have been made to reduce the size of the chip while securing the area occupied by the photodiode region by reducing the wiring area ratio of the charge transfer portion and the peripheral circuit portion and reducing the area ratio of the wiring. Yes.

  Under these circumstances, maintaining the flatness of the interlayer insulating film between the wiring layers is an important technical issue in order to realize high integration by miniaturization of the wiring. Furthermore, a substrate (silicon substrate) on which a solid-state image sensor is built is mounted by laminating filters and lenses. For this reason, the positional accuracy between the lens and the photoelectric conversion unit is important, and the distance, that is, the distance in the height direction, is a big problem in terms of positional accuracy in the manufacturing process and sensitivity (photoelectric conversion efficiency) in use. .

  In order to improve the flatness, a structure in which the charge transfer portion has a single-layer electrode structure has been proposed. In the CCD, the gap between the electrodes is an important factor for determining the transfer efficiency, and how small the gap between the electrodes is important. However, in the formation of an electrode pattern by a normal photolithography technique, the limit is 0.2 μm, and it is difficult to form an electrode pattern smaller than this. Further, when the distance between the electrodes is miniaturized, the aspect ratio must be increased, and it is extremely difficult to embed an insulating film in the gap between the electrodes that is fine and has a large aspect ratio.

  For this reason, the miniaturization of the gap between the electrodes is extremely serious, and when sufficient pattern accuracy cannot be obtained, sensitivity variation and deterioration of charge transfer efficiency are caused, and improvement of pattern accuracy is a serious problem. In addition, miniaturization of the peripheral circuit portion is also demanded. Under such circumstances, in improving the pattern accuracy in the photolithography process and forming the insulating film in the gap between the electrodes, improving the film quality of the insulating film is an important issue for miniaturization.

  Under such circumstances, in order to improve the quality of the insulating film formed in the interelectrode gap, that is, the interelectrode insulating film, oxidation at a high temperature is required. Usually, in order to ensure sufficient insulation, it is necessary to perform heat treatment at 900 ° C. to 950 ° C.

  However, in a solid-state imaging device (CCD), after forming a functional layer by introducing various impurities such as forming a well in a substrate, forming a stopper layer, and forming a pn junction, As a result of the formation, impurity diffusion cannot be suppressed by normal heat treatment, and there is a problem that desired characteristics cannot be obtained due to variations in element characteristics due to extension of diffusion length. In addition, it is difficult to ensure a sufficient withstand voltage between adjacent electrodes only by forming an insulating film by a CVD method.

  In a conventional solid-state imaging device using a charge transfer electrode having a single-layer structure, a pattern of a first-layer conductive film is formed in order to achieve a finer resolution beyond the resolution of photolithography when a gap between electrodes is miniaturized. Thereafter, an interelectrode insulating film is formed, and a second-layer conductive film is laminated thereon, and then planarized by resist etchback or CMP (Chemical Mechanical Polishing) method has been proposed (patent) Reference 1).

  For example, a polycrystalline silicon or amorphous silicon film is used as a charge transfer electrode, and after forming a first electrode made of a first layer conductive film, the pattern surface of the first electrode is oxidized, and this oxide film is used as an electrode. A polycrystalline or amorphous silicon film serving as a second layer transfer electrode is deposited as an inter-layer insulating film, a resist is applied, and the entire surface is etched by a resist etch back method to form a single layer electrode. Yes.

  The interelectrode insulating film forms an interelectrode insulating film on the surface of the pattern of the first electrode by thermal oxidation, and further forms a silicon oxide film (HTO oxide film) on the upper layer.

  Then, a second layer doped amorphous silicon film is formed as an upper layer, and the second layer doped amorphous silicon film is flattened by CMP to form a solid-state imaging device electrode having a flat single layer structure. .

  However, since the interelectrode insulating film requires a desired withstand voltage, the film quality needs to be good. For this reason, as described above, thermal oxidation is necessary, and there is a problem that it is difficult to cope with miniaturization or further improvement in sensitivity.

  In addition to the formation of the interelectrode insulating film as described above, in the case of a solid-state imaging device, the charge transfer portion is formed after forming the impurity region in the substrate. There is a problem that it causes a large variation in characteristics. Particularly in a process involving the formation of an insulating film by thermal oxidation, characteristic deterioration is a serious problem.

JP 2004-179608 A

  As described above, in the conventional solid-state image pickup device, deterioration of device characteristics due to heat in forming an insulating film has become a serious problem with miniaturization.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a solid-state imaging device with high accuracy and high reliability even at high miniaturization.
It is another object of the present invention to form a solid-state imaging device having a single-layer electrode structure that is highly accurate and reliable even at high miniaturization.
Furthermore, the present invention improves the charge transfer efficiency by forming a charge transfer electrode having a high withstand voltage and high reliability when forming a charge transfer electrode having a single-layer electrode structure, even when the electrode pattern is miniaturized and thinned. It aims to plan.

  Therefore, the solid-state imaging device according to the present invention is a solid-state imaging device including a photoelectric conversion unit and a charge transfer unit including a charge transfer electrode that transfers charges generated in the photoelectric conversion unit. Is characterized in that it has a two-layer film structure of a radical oxide film formed by low-temperature plasma and a CVD film.

  According to this configuration, since the insulating film is formed by radical oxidation using high-density low-temperature plasma, a dense and high-quality oxide film is formed without being exposed to a high temperature of 900 to 950 ° C. as in the prior art. Therefore, even if a CVD film is formed on this upper layer, a high-quality insulating film having high insulation resistance can be obtained. Since formation at a low temperature is possible in this manner, a highly reliable film formation can be performed without causing an increase in the diffusion length of the underlying impurity region.

  In the solid-state imaging device according to the present invention, the charge transfer electrode is a single-layer electrode including a first electrode and a second electrode formed through an interelectrode insulating film that covers a side wall of the first electrode. The inter-electrode insulating film includes a structure having a two-layer structure of a radical oxide film formed by low-temperature plasma and a CVD film.

  According to this configuration, in addition to the above effects, a fine and high-quality insulating film can be formed even if the gap between the electrodes is reduced along with the miniaturization.

  In the solid-state imaging device of the present invention, the gate oxide film formed below the charge transfer electrode includes a two-layer film structure of a radical oxide film formed by low-temperature plasma and a CVD film.

  According to this configuration, it is possible to increase the breakdown voltage of the gate oxide film and form a highly reliable high quality film without causing an increase in the diffusion length of the underlying impurity region.

  The solid-state imaging device of the present invention includes an optical waveguide structure on the photoelectric conversion portion, and a peripheral portion of the optical waveguide is configured by a two-layer film structure of a radical oxide film by a low temperature plasma and a CVD film. Including things.

  According to this configuration, it is possible to form a thick interlayer insulating film for forming an optical waveguide structure without causing an increase in the diffusion length of the underlying impurity region, and to provide a solid-state imaging device having excellent characteristics Can do.

  In the solid-state imaging device of the present invention, the interlayer insulating film includes a two-layer film structure of a radical oxide film formed by low-temperature plasma and a CVD film.

  According to this configuration, the formation of the interlayer insulating film makes it possible to obtain a dense and excellent film quality without causing an increase in the diffusion length of the underlying impurity region, thereby reducing the film thickness of the interlayer insulating film. be able to.

  In the solid-state imaging device of the present invention, the CVD film is a silicon nitride film.

  According to this configuration, since it is a two-layer film of silicon oxide and silicon nitride, it is possible to obtain an insulating film with higher withstand voltage and higher reliability, so that the total film thickness of the insulating film can be reduced. .

  In the solid-state imaging device of the invention, the field oxide film is a recess LOCOS film formed by selective oxidation (LOCOS) after forming a trench.

  According to this configuration, the surface can be flattened, and further thinning and miniaturization are possible.

  The solid-state imaging device of the present invention includes one in which the field oxide film is a film having a shallow trench (STI) structure.

  According to this configuration, the surface can be flattened, and further thinning and miniaturization are possible.

  According to another aspect of the present invention, there is provided a method for manufacturing a solid-state imaging device including a photoelectric conversion unit and a charge transfer unit including a charge transfer electrode that transfers a charge generated in the photoelectric conversion unit. Forming a photoelectric conversion portion and a charge transfer channel; forming a gate oxide film on the surface of the semiconductor substrate; forming a charge transfer electrode on the surface of the semiconductor substrate on which the gate oxide film is formed; Forming an interlayer insulating film on the charge transfer electrode, wherein at least one of the photoelectric conversion unit, the charge transfer unit, or the interlayer insulating film is a radical oxide film forming step by low-temperature plasma, a CVD step, Including those formed in the two steps.

  According to this configuration, since the insulating film is formed by radical oxidation using high-density low-temperature plasma, a dense and high-quality oxide film is formed without being exposed to a high temperature of 900 to 950 ° C. as in the prior art. Therefore, since it can be formed at a low temperature, it is possible to form a highly reliable film without increasing the diffusion length of the underlying impurity region. Even if a CVD film is formed on the radical oxide film, a high-quality insulating film having high insulation resistance can be obtained.

  In the method of the present invention, the step of forming the charge transfer electrode includes a step of forming a pattern of the first layer conductive film constituting the first electrode, an interelectrode insulating film on at least the side wall of the first electrode, and Forming an insulating film, forming a second layer conductive film constituting a second electrode on the surface of the semiconductor substrate on which the first electrode and the interelectrode insulating film are formed, and at least the Removing the second-layer conductive film on the first electrode, and planarizing the surface of the semiconductor substrate on which the second conductive film is formed. By performing radical oxidation by plasma and performing interlayer oxidation, oxidation without crystal orientation dependency is possible, and variation in charge transfer electrode width as seen in normal thermal oxidation can be reduced.

According to this configuration, a number of insulating film forming steps are included, and at least one of them includes a step of forming a radical oxide film by low-temperature plasma and a CVD step, so that a two-layer structure film is formed. The impurity region formed in the base substrate can be formed without causing an increase in diffusion length.
In particular, when forming an interelectrode insulating film, it is possible to oxidize without dependency on crystal orientation by using radical oxidation by low-temperature plasma and performing interlayer oxidation, and the variation in the width of the charge transfer electrode as seen in normal thermal oxidation is reduced. Can be reduced.

  In the method of the present invention, the gate oxide film forming step includes two steps of a radical oxide film forming step by low temperature plasma and a CVD step.

  In the method of the present invention, the optical waveguide structure is provided on the photoelectric conversion portion, and the optical waveguide forming step is a two-step process in which the peripheral portion of the optical waveguide is a radical oxide film formed by low-temperature plasma and a CVD step. And a step of forming an opening on the photoelectric conversion portion and a step of filling the opening with a high refractive index material.

  In the method of the present invention, the step of forming the interlayer insulating film includes a radical oxidation step by low-temperature plasma and a CVD step, and a two-layer film structure is formed.

  According to this configuration, a dense and high-quality insulating film can be formed.

  The method of the present invention includes the method in which the CVD step is a step of forming a silicon nitride film.

  According to this configuration, a dense and high-quality insulating film can be formed.

  Further, the method of the present invention includes a step of forming a field oxide film by selective oxidation (LOCOS) after forming a trench by forming a recess LOCOS method and forming a trench prior to the formation of the photoelectric conversion portion and the charge transfer portion. Including.

  According to this configuration, the surface can be flattened and a highly accurate pattern can be formed.

  In addition, the method of the present invention includes a step of planarizing the entire surface of the semiconductor substrate after forming a field oxide film on the surface of the semiconductor substrate and prior to forming the charge transfer electrode.

  According to this configuration, the surface can be flattened and a highly accurate pattern can be formed.

  The method of the present invention includes a step of forming a film having a shallow trench (STI) structure prior to the formation of the photoelectric conversion portion and the charge transfer portion.

  According to this configuration, the surface level of the field oxide film provided in the peripheral circuit unit and the charge transfer unit so as to surround the effective imaging region of the photoelectric conversion unit is approximately the same as the surface level of the photoelectric conversion unit. For this reason, when the element region is formed, the entire substrate surface is flat, and the pattern accuracy by photolithography is greatly improved.

  Further, since the surface level is flat, it is possible to prevent the conductive film, particularly the second-layer conductive film, from being reduced when the charge transfer electrode is formed into a single layer. Therefore, since charge transfer electrodes and peripheral circuits with a uniform film thickness can be formed, variations in device characteristics can be prevented, and a highly reliable solid-state imaging device can be formed. Here, the effective imaging region includes a photoelectric conversion unit and a charge transfer unit.

  It should be noted that the surface level of the photoelectric conversion unit and the gates of the charge transfer unit and the peripheral circuit unit for forming the charge transfer electrode in the planarization process such as the CMP (Chemical Mechanical Polishing) process or the etch back process of the second layer conductive film It is desirable that the upper surface level surface of the oxide film be approximately the same, and it is sufficient that at least the surface level of the substrate in the region where the photoelectric conversion portion is formed and the surface level of the field insulating film are approximately the same.

  Further, in the method for producing a solid-state imaging device of the present invention, the step of flattening the surface of the semiconductor substrate includes a step of applying a resist to the surface of the semiconductor substrate by a spin coat method and a step of flattening by a resist etch back method. Including those containing.

  In the solid-state imaging device manufacturing method of the present invention, the step of planarizing the surface of the semiconductor substrate includes a step of planarizing the surface of the semiconductor substrate by a CMP (Chemical Mechanical Polishing) method.

According to the above configuration, by using radical oxidation by low-temperature plasma, it is possible to prevent diffusion of impurities injected into the base substrate and provide a high-quality solid-state imaging device.
Further, by performing radical oxidation with low-temperature plasma after forming a gap between adjacent electrodes, it is possible to replace a short-circuit portion due to a foreign matter between the electrodes with an insulator and reduce DC defects in adjacent wiring.

In addition, by forming the charge transfer electrode having a single layer structure, it is possible to prevent a decrease in sensitivity due to vignetting of incident light.
Furthermore, since the film quality can be improved, the interval between adjacent charge transfer electrodes can be reduced, and the opening area above the photodiode can be increased.
When forming the interelectrode insulating film, it is possible to oxidize without dependency on crystal orientation by using radical oxidation by low-temperature plasma and performing interlayer oxidation, reducing the variation in the width of the charge transfer electrode as seen in normal thermal oxidation can do.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)

  As shown in FIGS. 1 and 2 (FIG. 1 is a diagram showing a cross section AA in FIG. 2), the solid-state imaging device of the present embodiment includes a photoelectric conversion unit and charges generated in the photoelectric conversion unit. In the solid-state imaging device including the charge transfer unit including the charge transfer electrode for transferring the charge, the gate oxide film 2, the interelectrode insulating film is a silicon oxide film formed by low-temperature plasma, and a CVD film formed on the upper layer 2 It is formed by a layer structure.

As shown in FIGS. 1 and 2, the silicon substrate 1 has a plurality of photodiode regions 30 constituting a photoelectric conversion unit, and a charge transfer unit 40 for transferring signal charges detected by the photodiode. , Formed between the photodiode regions 30.
About parts other than an insulating film, it forms similarly to a usual solid-state image sensor.

  Note that a field oxide film 100 formed in a frame shape so as to surround the effective imaging region (light receiving region) A is formed in the trench T by the Recess LOCOS method, and the photoelectric conversion unit including the photosensor and the charge It is formed so that the surface level of the transfer part and the surface level of the field oxide film 100 are the same (see FIG. 3).

  Here, the effective imaging region is composed of a light receiving region including a photoelectric conversion unit and a vertical transfer path (a part of the charge transfer unit) and a horizontal transfer path (a part of the charge transfer unit), and a peripheral circuit outside thereof. A peripheral portion (non-imaging region) B including the output circuit is formed.

  Here, the gate oxide film 2 is formed to have a total film thickness of about 50 nm of the radical oxide film and the CVD film. Further, a silicon oxide film as a field oxide film 100 having a thickness of 400 nm is formed by selective oxidation in a trench T having a depth of about 40 nm formed in the non-imaging region of the silicon substrate 1 and the element isolation region of the charge transfer portion. ing. On the field oxide film 100, a horizontal transfer register, a signal processing circuit, and wiring for transferring signal charges in the horizontal direction are formed.

  That is, as shown in FIG. 1 and FIG. 2, a cross-sectional schematic diagram and a plan view of the solid-state imaging device chip (FIG. 1 is a cross-sectional view taken along line AA in FIG. 2), the silicon substrate 1 is surrounded by a field oxide film 100. A photoelectric conversion unit and a charge transfer unit including a photodiode are formed in the effective imaging region (light receiving region), and an upper layer thereof is covered with an insulating film.

  In the silicon substrate 1, photoelectric conversion portions (31, 32), a charge transfer channel 35, a channel stop region 34, and a charge readout region 33 are formed, and a gate oxide film 2 is formed on the surface of the silicon substrate 1. An interelectrode insulating film 8 made of a silicon oxide film and a charge transfer electrode 3 (doped amorphous silicon film) are formed on the surface of the gate oxide film 2.

  A wiring is formed on the field oxide film 100. Further, an insulating film 15 having an optical waveguide structure is formed as an intermediate layer including a planarizing film on the upper layer, and a color filter 50 and a microlens 60 are formed on the upper layer. An optical system is provided.

  According to this configuration, a dense and high-quality insulating film can be formed at a low temperature, so that the width of the interelectrode insulating film can be reduced and miniaturization can be achieved. Further, as shown in FIGS. 1 and 2, since a pattern is formed on a flat surface, it is possible to form a pattern with extremely high accuracy, and it is possible to form a very fine charge transfer portion. Also, the wiring including the peripheral circuit portion can be miniaturized.

  Next, the manufacturing process of the solid-state imaging device of the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 3A, an n-type silicon substrate 1 is prepared.
Then, a buffer silicon oxide film M1 and a silicon nitride film M2 are formed and patterned by photolithography to form a two-layer mask pattern.
Next, as shown in FIG. 3B, the substrate surface is etched away using this mask pattern as a mask, and a trench T is formed on the surface.

  In this state, heating is performed in an oxidizing atmosphere of 900 to 1000 ° C. to form a field oxide film 100 made of a silicon oxide film having a thickness of about 400 to 600 nm as shown in FIG.

Then, as shown in FIG. 3D, the silicon nitride film M2 is removed.
Finally, as shown in FIG. 3E, planarization may be performed by CMP to form a field oxide film 100 having a flat surface with no step. At this time, the silicon oxide film M1 is also removed.

Although not shown in FIG. 2, the charge transfer channel 35 through which the signal charge transferred by the charge transfer electrode moves is formed in a direction crossing the direction in which the charge transfer portion extends.
Further, FIG. 2 shows a so-called honeycomb-structured solid-state imaging device, but it goes without saying that the present invention can also be applied to a square lattice type solid-state imaging device.

Next, a process of forming a solid-state imaging device on the surface of the silicon substrate on which the field oxide film is thus formed will be described in detail with reference to FIGS.
First, oxidation by radical oxidation by low-temperature plasma is performed on the surface of an n-type silicon substrate 1 having an impurity concentration of about 1.0 × 10 ¹⁶ cm ^{−3 in} which the charge transfer channel 35, the channel stop region 34, and the charge readout region 33 are formed. A silicon oxide film having a thickness of 15 to 35 nm and a silicon oxide film formed by a CVD method are formed to form a gate oxide film 2 having a two-layer structure.

Subsequently, a phosphorus-doped doped amorphous silicon film 3 having a film thickness of 0.25 μm is formed on the gate oxide film 2 by a low pressure CVD method using SiH ₄ added with PH ₃ and N ₂ as a reactive gas. To do. The substrate temperature at this time shall be 600-700 degreeC.

  Thereafter, a silicon oxide film 4 having a thickness of 15 nm, a silicon nitride film 5 having a thickness of 50 nm, and an organic antireflection film 6 are formed by a low pressure CVD method.

  Subsequently, a positive resist is applied to the upper layer so as to have a thickness of 0.5 to 1.4 μm, exposed using a desired mask by photolithography, developed, washed with water, and subjected to resist pattern R1 and necessary. Accordingly, a dummy (resist) pattern (not shown here) is formed (FIG. 4A). Here, the dummy pattern is formed at the time of layout so that the distance from the resist pattern R1 does not exceed a predetermined width (the distance between the first electrodes) at the peripheral edge of the silicon substrate 1. The distance between the resist patterns was 0.2 μm.

Thereafter, the silicon oxide film 4 and the silicon nitride film 5 are patterned by reactive ion etching using a mixed gas of CHF ₃ , C ₂ F ₆ , O ₂ and He to pattern the charge transfer electrode. A hard mask is formed. This hard mask is used for patterning the doped amorphous silicon film 3 as a charge transfer electrode having a single-layer electrode structure.

  Then, the resist pattern is removed by ashing (FIG. 4B).

Then, a silicon oxide film 7 is deposited by the CVD method (FIG. 4C), and then a sidewall oxide film is formed by reactive ion etching using a mixed gas of Cl ₂ and O ₂ and further doped. The triamorphous silicon film is selectively removed by etching to form electrodes and wiring for peripheral circuits (FIG. 5A). With this sidewall oxide film 7, the gap between the electrodes can be made finer beyond the resolution limit. Here, it is desirable to use an etching apparatus such as an ECR (Electron Cyclotron Resonance) system or an ICP (Inductively Coupled Plasma) system.

  Subsequently, radical oxidation by low-temperature plasma is performed on the surface of the electrode pattern, and film formation by CVD is performed to form an interelectrode insulating film 8 made of a silicon oxide film having a thickness of 50 to 75 nm (FIG. 5B). Then, ion implantation for forming a photodiode portion (not shown) is performed. Thereafter, flash lamp annealing is performed to activate the implanted ions.

Next, a resist is applied and photolithography is performed to form a resist pattern R2 for patterning the interelectrode insulating film 8 (FIG. 5C). Then, the silicon oxide film on the photodiode portion is removed by etching using this resist pattern as a mask.

  Subsequently, radical oxidation by low-temperature plasma and film formation by high-temperature CVD are performed to form a silicon oxide film 9 having a thickness of 15 to 35 nm and a silicon nitride film 10 as an antireflection film by CVD (FIG. 6A). )). Here, the high temperature by the high temperature CVD method is assumed to form a film at a high temperature that does not cause impurity diffusion, that is, about 800 ° C. or less.

  Next, a resist is applied and photolithography is performed to form a resist pattern R3 for patterning the silicon nitride film 10 to form an opening for hydrogen termination (FIG. 6B). Then, using this resist pattern as a mask, the silicon nitride film 10 is etched to form an opening for hydrogen termination (FIG. 6C).

  Subsequently, radical oxidation by low-temperature plasma and film formation by high-temperature CVD method are performed to form a silicon oxide film 11 having a film thickness of 50 to 75 nm as an interlayer insulating film for ensuring a breakdown voltage, and a TiN layer 12 as an adhesion layer by CVD method. Then, the W layer 13 as a light shielding film is sequentially formed (FIG. 7A).

  Next, a resist is applied and photolithography is performed to form a resist pattern R4 for patterning the light shielding film (W layer) 13 (FIG. 7B). Then, using this resist pattern as a mask, the W layer 13 is etched to form a silicon oxide film 14 for preventing the light shielding film from oxidation (FIG. 8A).

  Then, a BPSG film 15 having a thickness of 700 nm is formed on this upper layer, and is reflowed and flattened at 850 ° C. (FIG. 8B). Here, instead of the BPSG film 15, a silicon oxide film may be formed by radical oxidation using low-temperature plasma. Then, in order to form a waveguide, an opening is formed in the photodiode portion, a silicon nitride film 16 is formed by a CVD method, and an optical waveguide is formed. Then, an insulating film (passivation film: not shown) made of P-SiN and a planarizing layer 18 made of a transparent resin film are formed.

  Thereafter, the in-layer lens 21, the flattening layer 22, the color filter 50, the flattening layer 70, the microlens 60, and the like are formed to obtain a solid-state imaging device as shown in FIGS. 1 (a) and 1 (b). In FIG. 2, only the main part is shown, and the optical system and the like are omitted.

  According to this method, a gate oxide film, an interelectrode insulating film, and the like are formed by a two-layer film of a silicon oxide film by radical oxidation by a low temperature plasma and a silicon oxide film by a CVD method, so that it can be formed at a low temperature. It is possible to form a high-quality insulating film without causing an increase in the diffusion length of the film, to form a highly accurate and high withstand voltage insulating film, and to form a highly reliable solid-state imaging device It becomes.

  Further, by embedding a field oxide film in the trench by the recess locos method, the photoelectric conversion part, the charge transfer part, and the peripheral circuit part are formed on the substrate surface of the step difference 0 completely. The film can be made thin, and because it is formed by radical oxidation using low-temperature plasma, it can maintain a sufficiently high breakdown voltage even if the film quality is good and thin, so that highly accurate pattern formation can be realized. Therefore, it is possible to obtain a fine and functionally reliable operation characteristic.

In the above-described embodiment, the gate oxide film, the interelectrode insulating film, the interlayer insulating film, the planarizing film surrounding the waveguide, etc. are all composed of a two-layer film of a radical oxide film by CVD and a CVD film. Needless to say, even one of them is effective. Any one may be appropriately selected and used according to the necessity.
Furthermore, although the optical waveguide structure is formed in the above embodiment, it is needless to say that the optical waveguide structure is not necessarily configured.

In addition, if necessary, dummy patterns may be formed so that the resist surface level does not become low when applying the resist by spin coating, such as where the pattern density of the electrode wiring is small, such as the periphery of the substrate. May be.
In this way, it is possible to form a solid-state imaging device that is fine, has no characteristic variation, and has high reliability.

(Embodiment 2)
In the first embodiment, the interelectrode insulating film is formed by a two-layer film of a silicon oxide film formed by radical oxidation using low-temperature plasma and a silicon oxide film formed by a CVD method. However, as shown in FIGS. The interlayer insulating film 8N may be formed by a two-layer film of a silicon oxide film formed by radical oxidation using low-temperature plasma and a silicon nitride film formed by a CVD method.
FIGS. 9 to 12 correspond to the processes of FIGS. 5 to 8 described in the first embodiment, and the difference is a two-layer film of a silicon oxide film by radical oxidation by low-temperature plasma and a silicon oxide film by CVD. Instead of the interelectrode insulating film 8, an interelectrode insulating film 8N composed of a two-layer film of a silicon oxide film by radical oxidation by low-temperature plasma and a silicon nitride film by a CVD method is used, and an antireflection film formed further thereon 29 is composed of a two-layer film of a silicon oxide film formed by radical oxidation using low-temperature plasma and a silicon nitride film formed by a CVD method. Others are the same as in the first embodiment, but since it is a low-temperature process, there is almost no increase in the diffusion length even if radical oxidation is repeated many times, so that a high breakdown voltage can be reliably achieved.
That is, the field oxide film is formed through the processes of FIGS. 3 and 4, and the surface of the n-type silicon substrate 1 on which the charge transfer channel 35, the channel stop region 34, and the charge readout region 33 are formed is exposed to radicals caused by low temperature plasma. A silicon oxide film by oxidation and a silicon oxide film by CVD are formed to form a gate oxide film 2 having a two-layer structure.

  Then, similarly to the first embodiment, a phosphorus-doped doped amorphous silicon film 3 is formed on the gate oxide film 2, and a sidewall oxide film 7 is formed by reactive ion etching. Further, a doped amorphous silicon film is formed. Are selectively removed by etching to form wiring for electrodes and peripheral circuits (FIG. 9A).

  Subsequently, radical oxidation by low-temperature plasma is performed on the surface of the electrode pattern, and film formation is performed by a CVD method to form an interelectrode insulating film 8N composed of a laminated film of a silicon oxide film and a silicon nitride film having a total film thickness of 50 to 75 nm. (FIG. 9B). Then, ion implantation for forming the photodiode portion is performed. Thereafter, flash lamp annealing is performed to activate the implanted ions.

  Next, a resist is applied and photolithography is performed to form a resist pattern R5 for patterning the interelectrode insulating film 8N (FIG. 9C). Then, the laminated film on the photodiode region is removed by etching using this resist pattern as a mask.

  Subsequently, radical oxidation by low-temperature plasma and film formation by high-temperature CVD are performed to form a laminated film of a silicon oxide film and a silicon nitride film having a film thickness of 50 to 75 nm as the antireflection film 29 (FIG. 10A). .

  Next, a resist is applied and photolithography is performed to form a resist pattern R6 for patterning the antireflection film 29 to form a hydrogen termination processing opening (FIG. 10B). Then, using this resist pattern as a mask, the antireflection film 29 is etched to form an opening for hydrogen termination (FIG. 10C).

  Subsequently, radical oxidation by low temperature plasma and film formation by high temperature CVD method are performed to form a silicon oxide film 11 having a film thickness of 50 to 75 nm as an interlayer insulating film for ensuring a withstand voltage, and an adhesion layer by CVD method or PVD method. A TiN layer 12 and a W layer 13 as a light shielding film are sequentially formed (FIG. 11A). Here, since the antireflection film 29 has a high breakdown voltage, the silicon oxide 11 may be omitted. Thereby, the opening of the photodiode can be widened.

  Next, a resist is applied and photolithography is performed to form a resist pattern R7 for patterning the light shielding film 13 (FIG. 11B). Then, using this resist pattern as a mask, the W layer 13 is etched to form a silicon oxide film 14 for preventing the light shielding film from being oxidized (FIG. 12A).

  Then, a BPSG film 15 having a thickness of 700 nm is formed on this upper layer, and is reflowed and flattened at 850 ° C. (FIG. 12B). Here, instead of the BPSG film 15, a silicon oxide film may be formed by radical oxidation using low-temperature plasma. In order to form a waveguide, an opening is formed in the photodiode portion, and a silicon nitride film (not shown) is formed by a CVD method to form an optical waveguide. Then, an insulating film (passivation film: not shown) made of P-SiN and a planarizing layer (not shown) made of a transparent resin film are formed.

Thereafter, as in the first embodiment, the inner lens 21, the planarizing layer 22, the color filter 50, the planarizing layer 70, the microlens 60, and the like are formed.
According to this configuration, it is possible to achieve a higher breakdown voltage than in the first embodiment.

(Embodiment 3)
In the second embodiment, as shown in FIGS. 9 to 12, the interelectrode insulating film is formed by a two-layer film of a silicon oxide film formed by radical oxidation using low-temperature plasma and a silicon nitride film formed by a CVD method. The silicon nitride film in the region is removed and an antireflection film is formed. In this embodiment, as shown in FIGS. 13 to 15, the silicon nitride film in the photodiode region is left as an antireflection film, and the photodiode region And an opening in the hydrogen termination process is formed in the vicinity of the boundary between the charge transfer unit and the charge transfer unit.
In this step, after the formation of the antireflection film 29 shown in FIG. 10A, a resist pattern R8 for forming the opening for hydrogen termination is left in the photodiode formation region as shown in FIG. 13A. Thus, an antireflection film in the photodiode region is configured.
That is, using the resist pattern as a mask, the antireflection film 29 is etched to form an opening for hydrogen termination so as to leave the antireflection film in the photodiode region (FIG. 13B).

  Subsequently, radical oxidation by low temperature plasma and film formation by high temperature CVD method are performed to form a silicon oxide film 11 having a film thickness of 50 to 75 nm as an interlayer insulating film for ensuring a withstand voltage, and an adhesion layer by CVD method or PVD method. A TiN layer 12 and a W layer 13 as a light shielding film are sequentially formed (FIG. 14A). Here, since the antireflection film 29 has a high breakdown voltage, the silicon oxide 11 may be omitted. Thereby, the opening of the photodiode can be widened.

  Next, a resist is applied and photolithography is performed to form a resist pattern R9 for patterning the light shielding film 13 (FIG. 14B). Then, using this resist pattern as a mask, the W layer 13 is etched to form a silicon oxide film 14 for preventing the light shielding film from being oxidized (FIG. 15A).

  Then, a BPSG film 15 having a thickness of 700 nm is formed on this upper layer, and is reflowed and flattened at 850 ° C. (FIG. 15B). Here, instead of the BPSG film 15, a silicon oxide film may be formed by radical oxidation using low-temperature plasma. In order to form a waveguide, an opening is formed in the photodiode portion, and a silicon nitride film (not shown) is formed by a CVD method to form an optical waveguide. Then, an insulating film (passivation film: not shown) made of P-SiN and a planarizing layer (not shown) made of a transparent resin film are formed.

Thereafter, as in the first embodiment, the inner lens 21, the planarizing layer 22, the color filter 50, the planarizing layer 70, the microlens 60, and the like are formed.
According to this configuration, in addition to the above effects, the thermal history received by the substrate can be reduced by the amount that the film formation is not performed again.

In the first embodiment, the example in which the field oxide film is formed by the LOCOS method has been described. However, it is also effective that the trench T is filled with the silicon oxide film by the CVD method and the surface is planarized by CMP polishing. It is.
According to this method, miniaturization can be achieved without bird's beaks compared to the case of LOCOS. However, the generation of cracks due to thermal strain can be solved by optimizing the conditions during CVD growth.

  As described above, according to the method of the present invention, since the photoelectric conversion portion and the charge transfer portion are formed on the surface of the substrate that has been flattened with high accuracy, fine patterning becomes possible, and 0.1 μm A photoelectric conversion unit having the following inter-electrode distance can be easily formed, and it is possible to obtain a highly reliable charge transfer electrode with reduced variation in characteristics. It is effective for formation.

  According to this configuration, since it is possible to obtain an insulating film with good film quality without causing an increase in diffusion length, it is possible to reduce the size and to be useful as a solid-state imaging device in an electronic device such as a mobile phone. It is.

It is a figure which shows the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is sectional drawing which shows the shape manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing process of the solid-state image sensor of Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing process of the solid-state image sensor of Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing process of the solid-state image sensor of Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing process of the solid-state image sensor of Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing process of the solid-state image sensor of Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing process of the solid-state image sensor of Embodiment 3 of this invention.

Explanation of symbols

1 Silicon substrate 2 Gate oxide film 3 Charge transfer electrode (doped amorphous silicon layer)
4 Silicon oxide film 5 Silicon nitride film 6 Organic antireflection film 7 Silicon oxide film 8 Interelectrode insulating film 8N Interelectrode insulating film 9 Silicon oxide film 10 Silicon nitride film 11 Silicon oxide film 12 TiN layer 13 W layer 15 Insulating film (BPSG) film)
16 Silicon nitride film 50 Color filter 60 Micro lens 70 Flattening layer 100 Field oxide film A Effective imaging area B Non-imaging area

Claims (17)

In a solid-state imaging device including a photoelectric conversion unit, and a charge transfer unit including a charge transfer electrode that transfers charges generated in the photoelectric conversion unit,
A solid-state imaging device in which at least one of the insulating films has a two-layer structure of a radical oxide film formed by low-temperature plasma and a CVD film. The solid-state imaging device according to claim 1,
The charge transfer electrode has a single-layer electrode structure of a first electrode and a second electrode formed via an interelectrode insulating film covering a side wall of the first electrode;
A solid-state imaging device in which the inter-electrode insulating film has a two-layer film structure of a radical oxide film formed by low-temperature plasma and a CVD film. The solid-state imaging device according to claim 1 or 2,
A solid-state imaging device in which a gate oxide film formed under the charge transfer electrode has a two-layer film structure of a radical oxide film formed by low-temperature plasma and a CVD film. The solid-state imaging device according to any one of claims 1 to 3,
Wherein the photoelectric conversion unit, and an optical waveguide structure, and the radical oxide film by low temperature plasma periphery of the optical waveguide, the solid-state imaging device composed of a two-layer film structure of the CVD film. The solid-state imaging device according to any one of claims 1 to 4,
A solid-state imaging device in which an interlayer insulating film is configured by a two-layer film structure of a radical oxide film formed by low-temperature plasma and a CVD film. The solid-state imaging device according to claim 2,
The solid-state imaging device, wherein the CVD film is a silicon nitride film. The solid-state imaging device according to any one of claims 1 to 6,
A solid-state imaging device, wherein the field oxide film is a recess LOCOS film formed by selective oxidation (LOCOS) after forming a trench. The solid-state imaging device according to any one of claims 1 to 6,
A solid-state imaging device in which the field oxide film is a film having a shallow trench (STI) structure. In a method for manufacturing a solid-state imaging device, comprising: a photoelectric conversion unit; and a charge transfer unit including a charge transfer electrode that transfers charges generated in the photoelectric conversion unit.
Forming a photoelectric conversion portion and a charge transfer channel on a semiconductor substrate surface;
Forming a gate oxide film on the surface of the semiconductor substrate;
Forming a charge transfer electrode on the surface of the semiconductor substrate on which the gate oxide film is formed;
Forming an interlayer insulating film on the charge transfer electrode,
A method of manufacturing a solid-state imaging device, wherein at least one of the photoelectric conversion unit, the charge transfer unit, or the interlayer insulating film is formed in two steps, a radical oxide film forming step by low-temperature plasma and a CVD film forming step. It is a manufacturing method of the solid-state image sensing device according to claim 9,
The step of forming the charge transfer electrode comprises the step of forming a pattern of the first layer conductive film constituting the first electrode;
Forming an insulating film to be an interelectrode insulating film on at least the side wall of the first electrode;
Forming a second layer conductive film constituting a second electrode on the surface of the semiconductor substrate on which the first electrode and the interelectrode insulating film are formed;
Removing at least the second layer conductive film on the first electrode, and planarizing the surface of the semiconductor substrate on which the second conductive film is formed,
Forming the interelectrode insulating film comprises:
A method for manufacturing a solid-state imaging device, comprising two steps of a radical oxide film forming step by low-temperature plasma and a CVD film forming step. It is a manufacturing method of the solid-state image sensing device according to claim 10,
The step of forming the gate oxide film includes a step of forming a radical oxide film by low temperature plasma,
A method for manufacturing a solid-state imaging device including two steps including a CVD step. It is a manufacturing method of the solid-state image sensing device according to claim 10,
An optical waveguide structure is provided on the photoelectric conversion unit,
Step of forming the optical waveguide, a step of the periphery of the optical waveguide is formed and the formation process of radical oxidation film by low temperature plasma, the insulating film consists of two steps with the CVD process,
Forming an opening on the photoelectric conversion portion;
And a step of filling the opening with a high refractive index material. It is a manufacturing method of the solid-state image sensing device according to claim 10,
A method for manufacturing a solid-state imaging device, wherein the step of forming an interlayer insulating film includes a step of forming a radical oxide film by low-temperature plasma and a CVD step. The solid-state imaging device according to claim 11,
The said CVD process is a manufacturing method of the solid-state image sensor which is a process of forming a silicon nitride film.
Solid-state image sensor. A method for manufacturing a solid-state imaging device according to any one of claims 9 to 14,
A method of manufacturing a solid-state imaging device including a step of forming a field oxide film by selective oxidation (LOCOS) after forming a trench by forming a recess before forming the photoelectric conversion unit and the charge transfer unit. It is a manufacturing method of the solid-state image sensing device according to claim 15,
After forming the field oxide film on the surface of the semiconductor substrate, prior to forming the charge transfer electrode,
A method for producing a solid-state imaging device, comprising the step of planarizing the entire surface of the semiconductor substrate. A method for manufacturing a solid-state imaging device according to any one of claims 9 to 14,
A method of manufacturing a solid-state imaging device including a step of forming a film having a shallow trench (STI) structure prior to formation of the photoelectric conversion unit and the charge transfer unit.

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