JP2006041484A - Solid-state image pickup device and manufacturing method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable photoelectric conversion device by preventing variation in characteristic of an amplifier section configuring a peripheral circuit section in a solid-state image pickup device having a charge transfer electrode in a single-layer electrode structure which is formed by forming a second-layer conductive film on a pattern of a first-layer conductive film, and then removing the second-layer conductive film on the first-layer conductive film for planarization. <P>SOLUTION: A solid-state image pickup element includes: a photoelectric conversion section; a charge transfer section having a charge transfer electrode for transferring charges generated in the photoelectric conversion section; and a peripheral circuit section connected to the charge transfer section. The charge transfer section is configured by a first electrode comprising a first-layer conductive film, and a second electrode comprising a second-layer conductive film, which is arranged parallel to the first electrode via an inter-electrode insulating film, wherein at least part of electrode wiring of the peripheral circuit section comprises the first-layer conductive film. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device and a method for manufacturing the same, and more particularly to a solid-state imaging device having a single-layer electrode structure CCD (charge coupled device).

  A solid-state imaging device using a CCD used for an area sensor or the like includes a photoelectric conversion unit such as a photodiode and a charge transfer unit including a charge transfer electrode for transferring a signal charge from the photoelectric conversion unit. A plurality of charge transfer electrodes are arranged adjacent to each other on a charge transfer path formed on the semiconductor substrate, and are sequentially driven.

  In recent years, demands for higher resolution and higher sensitivity have been increasing in solid-state imaging devices, and the number of imaging pixels has been increasing to more than gigapixels. A substrate (silicon substrate) on which a solid-state image sensor is built is mounted by stacking filters and lenses. For this reason, the positional accuracy between the lens and the photoelectric conversion unit is important, and the distance, that is, the distance in the height direction, is a big problem in terms of positional accuracy in the manufacturing process and sensitivity (photoelectric conversion efficiency) in use. .

Furthermore, in such a situation, in order to obtain high resolution without increasing the chip size, it is necessary to reduce the area per unit pixel and achieve high integration. On the other hand, if the area of the photodiode constituting the photoelectric conversion unit is reduced, the sensitivity is lowered, so the area of the photodiode region must be ensured.
Therefore, various studies have been made to reduce the size of the chip while securing the area occupied by the photodiode region by reducing the wiring area ratio by reducing the wiring area of the charge transfer portion and the peripheral circuit. .

  Under these circumstances, maintaining the flatness of the interlayer insulating film between the wiring layers is an important technical issue in order to realize high integration by miniaturization of the wiring. In order to improve the flatness, a structure in which the charge transfer portion has a single-layer electrode structure has been proposed (for example, Patent Document 1).

  By the way, in a conventional solid-state imaging device using a charge transfer electrode having a single layer structure, a polycrystalline silicon or amorphous silicon layer is used as the charge transfer electrode, and after forming the first layer wiring, the pattern surface of the first layer wiring is formed. Is oxidized, and a polycrystalline silicon or amorphous silicon layer serving as a second transfer electrode is deposited and polished by CMP (Chemical Mechanical Polishing), or a resist is applied, and the entire surface is etched by resist etch back. The electrode is made into a single layer.

  For example, in the conventional method, a silicon oxide film 2a having a thickness of 15 to 35 nm, a silicon nitride film 2b having a thickness of 50 nm, and a silicon oxide film 2c having a thickness of 5 to 10 nm are formed on the surface of the n-type silicon substrate 1. A gate oxide film 2 having a three-layer structure is formed.

Subsequently, a first layer doped amorphous silicon film 3a is formed on the gate oxide film 2, and a silicon oxide film 4a and a silicon nitride film 4b are formed.
Subsequently, a resist is applied to the upper layer.

  Then, exposure is performed using a desired mask by photolithography, development and water washing are performed to form a resist pattern R1 having a pattern width of 0.3 to several μm (FIG. 6A). Here, the pattern width may be 0.3 μm or less.

Thereafter, using this resist pattern as a mask, the silicon oxide film 4a and the silicon nitride film 4b are etched to form a mask pattern for patterning the first electrode (FIG. 6B). Note that a resist pattern may be used directly as a mask without forming a mask pattern in this way.
Then, the resist pattern R1 is peeled and removed by ashing (FIG. 6C), and the first layer doped amorphous silicon film 3a is selectively used by using the mask pattern as a mask and the silicon nitride film 2b of the gate oxide film 2 as an etching stopper. The first electrode is formed by etching away (FIG. 6D).

Subsequently, an interelectrode insulating film 5 is formed on the surface of the first electrode pattern by thermal oxidation (FIG. 6E), and a second-layer doped amorphous silicon film 3b is formed thereon (FIG. 7). (F)).
After that, the second layer doped amorphous silicon film 3b is planarized by CMP (FIG. 7G). At this time, in order to suppress variation in the electrode film thickness due to CMP, dummy patterns that do not contribute to the operation of the solid-state imaging device are arranged. However, since the dummy patterns cannot be arranged in the active region, the second layer transfer electrode is formed by CMP. When flattening, so-called dishing occurs in the active region, where a dish-shaped recess is formed.

And as shown in FIG.7 (h), it coat | covers with the desired resist pattern R3.
Thereafter, using this resist pattern R3 as a mask, the second layer doped amorphous silicon film 3b on the photodiode 30 constituting the photoelectric conversion portion is selectively removed by etching and the peripheral circuit portion is patterned.

Then, as shown in FIG. 7I, the resist pattern R3 is removed by ashing.
In this way, the second electrode composed of the second layer doped amorphous silicon film 3b is formed, and a charge transfer electrode having a flat surface is formed.

  In the case of this method, the second layer doped amorphous silicon film is planarized by using the CMP method to be separated to manufacture a single layer structure charge transfer electrode. When resist etchback is used instead of the CMP method, a resist is applied to the upper layer of the second polycrystalline silicon film 3b by spin coating, and the etching rate between the resist and the second layer doped amorphous silicon film is increased. Etching is performed to achieve the same level, and the surface is flattened.

  However, dummy patterns that do not contribute to the operation of the solid-state imaging device are arranged in order to suppress the film thickness variation in the CMP and resist etch back processes as described above. It is difficult to arrange the patterns. For this reason, a layout is formed without forming a dummy pattern in the active region, but pattern density is low in peripheral circuits, particularly in the amplifier section. Conventionally, this amplifier section is composed of a second-layer doped amorphous silicon film, but when the second-layer doped amorphous silicon film is flattened, so-called dishing occurs in which a recess is formed and becomes dish-shaped. Due to the film thickness variation due to the difference in thickness, the gate electrode film thickness of the amplifier circuit may vary, resulting in poor detection sensitivity or variation in wiring resistance, which is a major cause of reduced charge transfer efficiency. .

In addition, in the region where the pattern density of the first electrode constituting the first layer on the semiconductor substrate is small, the film thickness of the second layer doped amorphous silicon film may be small.
As shown in the schematic diagram of the planar structure of the solid-state imaging device chip in FIG. 8, the light receiving region A composed of the photoelectric conversion unit and the vertical charge transfer electrode, and the charge received and photoelectrically converted by the light receiving region A are transferred. It is composed of a horizontal transfer path B, an output circuit C including an amplifier, and a pad P for external connection. Here, the element portion T includes the light receiving region A and the horizontal transfer path B.
For example, the horizontal transfer path has a close structure in which the charge transfer electrodes 3S in the horizontal direction are arranged via the interelectrode insulating film 5 as shown in the cross-sectional view along line aa in FIG. On the other hand, as shown in the cross-sectional view of FIG. 10 taken along line bb in FIG. It is arranged. Thus, both the light receiving area and the horizontal transfer path have a certain density. On the other hand, the electrode density of the output circuit is such that the electrode 3e is formed as shown in the cc cross-sectional view of FIG.
For this reason, there has been a problem that the dishing phenomenon as shown in FIG. 7G cannot be avoided, and variations occur in the direction of decreasing film thickness.

JP-A-8-274302

  As described above, in a conventional solid-state imaging device, dishing occurs in an active region where a dummy pattern cannot be formed, resulting in variations in the thickness of the wiring layer, and an amplifier unit that requires a high-precision pattern. In this case, the film thickness of the gate electrode varies, which causes the characteristic fluctuation.

  The present invention has been made in view of the above circumstances, and a second layer conductive film is formed on the pattern of the first layer conductive film, and the second layer conductive film on the first layer conductive film is removed. In a solid-state imaging device having a charge transfer electrode having a single-layer electrode structure formed by flattening, the characteristics of the amplifier section constituting the peripheral circuit section is prevented from changing and a highly reliable solid-state imaging device is provided. With the goal.

Therefore, in the solid-state imaging device of the present invention, a photoelectric conversion unit, a charge transfer unit including a charge transfer electrode that transfers charges generated in the photoelectric conversion unit, and a peripheral circuit unit connected to the charge transfer unit, And the charge transfer section is composed of a first electrode made of a first layer conductive film and a second electrode made of a second layer conductive film juxtaposed via an interelectrode insulating film. Further, in the solid-state imaging device constituted by the charge transfer electrode having a single layer structure, at least a part of the electrode wiring of the peripheral circuit portion is constituted by a first layer conductive film.
According to this configuration, since the electrode wiring of the peripheral circuit portion, for example, the amplifier of the output circuit, is configured by the first layer conductive film, the characteristics can be obtained without causing variations in resistance due to the film reduction of the second layer conductive film. An excellent solid-state imaging device without fluctuation can be provided. Further, since the first layer conductive film constitutes at least a part of these peripheral circuit portions, it is possible to obtain the same effect as the dummy pattern also exists in the region where the dummy pattern is difficult to form. It is also possible to prevent the second layer silicon-based conductive film from being reduced in the periphery of the chip, particularly in the periphery of the chip.

In the solid-state imaging device of the present invention, the gate electrode of the transistor constituting the amplifier in the peripheral circuit portion includes the first layer conductive film.
According to this configuration, the gate electrode is formed with high accuracy, and variations in output characteristics can be reduced.

  In the solid-state imaging device according to the present invention, the first layer conductive film and the second layer conductive film include a silicon-based conductive film.

  In the solid-state imaging device of the present invention, the silicon-based conductive film includes a doped amorphous silicon film.

  In the solid-state imaging device of the present invention, the silicon-based conductive film includes a doped polysilicon film.

In the solid-state imaging device of the present invention, the surface level of the field oxide film provided in the peripheral circuit unit and the charge transfer unit so as to surround the effective imaging region of the photoelectric conversion unit is the surface level of the photoelectric conversion unit. Including the same level.
According to this configuration, the surface can be easily flattened. .

  In the solid-state imaging device of the present invention, the field oxide film includes a film formed by selective oxidation (LOCOS).

  In the solid-state imaging device manufacturing method of the present invention, a photoelectric transfer unit, a charge transfer unit including a charge transfer electrode having a single-layer electrode structure that transfers a charge generated in the photoelectric conversion unit, and the charge transfer In a method for manufacturing a solid-state imaging device including a peripheral circuit portion connected to a portion, a first electrode, the photoelectric conversion portion, and a first layer of the peripheral circuit portion on a semiconductor substrate surface on which a gate oxide film is formed A step of forming a pattern of a first-layer conductive film constituting the wiring, a step of forming an insulating film serving as an inter-electrode insulating film on at least a side wall of the first electrode, and the first electrode and the gap between the electrodes Forming a second-layer conductive film constituting a second electrode on the surface of the semiconductor substrate on which an insulating film is formed; and a protruding portion of the second-layer conductive film protruding on the first electrode. Removing and planarizing the surface, and photoelectric And a step of patterning so as to remove the second layer conductive film remaining on section.

  With this configuration, the pattern density of the pattern formed by the first layer conductive film is sparse, and the first layer wiring of the peripheral circuit portion where it is difficult to form a dummy pattern because of the active region is formed of the first layer conductive film. Thus, a reduction in film thickness due to dishing can be suppressed, and a highly accurate pattern can be formed, so that variation in characteristics can be reduced.

In the solid-state imaging device manufacturing method of the present invention, the step of forming the pattern of the first layer conductive film includes the step of forming a pattern of the gate electrode of the transistor constituting the amplifier of the peripheral circuit section. Including.
With this configuration, it is possible to form the gate electrode film thickness causing the characteristic variation as designed.

In the solid-state imaging device manufacturing method of the present invention, the step of forming the pattern of the first layer conductive film includes the step of forming a pattern of a gate electrode and a jumper wiring of a transistor constituting an amplifier of the peripheral circuit unit. Including what is included.
With this configuration, since the main configuration that causes the characteristic variation is formed of the first layer conductive film, the gate length can be formed as designed.

  In the solid-state imaging device manufacturing method of the present invention, the first layer conductive film pattern and the second layer conductive film include a silicon-based conductive film.

  In the solid-state imaging device manufacturing method of the present invention, the silicon-based conductive film may be a doped amorphous silicon film.

  In the solid-state imaging device manufacturing method of the present invention, the silicon-based conductive film may be a doped polysilicon film.

Moreover, the manufacturing method of the solid-state imaging device of the present invention includes a method in which the flattening step is a CMP (Chemical Mechanical Polishing) step.
When CMP is used, dishing may occur. According to this configuration, a highly reliable amplifier circuit and peripheral circuit portion can be formed without causing dishing.

  In the solid-state imaging device manufacturing method of the present invention, the flattening step has a similar etching rate to the step of applying a resist to the surface of the semiconductor substrate and the resist and the second layer conductive film. And a step of etching back under conditions.

  In this way, in areas with low pattern density, such as areas other than the wiring section and photodiode section on the semiconductor substrate, especially in the peripheral circuit section, high pattern accuracy such as the gates of the transistors constituting the amplifier is required. There is a problem that the second layer silicon-based conductive film tends to be reduced due to the dishing phenomenon, and characteristic variations are likely to occur. However, according to the present invention, the amplifier is configured by the first layer conductive film. High-accuracy pattern formation is possible. Further, a wiring portion having a more uniform film thickness can be formed for a wiring portion such as a jumper wiring.

In the method of the present invention, a trench is formed in a field oxide film formation region provided in a peripheral circuit portion and the charge transfer portion so as to surround an effective imaging region of the photoelectric conversion portion on a semiconductor substrate surface. A step of forming a field oxide film in the trench, a step of flattening the surface of the semiconductor substrate on which the field oxide film is formed, the charge transfer electrode, the photoelectric conversion unit, and the semiconductor substrate surface And a step of forming an element portion such as the peripheral circuit portion.
By this method, the surface can be easily flattened. In this case, if the trench depth and the field oxide film can be formed so as to coincide with each other, the planarization process may not be particularly necessary.

In the solid-state imaging device manufacturing method of the present invention, the step of forming the field oxide film includes a selective oxidation (LOCOS) step.
According to this method, it is possible to form a field oxide film having a good film quality although it takes a long time.

In the solid-state imaging device manufacturing method of the present invention, the step of forming the field oxide film includes a step of filling the trench with an insulating film by a CVD method.
According to this method, the time required for forming the field oxide film can be shortened. It should be noted that LOCOS and CVD may be used in combination, and a plurality of methods may be used in the same substrate surface, such as LOCOS in the vicinity of an amplifier unit that emphasizes element isolation and CVD in a portion that emphasizes flatness.

  Further, in the method of manufacturing a solid-state imaging device according to the present invention, the step of forming the pattern of the first layer conductive film may be performed so that a surface level of the resist does not become a predetermined value or less on the semiconductor substrate. Including the step of forming the pattern including:

  In the solid-state imaging device manufacturing method of the present invention, in the step of forming the pattern of the first layer conductive film, the surface level of the second layer conductive film does not fall below a predetermined value on the semiconductor substrate. Thus, the process of forming the said pattern containing a dummy pattern is included.

  According to the solid-state imaging device and the method of manufacturing the same of the present invention, the first layer conductive film is formed even in the peripheral circuit portion in the active region where the dummy pattern cannot be formed when planarization is performed by, for example, the CMP method or the resist etch back method. Since these peripheral circuit portions are configured, it is possible to obtain the same effect as the presence of dummy patterns in regions where it is difficult to form dummy patterns. It is possible to prevent the silicon conductive film from being reduced, and to form a solid-state imaging device with uniform characteristics and good charge transfer efficiency. This solid-state imaging device is effective by miniaturization.

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)

As shown in FIGS. 1 to 2, the solid-state imaging device includes a gate of an amplifier section that constitutes an output circuit (peripheral circuit) in a solid-state imaging device including a charge transfer electrode having a single-layer electrode structure. The electrode is composed of a first layer amorphous silicon film which is a first layer conductive film. As a result, the gate electrode 3g of the amplifier section is configured by the pattern of the first layer conductive film in the active region T (see FIG. 3) where the dummy pattern cannot be formed in order to prevent the formation of the parasitic capacitance. A highly accurate pattern can be formed without variation.
Thereby, not only the characteristic variation of the amplifier part can be suppressed, but also the second electrode formed of the second layer amorphous silicon and the wiring in the peripheral part of the chip by the flattening process by resist etch back do not reduce the film. Therefore, the surface of the charge transfer portion and the peripheral circuit portion can be satisfactorily flattened without reducing the film thickness.

  As shown in FIG. 3 and FIG. 4 and FIG. 5, the silicon substrate 1 is provided with a photoelectric conversion portion. A plurality of photodiode regions 30 are formed, and a charge transfer unit 40 for transferring signal charges detected by the photodiodes is formed between the photodiode regions 30. Here, FIGS. 1 and 2 are diagrams showing manufacturing process diagrams of a region corresponding to the dd cross-sectional view of FIG. FIG. 5 is a cross section obtained by cutting along line AA in FIG.

  Although not shown in FIG. 4, the charge transfer channel 33 through which the signal charge transferred by the charge transfer electrode moves is formed in a direction crossing the direction in which the charge transfer unit 40 extends.

  In FIG. 4, the description of the interelectrode insulating film 5 formed near the boundary between the photodiode region and the charge transfer portion 40 is omitted.

  As shown in FIG. 5, a photodiode region 30, a charge transfer channel 33, a channel stop region 32, and a charge readout region 34 are formed in the silicon substrate 1, and a gate oxide film 2 is formed on the surface of the silicon substrate 1. Is done. On the surface of the gate oxide film 2, an interelectrode insulating film 5 made of a silicon oxide film and a charge transfer electrode 3 (a first electrode made of a first layer doped amorphous silicon film 3a, a second layer doped amorphous silicon film 3b) Second electrode) is formed.

  Although the charge transfer unit 40 is as described above, an intermediate layer 70 is formed on the upper surface of the charge transfer electrode of the charge transfer unit 40 as shown in FIG. 71 is a light shielding film, 72 is an insulating film made of BPSG (borophospho silicate glass), 73 is an insulating film (passivation film) made of P-SiN, and 74 is a flattening layer made of a transparent resin film.

Above the solid-state imaging device, a light shielding film 71 is provided except for the light detection portion of the photodiode region 30, and a color filter 50 and a microlens 60 are further provided. Further, a flattening layer 61 made of an insulating transparent resin or the like is filled between the color filter 50 and the microlens 60.
FIG. 5 shows a so-called honeycomb-structured solid-state image pickup device, but it goes without saying that the present invention can also be applied to a square lattice type solid-state image pickup device.

Next, the manufacturing process of the solid-state imaging device will be described in detail with reference to FIGS. 1 (a) to 2 (i).
First, a silicon oxide film 2a having a thickness of 15 to 35 nm, a silicon nitride film 2b having a thickness of 50 nm, and a thickness of 5 to 5 are formed on the surface of an n-type silicon substrate 1 having an impurity concentration of about 1.0 × 10 ¹⁶ cm ^−3. A 10 nm silicon oxide film 2c is formed, and a gate oxide film 2 having a three-layer structure is formed.

Subsequently, a phosphorus-doped first layer doped amorphous silicon film having a film thickness of 0.4 μm is formed on the gate oxide film 2 by a low pressure CVD method using SiH ₄ added with PH ₃ and N ₂ as a reactive gas. 3a is formed. The substrate temperature at this time shall be 600-700 degreeC.

  Thereafter, a silicon oxide film 4a having a thickness of 15 nm and a silicon nitride film 4b having a thickness of 50 nm are formed by low pressure CVD.

Subsequently, a positive resist is applied to the upper layer so as to have a thickness of 0.5 to 1.4 μm, exposed by photolithography using a desired mask, developed, and washed with water to form a resist pattern R1. (FIG. 1 (a)). Here, a dummy pattern _RD is formed on the peripheral portion of the silicon substrate 1, and as is apparent from comparison with FIG. 11, the resist pattern R1 is located between the dummy pattern _RD and the gate of the transistor in the amplifier section. A resist pattern _R1A for electrode formation is included. The dummy pattern is formed at the time of layout so that the interval from the resist pattern R1 does not exceed a predetermined width (interval of the first electrodes).

Thereafter, the silicon oxide film 4a and the silicon nitride film 4b are etched by reactive ion etching using a mixed gas of CHF ₃ , C ₂ F ₆ , O ₂ and He, and the first layer doped amorphous silicon A mask pattern for patterning the film 3a is formed. Again, the dummy mask pattern is formed on the left hand side of the original first electrode forming mask pattern.
Then, the resist pattern is removed by ashing (FIG. 1C).

Thereafter, the first layer as the first conductive film is formed by reactive ion etching using a mixed gas of HBr and O ₂ with this mask pattern as a mask and the silicon nitride film 2b of the gate oxide film 2 as an etching stopper. The doped amorphous silicon film 3a is selectively removed by etching to form the first electrode and peripheral circuit wiring (FIG. 1D). In the present embodiment, a gate electrode and a jumper wiring (not shown) of a transistor that constitutes an amplifier section are formed as electrode wirings in the peripheral circuit section by a first layer conductive film. Here, it is desirable to use an etching apparatus such as an ECR (Electron Cyclotoron Resonance) system or an ICP (Inductively Coupled Plasma) system.

  Subsequently, an inter-electrode insulating film 5 made of a silicon oxide film having a thickness of 80 nm is formed around the side surface of the first electrode pattern by thermal oxidation (FIG. 1E). Here, the temperature of thermal oxidation is about 900 ° C. Desirably, it is 850 degreeC. Thereby, the elongation of the diffusion length can be prevented.

Next, a second layer doped amorphous silicon film 3b having a film thickness of 0.4 to 0.7 μm is formed by a low pressure CVD method using a reactive gas obtained by adding PH ₃ and N ₂ to SiH ₄ gas. At this time, the film thickness of the second layer doped amorphous silicon film 3b is equal to or more than the total film thickness of the first layer doped amorphous silicon film and the silicon oxide film 4a and the silicon nitride film 4b in the upper layer. It needs to be formed to be thick. (Fig. 2 (f))

  Then, as shown in FIG. 2 (g), a resist R2 (not shown) is applied, and the entire surface is etched under the condition that the etching rate of the resist and the second layer doped amorphous silicon film 3b is almost the same. Then, the second layer doped amorphous silicon film 3b is planarized.

  Thereafter, as shown in FIG. 2H, an active region including a resist pattern R3A for forming the gate electrode of the amplifier section and a resist pattern R3 for forming the peripheral circuit are formed. Here, the resist pattern R3 is formed so as to cover a part of the solid-state imaging element forming portion and the peripheral circuit portion.

Then, as shown in FIG. 2 (i), by using this resist pattern R3 as a mask, the second layer doped amorphous silicon film 3b on the photodiode region 30 is removed by etching and other patterns of peripheral circuits (not shown). ) Remain.
Then, by removing the resist by ashing, the second-layer doped amorphous silicon film 3b constituting part of the solid-state imaging element forming part and the peripheral circuit part (including the gate electrode 3g of the amplifier part) is formed.

In this way, the second electrode composed of the second layer doped amorphous silicon film 3b as the second layer conductive film is formed, and the charge transfer electrode having a flat surface is formed. At this time, a dummy pattern (not shown) remains on the periphery of the substrate. This dummy pattern has a mesh shape and is preferably connected to the ground potential. Thereby, a stable connection is possible.
Further, according to this method, since the amplifier part is composed of the first layer doped amorphous silicon film, not only variation in the film thickness of the amplifier part is suppressed, but also the dummy pattern _{RD in} the vicinity thereof is reduced in film thickness. It becomes possible to suppress.

Then, a light-shielding film pattern 71 and a BPSG film 72 having a thickness of 700 nm are formed on this upper layer and reflowed at 850 ° C. to be flattened. Then, an insulating film (passivation film) 73 made of P-SiN and a planarization layer 74 made of a transparent resin film are formed.
Thereafter, the color filter 50, the flattening layer 61, the microlens 60, and the like are formed to obtain a solid-state imaging device as shown in FIGS.

According to this method, the gate electrode and the jumper wiring of the amplifier section are formed of the first layer conductive film, thereby preventing the second layer conductive film from being reduced in the planarization step and reducing the film thickness in the peripheral region. It also serves as a dummy pattern for prevention, and can reduce variation in characteristics. Moreover, since a highly reliable solid-state image sensor can be obtained, a fine and highly sensitive solid-state image sensor can be formed.
Since the first layer conductive film is covered with a stopper made of the silicon oxide film 4a and the silicon nitride film 4b on the upper layer, the desired film thickness can be obtained without being etched even in the etch back process. Can be maintained.

  Furthermore, a removal suppression layer pattern may be formed on the second layer doped amorphous silicon film in the active region. With this configuration, the surface level of the resist for etch back can be formed to be the same as that of the central portion, and high-precision pattern formation can be realized without film loss at the peripheral portion. In addition, functionally reliable operation characteristics can be obtained.

As described above, according to such a configuration, since the gate electrode and the jumper wiring of the amplifier unit are configured by the first layer conductive film, the resistance caused by the film reduction of the second layer conductive film in the planarization step. Variation can be suppressed, and the uniformity of the amplifier characteristics can be improved. Also, dummy patterns are additionally formed where the pattern density of the first electrode is small, such as the periphery of the substrate, so that the surface level of the resist is not lowered when the resist is applied by spin coating, particularly in the periphery of the substrate. Therefore, a highly reliable solid-state imaging device can be formed with no variation in characteristics. Furthermore, the dummy pattern has a role as a so-called dummy that suppresses film loss.
Since the peripheral circuit portion undergoes two oxidation steps, if a process in which the oxidation temperature is lowered to 900 ° C. or lower is used, the diffusion length does not increase and the gate, source, The offset with the drain can be prevented, which is more effective.

  In the embodiment, the interelectrode insulating film 5 is formed around the first electrode by thermal oxidation. That is, the first electrode patterning mask and the silicon nitride film, which is a two-layer silicon nitride film used as an etching stopper when planarizing the second electrode, are used as an antioxidant film, and the heat of the first electrode By performing oxidation, a silicon oxide film is selectively formed on the side wall of the first electrode, and this is used as an interelectrode insulating film. In this case, it is necessary to form a resist pattern in advance so that the first electrode width is increased by the oxidized region. Instead of this thermal oxidation, an interelectrode insulating film may be formed by a low pressure CVD method.

(Second Embodiment)
In the first embodiment, the second layer amorphous silicon film is planarized using the resist etch back method, but it goes without saying that the CMP method may be used. Similar effects can be obtained when the CMP method is used.
In addition, it is possible to form the dummy pattern without causing variations in the film thickness of the wiring layer by forming the dummy pattern so as to be equal to or higher than the density of the light receiving region, particularly the first layer wiring of the photoelectric conversion portion.

In the above-described embodiment, doped amorphous silicon is used as the first layer and the second layer conductive films. However, doped polysilicon, metal, metal silicide, and the like can be appropriately changed.
Further, the amplifier unit has been described, but the present invention is not limited to the amplifier unit, and can be applied to a region having a low pattern density.
In addition, the pattern formation using the first conductive film may be performed not only on the active region but also on the field oxide film.

  Although not described in detail in the embodiment, a field oxide film is formed in a frame shape so as to surround the effective imaging region on the periphery of the chip, but a photoelectric conversion unit including a photosensor and It is desirable to form by the Recess LOCOS method so as to be the same as the surface level of the charge transfer portion.

  As described above, according to the solid-state imaging device of the present invention, the second layer conductive film is formed on the pattern of the first layer conductive film via the interelectrode insulating film. When a charge transfer electrode having a single-layer electrode structure is formed by flattening the conductive film, the peripheral circuit, particularly the amplifier part, is formed of the first layer conductive film, thereby preventing film loss and reducing variation in characteristics. Since a highly reliable solid-state imaging device can be obtained, it is effective for forming a fine and highly sensitive solid-state imaging device.

It is a figure which shows the manufacturing process of the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of the 1st Embodiment of this invention. 1 is an overall schematic explanatory diagram of a solid-state imaging device according to a first embodiment of the present invention. It is principal part explanatory drawing which shows the solid-state image sensor of the 1st Embodiment of this invention. It is sectional drawing which shows the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of a prior art example. It is a figure which shows the manufacturing process of the solid-state image sensor of a prior art example. It is a figure which shows the manufacturing process of the solid-state image sensor of the 2nd Embodiment of this invention. It is a whole schematic diagram of the solid-state image sensor of a prior art example. It is sectional drawing which shows the horizontal transfer path of the solid-state image sensor of a prior art example. It is sectional drawing which shows the light-receiving area | region of the solid-state image sensor of a prior art example. It is sectional drawing which shows the amplifier part of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Gate oxide film 3a 1st electrode (1st layer doped amorphous silicon film)
3b Second electrode (second layer doped amorphous silicon film)
3 Charge Transfer Electrode 4a Silicon Oxide Film 4b Silicon Nitride Film 5 Interelectrode Insulating Film 8 Removal Suppression Layer 30 Photodiode Region 40 Charge Transfer Unit 50 Color Filter 60 Micro Lens 70 Intermediate Layer

Claims (20)

A photoelectric conversion unit, a charge transfer unit including a charge transfer electrode for transferring charges generated in the photoelectric conversion unit, and a peripheral circuit unit connected to the charge transfer unit,
A single-layer structure in which the charge transfer section is composed of a first electrode made of a first layer conductive film and a second electrode made of a second layer conductive film juxtaposed via an interelectrode insulating film In a solid-state imaging device composed of a charge transfer electrode of
A solid-state imaging device, wherein at least a part of the electrode wiring of the peripheral circuit portion is constituted by the first layer conductive film. The solid-state imaging device according to claim 1,
A solid-state imaging device, wherein a gate electrode of a transistor constituting an amplifier in the peripheral circuit portion is formed of the first layer conductive film. The solid-state imaging device according to claim 1 or 2,
The solid-state imaging device, wherein the first layer conductive film and the second layer conductive film are silicon-based conductive films. The solid-state imaging device according to claim 3,
A solid-state imaging device, wherein the silicon-based conductive film is a doped amorphous silicon film. The solid-state imaging device according to claim 3,
A solid-state imaging device, wherein the silicon-based conductive film is a doped polysilicon film. The solid-state imaging device according to claim 1,
The surface level of the field oxide film provided in the peripheral circuit unit and the charge transfer unit so as to surround the effective imaging region of the photoelectric conversion unit is approximately the same as the surface level of the photoelectric conversion unit. Solid-state image sensor. The solid-state imaging device according to claim 6,
The solid-state imaging device, wherein the field oxide film is a film formed by selective oxidation (LOCOS). Solid comprising: a photoelectric conversion unit; a charge transfer unit including a charge transfer electrode having a single-layer electrode structure that transfers charges generated in the photoelectric conversion unit; and a peripheral circuit unit connected to the charge transfer unit In the manufacturing method of the image sensor,
Forming a pattern of a first layer conductive film constituting a first layer wiring of the first electrode, the photoelectric conversion unit and the peripheral circuit unit on the surface of the semiconductor substrate on which the gate oxide film is formed;
Forming an insulating film to be an inter-electrode insulating film on at least the side wall of the first electrode;
Forming a second layer conductive film constituting a second electrode on the surface of the semiconductor substrate on which the first electrode and the interelectrode insulating film are formed;
Removing the protruding portion of the second conductive film protruding on the first electrode, and planarizing the surface;
And a step of patterning so as to remove the second-layer conductive film remaining in the photoelectric conversion unit. It is a manufacturing method of the solid-state image sensing device according to claim 8,
The method of forming a pattern of the first layer conductive film includes a step of forming a pattern of a gate electrode of a transistor constituting an amplifier of the peripheral circuit section. It is a manufacturing method of the solid-state image sensing device according to claim 8,
The step of forming a pattern of the first layer conductive film includes a step of forming a pattern of a gate electrode and a jumper wiring of a transistor constituting an amplifier of the peripheral circuit unit. . It is a manufacturing method of the solid-state image sensing device according to any one of claims 8 to 10,
The solid-state imaging device, wherein the first layer conductive film and the second layer conductive film include a silicon-based conductive film. The solid-state imaging device according to claim 11,
A solid-state imaging device, wherein the silicon-based conductive film is a doped amorphous silicon film. The solid-state imaging device according to claim 11,
A solid-state imaging device, wherein the silicon-based conductive film is a doped polysilicon film. It is a manufacturing method of the solid-state image sensing device according to any one of claims 8 to 13,
The method of manufacturing a solid-state imaging device, wherein the planarizing step is a CMP (Chemical Mechanical Polishing) step. It is a manufacturing method of the solid-state image sensing device according to any one of claims 8 to 13,
The planarizing step includes a step of applying a resist to the semiconductor substrate surface;
And a step of etching back the resist and the second-layer conductive film under the condition that the etching rate is comparable. It is a manufacturing method of the solid-state image sensing device according to claim 8,
Prior to the formation of the charge transfer portion,
Forming a trench in a formation region of a field oxide film provided in a peripheral circuit portion and the charge transfer portion so as to surround an effective imaging region of the photoelectric conversion portion on a semiconductor substrate surface;
Forming a field oxide film in the trench;
Planarizing the semiconductor substrate surface on which the field oxide film is formed;
Forming a device portion such as the charge transfer electrode, the photoelectric conversion portion, and the peripheral circuit portion on the surface of the semiconductor substrate. It is a manufacturing method of the solid-state image sensing device according to claim 16,
The method of manufacturing a solid-state imaging device, wherein the step of forming the field oxide film includes a selective oxidation (LOCOS) step. It is a manufacturing method of the solid-state image sensing device according to claim 16,
The step of forming the field oxide film includes a step of filling the trench with an insulating film by a CVD method. It is a manufacturing method of the solid-state image sensing device according to claim 16,
The step of forming the pattern of the first layer conductive film includes a step of forming the pattern including a dummy pattern so that a surface level of the resist does not become a predetermined value or less on the semiconductor substrate. Manufacturing method. It is a manufacturing method of the solid-state image sensing device according to claim 16,
The step of forming the pattern of the first layer conductive film includes the step of forming the pattern including a dummy pattern so that the surface level of the second layer conductive film does not become a predetermined value or less on the semiconductor substrate. A method for manufacturing a solid-state imaging device including:

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