JP2006013459A - Manufacturing method for solid-state image pickup element and the image pickup element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve charge transfer efficiency by preventing a film decrease due to a flattening process of a second layer conductive film and forming a charge transfer electrode of uniform film thickness when the charge transfer electrode of a single layer electrode structure is formed. <P>SOLUTION: The manufacturing method for a solid-state image pickup element includes a process for forming the pattern of a first layer conductive film constituting a first electrode on the surface of a semiconductor substrate where a gate oxide film is formed, a process for forming an insulating film becoming an inter-electrode insulating film at least on a side wall of the first electrode, a process for forming the second layer conductive film constituting a second electrode on the surface of the semiconductor substrate where the first electrode and the inter-electrode insulating film are formed, and a process for removing the second layer conductive film on the first electrode and flattening the film. The method also includes a process for forming a removal suppression layer on a part of an upper layer of the second layer conductive film prior to the flattening process. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device manufacturing method and a solid-state imaging device, and more particularly to a solid-state imaging device having a single-layer electrode CCD (charge coupled device) structure.

  A solid-state imaging device using a CCD used for an area sensor or the like includes a photoelectric conversion unit such as a photodiode and a charge transfer unit including a charge transfer electrode for transferring a signal charge from the photoelectric conversion unit. A plurality of charge transfer electrodes are arranged adjacent to each other on a charge transfer path formed on the semiconductor substrate, and are sequentially driven.

  In recent years, demands for higher resolution and higher sensitivity have been increasing in solid-state imaging devices, and the number of imaging pixels has been increasing to more than gigapixels. A substrate (silicon substrate) on which a solid-state image sensor is built is mounted by stacking filters and lenses. For this reason, the positional accuracy between the lens and the photoelectric conversion unit is important, and the distance, that is, the distance in the height direction, is a big problem in terms of positional accuracy in the manufacturing process and sensitivity (photoelectric conversion efficiency) in use. .

Furthermore, in such a situation, in order to obtain high resolution without increasing the chip size, it is necessary to reduce the area per unit pixel and achieve high integration. On the other hand, if the area of the photodiode constituting the photoelectric conversion unit is reduced, the sensitivity is lowered, so the area of the photodiode region must be ensured.
Therefore, various studies have been made to reduce the size of the chip while securing the area occupied by the photodiode region by reducing the wiring area ratio by reducing the wiring area of the charge transfer portion and the peripheral circuit. .

  In such a situation, maintaining the flatness of the interlayer insulating film between the wiring layers is an important technical issue in order to realize high integration by miniaturization of the wiring. In order to improve the flatness, a structure in which the charge transfer portion has a single-layer electrode structure has been proposed (for example, Patent Document 1).

  By the way, in a conventional solid-state imaging device using a charge transfer electrode having a single layer structure, a polycrystalline silicon or amorphous silicon layer is used as the charge transfer electrode, and after forming the first layer wiring, the pattern surface of the first layer wiring is formed. Is oxidized, a polycrystalline silicon layer or an amorphous silicon layer serving as a transfer electrode of the second layer is deposited, a resist is applied, and the entire surface is etched by a resist etch back method to form a single layer of the electrode. .

  8A to 8D, 9A to 9D, and FIGS. 10A to 10B are manufacturing process diagrams of a solid-state imaging device using a conventional charge transfer electrode having a single layer structure. Show. For example, in the conventional method, a silicon oxide film 2 a having a thickness of 15 to 35 nm, a silicon nitride film 2 b having a thickness of 50 nm, and a silicon oxide film 2 c having a thickness of 10 nm are formed on the surface of the n-type silicon substrate 1. A layered gate oxide film 2 is formed.

Subsequently, a first layer doped amorphous silicon film 3a is formed on the gate oxide film 2, and a silicon oxide film 4 and a silicon nitride film 5 are formed.
Subsequently, a resist is applied to the upper layer.

  Then, as shown in FIG. 8A, exposure is performed using a desired mask by photolithography, development and water washing are performed to form a resist pattern R1 having a pattern width of 0.3 to several μm. Here, the pattern width may be 0.3 μm or less.

Thereafter, as shown in FIG. 8B, the silicon oxide film 4 and the silicon nitride film 5 are etched using the resist pattern R1 as a mask to form a mask pattern for patterning the first electrode.
Then, the resist pattern is peeled and removed by ashing (FIG. 8C), and the first layer doped amorphous silicon film 3a is selectively used by using the mask pattern as a mask and the silicon nitride film 2b of the gate oxide film 2 as an etching stopper. Etching is removed to form a first electrode (FIG. 8D).

Subsequently, an interelectrode insulating film 6 is formed on the surface of the first electrode pattern by thermal oxidation (FIG. 9A), and a second-layer doped amorphous silicon film 3b is formed thereon (FIG. 9). (B)).
Thereafter, a resist R2 is applied to the entire surface (FIG. 9C), and the second-layer doped amorphous silicon film 3b is planarized by resist etchback (FIG. 9D).

Then, as shown in FIG. 10A, a desired resist pattern R3 is covered.
Thereafter, using the resist pattern R2 as a mask, the second layer doped amorphous silicon film 3b on the photodiode region 30 is selectively removed by etching.

Then, as shown in FIG. 10B, the resist pattern R2 is removed by ashing.
In this way, the second electrode composed of the second layer doped amorphous silicon film 3b is formed, and a solid-state imaging device electrode having a flat surface is formed.

  In this method, when a charge transfer electrode having a single layer structure is manufactured by etching back the second layer doped amorphous silicon film, a resist is applied to the upper layer of the second layer polycrystalline silicon film 3b by spin coating. And the second layer-doped amorphous silicon film are etched so that the etching rates are approximately the same, and the surface is flattened.

However, when the region where the density of the first layer doped amorphous silicon film is small is at the peripheral portion of the wafer, when the resist is formed by spin coating, as shown in FIG. As a result, as shown in FIG. 10B, the second-layer doped amorphous silicon film may be reduced at the peripheral edge of the wafer.
In addition, not only in the peripheral portion, but in a region where the density of the first layer doped amorphous silicon film is low, a thin region of resist may be formed between patterns. In such a case, there is a problem that the wiring resistance varies.

Further, not only in resist etch-back, but also in the case where planarization is performed by chemical mechanical polishing (CMP), the thickness of the second layer doped amorphous silicon film (second layer conductive film) is also similar. Variation may occur.

  Such variations in film thickness cause variations in wiring resistance and deterioration in transfer efficiency. In addition, the film thickness of various films such as the flattening film, microlens, and color filter above the charge transfer electrode may become non-uniform and increase in shape variation, resulting in shading, sensitivity variation, and deterioration of smear due to stray light. There is also a problem that occurs.

  For this reason, it has been difficult for the method as described above to cope with further improvement in sensitivity.

JP 11-26743 A

  As described above, in the conventional solid-state imaging device, when the charge transfer electrode having the single-layer electrode structure is formed, when the second-layer conductive film is planarized, the film is reduced in the resist etchback process or the CMP process, and the second There has been a problem that the film thickness of the layer-doped amorphous silicon film becomes small.

  The present invention has been made in view of the above circumstances, and a second layer conductive film is formed on the pattern of the first layer conductive film, and the second layer conductive film on the first layer conductive film is removed. When forming a charge transfer electrode having a single-layer electrode structure by flattening, it is possible to prevent film loss due to the flattening step of the second conductive film and to form a charge transfer electrode having a uniform film thickness. The purpose is to improve the charge transfer efficiency.

  Therefore, in the solid-state imaging device manufacturing method of the present invention, a solid-state imaging device including a photoelectric conversion unit and a charge transfer unit including a charge transfer electrode having a single-layer electrode structure that transfers a charge generated in the photoelectric conversion unit. In the device manufacturing method, a step of forming a pattern of a first layer conductive film constituting the first electrode on the surface of the semiconductor substrate on which the gate oxide film is formed, and between the electrodes on at least the side wall of the first electrode Forming an insulating film to be an insulating film; forming a second-layer conductive film constituting a second electrode on the surface of the semiconductor substrate on which the first electrode and the interelectrode insulating film are formed; Removing at least the second layer conductive film on the first electrode and flattening, and removing the second layer conductive film to a part of the upper layer of the second layer conductive film prior to the flattening process. Forming a suppression layer.

  According to such a configuration, by forming the removal suppression layer in the region where etching is desired to be suppressed on the second layer silicon-based conductive film, it is possible to prevent the surface level from being lowered even at the peripheral portion. It is possible to prevent a reduction in the thickness of the silicon-based conductive film, particularly the second-layer silicon-based conductive film, which is generated when the charge transfer electrode is formed into a single layer, and a charge transfer electrode having a uniform thickness can be formed. . Therefore, variation in element characteristics can be prevented and a highly reliable solid-state imaging element can be formed. In addition, when spin-coating a resist, the resist surface level is likely to decrease at the peripheral portion of the wafer, but a removal suppression layer is formed in a region where the resist surface level is also likely to decrease in regions other than the peripheral portion. Overetching can be prevented.

In the method for manufacturing a solid-state imaging device according to the present invention, the step of forming the removal suppressing layer includes a step of patterning by isotropic etching.
By forming the removal inhibiting layer by isotropic etching, a desired removal inhibiting layer pattern can be formed without overetching the horizontal portion.

  In the method for manufacturing a solid-state imaging device according to the present invention, the step of forming the removal suppressing layer includes a step of selectively leaving the removal suppressing layer only at the peripheral edge of the semiconductor substrate.

  In the method for manufacturing a solid-state imaging device of the present invention, the planarization step includes a CMP step.

In the solid-state imaging device manufacturing method of the present invention, the flattening step includes a step of applying a resist on the second layer conductive film, and an etching rate of the resist and the second layer conductive film is substantially the same. And a resist etch back step of etching under equal conditions.
According to this configuration, since the removal suppressing layer is added, the etching is suppressed by the removal suppressing layer even when the surface level of the photoresist is lowered at the periphery of the wafer, and the second layer silicon-based conductive film is formed. Reduction can be prevented.

Further, the method for manufacturing a solid-state imaging device of the present invention includes a step of removing the removal suppression layer after the planarization step.
By removing the removal suppression layer, it is possible to prevent subsequent processes or device characteristics from being affected.

In the method for manufacturing a solid-state imaging device of the present invention, the removal suppressing layer is made of an insulating material.
In this case, it may be left as it is without being removed.

In the method for manufacturing a solid-state imaging device of the present invention, the removal suppression layer is made of a conductive material.
In this case, it may be left without being removed, and an increase in the specific resistance of the second layer conductive film can be prevented.

In the method of the present invention, a trench is formed in a field oxide film formation region provided in a peripheral circuit portion and the charge transfer portion so as to surround an effective imaging region of the photoelectric conversion portion on a semiconductor substrate surface. A step of forming a field oxide film in the trench, a step of flattening the surface of the semiconductor substrate on which the field oxide film is formed, the charge transfer electrode, the photoelectric conversion unit, and the semiconductor substrate surface And a step of forming an element portion such as the peripheral circuit portion.
By this method, the surface can be easily flattened. In this case, if the trench depth and the field oxide film can be formed so as to coincide with each other, the planarization process may not be particularly necessary.

In the solid-state imaging device manufacturing method of the present invention, the step of forming the field oxide film includes a selective oxidation (LOCOS) step.
According to this method, it is possible to form a field oxide film having a good film quality although it takes a long time.

In the solid-state imaging device manufacturing method of the present invention, the step of forming the field oxide film includes a step of filling the trench with an insulating film by a CVD method.
According to this method, the time required for forming the field oxide film can be shortened. It should be noted that LOCOS and CVD may be used in combination, and a plurality of methods may be used in the same substrate surface, such as LOCOS in the vicinity of an amplifier unit that emphasizes element isolation and CVD in a portion that emphasizes flatness.

  Further, in the method for producing a solid-state imaging device of the present invention, the step of flattening the surface of the semiconductor substrate includes a step of applying a resist to the surface of the semiconductor substrate by a spin coat method and a step of flattening by a resist etch back method. Including those containing.

  In the solid-state imaging device manufacturing method of the present invention, the step of planarizing the surface of the semiconductor substrate includes a step of planarizing the surface of the semiconductor substrate by a CMP (Chemical Mechanical Polishing) method.

  Further, in the method of manufacturing a solid-state imaging device according to the present invention, the step of forming the pattern of the first layer conductive film may be performed so that a surface level of the resist does not become a predetermined value or less on the semiconductor substrate. Including the step of forming the pattern including:

  In the solid-state imaging device manufacturing method of the present invention, in the step of forming the pattern of the first layer conductive film, the surface level of the second layer conductive film does not fall below a predetermined value on the semiconductor substrate. Thus, the process of forming the said pattern containing a dummy pattern is included.

  In areas with low pattern density, such as areas other than the wiring and photodiode areas on the semiconductor substrate, especially in the wafer periphery, the resist film thickness tends to decrease and the surface level tends to decrease. In this configuration, dummy patterns are added. Therefore, it is possible to prevent the surface level from being lowered even at the peripheral portion prior to resist etch back, thereby preventing the conductive film, particularly the second-layer conductive film, from being reduced when the charge transfer electrode is formed as a single layer. can do. Therefore, since charge transfer electrodes and peripheral circuits with a uniform film thickness can be formed, variations in device characteristics can be prevented, and a highly reliable solid-state imaging device can be formed. When spin-coating a resist, the surface level of the resist is likely to decrease at the peripheral edge of the wafer, but the surface level of the resist should be increased by a dummy pattern in an area where the resist surface level is likely to decrease even in areas other than the peripheral edge. It is desirable to make it.

  The solid-state imaging device manufacturing method of the present invention includes a step of forming a stopper layer serving as a CMP stopper on the surface of the first electrode prior to the step of forming the second layer conductive film, The forming step includes a step of performing CMP using the stopper layer as a stopper.

  With this configuration, CMP can be stopped on the first electrode without the first electrode being scraped, so that a charge transfer portion with good flatness and high yield can be formed. Here, when the second-layer conductive film is composed of a silicon-based conductive film, it is desirable to use silicon nitride or the like. Also, when patterning the first electrode, a two-layer film of silicon oxide and silicon nitride is used as a mask, and this is used as it is for a CMP stopper, thereby enabling good patterning without increasing the number of steps. At the same time, it is possible to form a charge transfer portion having excellent flatness.

In the solid-state imaging device of the present invention, a photoelectric conversion unit, a charge transfer unit including a charge transfer electrode that transfers charges generated in the photoelectric conversion unit, and a peripheral circuit unit connected to the charge transfer unit, In the solid-state imaging device, the charge transfer electrode is a second layer formed through a first electrode made of a first layer conductive film and an interelectrode insulating film covering a side wall of the first electrode. It has a single layer electrode structure with a second electrode made of a conductive film, and at least a part of the surface of the second electrode or the peripheral circuit portion is made of a material different from that of the second layer conductive film. It is covered.
With this configuration, since the second layer conductive film is coated with a different material, it can act as an etching stopper in the etch back or CMP process when manufacturing the solid-state imaging device.

The solid-state imaging device of the present invention includes one in which the entire surface located at the peripheral edge of the substrate in the peripheral circuit portion is coated with a material different from that of the second layer conductive film.
With this configuration, in addition to the above effects, it can be used as a pad during mounting.

  In the solid-state imaging device of the present invention, the surface level of the field oxide film provided in the peripheral circuit unit and the charge transfer unit so as to surround the effective imaging region of the photoelectric conversion unit is the surface level of the photoelectric conversion unit. Includes those that are comparable.

According to this configuration, the surface level of the field oxide film provided in the peripheral circuit unit and the charge transfer unit so as to surround the effective imaging region of the photoelectric conversion unit is approximately the same as the surface level of the photoelectric conversion unit. Therefore, when the element region is formed, the entire substrate surface is flat, and the pattern accuracy by photolithography is greatly improved, which is effective not only in the case of a two-layer electrode structure but also in a single-layer electrode structure.
Further, since the surface level is flat, it is possible to prevent the conductive film, particularly the second-layer conductive film, from being reduced when the charge transfer electrode is formed into a single layer. Therefore, since charge transfer electrodes and peripheral circuits with a uniform film thickness can be formed, variations in device characteristics can be prevented, and a highly reliable solid-state imaging device can be formed. When spin-coating a resist, the surface level of the resist is likely to decrease at the peripheral edge of the wafer, but the surface level of the resist should be increased by a dummy pattern in an area where the resist surface level is likely to decrease even in areas other than the peripheral edge. It is desirable to make it.
Here, the effective imaging region includes a photoelectric conversion unit and a charge transfer unit.
Note that the surface level of the photoelectric conversion unit and the gate transfer of the charge transfer unit and the peripheral circuit unit for forming the charge transfer electrode during the planarization process such as the CMP (Chemical Mechanical Polishing) process or the etch back process of the second layer conductive film. It is desirable that the upper surface level of the film be approximately the same, and it is sufficient that at least the surface level of the substrate in the region where the photoelectric conversion portion is formed and the surface level of the field insulating film are approximately the same.

  According to the method of the present invention, when a planarization is performed by a resist etch back method or a CMP method, and a charge transfer electrode having a single-layer electrode structure is formed, a removal suppression layer is formed in a region where film reduction is likely to occur. A solid-state image sensor with good charge transfer efficiency that can prevent the second layer silicon conductive film from being reduced due to surface level variations caused by the presence or absence of the underlying pattern, or from excessive etching, etc. It becomes possible to form.

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)

  As shown in FIGS. 1 to 4, the solid-state imaging device is formed by a planarization process using resist etch back when forming a solid-state imaging device having a charge transfer electrode having a single-layer electrode structure. Prior to forming the second electrode and the wiring composed of the second layer amorphous silicon, the second layer conductive film is removed so as to suppress the etching removal of the second layer conductive film on a part of the upper layer of the second layer conductive film. Forming a suppression layer (hereinafter referred to as an etching suppression layer). This etching suppression layer is formed on a part of the region on the second layer conductive film that is not opposed to the first electrode.

  As a result, the second electrode and the wiring composed of the second layer amorphous silicon by the planarization process by resist etch back also reduce the film in the region where the surface level of the resist is low, such as in the peripheral portion. There is nothing. Therefore, the surface of the charge transfer portion and the peripheral circuit portion can be satisfactorily flattened without reducing the film thickness.

  As shown in FIG. 5 and FIG. 6 as an overall schematic explanatory diagram (the peripheral portion is not shown in this figure), a photodiode region 30 including a plurality of photodiodes is formed on the silicon substrate 1, A charge transfer unit 40 for transferring signal charges detected by the photodiode is formed between the photodiode regions 30. 6 is a cross-sectional view taken along the line AA in FIG.

  Although not shown in FIG. 5, the charge transfer channel 31 through which the signal charge transferred by the charge transfer electrode moves is formed in a direction crossing the direction in which the charge transfer unit 40 extends.

  In FIG. 5, the description of the interelectrode insulating film 6 formed near the boundary between the photoelectric conversion unit including the photodiode region 30 and the charge transfer unit 40 is omitted.

  As shown in FIG. 6, a photodiode region 30, a charge transfer channel 33, a channel stop region 32, and a charge readout region 34 are formed in the silicon substrate 1, and a gate oxide film 2 is formed on the surface of the silicon substrate 1. Is done. On the surface of the gate oxide film 2, an interelectrode insulating film 6 made of a silicon oxide film and a charge transfer electrode 3 (a first electrode made of a first layer doped amorphous silicon film 3a, a second layer doped amorphous silicon film 3b) Second electrode) is formed.

  Although the charge transfer unit 40 is as described above, an intermediate layer 70 is formed on the upper surface of the charge transfer electrode of the charge transfer unit 40 as shown in FIG. 71 is a light shielding film, 72 is an insulating film made of BPSG (borophospho silicate glass), 73 is an insulating film (passivation film) made of P-SiN, and 74 is a flattening layer made of a transparent resin film.

Above the solid-state imaging device, a light shielding film 71 is provided except for the photodiode region 30, and a color filter 50 and a microlens 60 are further provided. Further, a flattening layer 61 made of an insulating transparent resin or the like is filled between the color filter 50 and the microlens 60.
FIG. 5 shows a so-called honeycomb-structured solid-state image pickup device, but it goes without saying that the present invention can also be applied to a square lattice type solid-state image pickup device.

Next, the manufacturing process of this solid-state image sensor will be described in detail.
First, a silicon oxide film 2a having a film thickness of 15 to 35 nm, a silicon nitride film 2b having a film thickness of 50 nm, and a film having a film thickness of 10 nm are formed on the surface of an n-type silicon substrate 1 having an impurity concentration of about 1.0 × 10 ¹⁶ cm ⁻³ . A silicon oxide film 2c is formed, and a gate oxide film 2 having a three-layer structure is formed.

Subsequently, a phosphorous-doped first layer doped amorphous silicon film 3a having a thickness of 0.4 μm is formed on the gate oxide film 2 by a low pressure CVD method using SiH ₄ added with PH ₃ and He as a reactive gas. Form. The substrate temperature at this time shall be 600-700 degreeC.

  Thereafter, a silicon oxide film 4 having a thickness of 15 nm and a silicon nitride film 5 having a thickness of 50 nm are formed by low pressure CVD.

  Subsequently, a positive resist is applied to the upper layer so as to have a thickness of 0.5 to 1.4 μm, exposed by photolithography using a desired mask, developed, and washed with water to form a resist pattern R1. (FIG. 1 (a)).

Thereafter, the silicon oxide film 4 and the silicon nitride film 5 are etched by reactive ion etching using a mixed gas of CHF ₃ , C ₂ F ₆ , O ₂ and He (FIG. 1B), A mask pattern for patterning the first layer doped amorphous silicon film 3a is formed.
Then, the resist pattern is removed by ashing (FIG. 1C).

Thereafter, the first layer doped amorphous silicon film 3a is selected by reactive ion etching using a mixed gas of HBr and O ₂ with the mask pattern as a mask and the silicon nitride film 2b of the gate oxide film 2 as an etching stopper. Etching is performed to form wirings for the first electrode and the peripheral circuit (FIG. 1D). Here, it is desirable to use an etching apparatus such as an ECR (Electron Cyclotoron Resonance) system or an ICP (Inductively Coupled Plasma) system.

  Subsequently, an interelectrode insulating film 6 made of a silicon oxide film having a thickness of 80 nm is formed on the side surface of the first electrode pattern by thermal oxidation (FIG. 2A).

Next, a second layer doped amorphous silicon film 3b having a film thickness of 0.4 to 0.7 μm is formed by a low pressure CVD method using a reactive gas obtained by adding PH ₃ and He to SiH ₄ gas (FIG. 2). (B)). At this time, the thickness of the second layer doped amorphous silicon film 3b is equal to or more than the total thickness of the first layer doped amorphous silicon film and the silicon oxide film 4 and the silicon nitride film 5 thereabove. It needs to be formed to be thick.

Thereafter, a silicon oxide film as the etching suppression layer 7 is formed to a film thickness of 150 nm by a low pressure CVD method. Here, a mixed gas of SiH ₄ (50 sccm) and N ₂ (2500 sccm) was used as the reactive gas, the pressure was 1.2 Torr, and the substrate temperature was 750 ° C.

  Next, as shown in FIG. 2C, a resist pattern R2 for patterning the etching suppression layer 7 is formed.

  Then, as shown in FIG. 2D, isotropic etching is performed using the resist pattern R2 as a mask, and the etching suppression layer 7 is patterned.

  Further, a resist R3 is applied on the second layer doped amorphous silicon film 3b on which the pattern of the etching suppression layer 7 is formed so that the surface level becomes completely flat (FIG. 3A). Here, as the resist R3, OFPR800 was used and applied so as to have a film thickness of 700 to 800 nm.

  Subsequently, as shown in FIG. 3B, the entire surface is etched under the condition that the etching rates of the resist and the second layer doped amorphous silicon film 3b are almost the same, and the second layer doped amorphous silicon film 3b is etched. Perform flattening. Since the etching suppression layer 7 is formed here, the second layer doped amorphous silicon film 3b having a desired surface level is obtained without causing film reduction even when the resist surface level is low at the peripheral edge of the substrate. be able to.

  Thereafter, as shown in FIG. 3C, the element formation portion is covered with a resist pattern R4, and the etching suppression layer 7 made of a silicon oxide film is removed by etching using the resist pattern R4 as a mask.

  In this way, as shown in FIG. 4A, the second layer doped amorphous silicon film 3b having a desired surface level can be obtained without film loss.

  Thereafter, as shown in FIG. 4B, a resist pattern R5 for forming a peripheral circuit is formed. Here, the resist pattern R5 is formed so as to cover a part of the solid-state imaging element forming portion and the peripheral circuit portion.

Then, as shown in FIG. 4C, by using this resist pattern R5 as a mask, the second layer doped amorphous silicon film 3b on the photodiode region 30 is removed by etching and the peripheral circuit pattern 3S is left.
Then, by removing the resist by ashing, the second-layer doped amorphous silicon film 3b is formed so as to cover a part of the solid-state imaging element forming portion and the peripheral circuit portion.

  In this way, the second electrode composed of the second layer doped amorphous silicon film 3b is formed, and a charge transfer electrode having a flat surface is formed.

Then, a light-shielding film pattern 71 and a BPSG film 72 having a thickness of 700 nm are formed on this upper layer and reflowed at 850 ° C. to be flattened. Then, an insulating film (passivation film) 73 made of P-SiN and a planarization layer 74 made of a transparent resin film are formed.
Thereafter, the color filter 50, the flattening layer 61, the microlens 60, and the like are formed to obtain a solid-state imaging device as shown in FIGS.

  According to this method, since the etching suppression layer 7 made of a silicon nitride film is formed outside the peripheral edge portion of the substrate, that is, the peripheral circuit portion, the film loss is suppressed and the resist surface level for etch back is lowered. Even in such a case, it is possible to realize highly accurate pattern formation without reducing the film thickness at the periphery, and to obtain functionally and highly reliable operation characteristics.

  As described above, according to this configuration, the pattern density of the first electrode, such as the peripheral edge of the substrate, is small, particularly where the resist surface level is low when applying the resist by spin coating, such as the peripheral edge of the substrate. For example, a flat second electrode and a peripheral circuit can be formed by forming a pattern of the etching suppression layer. Therefore, it is possible to form a solid-state imaging device with no characteristic variation and high reliability.

  Note that the etching suppression layer is not limited to silicon oxide, and a laminated film with another insulating film such as a silicon nitride film may be used. The etching suppression layer is removed by etching, but may be left without being removed by etching. In this case, at least a part of the surface of the second electrode or the peripheral circuit portion is covered with a material different from that of the second layer conductive film.

Example 1
Conventional methods were used for the other steps, and the following conditions were used for the formation and patterning of the etching suppression layer 7. That is, a silicon oxide film as the etching suppression layer 7 is formed to have a film thickness of 10 to 30 nm by a low pressure CVD method (FIG. 2B). Here, a mixed gas of SiH ₄ (50 sccm) and N ₂ (2500 sccm) was used as the reactive gas, the pressure was 1.2 Torr, and the substrate temperature was 750 ° C.

  Then, as shown in FIG. 2C, a resist pattern R2 for patterning the etching suppression layer 7 is formed.

  Then, as shown in FIG. 2D, isotropic etching is performed using the resist pattern R2 as a mask, and the etching suppression layer 7 is patterned. As etching conditions at this time, dilute HF wet etching was used.

  According to this method, since the etching suppression layer 7 made of a silicon oxide film is formed outside the peripheral edge of the substrate, even if the film level is suppressed and the surface level of the resist for etch back is lowered, High-precision pattern formation without film loss at the peripheral edge can be realized, and functionally reliable operation characteristics can be obtained.

(Example 2)
Conventional methods were used for the other steps, and the following conditions were used for the formation and patterning of the etching suppression layer 7. That is, a silicon nitride film as the etching suppression layer 7 is formed to a thickness of 150 nm by low pressure CVD (FIG. 2B). Here, as reactive gases, SiH ₂ Cl ₂ (90 sccm) and NH ₃ (900 scc)
m), a pressure of 0.5 Torr, and a substrate temperature of 780 ° C. were used.

  Then, as shown in FIG. 2C, a resist pattern R2 for patterning the etching suppression layer 7 is formed.

Then, as shown in FIG. 2D, anisotropic etching is performed using the resist pattern R2 as a mask, and the etching suppression layer 7 is patterned. Etching conditions at this time are a mixed gas of CHF ₃ (33 sccm), C ₂ F ₆ (13 sccm), 0 ₂ (7.5 sccm), and He (40 sccm), pressure 1550 mTorr, power 700 W, substrate temperature 30 ° C. did.

  According to this method, since the etching suppression layer 7 made of a silicon nitride film is formed outside the peripheral edge of the substrate, even if the surface level of the resist for etching back is reduced by suppressing film loss, High-precision pattern formation without film loss at the peripheral edge can be realized, and functionally reliable operation characteristics can be obtained.

(Comparative Example 1)
The other steps were formed in the same manner as in Examples 1 and 2 except that the usual method was used and the etching suppression layer 7 was not formed.

  As a result, in Examples 1 and 2, the first and second electrodes and the difference in film thickness from the substrate surface in the peripheral circuit portion can be realized as 0 μm as compared with the conventional 0.2 μm, and good flatness can be realized. Significantly good characteristics could be obtained.

In the first and second embodiments, the case where planarization is performed by etch back has been described. However, it goes without saying that the present invention can also be applied to the case where planarization is performed by CMP.
(Second Embodiment)

In the solid-state imaging device of the present embodiment, the surface level of the field oxide film provided in the peripheral circuit unit and the charge transfer unit is set to be approximately the same as the surface level of the photoelectric conversion unit, and the element region is formed. The entire surface of the substrate is flattened and the pattern accuracy by photolithography is improved, and the conductive film generated when the charge transfer electrode is made into a single layer, particularly the second layer conductive film is reduced. The charge transfer electrode and the peripheral circuit having a uniform film thickness can be formed. That is, as shown in FIGS. 7A and 7B, a photoelectric transfer unit, a charge transfer unit including a charge transfer electrode that transfers charges generated in the photoelectric conversion unit, and the charge transfer unit The surface of the field oxide film 10 formed in a frame shape so as to surround the effective imaging region (light receiving region) A in the solid-state imaging device including the peripheral circuit unit including the output circuit to be connected is provided with a photosensor. It is formed by a recess LOCOS method so as to be the same as the surface level of the photoelectric conversion part and the charge transfer part. Here, FIG. 7A is a schematic diagram showing a solid-state imaging device chip. Here, the effective imaging region includes a light receiving region including a photoelectric conversion unit and a vertical transfer path (a part of a charge transfer unit) and a horizontal transfer path ( A part of the charge transfer unit) is formed, and an output circuit as a peripheral circuit O is formed outside thereof. Here, p is a pad provided on the periphery of the solid-state imaging device chip. The peripheral circuit portion including the output circuit corresponds to the non-imaging region B.
7A and 7B, the silicon substrate 1 is formed with a plurality of photodiode regions constituting a photoelectric conversion unit, and transfers signal charges detected by the photodiodes. A charge transfer section for forming the same is formed between the photodiode regions. Here, FIG. 7B is a cross section obtained by cutting along the line AA in FIG.
The portions other than the field insulating film are formed in the same manner as the usual solid-state imaging device shown in the first embodiment.

  That is, as shown in FIGS. 7A and 7B, the field oxide film 10 is formed in the trench T formed on the surface of the substrate 1, and the surface level of the substrate 1 and the surface level of the field oxide film 10 are Are formed to be the same.

  A field oxide film 10 is formed by selective oxidation in the trench T formed on the surface of the silicon substrate 1, and the CMP process is performed so that the level difference at the interface between the non-imaging region B and the effective imaging region A becomes zero. Has been made. A photoelectric conversion unit including a photodiode is formed in the silicon substrate 1, and a photoelectric current generated by the photodiode is read out through the charge transfer unit.

  Here, a silicon oxide film as a field oxide film 10 having a thickness of 600 nm is formed by selective oxidation in a trench T having a depth of about 600 nm formed in the non-imaging region of the silicon substrate 1 and the element isolation region of the charge transfer portion. Has been. On the field oxide film 10, a horizontal transfer register for transferring signal charges in the horizontal direction, a signal processing circuit, and a wiring 7 are formed.

According to such a configuration, as shown in FIGS. 7A and 7B, since a pattern is formed on a flat surface, it is possible to form a pattern with extremely high accuracy, and an extremely fine charge transfer portion can be formed. Formation is possible. Further, the wiring 3S including the peripheral circuit portion can be miniaturized.
In the above embodiment, the field oxide film 10 is formed by selective oxidation in the trench T formed on the surface of the silicon substrate 1, but a silicon oxide film or the like may be filled in the trench.

  As described above, according to the method of the present invention, when a charge transfer electrode having a single-layer electrode structure is formed by planarizing the second-layer conductive film by etch-back, film loss occurs prior to etch-back. The pattern of the etching suppression layer is formed in an easy area to prevent the film from being reduced. Therefore, it is possible to reduce the characteristic variation and obtain a highly reliable charge transfer electrode. It is effective for forming a solid-state imaging device with sensitivity.

It is a figure which shows the manufacturing process of the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the solid-state image sensor of the 1st Embodiment of this invention. It is sectional drawing which shows the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the solid-state image sensor of the 2nd Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of a prior art example. It is a figure which shows the manufacturing process of the solid-state image sensor of a prior art example. It is a figure which shows the manufacturing process of the solid-state image sensor of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Gate oxide film 3a 1st electrode (1st layer doped amorphous silicon film)
3b Second electrode (second layer doped amorphous silicon film)
3 Charge Transfer Electrode 4 Silicon Oxide Film 5 Silicon Nitride Film 6 Interelectrode Insulating Film 7 Etching Suppression Layer 30 Photodiode Region 40 Charge Transfer Part 50 Color Filter 60 Micro Lens 70 Intermediate Layer

Claims (18)

In a method for manufacturing a solid-state imaging device, comprising: a photoelectric conversion unit; and a charge transfer unit including a charge transfer electrode having a single-layer electrode structure that transfers charges generated in the photoelectric conversion unit.
Forming a pattern of a first layer conductive film constituting the first electrode on the surface of the semiconductor substrate on which the gate oxide film is formed;
Forming an insulating film to be an interelectrode insulating film on at least the side wall of the first electrode;
Forming a second layer conductive film constituting a second electrode on the surface of the semiconductor substrate on which the first electrode and the interelectrode insulating film are formed;
And a step of removing at least the second layer conductive film on the first electrode and flattening the surface of the semiconductor substrate on which the second conductive film is formed. And
Prior to the planarization step, a solid-state imaging device including a step of forming a removal suppression layer that suppresses removal of the second layer conductive film on a part of the upper layer of the second layer conductive film. Method. It is a manufacturing method of the solid-state image sensing device according to claim 1,
The step of forming the removal suppressing layer includes a step of patterning by isotropic etching. It is a manufacturing method of the solid-state image sensing device according to claim 1,
The step of forming the removal suppression layer includes a step of selectively leaving the removal suppression layer only at a peripheral portion of the semiconductor substrate. It is a manufacturing method of the solid-state image sensing device according to any one of claims 1 to 3,
The method of manufacturing a solid-state imaging device, wherein the planarizing step is a CMP step. It is a manufacturing method of the solid-state image sensing device according to any one of claims 1 to 3,
The planarizing step includes a step of applying a resist on the second-layer conductive film, and a resist etch-back step of etching under conditions where etching rates of the resist and the second-layer conductive film are substantially equal. A method for manufacturing a solid-state imaging device. A method for manufacturing a solid-state imaging device according to any one of claims 1 to 5,
A method of manufacturing a solid-state imaging device, comprising a step of removing the removal suppression layer after the planarization step. A method for manufacturing a solid-state imaging device according to any one of claims 1 to 6,
The method for manufacturing a solid-state imaging device, wherein the removal suppression layer is an insulating material. It is a manufacturing method of the solid-state image sensing device according to claim 1,
Prior to the formation of the charge transfer portion,
Forming a trench in a formation region of a field oxide film provided in a peripheral circuit portion and the charge transfer portion so as to surround an effective imaging region of the photoelectric conversion portion on a semiconductor substrate surface;
Forming a field oxide film in the trench;
Planarizing the semiconductor substrate surface on which the field oxide film is formed;
Forming a device portion such as the charge transfer electrode, the photoelectric conversion portion, and the peripheral circuit portion on the surface of the semiconductor substrate. It is a manufacturing method of the solid-state image sensing device according to claim 8,
The method of manufacturing a solid-state imaging device, wherein the step of forming the field oxide film includes a selective oxidation (LOCOS) step. It is a manufacturing method of the solid-state image sensing device according to claim 8,
The step of forming the field oxide film includes a step of filling the trench with an insulating film by a CVD method. It is a manufacturing method of the solid-state image sensing device according to any one of claims 8 to 10,
The step of planarizing the semiconductor substrate surface includes:
Applying a resist to the semiconductor substrate surface by spin coating;
And a flattening process using a resist etch-back method. It is a manufacturing method of the solid-state image sensing device according to any one of claims 8 to 10,
The step of planarizing the semiconductor substrate surface includes:
And a step of planarizing the surface of the semiconductor substrate by a CMP (Chemical Mechanical Polishing) method. It is a manufacturing method of the solid-state image sensing device according to claim 1,
The step of forming the pattern of the first layer conductive film includes a step of forming the pattern including a dummy pattern so that a surface level of the resist does not become a predetermined value or less on the semiconductor substrate. Manufacturing method. It is a manufacturing method of the solid-state image sensing device according to claim 1,
The step of forming the pattern of the first layer conductive film includes the step of forming the pattern including a dummy pattern so that the surface level of the second layer conductive film does not become a predetermined value or less on the semiconductor substrate. A method for manufacturing a solid-state imaging device including: It is a manufacturing method of the solid-state image sensing device according to claim 1,
Prior to the step of forming the second layer conductive film, including a step of forming a stopper layer serving as a CMP stopper on the surface of the first electrode,
The method of manufacturing a solid-state imaging device, wherein the planarization step is a step of performing CMP using the stopper layer as a stopper. In the solid-state imaging device comprising: a photoelectric conversion unit; a charge transfer unit including a charge transfer electrode that transfers charges generated in the photoelectric conversion unit; and a peripheral circuit unit connected to the charge transfer unit. The charge transfer electrode is a first electrode made of a first layer conductive film, and a second electrode made of a second layer conductive film formed via an interelectrode insulating film covering the side wall of the first electrode. And has a single-layer electrode structure,
A solid-state imaging device in which at least a part of the surface of the second electrode or the peripheral circuit portion is covered with a material different from that of the second layer conductive film. The solid-state imaging device according to claim 16,
A solid-state imaging device in which the entire surface located at the peripheral edge of the substrate in the peripheral circuit portion is covered with a material different from that of the second layer conductive film. The solid-state imaging device according to claim 16,
The surface level of the field oxide film provided in the peripheral circuit unit and the charge transfer unit so as to surround the effective imaging region of the photoelectric conversion unit is approximately the same as the surface level of the photoelectric conversion unit. Solid-state image sensor.

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