JP2006041483A - Manufacturing method of solid-state image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a variation in wiring resistance by preventing a decrease in film thickness in an active region during a planarization step and thus forming a wiring line having a uniform film-thickness in forming a charge transfer electrode having a single-layer electrode structure. <P>SOLUTION: A manufacturing method of a solid-state image pickup element includes a step of forming a first electrode, a photoelectric conversion section, and a pattern of a first-layer conductive film configuring the first-layer wiring of a peripheral circuit on the surface of a semiconductor substrate on which a gate oxidation film is formed; a step of forming an insulating film as an inter-electrode insulating film on at least the side face of the first electrode; a step of forming a second-layer conductive film configuring a second electrode on the semiconductor surface on which the first electrode and the inter-electrode insulating film are formed; a step of planarizing the surface by removing a projecting portion of the second-layer conductive film projecting on the first electrode; and a step of patterning the second-layer conductive film in the active region. In addition, the manufacturing method includes a step of forming a removal-inhibiting layer in the active region before the planarizing step. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a solid-state imaging device, and more particularly to a solid-state imaging device having a single-layer electrode CCD (charge coupled device) structure.

  A solid-state imaging device using a CCD used for an area sensor or the like includes a photoelectric conversion unit such as a photodiode and a charge transfer unit including a charge transfer electrode for transferring a signal charge from the photoelectric conversion unit. A plurality of charge transfer electrodes are arranged adjacent to each other on a charge transfer path formed on the semiconductor substrate, and are sequentially driven.

  In recent years, demands for higher resolution and higher sensitivity have been increasing in solid-state imaging devices, and the number of imaging pixels has been increasing to more than gigapixels. A substrate (silicon substrate) on which a solid-state image sensor is built is mounted by stacking filters and lenses. For this reason, the positional accuracy between the lens and the photoelectric conversion unit is important, and the distance, that is, the distance in the height direction, is a big problem in terms of positional accuracy in the manufacturing process and sensitivity (photoelectric conversion efficiency) in use. .

Furthermore, in such a situation, in order to obtain high resolution without increasing the chip size, it is necessary to reduce the area per unit pixel and achieve high integration. On the other hand, if the area of the photodiode constituting the photoelectric conversion unit is reduced, the sensitivity is lowered, so the area of the photodiode region must be ensured.
Therefore, various studies have been made to reduce the size of the chip while securing the area occupied by the photodiode region by reducing the wiring area ratio by reducing the wiring area of the charge transfer portion and the peripheral circuit. .

  Under these circumstances, maintaining the flatness of the interlayer insulating film between the wiring layers is an important technical issue in order to realize high integration by miniaturization of the wiring. In order to improve the flatness, a structure in which the charge transfer portion has a single-layer electrode structure has been proposed (for example, Patent Document 1).

  By the way, in a conventional solid-state imaging device using a charge transfer electrode having a single layer structure, a polycrystalline silicon or amorphous silicon layer is used as the charge transfer electrode, and after forming the first layer wiring, the pattern surface of the first layer wiring is formed. Is oxidized, and a polycrystalline silicon or amorphous silicon layer serving as a second transfer electrode is deposited and polished by CMP (Chemical Mechanical Polishing), or a resist is applied, and the entire surface is etched by resist etch back. The electrode is made into a single layer.

  For example, in the conventional method, a silicon oxide film 2a having a thickness of 15 to 35 nm, a silicon nitride film 2b having a thickness of 50 nm, and a silicon oxide film 2c having a thickness of 5 to 10 nm are formed on the surface of the n-type silicon substrate 1. A gate oxide film 2 having a three-layer structure is formed.

Subsequently, a first layer doped amorphous silicon film 3a is formed on the gate oxide film 2, and a silicon oxide film 4a and a silicon nitride film 4b are formed.
Subsequently, a resist is applied to the upper layer.

  Then, exposure is performed using a desired mask by photolithography, development and washing with water are performed to form a resist pattern having a pattern width of 0.3 to several μm (FIG. 8A). Here, the pattern width may be 0.3 μm or less.

Thereafter, using this resist pattern as a mask, the silicon oxide film 4a and the silicon nitride film 4b are etched to form a mask pattern for patterning the first electrode (FIG. 8B).
Then, the resist pattern is peeled and removed by ashing (FIG. 8C), and the first layer doped amorphous silicon film 3a is selectively used by using the mask pattern as a mask and the silicon nitride film 2b of the gate oxide film 2 as an etching stopper. Etching is removed to form a first electrode (FIG. 8D).

Subsequently, an interelectrode insulating film 5 is formed on the surface of the first electrode pattern by thermal oxidation (FIG. 8E), and a second-layer doped amorphous silicon film 3b is formed thereon (FIG. 9 (FIG. 9). f)).
After that, the second layer doped amorphous silicon film 3b is planarized by CMP (FIG. 9G). At this time, in order to suppress variation in the electrode film thickness due to CMP, dummy patterns that do not contribute to the operation of the solid-state imaging device are arranged. However, since the dummy patterns cannot be arranged in the active region, the second layer transfer electrode is formed by CMP. When flattening, so-called dishing is generated in which the active portion has a dish-like recess.

And as shown in FIG.9 (h), it coat | covers with the desired resist pattern R3.
Thereafter, using the resist pattern R3 as a mask, the second layer doped amorphous silicon film 3b on the photodiode region 30 constituting the photoelectric conversion portion is selectively removed by etching.

Then, as shown in FIG. 9I, the resist pattern R3 is removed by ashing.
In this way, the second electrode composed of the second layer doped amorphous silicon film 3b is formed, and a charge transfer electrode having a flat surface is formed.

  In the case of this method, the second layer doped amorphous silicon film is planarized by using the CMP method to be separated to manufacture a single layer structure charge transfer electrode. When resist etchback is used instead of the CMP method, a resist is applied to the upper layer of the second polycrystalline silicon film 3b by spin coating, and the etching rate between the resist and the second layer doped amorphous silicon film is increased. Etching is performed to achieve the same level, and the surface is planarized.

However, dummy patterns that do not contribute to the operation of the solid-state imaging device are arranged in order to suppress film thickness variations in the CMP and resist etch-back processes in this way, but it is difficult to arrange dummy patterns in the active region. is there. For this reason, the active region is formed without forming a dummy pattern, but dishing occurs when the second-layer doped amorphous silicon film is planarized, and variations in wiring resistance due to film thickness variations due to dishing. This causes a significant decrease in charge transfer efficiency.
In addition, in the region where the pattern density of the first electrode constituting the first layer on the semiconductor substrate is small, particularly in the peripheral portion of the semiconductor substrate (semiconductor chip), the film thickness of the second layer doped amorphous silicon film is reduced. was there.

JP-A-8-274302

  As described above, in the conventional solid-state imaging device, dishing occurs in an active region where a dummy pattern cannot be formed, resulting in variations in the film thickness of the wiring layer, which causes a decrease in charge transfer efficiency. .

  The present invention has been made in view of the above circumstances, and a second layer conductive film is formed on the pattern of the first layer conductive film, and the second layer conductive film on the first layer conductive film is removed. When the charge transfer electrode having a single-layer electrode structure is formed by flattening, the thinning due to the fact that the pattern of the first layer conductive film cannot be formed in the active region is prevented in the flattening step, and uniform An object is to improve charge transfer efficiency by forming a charge transfer electrode having a film thickness.

  Therefore, in the method for manufacturing a solid-state imaging device of the present invention, a photoelectric transfer unit, a charge transfer unit including a charge transfer electrode having a single-layer electrode structure that transfers charges generated in the photoelectric conversion unit, and the charge transfer unit In the method of manufacturing a solid-state imaging device including a peripheral circuit portion connected to a first substrate, a first electrode, the photoelectric conversion portion, and a first layer wiring of the peripheral circuit portion on a semiconductor substrate surface on which a gate oxide film is formed Forming a pattern of the first layer conductive film constituting the structure, forming an insulating film serving as an inter-electrode insulating film on at least a side wall of the first electrode, the first electrode and the inter-electrode insulation Forming a second layer conductive film constituting a second electrode on the surface of the semiconductor substrate on which the film is formed, and removing the protruding portion of the second layer conductive film protruding on the first electrode; The process of flattening the surface and the Removing a second layer conductive film in the active region prior to the planarization step, and a step of patterning the second layer conductive film in the active region. Forming.

  With this configuration, the removal suppression layer that suppresses the removal of the second layer conductive film is formed on the second layer conductive film in the active region where the pattern of the first layer conductive film cannot be formed. Thus, it is possible to suppress the decrease in the second layer conductive film and form the second layer electrode with little variation.

In the method for manufacturing a solid-state imaging device of the present invention, the step of forming the removal suppressing layer is performed after the step of forming the second layer conductive film.
According to this configuration, since the removal suppressing layer is formed on the second layer conductive film, the second layer conductive film can be formed without being interrupted, so that workability is good.

In the method of the present invention, the step of forming the second layer conductive film includes a step before forming the second layer conductive film having the same thickness as that of the first conductive film, and a step thereafter. And a post-process for forming the removal suppressing layer and further forming the second-layer conductive film.
According to this method, since the patterning can be performed on the surface having good flatness when forming the removal suppressing layer, the accuracy is further improved.

  In the method for manufacturing a solid-state imaging device of the present invention, the second layer conductive film includes a silicon-based conductive film.

  In the method for manufacturing a solid-state imaging device according to the present invention, the silicon conductive film includes doped amorphous silicon.

  In the method for manufacturing a solid-state imaging device according to the present invention, the silicon conductive film includes doped polysilicon.

  In the method for manufacturing a solid-state imaging device of the present invention, the step of forming the removal suppressing layer includes a step of forming a silicon oxide film and a step of forming a silicon nitride film on the silicon oxide film. Including.

  In the method for manufacturing a solid-state imaging device according to the present invention, the step of forming the removal suppressing layer includes a step of patterning by isotropic etching.

In the method for manufacturing a solid-state imaging device according to the present invention, the flattening step includes a step of applying a resist on the surface of the semiconductor substrate, and the etching rate of the resist and the second layer conductive film is comparable. And a process of etching back under conditions.
According to this method, it is possible to suppress the film loss due to the presence of the removal suppression layer and to obtain a wiring with little variation.
Further, in the peripheral circuit portion of the solid-state imaging device on the semiconductor substrate, in the region where the pattern density is low, particularly in the peripheral portion of the semiconductor substrate (semiconductor chip), the film thickness of the resist is small and the surface level tends to be reduced. In addition to the resist etchback, the surface level can be prevented from being lowered even at the peripheral portion, so that the silicon-based conductive film generated when the charge transfer electrode is formed into a single layer, particularly the second-layer silicon-based conductive layer. It is possible to prevent film loss. Accordingly, a wiring portion having a more uniform film thickness can be formed.

In the method of the present invention, a trench is formed in a field oxide film formation region provided in a peripheral circuit portion and the charge transfer portion so as to surround an effective imaging region of the photoelectric conversion portion on a semiconductor substrate surface. A step of forming a field oxide film in the trench, a step of flattening the surface of the semiconductor substrate on which the field oxide film is formed, the charge transfer electrode, the photoelectric conversion unit, and the semiconductor substrate surface And a step of forming an element portion such as the peripheral circuit portion.
By this method, the surface can be easily flattened. In this case, if the trench depth and the field oxide film can be formed so as to coincide with each other, the planarization process may not be particularly necessary.

In the solid-state imaging device manufacturing method of the present invention, the step of forming the field oxide film includes a selective oxidation (LOCOS) step.
According to this method, it is possible to form a field oxide film having a good film quality although it takes a long time.

In the solid-state imaging device manufacturing method of the present invention, the step of forming the field oxide film includes a step of filling the trench with an insulating film by a CVD method.
According to this method, the time required for forming the field oxide film can be shortened. It should be noted that LOCOS and CVD may be used in combination, and a plurality of methods may be used in the same substrate surface, such as LOCOS in the vicinity of an amplifier unit that emphasizes element isolation and CVD in a portion that emphasizes flatness.

  Further, in the method for producing a solid-state imaging device of the present invention, the step of flattening the surface of the semiconductor substrate includes a step of applying a resist to the surface of the semiconductor substrate by a spin coat method and a step of flattening by a resist etch back method. Including those containing.

  In the solid-state imaging device manufacturing method of the present invention, the step of planarizing the surface of the semiconductor substrate includes a step of planarizing the surface of the semiconductor substrate by a CMP (Chemical Mechanical Polishing) method.

  Further, in the method of manufacturing a solid-state imaging device according to the present invention, the step of forming the pattern of the first layer conductive film may be performed so that a surface level of the resist does not become a predetermined value or less on the semiconductor substrate. Including the step of forming the pattern including:

  In the solid-state imaging device manufacturing method of the present invention, in the step of forming the pattern of the first layer conductive film, the surface level of the second layer conductive film does not fall below a predetermined value on the semiconductor substrate. Thus, the process of forming the said pattern containing a dummy pattern is included.

  The solid-state imaging device manufacturing method of the present invention includes a step of forming a stopper layer serving as an etching stopper on the surface of the first electrode prior to the step of forming the second layer conductive film. The forming step includes a step of performing etch back using the stopper layer as a stopper.

  With this configuration, the etch back can be stopped on the first electrode without the first electrode being scraped, so that it is possible to form a charge transfer portion with good flatness and high yield. . Here, when the second-layer conductive film is composed of a silicon-based conductive film, it is desirable to use silicon nitride or the like. Also, when patterning the first electrode, a two-layer film of silicon oxide and silicon nitride is used as a mask, and this is used as it is as an etching stopper, thereby enabling good patterning without increasing the number of steps. At the same time, it is possible to form a charge transfer portion having excellent flatness.

  According to the method for manufacturing a solid-state imaging device of the present invention, when planarization is performed by CMP or resist etch-back, the second layer is formed by forming a removal suppression layer (etching stopper) even in an active region where a dummy pattern cannot be formed. It is possible to prevent the silicon conductive film from being reduced, and to form a solid-state imaging device with uniform wiring resistance and good charge transfer efficiency.

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)

As shown in FIG. 1 to FIG. 3, the solid-state imaging device has a first layer constituting the first electrode when forming a solid-state imaging device having a charge transfer electrode having a single-layer electrode structure. A removal suppression layer (etching stopper) is formed in the active region (here, the region between the first electrodes 3a in FIG. 3K) where the dummy pattern of the first layer amorphous silicon film as the conductive film cannot be formed. It is characterized in that the film loss of the second layer amorphous silicon film in the region is suppressed.
As a result, neither the second electrode or the wiring formed of the second layer amorphous silicon as the second layer conductive film by the planarization process by resist etch back is reduced in the active region. Therefore, the surface of the charge transfer portion and the peripheral circuit portion can be satisfactorily flattened without reducing the film thickness.

  As shown in FIG. 4 and FIG. 5 as a schematic explanatory diagram of the whole (the peripheral portion is not shown in this figure), a plurality of photodiode regions 30 constituting the photoelectric conversion portion are formed on the silicon substrate 1. Then, a charge transfer unit 40 for transferring the signal charge detected by the photodiode is formed between the photodiode regions 30. Here, FIG. 5 is a cross-section obtained by cutting along a plane including the photodiode region along the line AA in FIG. 1 to 3 show a cross section including an active region having a pattern of a second layer conductive film as a wiring pattern constituting a functional circuit.

  Although not shown in FIG. 4, the charge transfer channel 33 through which the signal charge transferred by the charge transfer electrode moves is formed in a direction crossing the direction in which the charge transfer unit 40 extends.

  In FIG. 4, the description of the interelectrode insulating film 5 formed near the boundary between the photodiode region and the charge transfer portion 40 is omitted.

  As shown in FIG. 5, a photodiode region 30, a charge transfer channel 33, a channel stop region 32, and a charge readout region 34 are formed in the silicon substrate 1, and a gate oxide film 2 is formed on the surface of the silicon substrate 1. Is done. On the surface of the gate oxide film 2, an interelectrode insulating film 5 made of a silicon oxide film and a charge transfer electrode 3 (a first electrode made of a first layer doped amorphous silicon film 3a, a second layer doped amorphous silicon film 3b) Second electrode) is formed.

  Although the charge transfer unit 40 is as described above, an intermediate layer 70 is formed on the upper surface of the charge transfer electrode of the charge transfer unit 40 as shown in FIG. 71 is a light shielding film, 72 is an insulating film made of BPSG (borophospho silicate glass), 73 is an insulating film (passivation film) made of P-SiN, and 74 is a flattening layer made of a transparent resin film.

Above the solid-state imaging device, a light shielding film 71 is provided except for the light detection portion of the photodiode region 30, and a color filter 50 and a microlens 60 are further provided. Further, a flattening layer 61 made of an insulating transparent resin or the like is filled between the color filter 50 and the microlens 60.
FIG. 5 shows a so-called honeycomb-structured solid-state image pickup device, but it goes without saying that the present invention can also be applied to a square lattice type solid-state image pickup device.

Next, the manufacturing process of this solid-state image sensor will be described in detail.
First, a silicon oxide film 2a having a thickness of 15 to 35 nm, a silicon nitride film 2b having a thickness of 50 nm, and a thickness of 5 to 5 are formed on the surface of an n-type silicon substrate 1 having an impurity concentration of about 1.0 × 10 ¹⁶ cm ^−3. A 10 nm silicon oxide film 2c is formed, and a gate oxide film 2 having a three-layer structure is formed.

Subsequently, a phosphorus-doped first layer dope with a film thickness of 0.3 to 0.4 μm is formed on the gate oxide film 2 by a low pressure CVD method using SiH ₄ to which PH ₃ and N ₂ are added as a reactive gas. A triamorphous silicon film 3a is formed. The substrate temperature at this time shall be 500-650 degreeC.

  Thereafter, a silicon oxide film 4 having a thickness of 10 to 30 nm and a silicon nitride film 5 having a thickness of 50 nm are formed by low pressure CVD.

  Subsequently, a positive resist is applied to the upper layer so as to have a thickness of 0.5 to 1.4 μm, exposed by photolithography using a desired mask, developed, and washed with water to form a resist pattern R1. (FIG. 1 (a)). Here, a dummy pattern (not shown) may be formed on the peripheral edge of the silicon substrate 1. The dummy pattern is formed at the time of layout so that the interval from the resist pattern R1 does not exceed a predetermined width (interval of the first electrodes).

Thereafter, the silicon oxide film 4 and the silicon nitride film 5 are etched by reactive ion etching using a mixed gas of CHF ₃ , C ₂ F ₆ , O ₂ and He, and the first layer doped amorphous silicon A mask pattern for patterning the film 3a is formed (FIG. 1B). Again, the dummy mask pattern is formed on the left hand side of the original first electrode forming mask pattern.
Then, the resist pattern is removed by ashing (FIG. 1C).

Thereafter, the first layer doped amorphous silicon film 3a is selected by reactive ion etching using a mixed gas of HBr and O ₂ with the mask pattern as a mask and the silicon nitride film 2b of the gate oxide film 2 as an etching stopper. Etching is performed to form wirings for the first electrode and the peripheral circuit (FIG. 1D). Here, it is desirable to use an etching apparatus such as an ECR (Electron Cyclotoron Resonance) system or an ICP (Inductively Coupled Plasma) system.

  Subsequently, an interelectrode insulating film 5 made of a silicon oxide film having a thickness of 80 to 90 nm is formed around the first electrode pattern by a thermal oxidation method (FIG. 2E).

Next, a second layer doped amorphous silicon film 3b having a film thickness of 0.4 to 0.7 μm is formed by a low pressure CVD method using a reactive gas obtained by adding PH ₃ and N ₂ to SiH ₄ gas. At this time, the film thickness of the second layer doped amorphous silicon film 3b is equal to or more than the total film thickness of the first layer doped amorphous silicon film and the silicon oxide film 4 and silicon nitride film 5 thereabove. It needs to be formed to be thick.

Then, a two-layer film of a silicon oxide film and a silicon nitride film is formed as a removal suppression layer 8 on the surface where the second layer doped amorphous silicon film 3b is formed (FIG. 2F).
Then, as shown in FIG. 2G, a resist R2 is applied to this upper layer and patterned by photolithography. Here, as the resist R2, GKR4403 is used and applied to a film thickness of 700 to 800 nm.

Subsequently, as shown in FIG. 3H, the removal suppressing layer 8 is patterned by isotropic etching using the pattern of the resist R2 as a mask.
Then, as shown in FIG. 3I, the entire surface is etched under the condition that the etching rate of the second layer doped amorphous silicon film 3b is almost the same, and the second layer doped amorphous silicon film 3b is planarized. Do.

  Thereafter, as shown in FIG. 3J, a resist pattern R3 for forming an active region and a peripheral circuit is formed. Here, the resist pattern R3 is formed so as to cover a part of the solid-state imaging element forming portion and the peripheral circuit portion.

Then, as shown in FIG. 3 (k), using this resist pattern R3 as a mask, the second layer doped amorphous silicon film 3b on the photodiode region 30 is removed by etching and a peripheral circuit pattern (not shown) remains. Let
Then, by removing the resist by ashing, a pattern of the second layer doped amorphous silicon film 3b constituting part of the solid-state imaging element forming portion and the peripheral circuit portion is formed.

  In this way, the second electrode composed of the second layer doped amorphous silicon film 3b is formed, and a charge transfer electrode having a flat surface is formed. At this time, a dummy pattern (not shown) remains on the periphery of the substrate. This dummy pattern is formed in a mesh shape, and is preferably connected to the ground potential. Thereby, a stable connection is possible.

Then, a light-shielding film pattern 71 and a BPSG film 72 having a thickness of 700 nm are formed on this upper layer and reflowed at 850 ° C. to be flattened. Then, an insulating film (passivation film) 73 made of P-SiN and a planarization layer 74 made of a transparent resin film are formed. Reference numeral 6 denotes an insulating film.
Thereafter, the color filter 50, the flattening layer 61, the microlens 60, and the like are formed to obtain a solid-state imaging device as shown in FIGS.

  According to this method, since the pattern of the removal suppressing layer is formed on the second layer doped amorphous silicon film in the active region, the surface level of the resist for etch back can be formed to be the same as the central portion. In addition, it is possible to realize highly accurate pattern formation without film loss at the peripheral portion, and to obtain functionally highly reliable operation characteristics.

As described above, according to such a configuration, since the removal suppression layer is provided in the active region and is planarized, an increase in resistance due to the film reduction in the active region can be prevented. In addition, when the pattern density of the first electrode is small, such as at the periphery of the semiconductor substrate, a dummy pattern should be formed so that the surface level of the resist is not lowered when the resist is applied by spin coating, particularly in a scribe line. In other words, a highly reliable solid-state imaging device can be formed with no variation in characteristics.
In the present embodiment, the peripheral edge of the semiconductor substrate refers to the peripheral edge of the semiconductor chip.

  In the embodiment, the interelectrode insulating film 5 is formed around the first electrode by thermal oxidation. That is, the first electrode patterning mask and the silicon nitride film, which is a two-layer silicon nitride film used as an etching stopper when planarizing the second electrode, are used as an antioxidant film, and the heat of the first electrode By performing oxidation, a silicon oxide film is selectively formed on the side wall of the first electrode, and this is used as an interelectrode insulating film. In this case, it is necessary to form a resist pattern in advance so that the first electrode width is increased by the oxidized region. Instead of this thermal oxidation, an interelectrode insulating film may be formed by a low pressure CVD method.

(Second Embodiment)
In the first embodiment, the removal suppressing layer is formed as the uppermost layer of the second layer amorphous silicon film. However, in the present embodiment, the second layer amorphous silicon film is formed in two steps, and an intermediate layer is formed. The removal suppression layer is formed in the part. Other parts are the same as those in the first embodiment. That is, as shown in FIGS. 1A to 2F, after the interelectrode insulating film 5 is formed, the second layer amorphous silicon film 3b is removed to the same height as the surface of the first layer amorphous silicon film. The suppression layer 8 is formed.

Thereafter, a resist pattern R2 is patterned as shown in FIG.
Then, the removal suppression layer 8 is patterned using the resist pattern R2 as a mask (FIG. 6B).

Further, as shown in FIG. 6C, a second amorphous silicon layer is formed on the removal suppressing layer 8 as an upper layer.
Then, as shown in FIG. 7D, the entire surface is etched under the condition that the etching rate of the second layer doped amorphous silicon film 3b is almost the same, and the second layer doped amorphous silicon film 3b is planarized. Do.

  Thereafter, as shown in FIG. 7E, a resist pattern R3 for forming an active region and a peripheral circuit is formed. Here, the resist pattern R3 is formed so as to cover a part of the solid-state imaging element forming portion and the peripheral circuit portion.

Then, as shown in FIG. 7F, using this resist pattern R3 as a mask, the second layer doped amorphous silicon film 3b on the photodiode region is removed by etching and a peripheral circuit pattern (not shown) is left. .
Then, by removing the resist by ashing, the second-layer doped amorphous silicon film 3b is formed so as to cover a part of the solid-state imaging element forming portion and the peripheral circuit portion.

According to this method, it is possible to reduce variations in the wiring resistance in the active region and form a highly reliable solid-state imaging device.
In addition, the dummy pattern can be formed without causing a decrease in the surface level by being formed so as to be equal to or higher than the density of the first layer wiring of the photoelectric conversion portion.

(Third embodiment)
Although not described in detail in the embodiment, a field oxide film is formed in a frame shape so as to surround the effective imaging region on the periphery of the chip, but a photoelectric conversion unit including a photosensor and It is desirable to form by the Recess LOCOS method so as to be the same as the surface level of the charge transfer portion.

  In the solid-state imaging device of the present embodiment, the surface level of the field oxide film provided in the peripheral circuit unit and the charge transfer unit is set to be approximately the same as the surface level of the photoelectric conversion unit, and the element region is formed. The entire surface of the substrate is flattened and the pattern accuracy by photolithography is improved, and the conductive film generated when the charge transfer electrode is made into a single layer, particularly the second layer conductive film is reduced. The charge transfer electrode and the peripheral circuit having a uniform film thickness can be formed. That is, a photoelectric transfer unit, a charge transfer unit including a charge transfer electrode that transfers charges generated in the photoelectric conversion unit, and a peripheral circuit unit including an output circuit connected to the charge transfer unit are provided. In the solid-state imaging device, the surface of the field oxide film formed in a frame shape so as to surround the effective imaging region (light receiving region) is the same as the surface level of the photoelectric conversion unit including the photosensor and the charge transfer unit. It is formed by the Recess LOCOS method.

According to such a configuration, since a pattern is formed on a flat surface, it is possible to form a pattern with extremely high accuracy, and it is possible to form a very fine charge transfer portion. Also, the wiring including the peripheral circuit portion can be miniaturized.
In the above embodiment, the field oxide film 10 is formed by selective oxidation in the trench T formed on the surface of the silicon substrate 1, but a silicon oxide film or the like may be filled in the trench.

  As described above, according to the method of the present invention, the second layer conductive film is formed on the pattern of the first layer conductive film via the interelectrode insulating film, and this second layer conductive film is formed. When a charge transfer electrode having a single-layer electrode structure is formed by flattening the film, the removal suppression layer is formed in the active region prior to the flattening to prevent film loss. Therefore, it is possible to obtain a solid-state imaging device that is reduced and has high reliability, and is effective in forming a fine and highly sensitive solid-state imaging device.

It is a figure which shows the manufacturing process of the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the solid-state image sensor of the 1st Embodiment of this invention. It is sectional drawing which shows the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of the 2nd Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of the 2nd Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of a prior art example. It is a figure which shows the manufacturing process of the solid-state image sensor of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Gate oxide film 3a 1st electrode (1st layer doped amorphous silicon film)
3b Second electrode (second layer doped amorphous silicon film)
3 Charge Transfer Electrode 4a Silicon Oxide Film 4b Silicon Nitride Film 5 Interelectrode Insulating Film 8 Removal Suppression Layer 30 Photodiode Region 40 Charge Transfer Unit 50 Color Filter 60 Micro Lens 70 Intermediate Layer

Claims (17)

Solid comprising: a photoelectric conversion unit; a charge transfer unit including a charge transfer electrode having a single-layer electrode structure that transfers charges generated in the photoelectric conversion unit; and a peripheral circuit unit connected to the charge transfer unit In the manufacturing method of the image sensor,
Forming a pattern of a first layer conductive film constituting a first layer wiring of the first electrode, the photoelectric conversion unit and the peripheral circuit unit on the surface of the semiconductor substrate on which the gate oxide film is formed;
Forming an insulating film to be an inter-electrode insulating film on at least the side wall of the first electrode;
Forming a second layer conductive film constituting a second electrode on the surface of the semiconductor substrate on which the first electrode and the interelectrode insulating film are formed;
Removing the protruding portion of the second conductive film protruding on the first electrode, and planarizing the surface;
Patterning said second layer conductive film in an active region,
Prior to the flattening step, a method of manufacturing a solid-state imaging device including a step of forming a removal suppression layer that suppresses the removal of the second-layer conductive film in the active region. It is a manufacturing method of the solid-state image sensing device according to claim 1,
The method of manufacturing a solid-state imaging device, wherein the step of forming the removal suppression layer is performed after the step of forming the second layer conductive film. It is a manufacturing method of the solid-state image sensing device according to claim 1,
The step of forming the second-layer conductive film includes a pre-process for forming the second-layer conductive film having the same film thickness as that of the first conductive film, and then forming the removal suppressing layer. And a post-process for forming the second-layer conductive film. It is a manufacturing method of the solid-state image sensing device according to any one of claims 1 to 3,
The method of manufacturing a solid-state imaging device, wherein the second layer conductive film is a silicon-based conductive film. It is a manufacturing method of the solid-state image sensing device according to claim 4,
The method for manufacturing a solid-state imaging device, wherein the silicon-based conductive film is doped amorphous silicon. It is a manufacturing method of the solid-state image sensing device according to claim 4,
The method for manufacturing a solid-state imaging device, wherein the silicon-based conductive film is doped polysilicon. A method for manufacturing a solid-state imaging device according to any one of claims 1 to 6,
The method of forming a removal suppressing layer includes a step of forming a silicon oxide film and a step of forming a silicon nitride film on the silicon oxide film. It is a manufacturing method of the solid-state image sensing device according to claim 7,
The step of forming the removal suppressing layer includes a step of patterning by isotropic etching. A method for manufacturing a solid-state imaging device according to any one of claims 1 to 8,
The planarizing step includes a step of applying a resist to the semiconductor substrate surface;
And a step of etching back the resist and the second-layer conductive film under the condition that the etching rate is comparable. It is a manufacturing method of the solid-state image sensing device according to claim 9,
The method of manufacturing a solid-state imaging device, wherein the planarizing step is a CMP (Chemical Mechanical Polishing) step. It is a manufacturing method of the solid-state image sensing device according to claim 1,
Prior to the formation of the charge transfer portion,
Forming a trench in a field oxide film formation region provided in a peripheral circuit portion and the charge transfer portion so as to surround an effective imaging region of the photoelectric conversion portion on a surface of the semiconductor substrate; and field oxidation in the trench Forming a film;
Planarizing the semiconductor substrate surface on which the field oxide film is formed;
Forming a device portion such as the charge transfer electrode, the photoelectric conversion portion, and the peripheral circuit portion on the surface of the semiconductor substrate. It is a manufacturing method of the solid-state image sensing device according to claim 11,
The method of manufacturing a solid-state imaging device, wherein the step of forming the field oxide film includes a selective oxidation (LOCOS) step. It is a manufacturing method of the solid-state image sensing device according to claim 9,
The step of forming the field oxide film includes a step of filling the trench with an insulating film by a CVD method. It is a manufacturing method of the solid-state image sensing device according to any one of claims 11 to 13,
The step of planarizing the semiconductor substrate surface includes:
Applying a resist to the semiconductor substrate surface by spin coating;
And a flattening process using a resist etch-back method. It is a manufacturing method of the solid-state image sensing device according to any one of claims 11 to 13,
The step of planarizing the semiconductor substrate surface includes:
And a step of planarizing the surface of the semiconductor substrate by a CMP (Chemical Mechanical Polishing) method. It is a manufacturing method of the solid-state image sensing device according to claim 1,
The step of forming the pattern of the first layer conductive film includes a step of forming the pattern including a dummy pattern so that a surface level of the resist does not become a predetermined value or less on the semiconductor substrate. Manufacturing method. It is a manufacturing method of the solid-state image sensing device according to claim 1,
Prior to the step of forming the second layer conductive film, including a step of forming a stopper layer serving as an etching stopper on the surface of the first electrode,
The method of manufacturing a solid-state imaging device, wherein the planarizing step is a step of performing etch back using the stopper layer as a stopper.

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