JP2009060026A - Manufacturing method of solid-state imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging element which has high reliability by suppressing current leakages, by avoiding forming a sub-trench in an etching-back process for forming a sidewall insulating film as an inter-electrode insulating film, and then forming the inter-electrode insulating film which is readily made fine and which is high in quality. <P>SOLUTION: The process of forming the sidewall insulating film as the inter-electrode insulating film for a solid-state imaging element, having a single-layer electrode structure includes a first etching process of anisotropically etching an insulating film, covering a substrate except for a part of it; and a second etching process of isotropically etching the insulating film left on the substrate; as well as, a process of heat-treating the insulating film, prior to at least the second etching process. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a solid-state imaging device, and more particularly to reduction of leakage current in a charge transfer electrode of the solid-state imaging device.

  A solid-state imaging device using a CCD used for an area sensor or the like includes a photoelectric conversion unit including a photodiode and a charge transfer unit including a charge transfer electrode for transferring a signal charge from the photoelectric conversion unit. . A plurality of charge transfer electrodes are arranged adjacent to each other on a charge transfer path formed on the semiconductor substrate, and are sequentially driven.

In recent years, with the increase in the number of pixels of a CCD, the demand for higher resolution and higher sensitivity is increasing in solid-state imaging devices, and the number of imaging pixels is increasing to more than gigapixels.
In order to ensure high sensitivity in such a situation, it is difficult to reduce the light receiving area, and as a result, the area occupied by the charge transfer electrode must be reduced.

  By the way, the interelectrode insulating film provided between the charge transfer electrodes can be formed thin by oxidation (900 to 950 ° C.) of the electrode material. However, if an oxide film having a thin and good quality is to be formed, the oxidation temperature needs to be as high as 900 ° C. or more as described above, so that impurity diffusion on the substrate side proceeds due to the thermal history due to oxidation, and transfer efficiency is deteriorated. Or, various problems such as a decrease in sensitivity are caused.

  In addition, the charge transfer electrode is reduced due to thermal oxidation, and the formation of the interelectrode insulating film using thermal oxidation increases the pixel size, miniaturization (higher quality), and speedup of the solid-state imaging device. It is a big wall to block.

  Therefore, a method has been proposed in which an insulating film is formed on the entire surface and sidewalls are formed by etchback so that the electrodes are not reduced when the interelectrode insulating film is formed (Patent Document 1).

  In addition, the present applicant intends to use a high-quality interelectrode insulating film that can be formed at a low temperature and can be easily miniaturized, and the present applicant has applied a sidewall formed by a CVD method at a substrate temperature of 700 ° C. to 850 ° C. A solid-state imaging device that is insulated and separated by an inter-electrode insulating film made of an insulating film has been proposed (Patent Document 2).

  In the above method, when the interelectrode insulating film between the first electrode composed of the first layer conductive film and the second electrode composed of the second layer conductive film is formed by the CVD method, After the formation of the first electrode, a silicon oxide film is formed by the CVD method, and then the entire surface is etched back by anisotropic etching to remove the silicon oxide film other than the side surface of the first electrode and form a sidewall. The method is taken.

JP-A-2005-64202 JP 2006-1000036 A

However, in Patent Document 1, the second layer conductive film is formed on the first electrode by the CVD method, and the sidewall insulating film is formed on the side surface of the transfer electrode by etch back when forming the second electrode. Thus, a method of forming an interelectrode insulating film is employed.

  In this case, a method is employed in which the silicon oxide film other than the side surface of the first electrode is removed by etching the entire surface using anisotropic etching to form a sidewall insulating film. This method has a problem in that ion concentration occurs in the vicinity of the sidewall, and a sub-trench is formed in a portion of the gate insulating film in contact with the sidewall.

  In this way, after the sidewall insulating film is formed, the second electrode is formed on the upper layer. However, since the sub-trench is formed so as to be in contact with the first electrode, the sub-trench is just formed. It will be located under the second electrode, and the second electrode formed in this upper layer will be partly pointed.

  Such a sharp shape causes an electric field concentration at the sharpness when the element is driven, and the insulation between the semiconductor substrate and the second electrode, and between the first electrode and the second electrode is reduced, resulting in current leakage. There was a cause. This has become more serious as device miniaturization proceeds.

As described above, in the manufacture of a solid-state imaging device, current leakage caused by generation of a sub-trench in an etch-back process for forming a sidewall insulating film to be an inter-electrode insulating film so as to withstand further miniaturization. Has become a serious problem.
The present invention has been made in view of the above circumstances, and avoids generation of sub-trench in an etch-back process for forming a sidewall insulating film to be an inter-electrode insulating film, and suppresses current leakage, thereby miniaturizing. An object of the present invention is to provide a solid-state imaging device with high reliability by forming an interelectrode insulating film that is easy and high quality.

Therefore, the present invention forms a photoelectric conversion portion on a substrate, forms a gate insulating film on the substrate, and forms a first electrode made of a first layer conductive film on the substrate. Forming an insulating film on the upper layer of the first electrode; and etching the insulating film to selectively remain on the side wall of the first electrode, thereby forming a sidewall insulating film And a step of forming a second-layer conductive film on the sidewall insulating film and patterning it to form a charge transfer electrode including a first electrode and a second electrode; And forming the sidewall insulating film includes a first etching step of performing anisotropic etching leaving a part of the insulating film covering the substrate, and the insulating film remaining on the substrate. Second etch removed by isotropic etching Together and a grayed step, prior to at least a second etching step, characterized in that it comprises a step of heat-treating the insulating film.
According to this method, when forming the sidewall insulating film, a step of performing two-step etching of anisotropic etching and isotropic etching and heat-treating the insulating film at least prior to the second etching step are performed. Accordingly, the insulating film can be densified, the etching controllability can be improved even during isotropic etching, and a sidewall insulating film with higher accuracy and quality can be formed. In addition, since the insulating film is a dense film by heat treatment, the insulating property is improved, and leakage between the substrate and the second electrode, and the first electrode and the second electrode is reduced.
Further, it is possible to form the sidewall with high accuracy while suppressing the generation of the sub-trench.

  Further, the present invention includes the method for manufacturing a solid-state imaging device, wherein the second etching step is a wet etching step.

According to the present invention, in the method for manufacturing a solid-state imaging device, the step of forming the insulating film includes a step of forming an insulating film by a CVD method.
According to this method, since the sidewall insulating film is formed by the CVD method, an interelectrode insulating film having a good film quality can be formed in a self-aligned manner at a low temperature, easy to manufacture, highly reliable, fine Can be easily formed.

In the method for manufacturing a solid-state imaging device according to the present invention, the step of forming the insulating film includes a step of forming an HTO film by a CVD method at a substrate temperature of 700 ° C. to 850 ° C.
According to this method, a dense and high-quality sidewall insulating film can be efficiently formed at a low temperature (700 ° C. to 850 ° C.).

In the method for manufacturing a solid-state imaging device according to the present invention, the step of forming the insulating film includes a step of forming an LP-TEOS film at a substrate temperature of 600 ° C. to 700 ° C.
According to this method, the sidewall insulating film can be efficiently formed at a lower temperature.

  Furthermore, the present invention includes the method for manufacturing a solid-state imaging device, wherein the wet etching step is a step of performing etching under conditions that allow a sufficient selection ratio with the gate insulating film.

  The present invention also includes the step of performing a heat treatment on the insulating film prior to the first etching step in the method for manufacturing a solid-state imaging device.

  In the method for manufacturing a solid-state imaging device according to the present invention, the step of performing a heat treatment on the insulating film includes a heat treatment step of not less than a CVD film forming temperature (900 ° C. or less) for 30 minutes or more.

  In the method for manufacturing a solid-state imaging device according to the present invention, the step of performing the heat treatment on the insulating film includes a heat treatment step of 950 to 1100 ° C. for 30 seconds or less.

  The present invention includes the above-described method for manufacturing a solid-state imaging device, including a step of performing a heat treatment on the insulating film after the first etching step and prior to the second etching step.

  In the method for manufacturing a solid-state imaging device according to the present invention, the step of performing a heat treatment on the insulating film includes a heat treatment step of not less than a CVD film forming temperature (900 ° C. or less) for 30 minutes or more.

  In the method for manufacturing a solid-state imaging device according to the present invention, the step of performing the heat treatment on the insulating film includes a heat treatment step of 950 to 1100 ° C. for 30 seconds or less.

  Further, the present invention includes the above-described solid-state imaging device manufacturing method, wherein the gate insulating film has an ONO film structure in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially stacked.

  Further, the present invention includes the method for manufacturing a solid-state imaging device, wherein the insulating film is a silicon oxide film.

  In addition, the present invention includes a method of forming a silicon oxide film by a CVD method before the formation of the second-layer conductive film after the formation process of the sidewall insulating film in the method for manufacturing the solid-state imaging device.

According to the present invention, in the method for manufacturing a solid-state imaging device, the step of forming the first electrode includes a step of forming a first layer conductive film, and an insulating film on the first layer conductive film. Forming a hard mask; and selectively removing the first-layer conductive film using the hard mask.
According to this method, a highly accurate and reliable first electrode pattern can be formed. In addition, this hard mask acts as a removal suppressing layer (stopper layer) that suppresses the removal of the first electrode when the second conductive film is planarized, so that a flat surface can be efficiently formed without reducing the film. Can do.

  The present invention includes the method for manufacturing a solid-state imaging device, wherein the hard mask is a single layer film made of a silicon oxide film, and the second layer conductive film is stacked on the hard mask.

According to the present invention, in the method of manufacturing a solid-state imaging device, the hard mask is a two-layer film of a silicon oxide film and a silicon nitride film, and the second-layer conductive film is stacked on the hard mask. Including things.
According to this method, contamination of the first conductive film constituting the first electrode can be prevented in resist ashing. Further, in the patterning process of the second layer conductive film, this hard mask works well as the first electrode removal suppressing layer, and after patterning the second layer conductive film, the sidewall insulating film is formed by anisotropic etching. Also when formed, it works well as a removal suppression layer on the first electrode.

  Further, when forming the second electrode by the resist etch-back process of the second layer conductive film, the hard mask works well as a removal suppression layer of the first electrode.

Further, the second layer conductive film is subjected to chemical mechanical polishing (CMP).
When the second electrode is formed by the flattening step, the hard mask works well as a removal suppression layer for the first electrode.

  According to the present invention, the step of forming the sidewall insulating film includes a first etching step of performing anisotropic etching while leaving a part of the insulating film covering the substrate, and the step of remaining on the substrate. A second etching step for removing the insulating film by isotropic etching, and at least a step for heat-treating the insulating film prior to the second etching step, so that the insulating film is densified. In the isotropic etching, the etching controllability is improved, and the sidewall insulating film with higher accuracy and quality can be formed. In addition, since the insulating film is a dense film by heat treatment, the insulating property is improved, and leakage of the first electrode and the second electrode is also reduced.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
As shown in FIG. 1 and FIG. 2, the method of the present embodiment includes a first electrode A in which the charge transfer electrode is made of a polycrystalline silicon layer as the first layer conductive film 3a, and a second layer conductivity. From the single-layer electrode structure in which the second electrodes B made of a polycrystalline silicon layer as the film 3b are alternately arranged, and the interelectrode insulating film is made of a sidewall insulating film made of an HTO film formed by a CVD method. A method for forming a solid-state imaging device comprising: a sidewall insulating film as an inter-electrode insulating film formed between a first electrode A and a second electrode B; The forming process is two-stage etching, and the insulating film is densified by heat treatment prior to the second etching process. That is, the step of forming the sidewall insulating film includes a first etching step of performing anisotropic etching while leaving a part of the insulating film covering the substrate, a step of heat-treating the insulating film, and a residue on the substrate. And a second etching step for removing the insulating film by isotropic etching.

  According to the above configuration, a high-quality sidewall insulating film can be formed at a low temperature by the HTO film in which the interelectrode insulating film is formed by the CVD method and is densified by heat treatment. Further, the occurrence of current leakage due to the generation of the sub-trench as described above can be suppressed.

Other structures are the same as those of a conventional solid-state imaging device, and a photoelectric transfer unit 30 and a charge transfer unit (not shown) including a charge transfer electrode 40 that transfers charges generated by the photoelectric conversion unit 30; A light shielding film (not shown) formed so as to have an opening in the photoelectric conversion portion and a flat BPSG (borophospho silicate glass) film filled in the photoelectric conversion portion so that the surface is substantially flat And an intermediate layer 70 including a chemical film, and the filter 50 and the lens 60 are formed on the intermediate layer.
As a result, the surface can be satisfactorily flattened, and the thickness can be greatly reduced.

  The gate oxide film 2 is composed of a three-layer structure film of a silicon oxide film 2a, a silicon nitride film 2b, and a silicon oxide film 2c.

  1 is a schematic cross-sectional view, and FIG. 2 is a schematic plan view. A plurality of photodiode regions 30 are formed on the silicon substrate 1, and charge transfer electrodes 40 for transferring signal charges detected in the photodiode regions 30 are formed between the photodiode regions 30.

  Although not shown in FIG. 2, the charge transfer portion to which the signal charge transferred by the charge transfer electrode moves is formed in a direction crossing the direction in which the charge transfer electrode 40 extends.

  In FIG. 2, the description of the interelectrode insulating film formed near the boundary between the photodiode region 30 and the charge transfer electrode 40 is omitted.

  Although the charge transfer portion is as described above, as shown in FIG. 1, an intermediate layer 70 is formed on the upper surface of the charge transfer electrode of the charge transfer portion. A light shielding film (not shown) is provided except for the photodiode region 30 (photoelectric conversion portion), an antireflection layer made of a silicon nitride film is provided on the photodiode region, and a planarizing film made of a BPSG film is formed in the recess. A passivation film made of a transparent resin film or a silicon nitride film is provided as an upper layer.

A color filter 50 and a microlens 60 are further provided above the intermediate layer 70. Further, a flattening layer made of an insulating transparent resin or the like may be filled between the color filter 50 and the microlens 60 as necessary.
In this example, a so-called honeycomb-structured solid-state imaging device is shown, but it goes without saying that the present invention can also be applied to a square lattice type solid-state imaging device.

Next, the manufacturing process of the solid-state imaging device will be described in detail with reference to FIGS. 3 to 9.
First, a 25 nm thick silicon oxide film 2a, a 50 nm thick silicon nitride film 2b, and a 5 nm thick silicon oxide film are formed on the surface of an n-type silicon substrate 1 having an impurity concentration of about 1.0 × 10 ¹⁶ cm ^−3. A film 2c is formed, and a gate oxide film 2 having a three-layer structure is formed.

Subsequently, a first-layer polycrystalline silicon film as a first-layer conductive film 3a having a thickness of 50 to 300 nm is formed on the gate oxide film 2 by a low pressure CVD method. The substrate temperature at this time shall be 500-600 degreeC. Then, an LP-TEOS film 5a having a film thickness of 50 to 200 nm and a silicon nitride film 5b having a film thickness of 50 to 100 nm are sequentially stacked on the upper layer by a CVD method at a substrate temperature of 850 ° C. (700 to 850 ° C.) (FIG. 3).

  Thereafter, a first resist pattern R1 is formed by photolithography (FIG. 4).

Then, etched by reactive ion etching using (Fig. 5) further LP-TEOS film 5a and CHF ₃ and _{C 2 F 6 O} 2 and the He with etched by reactive ion etching using the silicon nitride film 5b (FIG. 6), the resist pattern R1 is removed by ashing to form a hard mask (FIG. 7).

The first layer conductive film 3a is etched using the hard mask made of the LP-TEOS film 5a and the silicon nitride film 5b thus obtained (FIG. 8). In this etching, reactive ion etching using a mixed gas of HBr and O ₂ is performed to form wiring for the first electrode and the peripheral circuit. Here, it is desirable to use an etching apparatus such as an ECR (Electron Cyclotoron Resonance) system or an ICP (Inductively Coupled Plasma) system. A dummy pattern (not shown) is formed on the outside of the peripheral circuit where the wiring density is small, if necessary.

  Thereafter, an HTO (silicon oxide) film 6 having a thickness of 50 to 200 nm is formed on this upper layer by a low pressure CVD method at a substrate temperature of 700 to 850 ° C. (FIG. 9).

  Then, by reactive ion etching, the silicon oxide film 6 is removed on the horizontal portion so as to remain in a thickness of about 5 to 30 nm and is left on the side wall to form a side wall (insulating film) (FIG. 10).

  Thereafter, an RTA heat treatment at 1100 ° C. for 10 seconds is performed to perform a densification treatment of the silicon oxide film 6 (FIG. 11).

  Subsequently, the silicon oxide film remaining in the horizontal portion is removed by wet etching using dilute hydrofluoric acid (FIG. 12).

  Thereafter, the HTO film removed by wet etching is supplemented by a low pressure CVD method, and an HTO (silicon oxide) film 6S having a thickness of 3 to 10 nm is formed as a top oxide film of the ONO film (FIG. 13).

  Subsequently, a polycrystalline silicon film is formed as the second conductive film 3b on the upper layer by a low pressure CVD method so as to be equal to or higher than the height of the first conductive film 3a. The substrate temperature at this time shall be 500-600 degreeC (FIG. 14).

  Further, the projecting second layer conductive film 3b is removed by CMP to planarize the surface (FIG. 15).

  Further, an LP-TEOS film 7 having a film thickness of ˜50 nm is formed by a low pressure CVD method (FIG. 16).

Then, in order to perform patterning of the second electrode (second-layer conductive film) and open the window of the photoelectric conversion portion, as in the patterning of the first electrode, a film thickness of about A 50 nm silicon nitride film 9 is formed by a low pressure CVD method.
Thereafter, a second resist pattern R2 is formed by photolithography (FIG. 17).

Then, this silicon nitride film 9 is etched by reactive ion etching using CHF ₃ , CF _4, and Ar (FIG. 18), and the resist pattern R 2 is removed by ashing to form a hard mask (FIG. 19).

Then, the LP-TEOS film is patterned by reactive ion etching using CHF ₃ , CF _4, and Ar using the silicon nitride film 9 as a mask, and the LP-TEOS film 7 and the silicon nitride film 9 thus obtained are patterned. The polycrystalline silicon film as the second layer conductive film 3b is etched using the hard mask made of (FIG. 20). In this etching, reactive ion etching using a mixed gas of HBr and O ₂ or Cl ₂ and O ₂ is performed to form a window of the photoelectric conversion portion. Here, it is desirable to use an etching apparatus such as ECR or ICP.

  Then, an HTO (silicon oxide) film 10 having a thickness of 50 to 200 nm is formed (FIG. 21).

  Then, the HTO film 10 deposited on the horizontal portion is removed by reactive ion etching and left on the side wall to form a side wall (FIG. 22). At this time, in order to reduce the damage caused by the reactive ion etching on the substrate surface, it is made to remain slightly in the horizontal portion. Also at this time, the HTO film can be densified by performing a heat treatment at a temperature not lower than the HTO film forming temperature and not higher than 900 ° C. for not shorter than 30 minutes.

  Subsequently, the HTO film 10 remaining in the horizontal portion is removed by wet etching (FIG. 23)).

  In this way, a low resistance charge transfer electrode is formed.

  Then, an intermediate layer 70 such as an antireflection film, a light shielding layer, and a flattening film is formed, and a color filter 50, a microlens 60, and the like are formed, and a solid-state imaging device as shown in FIGS. 1 and 2 is obtained.

According to the above method, at the time of forming the sidewall insulating film, two-step etching of reactive ion etching (anisotropic etching) and wet etching (isotropic etching) is performed, and at least the isotropic etching process is performed. Since the insulating film is heat-treated by the RTA process in advance, the insulating film can be densified, and even during wet etching, the etching controllability is improved and the sidewall insulation with higher accuracy and quality is achieved. A film can be formed. Further, since the insulating film is a dense film by heat treatment, the insulating property can be improved, and leakage of the first electrode and the second electrode is also reduced.
Furthermore, the sidewall can be formed with high accuracy while suppressing the generation of the sub-trench.

  Further, according to the solid-state imaging device thus formed, the charge transfer electrode is composed of the first electrode composed of the first layer conductive film 3a composed of the polycrystalline silicon layer and the polycrystalline silicon. The second electrode made of the second-layer conductive film 3a is formed by the low pressure CVD method, and is arranged in parallel alternately through the side wall formed of the densified HTO film 6, and has a low resistance. Since the single-layer structure electrode is configured, a highly accurate and fine solid-state imaging device is formed, and high speed and miniaturization are possible. Even if a silicon oxide film formed by a low temperature CVD method is used instead of the HTO film 6, a high-quality sidewall insulating film can be obtained by densification by heat treatment, and there is no increase in diffusion length and reliability. A highly functional film can be obtained.

  According to this method, it is possible to form a miniaturized structure having an interelectrode distance of about 0.1 μm.

Further, in the planarization step, a two-layer etching stopper of a silicon oxide film and a silicon nitride film is used, and a dummy pattern is used, so that film loss can be prevented. This may be effective in planarization by CMP. The dummy pattern used here may not have electrical connection with the peripheral circuit portion.
Note that a two-layer film of an LP-TEOS film and a silicon nitride film is used as a hard mask for patterning and an etching stopper layer, and a fine pattern can be formed with high accuracy. Further, by using an etching stopper, film loss due to overpolishing can be prevented.

  A two-layer film is also used for patterning the second electrode. Thus, by configuring the hard mask with a two-layer film, not only the pattern accuracy is improved, but also the reliability as an insulating film is improved.

(Embodiment 2)
In the first embodiment, as shown in FIGS. 24 to 25, when the sidewall insulating film is formed, the anisotropic etching is performed and then the heat treatment is performed. However, in this embodiment, the anisotropic etching is performed. A heat treatment is performed prior to etching. The rest is the same as in the first embodiment.

  That is, the steps of FIGS. 9 to 11 in the first embodiment are replaced with FIGS. 24 to 26, and the other processes are the same as those of the first embodiment.

  In the same manner as shown in FIG. 9, an HTO (silicon oxide) film 6 having a film thickness of 50 to 200 nm is formed on this upper layer by a low pressure CVD method at a substrate temperature of 700 to 850 ° C.

  Thereafter, an RTA heat treatment at 1100 ° C. for 10 seconds is performed to perform a densification treatment of the silicon oxide film 6 (FIG. 24).

  Then, by reactive ion etching, the silicon oxide film 6 is removed on the horizontal portion so as to remain in a thickness of about 5 to 30 nm and is left on the side wall to form a side wall (insulating film) (FIG. 25).

  Then, the silicon oxide film remaining in the horizontal portion is removed by wet etching using dilute hydrofluoric acid (FIG. 12). Although the following is omitted, FIG. 12 and subsequent steps are the same as those in the first embodiment.

  In the first and second embodiments, the first electrode and the second electrode are formed of a polycrystalline silicon layer. However, both may have a structure in which a metal silicide layer such as tungsten silicide is formed on the surface. .

  Note that the metal constituting the silicide is not limited to tungsten, and can be appropriately changed to titanium (Ti), cobalt (Co), nickel (Ni), or the like. Further, the silicon layer is not limited to polycrystalline silicon, and can be appropriately changed such as an amorphous silicon layer or a microcrystal silicon layer.

  In addition, it can change suitably, without being limited to the said embodiment.

As described above, according to the present invention, since the insulating film formed by the CVD method is densified by heat treatment in forming the sidewall insulating film, the charge transfer electrode having a fine and reliable single-layer electrode structure Therefore, it is possible to reduce the thickness and reduce the margin with respect to the light incident angle, which is effective for forming a fine and highly sensitive solid-state imaging device such as a small camera.

It is sectional drawing which shows the solid-state image sensor of Embodiment 1 of this invention. It is a top view which shows the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 2 of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Gate oxide film 3a 1st layer conductive film 3b 2nd layer conductive film 5a LP-TEOS film 5b Silicon nitride film 6 Silicon oxide film 6S HTO film 7 LP-TEOS film 9 Silicon nitride film 30 Photodiode region 40 charge transfer electrode 50 color filter 60 micro lens 70 intermediate layer

Claims (18)

Forming a photoelectric conversion part on the substrate;
Forming a gate insulating film on the substrate on which the photoelectric conversion unit is formed;
Forming a first electrode comprising a first layer conductive film on the substrate;
Forming an insulating film on the upper layer of the first electrode;
Etching the insulating film and selectively remaining on the sidewalls of the first electrode, thereby forming a sidewall insulating film;
Forming a second-layer conductive film on the sidewall insulating film and patterning it to form a charge transfer electrode including a first electrode and a second electrode;
A step of forming the sidewall insulating film includes a first etching step of performing anisotropic etching while leaving a part of the insulating film covering the substrate;
And a second etching step for removing the insulating film remaining on the substrate by isotropic etching,
A method for manufacturing a solid-state imaging device, including a step of heat-treating the insulating film prior to at least a second etching step. It is a manufacturing method of the solid-state image sensing device according to claim 1,
The method for manufacturing a solid-state imaging device, wherein the second etching step is a wet etching step. It is a manufacturing method of the solid-state image sensing device according to claim 1 or 2,
The step of forming the insulating film is a method of manufacturing a solid-state imaging device, which is a step of forming an insulating film by a CVD method. It is a manufacturing method of the solid-state image sensing device according to claim 3,
The step of forming the insulating film is a method of manufacturing a solid-state imaging device, which is a step of forming an HTO film by a CVD method at a substrate temperature of 700 ° C. to 850 ° C. It is a manufacturing method of the solid-state image sensing device according to claim 3,
The step of forming the insulating film is a method of manufacturing a solid-state imaging device, which is a step of forming a TEOS film by LPCVD at a substrate temperature of 600 ° C. to 700 ° C. It is a manufacturing method of the solid-state image sensing device according to claim 2,
The method of manufacturing a solid-state imaging device, wherein the wet etching step is a step of performing etching under conditions that allow a sufficient selection ratio with the gate insulating film. A method for manufacturing a solid-state imaging device according to any one of claims 1 to 6,
A method for manufacturing a solid-state imaging device, including a step of performing a heat treatment on the insulating film prior to the first etching step. A method for manufacturing a solid-state imaging device according to any one of claims 1 to 6,
A method for manufacturing a solid-state imaging device, including a step of performing a heat treatment on the insulating film after the first etching step and prior to the second etching step. It is a manufacturing method of the solid-state image sensing device according to claim 7 or 8,
The process of performing heat treatment on the insulating film is a method for manufacturing a solid-state imaging device, which is a heat treatment process at 950 to 1100 ° C. for 30 seconds or less. It is a manufacturing method of the solid-state image sensing device according to claim 7 or 8,
The method of manufacturing a solid-state imaging device, wherein the step of heat-treating the insulating film is a heat-treatment step of 900 ° C. or lower and 30 minutes or longer. It is a manufacturing method of the solid-state image sensing device according to any one of claims 1 to 10,
The method for manufacturing a solid-state imaging device in which the gate insulating film has an ONO film structure in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially stacked. It is a manufacturing method of the solid-state image sensing device according to any one of claims 1 to 11,
The method for manufacturing a solid-state imaging device, wherein the insulating film is a silicon oxide film. It is a manufacturing method of the solid-state image sensing device according to any one of claims 1 to 12,
After forming the sidewall insulating film, prior to forming the second layer conductive film,
A method for manufacturing a solid-state imaging device, including a step of forming a silicon oxide film by a CVD method. It is a manufacturing method of the solid-state image sensing device according to any one of claims 1 to 13,
The step of forming the first electrode includes a step of forming a first layer conductive film, a step of forming a hard mask made of an insulating film on the first layer conductive film, and using the hard mask. A method of manufacturing a solid-state imaging device, comprising a step of selectively removing the first layer conductive film. It is a manufacturing method of the solid-state image sensing device according to claim 14,
The method of manufacturing a solid-state imaging device, wherein the hard mask is a single layer film made of a silicon oxide film, and the second layer conductive film is laminated on the hard mask. It is a manufacturing method of the solid-state image sensing device according to claim 15,
The method of manufacturing a solid-state imaging device, wherein the hard mask is a two-layer film of a silicon oxide film and a silicon nitride film, and the second-layer conductive film is laminated on the hard mask. It is a manufacturing method of the solid-state image sensing device according to any one of claims 1 to 16,
The step of forming the second electrode includes a step of forming a second layer conductive film and a step of planarizing the second layer conductive film by a resist etch back method. . It is a manufacturing method of the solid-state image sensing device according to any one of claims 1 to 16,
The step of forming the second electrode includes a step of forming a second layer conductive film and a step of planarizing the second layer conductive film by a CMP method.

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