JP2007522550A5 - - Google Patents

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Publication number
JP2007522550A5
JP2007522550A5 JP2006551090A JP2006551090A JP2007522550A5 JP 2007522550 A5 JP2007522550 A5 JP 2007522550A5 JP 2006551090 A JP2006551090 A JP 2006551090A JP 2006551090 A JP2006551090 A JP 2006551090A JP 2007522550 A5 JP2007522550 A5 JP 2007522550A5
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JP
Japan
Prior art keywords
memory access
direct memory
access device
information
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006551090A
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English (en)
Japanese (ja)
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JP4531773B2 (ja
JP2007522550A (ja
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Publication date
Priority claimed from US10/764,110 external-priority patent/US6920586B1/en
Application filed filed Critical
Publication of JP2007522550A publication Critical patent/JP2007522550A/ja
Publication of JP2007522550A5 publication Critical patent/JP2007522550A5/ja
Application granted granted Critical
Publication of JP4531773B2 publication Critical patent/JP4531773B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2006551090A 2004-01-23 2004-12-21 Ｄｍａデバイス用リアルタイムデバッグサポート及びその方法 Expired - Fee Related JP4531773B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/764,110 US6920586B1 (en) 2004-01-23 2004-01-23 Real-time debug support for a DMA device and method thereof
PCT/US2004/043491 WO2005073855A1 (en) 2004-01-23 2004-12-21 Real-time debug support for a dma device and method thereof

Publications (3)

Publication Number Publication Date
JP2007522550A JP2007522550A (ja) 2007-08-09
JP2007522550A5 true JP2007522550A5 (enExample) 2007-12-20
JP4531773B2 JP4531773B2 (ja) 2010-08-25

Family

ID=34740159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006551090A Expired - Fee Related JP4531773B2 (ja) 2004-01-23 2004-12-21 Ｄｍａデバイス用リアルタイムデバッグサポート及びその方法

Country Status (6)

Country Link
US (2) US6920586B1 (enExample)
JP (1) JP4531773B2 (enExample)
KR (1) KR101045475B1 (enExample)
CN (1) CN100440154C (enExample)
TW (1) TWI354885B (enExample)
WO (1) WO2005073855A1 (enExample)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6920586B1 (en) * 2004-01-23 2005-07-19 Freescale Semiconductor, Inc. Real-time debug support for a DMA device and method thereof
EP1899825B1 (en) * 2005-06-30 2009-07-22 Freescale Semiconductor, Inc. Device and method for controlling multiple dma tasks
US20090125647A1 (en) * 2005-06-30 2009-05-14 Citibank, N.A. Device And Method For Executing A DMA Task
JP4598858B2 (ja) * 2005-06-30 2010-12-15 フリースケール セミコンダクター インコーポレイテッド ダイレクトメモリアクセスタスク要求のアービトレーションを行うためのデバイスおよび方法
JP2009510543A (ja) * 2005-06-30 2009-03-12 フリースケール セミコンダクター インコーポレイテッド Ｄｍａタスクの実行を制御するためのデバイスおよび方法
US8054752B2 (en) * 2005-12-22 2011-11-08 Intuitive Surgical Operations, Inc. Synchronous data communication
US7757028B2 (en) * 2005-12-22 2010-07-13 Intuitive Surgical Operations, Inc. Multi-priority messaging
US7756036B2 (en) * 2005-12-22 2010-07-13 Intuitive Surgical Operations, Inc. Synchronous data communication
US7865704B2 (en) 2006-03-29 2011-01-04 Freescale Semiconductor, Inc. Selective instruction breakpoint generation based on a count of instruction source events
US8160084B2 (en) * 2006-09-22 2012-04-17 Nokia Corporation Method for time-stamping messages
US7958401B2 (en) * 2008-07-25 2011-06-07 Freescale Semiconductor, Inc. Debug trace messaging with one or more characteristic indicators
US8402258B2 (en) 2008-07-25 2013-03-19 Freescale Semiconductor, Inc. Debug message generation using a selected address type
US8024620B2 (en) * 2008-07-25 2011-09-20 Freescale Semiconductor, Inc. Dynamic address-type selection control in a data processing system
US8250250B2 (en) * 2009-10-28 2012-08-21 Apple Inc. Using central direct memory access (CDMA) controller to test integrated circuit
US8638792B2 (en) * 2010-01-22 2014-01-28 Synopsys, Inc. Packet switch based logic replication
US8397195B2 (en) * 2010-01-22 2013-03-12 Synopsys, Inc. Method and system for packet switch based logic replication
JP5528939B2 (ja) * 2010-07-29 2014-06-25 ルネサスエレクトロニクス株式会社 マイクロコンピュータ
US8713370B2 (en) * 2011-08-11 2014-04-29 Apple Inc. Non-intrusive processor tracing
US9256399B2 (en) * 2013-06-27 2016-02-09 Atmel Corporation Breaking program execution on events
US9645870B2 (en) 2013-06-27 2017-05-09 Atmel Corporation System for debugging DMA system data transfer
US9830245B2 (en) 2013-06-27 2017-11-28 Atmel Corporation Tracing events in an autonomous event system
US9552279B2 (en) * 2013-08-16 2017-01-24 Nxp Usa, Inc. Data bus network interface module and method therefor
US20160299859A1 (en) * 2013-11-22 2016-10-13 Freescale Semiconductor, Inc. Apparatus and method for external access to core resources of a processor, semiconductor systems development tool comprising the apparatus, and computer program product and non-transitory computer-readable storage medium associated with the method
US9419621B1 (en) 2015-09-18 2016-08-16 Freescale Semiconductor, Inc. System on chip and method of operating a system on chip
US11231987B1 (en) * 2019-06-28 2022-01-25 Amazon Technologies, Inc. Debugging of memory operations
US11099966B2 (en) * 2020-01-09 2021-08-24 International Business Machines Corporation Efficient generation of instrumentation data for direct memory access operations

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