TWI354885B - Real-time debug support for a dma device and metho - Google Patents

Real-time debug support for a dma device and metho Download PDF

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Publication number
TWI354885B
TWI354885B TW094100177A TW94100177A TWI354885B TW I354885 B TWI354885 B TW I354885B TW 094100177 A TW094100177 A TW 094100177A TW 94100177 A TW94100177 A TW 94100177A TW I354885 B TWI354885 B TW I354885B
Authority
TW
Taiwan
Prior art keywords
channel
debug
information
direct memory
memory access
Prior art date
Application number
TW094100177A
Other languages
English (en)
Chinese (zh)
Other versions
TW200602852A (en
Inventor
William C Moyer
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200602852A publication Critical patent/TW200602852A/zh
Application granted granted Critical
Publication of TWI354885B publication Critical patent/TWI354885B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/349—Performance evaluation by tracing or monitoring for interfaces, buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3485—Performance evaluation by tracing or monitoring for I/O devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3636—Debugging of software by tracing the execution of the program
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
TW094100177A 2004-01-23 2005-01-04 Real-time debug support for a dma device and metho TWI354885B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/764,110 US6920586B1 (en) 2004-01-23 2004-01-23 Real-time debug support for a DMA device and method thereof

Publications (2)

Publication Number Publication Date
TW200602852A TW200602852A (en) 2006-01-16
TWI354885B true TWI354885B (en) 2011-12-21

Family

ID=34740159

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094100177A TWI354885B (en) 2004-01-23 2005-01-04 Real-time debug support for a dma device and metho

Country Status (6)

Country Link
US (2) US6920586B1 (enExample)
JP (1) JP4531773B2 (enExample)
KR (1) KR101045475B1 (enExample)
CN (1) CN100440154C (enExample)
TW (1) TWI354885B (enExample)
WO (1) WO2005073855A1 (enExample)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6920586B1 (en) * 2004-01-23 2005-07-19 Freescale Semiconductor, Inc. Real-time debug support for a DMA device and method thereof
DE602005027003D1 (de) * 2005-06-30 2011-04-28 Freescale Semiconductor Inc Einrichtung und verfahren zur steuerung einer ausführung einer dma-task
EP1899827B1 (en) * 2005-06-30 2010-09-08 Freescale Semiconductor, Inc. Device and method for executing a dma task
US8572296B2 (en) * 2005-06-30 2013-10-29 Freescale Semiconductor, Inc. Device and method for arbitrating between direct memory access task requests
DE602005015632D1 (de) * 2005-06-30 2009-09-03 Freescale Semiconductor Inc Einrichtung und verfahren zur steuerung mehrerer dma-tasks
US7756036B2 (en) * 2005-12-22 2010-07-13 Intuitive Surgical Operations, Inc. Synchronous data communication
US8054752B2 (en) * 2005-12-22 2011-11-08 Intuitive Surgical Operations, Inc. Synchronous data communication
US7757028B2 (en) * 2005-12-22 2010-07-13 Intuitive Surgical Operations, Inc. Multi-priority messaging
US7865704B2 (en) 2006-03-29 2011-01-04 Freescale Semiconductor, Inc. Selective instruction breakpoint generation based on a count of instruction source events
US8160084B2 (en) * 2006-09-22 2012-04-17 Nokia Corporation Method for time-stamping messages
US8024620B2 (en) * 2008-07-25 2011-09-20 Freescale Semiconductor, Inc. Dynamic address-type selection control in a data processing system
US8402258B2 (en) 2008-07-25 2013-03-19 Freescale Semiconductor, Inc. Debug message generation using a selected address type
US7958401B2 (en) * 2008-07-25 2011-06-07 Freescale Semiconductor, Inc. Debug trace messaging with one or more characteristic indicators
US8250250B2 (en) * 2009-10-28 2012-08-21 Apple Inc. Using central direct memory access (CDMA) controller to test integrated circuit
US8638792B2 (en) * 2010-01-22 2014-01-28 Synopsys, Inc. Packet switch based logic replication
US8397195B2 (en) * 2010-01-22 2013-03-12 Synopsys, Inc. Method and system for packet switch based logic replication
JP5528939B2 (ja) * 2010-07-29 2014-06-25 ルネサスエレクトロニクス株式会社 マイクロコンピュータ
US8713370B2 (en) * 2011-08-11 2014-04-29 Apple Inc. Non-intrusive processor tracing
US9645870B2 (en) 2013-06-27 2017-05-09 Atmel Corporation System for debugging DMA system data transfer
US9830245B2 (en) 2013-06-27 2017-11-28 Atmel Corporation Tracing events in an autonomous event system
US9256399B2 (en) * 2013-06-27 2016-02-09 Atmel Corporation Breaking program execution on events
US9552279B2 (en) * 2013-08-16 2017-01-24 Nxp Usa, Inc. Data bus network interface module and method therefor
WO2015075505A1 (en) * 2013-11-22 2015-05-28 Freescale Semiconductor, Inc. Apparatus and method for external access to core resources of a processor, semiconductor systems development tool comprising the apparatus, and computer program product and non-transitory computer-readable storage medium associated with the method
US9419621B1 (en) 2015-09-18 2016-08-16 Freescale Semiconductor, Inc. System on chip and method of operating a system on chip
US11231987B1 (en) * 2019-06-28 2022-01-25 Amazon Technologies, Inc. Debugging of memory operations
US11099966B2 (en) * 2020-01-09 2021-08-24 International Business Machines Corporation Efficient generation of instrumentation data for direct memory access operations

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4688166A (en) 1984-08-03 1987-08-18 Motorola Computer Systems, Inc. Direct memory access controller supporting multiple input/output controllers and memory units
JPH0758475B2 (ja) * 1989-05-24 1995-06-21 株式会社日立製作所 端末装置のデータ収集システム
DE69033092D1 (de) * 1989-09-08 1999-06-10 Auspex Systems Inc Santa Clara Betriebssystemaufbau mit mehreren verarbeitungseinheiten
KR960016648B1 (ko) * 1993-12-29 1996-12-19 현대전자산업 주식회사 커먼 컨트롤 중복 스위치 방법
US6085037A (en) * 1996-09-13 2000-07-04 Concord Camera Corp. APS camera structure for film preloading
US6145007A (en) * 1997-11-14 2000-11-07 Cirrus Logic, Inc. Interprocessor communication circuitry and methods
US6145122A (en) 1998-04-27 2000-11-07 Motorola, Inc. Development interface for a data processor
US6032269A (en) * 1998-06-30 2000-02-29 Digi-Data Corporation Firmware recovery from hanging channels by buffer analysis
US6449732B1 (en) * 1998-12-18 2002-09-10 Triconex Corporation Method and apparatus for processing control using a multiple redundant processor control system
US6654801B2 (en) * 1999-01-04 2003-11-25 Cisco Technology, Inc. Remote system administration and seamless service integration of a data communication network management system
US6567933B1 (en) * 1999-02-19 2003-05-20 Texas Instruments Incorporated Emulation suspension mode with stop mode extension
US6615370B1 (en) * 1999-10-01 2003-09-02 Hitachi, Ltd. Circuit for storing trace information
US6816924B2 (en) * 2000-08-10 2004-11-09 Infineon Technologies North America Corp. System and method for tracing ATM cells and deriving trigger signals
US6470071B1 (en) 2001-01-31 2002-10-22 General Electric Company Real time data acquisition system including decoupled host computer
US20020165962A1 (en) * 2001-02-28 2002-11-07 Alvarez Mario F. Embedded controller architecture for a modular optical network, and methods and apparatus therefor
US7058858B2 (en) * 2001-04-23 2006-06-06 Hewlett-Packard Development Company, L.P. Systems and methods for providing automated diagnostic services for a cluster computer system
JP2003006003A (ja) * 2001-06-18 2003-01-10 Mitsubishi Electric Corp Ｄｍａコントローラおよび半導体集積回路
US20030195991A1 (en) * 2001-07-02 2003-10-16 Globespanvirata Incorporated Communications system using rings architecture
WO2003034225A2 (en) 2001-10-12 2003-04-24 Pts Corporation Debugging of processors
US6877114B2 (en) 2002-02-14 2005-04-05 Delphi Technologies, Inc. On-chip instrumentation
US6920586B1 (en) * 2004-01-23 2005-07-19 Freescale Semiconductor, Inc. Real-time debug support for a DMA device and method thereof

Also Published As

Publication number Publication date
CN100440154C (zh) 2008-12-03
JP4531773B2 (ja) 2010-08-25
WO2005073855A1 (en) 2005-08-11
KR101045475B1 (ko) 2011-06-30
US7287194B2 (en) 2007-10-23
US6920586B1 (en) 2005-07-19
KR20060126734A (ko) 2006-12-08
TW200602852A (en) 2006-01-16
US20050193256A1 (en) 2005-09-01
JP2007522550A (ja) 2007-08-09
CN1906589A (zh) 2007-01-31

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