JP2007513517A - 歪み半導体基板およびその製造プロセス - Google Patents

歪み半導体基板およびその製造プロセス Download PDF

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Publication number
JP2007513517A
JP2007513517A JP2006542572A JP2006542572A JP2007513517A JP 2007513517 A JP2007513517 A JP 2007513517A JP 2006542572 A JP2006542572 A JP 2006542572A JP 2006542572 A JP2006542572 A JP 2006542572A JP 2007513517 A JP2007513517 A JP 2007513517A
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Japan
Prior art keywords
layer
strained
trench
substrate
silicon
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JP2006542572A
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English (en)
Japanese (ja)
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JP2007513517A5 (https=
Inventor
エム． ペレラ マリオ
エス． チャン サイモン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2007513517A publication Critical patent/JP2007513517A/ja
Publication of JP2007513517A5 publication Critical patent/JP2007513517A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2924—Structures
    • H10P14/2925—Surface structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices

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JP2006542572A 2003-12-05 2004-10-26 歪み半導体基板およびその製造プロセス Pending JP2007513517A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/729,479 US7144818B2 (en) 2003-12-05 2003-12-05 Semiconductor substrate and processes therefor
PCT/US2004/035417 WO2005062357A1 (en) 2003-12-05 2004-10-26 Strained semiconductor substrate and processes therefor

Publications (2)

Publication Number Publication Date
JP2007513517A true JP2007513517A (ja) 2007-05-24
JP2007513517A5 JP2007513517A5 (https=) 2007-12-13

Family

ID=34633951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006542572A Pending JP2007513517A (ja) 2003-12-05 2004-10-26 歪み半導体基板およびその製造プロセス

Country Status (7)

Country Link
US (2) US7144818B2 (https=)
EP (1) EP1690288A1 (https=)
JP (1) JP2007513517A (https=)
KR (1) KR101086896B1 (https=)
CN (1) CN1890784B (https=)
TW (1) TWI369737B (https=)
WO (1) WO2005062357A1 (https=)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070015344A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US7598515B2 (en) * 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US7612366B2 (en) * 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US20070020833A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
US20070010040A1 (en) * 2003-06-26 2007-01-11 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
US20070063186A1 (en) * 2003-06-26 2007-03-22 Rj Mears, Llc Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layer
US20070063185A1 (en) * 2003-06-26 2007-03-22 Rj Mears, Llc Semiconductor device including a front side strained superlattice layer and a back side stress layer
US7531828B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US20070020860A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
US7144818B2 (en) * 2003-12-05 2006-12-05 Advanced Micro Devices, Inc. Semiconductor substrate and processes therefor
EP1905090A1 (en) * 2005-07-15 2008-04-02 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer and associated methods
DE102006007293B4 (de) 2006-01-31 2023-04-06 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zum Herstellen eines Quasi-Substratwafers und ein unter Verwendung eines solchen Quasi-Substratwafers hergestellter Halbleiterkörper
JP5055846B2 (ja) * 2006-06-09 2012-10-24 ソニー株式会社 半導体装置およびその製造方法
US9496227B2 (en) 2009-07-15 2016-11-15 Qualcomm Incorporated Semiconductor-on-insulator with back side support layer
US9466719B2 (en) 2009-07-15 2016-10-11 Qualcomm Incorporated Semiconductor-on-insulator with back side strain topology
US9390974B2 (en) 2012-12-21 2016-07-12 Qualcomm Incorporated Back-to-back stacked integrated circuit assembly and method of making
CN105097712A (zh) 2009-07-15 2015-11-25 斯兰纳半导体美国股份有限公司 具有背侧散热的绝缘体上半导体
US8921168B2 (en) 2009-07-15 2014-12-30 Silanna Semiconductor U.S.A., Inc. Thin integrated circuit chip-on-board assembly and method of making
CN102420253A (zh) * 2011-12-13 2012-04-18 清华大学 一种背面嵌入应变介质区的vdmos器件及其制备方法
US9515181B2 (en) 2014-08-06 2016-12-06 Qualcomm Incorporated Semiconductor device with self-aligned back side features
CN111883418B (zh) * 2020-08-05 2021-04-27 长江存储科技有限责任公司 半导体结构的制造方法
CN115332052B (zh) * 2022-08-15 2026-03-27 福建晶安光电有限公司 可降低形变应力的衬底加工方法及衬底

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03201536A (ja) * 1989-12-28 1991-09-03 Mitsubishi Electric Corp 半導体装置の製造方法
JPH0487338A (ja) * 1990-07-30 1992-03-19 Sharp Corp 半導体ウェーハーのゲッタリング方法
JPH05273591A (ja) * 1991-08-02 1993-10-22 Canon Inc 液晶画像表示装置及び半導体光学部材の製造方法
JP2004228273A (ja) * 2003-01-22 2004-08-12 Renesas Technology Corp 半導体装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58138033A (ja) * 1982-02-10 1983-08-16 Toshiba Corp 半導体基板及び半導体装置の製造方法
JPS61181931A (ja) 1985-02-08 1986-08-14 Fuji Electric Co Ltd 圧覚センサ
JP2803321B2 (ja) 1990-04-27 1998-09-24 株式会社デンソー 半導体感歪センサ
US5294559A (en) * 1990-07-30 1994-03-15 Texas Instruments Incorporated Method of forming a vertical transistor
JPH04245640A (ja) 1991-01-31 1992-09-02 Kawasaki Steel Corp 半導体基板の加工方法
JPH05198783A (ja) 1992-01-23 1993-08-06 Hitachi Ltd 半導体集積回路装置の製造方法
US6191432B1 (en) * 1996-09-02 2001-02-20 Kabushiki Kaisha Toshiba Semiconductor device and memory device
US20020046985A1 (en) * 2000-03-24 2002-04-25 Daneman Michael J. Process for creating an electrically isolated electrode on a sidewall of a cavity in a base
US6969875B2 (en) * 2000-05-26 2005-11-29 Amberwave Systems Corporation Buried channel strained silicon FET using a supply layer created through ion implantation
US6580124B1 (en) * 2000-08-14 2003-06-17 Matrix Semiconductor Inc. Multigate semiconductor device with vertical channel current and method of fabrication
US6835246B2 (en) * 2001-11-16 2004-12-28 Saleem H. Zaidi Nanostructures for hetero-expitaxial growth on silicon substrates
US6900521B2 (en) * 2002-06-10 2005-05-31 Micron Technology, Inc. Vertical transistors and output prediction logic circuits containing same
US6707106B1 (en) * 2002-10-18 2004-03-16 Advanced Micro Devices, Inc. Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer
US6803631B2 (en) * 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet
US7144818B2 (en) * 2003-12-05 2006-12-05 Advanced Micro Devices, Inc. Semiconductor substrate and processes therefor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03201536A (ja) * 1989-12-28 1991-09-03 Mitsubishi Electric Corp 半導体装置の製造方法
JPH0487338A (ja) * 1990-07-30 1992-03-19 Sharp Corp 半導体ウェーハーのゲッタリング方法
JPH05273591A (ja) * 1991-08-02 1993-10-22 Canon Inc 液晶画像表示装置及び半導体光学部材の製造方法
JP2004228273A (ja) * 2003-01-22 2004-08-12 Renesas Technology Corp 半導体装置

Also Published As

Publication number Publication date
CN1890784B (zh) 2013-04-24
US7144818B2 (en) 2006-12-05
US20050124170A1 (en) 2005-06-09
KR20060121136A (ko) 2006-11-28
CN1890784A (zh) 2007-01-03
TWI369737B (en) 2012-08-01
TW200525641A (en) 2005-08-01
KR101086896B1 (ko) 2011-11-25
WO2005062357A1 (en) 2005-07-07
US20050263753A1 (en) 2005-12-01
EP1690288A1 (en) 2006-08-16
US7265420B2 (en) 2007-09-04

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