JP2007324376A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which can release electric field concentration on corner portions on the surface of a second semiconductor layer without executing high-temperature thermal oxidation. <P>SOLUTION: In a method of forming an SOI structure on a bulk Si substrate 1 using an SBSI method, cleaning processing using a hydrofluoric acid is applied to the silicon substrate 1 to trim a support 9 (i.e. form a minute line), and subsequently, a silicon germanium layer 2 is etched with a nitrohydrofluoric acid to form a cavity portion between a silicon layer 3 and the silicon substrate 1. Since the trench corners 4 of the silicon layer 3 are exposed from below the support 9 in forming the cavity portion using the nitrohydrofluoric acid, the trench corners 4 are subtly etched and the corners can be rounded. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor substrate with SOI (Silicon).
The present invention relates to a technique for forming an On Insulator structure.

  Conventionally, an SOI structure is formed on the entire surface of a bulk silicon substrate, and a field effect transistor is formed on the SOI structure. A field effect transistor (hereinafter also referred to as “SOI transistor”) formed on an SOI structure has a junction capacitance (between the source / drain region and the substrate) as compared with a transistor formed directly on a bulk silicon substrate. (Capacity) is small. Therefore, the SOI transistor has significant advantages such as low power consumption and high speed operation.

Patent Document 1 and Non-Patent Document 1 disclose an SBSI (Separation by Bonding Si Islands) method in which an SOI transistor can be formed at low cost by partially forming an SOI layer on a bulk silicon substrate. Yes.
In the SBSI method, a silicon germanium (SiGe) layer and a silicon (Si) layer are epitaxially grown sequentially on a silicon substrate, and a hole for forming a support (that is, a support hole) is formed in the silicon substrate (as described in the explanation). For convenience, the selective etching step for forming the support hole is also referred to as first patterning).

  Next, a support film is formed on the silicon layer so as to fill the support hole. The support film is, for example, a silicon oxide film, and is formed by CVD (Chemical Vapor Deposition) or the like. Then, the support film, the silicon layer and the silicon germanium layer thereunder are selectively and selectively dry-etched to form a support body. Here, the region in which the silicon layer is covered by the support is an element region, and the other region is an element isolation region. (For convenience of explanation, a selective etching step for forming this support is performed. Also referred to as second patterning).

Next, the silicon germanium remaining under the support is wet-etched with, for example, hydrofluoric acid from the side surface side of the support in a plan view to form a cavity between the silicon layer and the silicon substrate. Then, an insulating layer such as SiO ₂ is embedded in the hollow portion to form a BOX (Buri
ed Oxide) layer is formed. Thereafter, the substrate surface is planarized to expose the silicon layer on the surface, thereby completing the SOI structure on the bulk silicon substrate.
JP 2005-354024 A T.A. Sakai et al. “Separation by Bonding Si Islands (SBSI) for LSI Applications”, Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004)

13 (a) and 13 (b) are schematic views showing the problems associated with the conventional example, FIG. 13 (a) is a schematic plan view, and FIG. 13 (b) is a BB ′ disconnection in FIG. 13 (a). FIG.
In the SBSI method, the first patterning for forming the support hole 105 and the second patterning for selectively etching the support film allow the element around the element region (that is, the silicon layer having the SOI structure). A trench 113 serving as an isolation region is formed. The trench 1
13 is embedded in the insulating layer such as SiO _2. For example, in the case where a MOS transistor is formed in the element region, the gate electrode 121 is formed so as to straddle the corner (ie, trench corner) 104 of the surface of the silicon 103 layer formed by the second patterning.

  However, since the second patterning is performed by dry etching, the trench corner 104 is formed in a sharp shape at a substantially right angle in a sectional view. For this reason, when a voltage is applied to the gate electrode 121, the electric field tends to concentrate on the trench corner 104, and a parasitic MOS is formed in this portion, and the insulating reliability of the gate insulating film 121 may be deteriorated in this portion. (Problem 1).

  As a countermeasure for avoiding this problem 1, after the silicon germanium layer 102 is wet-etched, the silicon substrate 101 is subjected to high-temperature thermal oxidation to round the trench corner (hereinafter also referred to as “corner”) 104. There is a way to do it. However, this method requires a high temperature of about 1100 ° C., and there is a problem that the silicon layer 103 having the SOI structure is reduced by thermal oxidation. Further, due to the difference in thermal expansion coefficient between the silicon layer (hereinafter also referred to as “second semiconductor layer”) 103 and the silicon oxide film at a high temperature, unintentional stress is generated between these films, and the device is There was also a risk of deformation (Problem 2).

  The present invention has been made to solve the above problems 1 and 2. Manufacturing of a semiconductor device in which electric field concentration at the corner of the surface of the second semiconductor layer can be alleviated without performing high-temperature thermal oxidation. The purpose is to provide a method.

[Invention 1] In order to achieve the above object, a method of manufacturing a semiconductor device of Invention 1 includes a step of forming a single-crystal first semiconductor layer on a semiconductor substrate, and a single-crystal first semiconductor layer on the first semiconductor layer. Forming a second semiconductor layer; forming a first groove through the second semiconductor layer and the first semiconductor layer to expose the semiconductor substrate; and filling the first groove and the second semiconductor layer. Forming a support film on the semiconductor substrate so as to cover the semiconductor layer, and sequentially etching the support film, the second semiconductor layer, and the first semiconductor layer, Forming a support from the support film and forming a second groove exposing the first semiconductor layer from below the second semiconductor layer; and a surface of the second semiconductor layer located at an edge of the second groove Etching the corners of the The semiconductor substrate and the second semiconductor are etched by etching the first semiconductor layer through the second groove under a specific etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer. And a step of forming a cavity between the layers and a step of forming an insulating layer in the cavity.
With such a configuration, the corner of the surface of the second semiconductor layer located at the edge of the second groove is rounded (that is, the corner is rounded) without subjecting the substrate to high-temperature thermal oxidation at around 1100 ° C. be able to. Therefore, it is possible to alleviate the electric field concentration at the corners while avoiding the problem of device deformation due to high temperature thermal oxidation, and to improve the reliability of the gate insulating film.

[Invention 2] The method for manufacturing a semiconductor device according to Invention 2 is the method for manufacturing a semiconductor device according to Invention 1, wherein in the step of etching the corner portion, the support is trimmed to form the second semiconductor surface from below the support. The corner portion is exposed, and then the corner portion is etched using the trimmed support as a mask. Here, “trimming the support” is a process of thinning the support in plan view.
With such a configuration, when the corner portion of the second semiconductor surface is rounded, only the corner portion is etched, and the second semiconductor layer surface other than the corner portion (that is, the region covered with the support). Can be etched as little as possible.

[Invention 3] The semiconductor device manufacturing method of Invention 3 is the semiconductor device manufacturing method of Invention 2, wherein the first semiconductor layer is a silicon germanium layer, the second semiconductor layer is a silicon layer, and is trimmed. The step of etching the corner using the support as a mask and the step of forming the cavity are simultaneously performed by wet etching using hydrofluoric acid.
With such a configuration, the manufacturing process of the semiconductor device can be shortened, and the manufacturing cost can be reduced.

[Invention 4, 5] The method of manufacturing a semiconductor device of Invention 4 is the method of manufacturing a semiconductor device of Invention 1, wherein the step of etching the corner portion is the step of forming the second groove or the second groove. The wet etching is performed after the formation and before the formation of the cavity, and the wet etching uses a chemical that preferentially etches the (111) plane of the second semiconductor layer. Is.
According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein the first semiconductor layer is a silicon germanium layer, the second semiconductor layer is a silicon layer, and the chemical solution includes the following a): A liquid comprising any one of c) or any combination of a) to c),

a) HF + (COOH) ₂
b) HF + K ₂ Cr ₂ O ₇
c) HF + Cr ₂ O ₃ is used.

  According to inventions 4 and 5, since the etched surface of the second semiconductor layer (for example, silicon layer) is the (111) surface, the corner of the silicon layer is formed in a gentle shape with no sharp corners. Can do. Therefore, it is possible to reduce the electric field concentration at the corner.

Embodiments of the present invention will be described below with reference to the drawings.
(1) First Embodiment FIGS. 1 to 9 are schematic views showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Specifically, FIGS. 1A to 8A and 9A are schematic plan views, and FIGS. 1B to 8B are schematic views taken along the line AA 'in FIG. 1A. It is sectional drawing. Moreover, each figure (c) of FIGS. 3-8 is a schematic cross section which follows the BB 'broken line in the figure (a).

1A and 1B, first, a silicon germanium (SiGe) layer 2 as a first semiconductor layer is formed on a silicon substrate 1 which is a bulk silicon wafer, and a second semiconductor layer is formed thereon. A silicon (Si) layer 3 is formed. Each of the silicon germanium layer 2 and the silicon layer 3 is a single crystal and is formed by epitaxial growth.
Next, a region for forming the support hole 5 is opened, and a photoresist film R1 covering the other region is formed on the silicon layer 3. Then, using the photoresist film R1 as a mask, the silicon layer 3 and the silicon germanium layer 2 are sequentially etched to expose the surface of the silicon substrate 1, and the support hole 5 is formed. In FIG. 1A, a region sandwiched from both sides by the support hole 5 (in plan view) becomes a region for forming an element (that is, an element region).

  Although not shown, a base oxide film, an antioxidant film, or the like may be formed on the silicon layer 3 before forming the photoresist film R1 for forming the support hole. The base oxide film is, for example, a silicon oxide film, and can be formed by thermal oxidation of the silicon layer. The antioxidant film is a silicon nitride film, for example, and can be formed by CVD. When the antioxidant film is a silicon nitride film, it not only functions as a film for preventing the oxidation of the silicon layer 3, but can also function as a stopper layer for a planarization process by CMP (chemical mechanical polish). .

After the support hole 5 is formed, the photoresist film R1 is removed from the silicon substrate 1 by ashing using oxygen plasma or the like.
Next, as shown in FIGS. 2A and 2B, a support film 7 is formed on the entire upper surface of the silicon substrate 1 so as to fill the support hole 5 and cover the silicon layer 3. The support film 7 is a silicon oxide film, for example, and is formed by, for example, CVD. Then, as shown in FIGS. 3A to 3C, a photoresist film R2 is formed on the support film. The shape of the photoresist film R2 in plan view (that is, the planar shape) is, for example, a shape that covers the element region across the two support hole 5.

  Next, the support film, the silicon layer 3, and the silicon germanium layer 2 are sequentially dry etched using the photoresist film R2 as a mask. As shown in FIGS. 3A to 3C, by this etching, a support 9 made of a support film is formed on the silicon substrate 1, and the silicon substrate 1 is placed around the support 9 on the bottom surface. A trench 13 is formed. 3A to 3C, the silicon layer 3 and the silicon germanium layer 2 are exposed on the side surface 15 (facing the trench 13) below the support 9. After the trench 13 is formed, the photoresist film is removed from the support 9 as shown in FIGS.

  Next, as shown in FIGS. 5A to 5C, the support 9 is trimmed (that is, thinned) by a cleaning process using, for example, hydrofluoric acid (HF) and positioned at the edge of the trench 13. The corners (ie, trench corners) 4 on the surface of the silicon layer 3 are exposed from below the support 9. Then, the silicon germanium layer 2 is selectively etched and removed by bringing an etching solution such as hydrofluoric acid into contact with the silicon layer 3 and the silicon germanium layer 2 from the side surface 15 facing the trench 13.

  Thereby, as shown in FIGS. 6A to 6C, a cavity 10 is formed between the silicon substrate 1 and the silicon layer 3. In wet etching using hydrofluoric acid, silicon has a lower etching selectivity than silicon germanium (ie, silicon germanium is easier to etch than silicon), and only the silicon germanium layer is selectively etched leaving the silicon layer. And can be removed. After the formation of the cavity 10, the silicon layer 3 is completely supported by the support 9.

  In addition, as shown in FIGS. 6A to 6C, in this wet etching step, the support 9 is trimmed before the etching process is started, and the above-described trimming is performed from below the support 9 by the trimming. The trench corner 4 is exposed. Here, in wet etching using hydrofluoric acid, not only silicon germanium but also silicon is slightly etched. Therefore, in this wet etching process, the trench corner 4 of the silicon layer 3 exposed from under the support 9 is also slightly etched and the corners are rounded.

Subsequently, as shown in FIGS. 7A to 7C, the silicon substrate 1 is thermally oxidized to form a buried insulating layer (BOX layer) 11 made of a SiO ₂ film in the cavity 10. The formation of the buried insulating layer 11 is not limited to the thermal oxidation of the silicon substrate 1, and can be performed by CVD. Next, an insulating film for element isolation is formed on the entire upper surface of the silicon substrate 1. The trench 13 is buried by the formation of this insulating film. Further, when the filling of the cavity portion by the buried insulating layer 11 is insufficient, the filling of the cavity portion 10 is complemented by the formation of the insulating film. Thereafter, the entire upper surface of the silicon substrate 1 is planarized by CMP or the like, and the insulating film and a part of the support 9 are removed.

Thereby, as shown in FIGS. 8A to 8C, the upper surface of the silicon layer 3 is exposed, and the silicon layer 3 is element-isolated by the buried insulating layer 11 and the insulating film 12 (SOI structure). Is completed. As described above, when a silicon nitride film is formed as an antioxidant film on the silicon layer 3, the antioxidant film functions as a stopper layer in this planarization process. It is possible to prevent dishing that does not occur. Further, when a silicon nitride film is used as the stopper layer, it is removed by wet etching using, for example, hot phosphoric acid after the planarization process, and then the underlying oxide film (SiO 2) by wet etching using, for example, dilute hydrofluoric acid. ₍₂ films) may be removed.

  Thereafter, for example, a MOS transistor is formed in the SOI silicon layer 3. That is, the surface of the silicon layer is thermally oxidized to form a gate insulating film. Then, a polycrystalline silicon layer is formed on the gate insulating film by a method such as CVD. Thereafter, the polycrystalline silicon layer is patterned using a photolithography technique. Thereby, the gate electrode 21 is formed as shown in FIG.

Next, by using the gate electrode 21 as a mask, impurities such as As, P, and B are ion-implanted into the silicon layer 3 to form LDD layers each composed of a low-concentration impurity introduction layer in the silicon layer 3 on both sides of the gate electrode 21. Form.
Further, an insulating layer is formed on the silicon layer 3 on which the LDD layer is formed by a method such as CVD, and the insulating layer is etched back using dry etching such as RIE (reactive ion etching). Thereby, a sidewall is formed on the sidewall of the gate electrode. Then, impurities such as As, P, and B are ion-implanted into the silicon layer 3 using the gate electrode 21 and the sidewall as a mask, so that a source layer made of a high concentration impurity introduction layer is formed in each of the silicon layers 3 on both sides of the gate electrode 21. A drain layer is formed. Thus, a MOS transistor is completed.

Thus, according to the first embodiment of the present invention, the trench corner 4 of the silicon layer 3 is exposed from below the support 9 when the cavity 10 is formed using hydrofluoric acid. 4 is slightly etched to round its corners. That is, compared with the prior art, the corners of the trench corner 4 of the silicon layer 3 can be rounded without subjecting the silicon substrate 1 to high-temperature thermal oxidation at around 1100 ° C. Therefore, the electric field concentration in the trench corner 4 can be relaxed while avoiding the problem of device deformation due to high temperature thermal oxidation, and the reliability of the gate insulating film can be improved.
Further, since the support 9 after trimming functions as a mask, when the trench corner 4 is cut off, only the trench corner 4 is etched, and other than the trench corner 4 (that is, covered with the support 9). It is possible to prevent the surface of the silicon layer 3 in the region) from being etched as much as possible.

(2) Second Embodiment FIGS. 10 to 12 are schematic views showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention. (A) of each figure of FIGS. 10-12 is a schematic cross section which follows the AA 'broken line of a top view similarly to 1st Embodiment. Moreover, (b) of each figure of FIGS. 10-12 is a schematic cross section which follows the BB 'broken line of a top view similarly to 1st Embodiment. 10 to 12, parts having the same configurations and functions as those in FIGS. 1 to 9 described in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the second embodiment, as shown in FIGS. 10A and 10B, the support 9 is formed by dry etching the support film using the photoresist film R2 as a mask. At this time, the underlying silicon layer 3 is over-etched, and the silicon layer 3 is shaved to some extent. Next, as shown in FIGS. 11A and 11B, a portion (hereinafter simply referred to as “trench corner”) that becomes a trench corner of the silicon layer 3 by isotropic wet etching or anisotropic wet etching. ) 4 is etched.

In the case of isotropic wet etching, for example, a liquid composed of any one of A) to D) below or any combination of A) to D) is used as an etchant.
A) Fluoric acid B) Fluoric acid + acetic acid C) Fluoric acid D) Fluoric acid + ammonium fluoride

In the case of anisotropic wet etching, a chemical that preferentially etches the (111) plane of the silicon layer 3 is used as an etchant. Examples of such a chemical solution include a liquid composed of any one of the following a) to c) or any combination of a) to c).
a) HF + (COOH) ₂
b) HF + K ₂ Cr ₂ O ₇
c) HF + Cr ₂ O ₃

  After the corners of the trench corner 4 are cut by such an isotropic wet etch or anisotropic wet etch, as shown in FIGS. 12A and 12B, the remaining portions are left using the photoresist film R2 as a mask. The trenches 13 are formed by dry etching the silicon layer 3 and the silicon germanium layer 2. Since the subsequent steps are the same as those in the first embodiment, for example, the description thereof is omitted.

  Thus, according to the second embodiment of the present invention, it is possible to chamfer the trench corner 4 without trimming the support 9. In particular, when chamfering is performed using an anisotropic etchant as exemplified in the above (a) to (c), the etched surface of the silicon layer is the (111) plane. Here, the (111) plane is a plane orientation that intersects the (100) plane or the (110) plane at a gentle angle, and the plane orientation of the surface of the silicon substrate 1 or the surface of the silicon layer 3 is usually (100) plane. It has become. Therefore, the trench corner 4 can be formed in a gentle shape with not so sharp corners, and the electric field concentration at the trench corner 4 can be reduced.

(3) Third Embodiment In the second embodiment, the trench corner 4 is etched by isotropic wet etching or anisotropic wet etching in the process of forming the trench 13 (that is, before the trench 13 is completed). Explained when to do. However, the timing for performing the anisotropic wet etching is not limited to this.

  For example, as shown in FIGS. 3A to 3C, anisotropic wet etching may be performed on the silicon substrate 1 after the trench 13 is completed. For the etchant (chemical solution) used in the anisotropic wet etching, for example, a liquid composed of any one of the above a) to c) or any combination of a) to c) is used. Even in such a configuration, the surface to be etched of the silicon layer is the (111) plane, so that the shape of the trench corner 4 after chamfering is formed as shown in FIGS. 12 (a) and 12 (b). The corners can be formed in a gentle shape with no sharp edges, and the electric field concentration at the trench corner 4 can be reduced.

  In the first to third embodiments, the silicon substrate 1 corresponds to the “semiconductor substrate” of the present invention, the silicon germanium layer 2 corresponds to the “first semiconductor layer” of the present invention, and the silicon layer 3 corresponds to the present invention. To the “second semiconductor layer”. The support hole 5 still corresponds to the “first groove” of the present invention, and the trench 13 corresponds to the “second groove” of the present invention. Further, the buried insulating layer 11 corresponds to the “insulating layer” of the present invention. Further, the trench corner 4 corresponds to “a corner portion of the surface of the second semiconductor layer located on the edge of the second groove” of the present invention.

  In the first to third embodiments, the “semiconductor substrate” is a bulk silicon wafer, the material of the “first semiconductor layer” is silicon germanium, and the “second semiconductor layer” is silicon. explained. However, the material of the “semiconductor substrate”, “first semiconductor layer”, and “second semiconductor layer” of the present invention is not limited to this. For example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, A combination selected from InP, GaP, GaN, ZnSe, or the like can be used.

FIG. 3 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 1). FIG. 6 is a diagram (No. 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 3A and 3B are diagrams illustrating the method for manufacturing a semiconductor device according to the first embodiment (No. 3). 4A and 4B are diagrams illustrating the method for fabricating a semiconductor device according to the first embodiment (No. 4). FIG. 5 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 5). 6A and 6B are diagrams illustrating the method for manufacturing a semiconductor device according to the first embodiment (No. 6). FIG. 7 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 7). FIG. 8 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 8). FIG. 9 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 9). The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment (the 1). FIG. 6 is a view (No. 2) showing the method for manufacturing a semiconductor device according to the second embodiment. FIG. 9 is a diagram (No. 3) for illustrating a method for manufacturing a semiconductor device according to the second embodiment. The figure which shows the trouble which concerns on a prior art example.

Explanation of symbols

  1 silicon (Si) substrate, 2 silicon germanium (SiGe) layer, 3 silicon (Si) layer, 4 trench corner, 5 support hole, 7 support film, 9 support, 10 cavity, 11 buried insulating layer, 12 Insulating film, 21 gate electrode, R1, R2 photoresist film

Claims (5)

Forming a single-crystal first semiconductor layer on a semiconductor substrate;
Forming a single-crystal second semiconductor layer on the first semiconductor layer;
Forming a first groove through the second semiconductor layer and the first semiconductor layer to expose the semiconductor substrate;
Forming a support film on the semiconductor substrate so that the first groove is embedded and the second semiconductor layer is covered;
A support is formed from the support film by selectively etching the support film, the second semiconductor layer, and the first semiconductor layer sequentially, and the first semiconductor is formed from below the second semiconductor layer. Forming a second groove exposing the layer;
Etching a corner of the surface of the second semiconductor layer located at the edge of the second groove;
The semiconductor substrate and the second semiconductor are etched by etching the first semiconductor layer through the second groove under a specific etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer. Forming a cavity between the layers;
And a step of forming an insulating layer in the cavity. In the step of etching the corner,
Trimming the support to expose the corners of the second semiconductor surface from below the support,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the corner is etched using the trimmed support as a mask. The first semiconductor layer is a silicon germanium layer;
The second semiconductor layer is a silicon layer;
3. The semiconductor according to claim 2, wherein the step of etching the corner portion using the trimmed support as a mask and the step of forming the cavity portion are simultaneously performed by wet etching using hydrofluoric acid. Device manufacturing method. Etching the corner is performed by wet etching after forming the second groove or after forming the second groove and before forming the cavity,
The method for manufacturing a semiconductor device according to claim 1, wherein the wet etching uses a chemical that preferentially etches the (111) plane of the second semiconductor layer. The first semiconductor layer is a silicon germanium layer;
The second semiconductor layer is a silicon layer;
The chemical solution is a liquid comprising any one of the following a) to c), or any combination of a) to c):
a) HF + (COOH) ₂
b) HF + K ₂ Cr ₂ O ₇
c) HF + Cr ₂ O ₃
The method of manufacturing a semiconductor device according to claim 4, wherein:

Images