JP2007324290A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which can release electric field concentration in corner portions of the surface of a second semiconductor layer positioned on the peripheral edge of a first trench. <P>SOLUTION: In a method of forming an SOI structure on a bulk Si substrate 1 using an SBSI method, support holes 5 for exposing the Si substrate 1 through an Si layer 3 and an SiGe layer 2, thermal oxidation films 6a are subsequently formed on the corner portions on the surface of the Si layer 3 positioned on the peripheral edge of the support holes 5, and after that, a support film 7 is formed on the Si substrate 1 so that the support holes 5 are filled and the Si layer 3 is covered. Since the corners of the surface of the silicon layer 3 positioned on the peripheral edge of the support holes 5 can be rounded with this configuration, even if a gate electrode is arranged immediately above each of the corner portions of the silicon layer 3, the electric field concentration of the corner portions can be released. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor substrate with SOI (Silicon).
The present invention relates to a technique for forming an On Insulator structure.

A field effect transistor formed on an SOI substrate has a smaller junction capacitance (capacitance between the source / drain region and the substrate) than that formed on a bulk silicon substrate. It has great advantages such as high speed and high speed operation.
In general, an SOI substrate having an SOI structure formed on the entire surface of a bulk silicon substrate is prepared, and transistors are sequentially formed on the SOI structure, and this SOI structure is formed in a portion where the SOI structure is not required. It has been done to remove.

Patent Document 1 and Non-Patent Document 1 disclose an SBSI (Separation by Bonding Si Islands) method in which an SOI transistor can be formed at low cost by partially forming an SOI layer on a bulk silicon substrate. Yes.
In the SBSI method, first, a silicon germanium (SiGe) layer and a silicon (Si) layer are epitaxially grown on a silicon substrate, and a hole (that is, a support hole) for forming a support is formed therein. After an oxide film or the like is formed thereon, the peripheral oxide film, silicon layer, and silicon germanium layer are dry-etched so as to obtain an element region shape.

When the silicon germanium layer is selectively etched with hydrofluoric acid, the silicon layer is supported by the support and a cavity is formed under the silicon layer. And in this hollow portion, SiO ₂
By embedding an insulating layer such as BOX (Buried)
Oxide) layer is formed. Then, the SOI structure is obtained on the bulk silicon substrate by planarizing the substrate surface to expose the silicon layer on the surface.
JP 2005-354024 A T.A. Sakai et al. “Separation by Bonding Si Islands (SBSI) for LSI Applications”, Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004)

  When the gate electrode is formed on the exposed silicon layer of the SOI structure, a parasitic MOS is formed at the corner of the silicon layer surface, and the insulation reliability of the gate insulating film may be deteriorated at the corner. In general, in the manufacturing process of a semiconductor device having STI (Shallow Trench Isolation), it is possible to round the corners on the surface of the silicon layer by performing high-temperature heat treatment on the substrate after forming the trench.

  However, in the SBSI method, when high-temperature heat treatment is performed, there is a problem that germanium (Ge) in the silicon germanium layer is diffused into adjacent layers. Although it is possible to round the corners on the surface of the silicon layer by performing a heat treatment after etching the silicon germanium layer, at this stage, a part of the corners is covered with the support, and the support is covered with the support. The cracked corners could not be rounded even if heat treatment was performed. This point will be specifically described with reference to FIG.

  15A and 15B show steps in the process of manufacturing a semiconductor device according to a conventional example, FIG. 15A is a schematic plan view, and FIG. 15B is a schematic view taken along the line CC 'in FIG. It is sectional drawing. A silicon germanium layer 102 and a silicon layer 103 are epitaxially grown on the silicon substrate 101, and a hole (that is, a support hole) 105 for forming a support is formed therein. At this time, corners 110 on the surface of the silicon layer 103 exist at the periphery of the support hole 105. After that, a support 104 that fills the support hole 105 and covers the silicon layer 103 is formed. A region covered by the support 104 and positioned between the support holes 105 is a portion that becomes an element region.

Here, since the corner portion 110 of the silicon layer 103 is covered with the support 104, even if the silicon germanium layer 102 is etched and then subjected to heat treatment, the corner portion 110 cannot be rounded. Therefore, when the gate electrode 106 as shown by a two-dot chain line in FIG. 15A is arranged in a direction straddling two support body holes (hereinafter also referred to as “first groove”) 105 in a later step. , The electric field tends to concentrate on the corners 110 of the silicon layer (hereinafter also referred to as “second semiconductor layer”) 103, which may cause a leakage current.
The present invention has been made to solve the above-described problems, and provides a method for manufacturing a semiconductor device that can alleviate electric field concentration at the corner of the surface of the second semiconductor layer located at the periphery of the first groove. Objective.

[Invention 1] In order to achieve the above object, a method of manufacturing a semiconductor device of Invention 1 includes a step of forming a single-crystal first semiconductor layer on a semiconductor substrate, Forming a second semiconductor layer; forming a first groove through the second semiconductor layer and the first semiconductor layer to expose the semiconductor substrate; and the first groove positioned at a periphery of the first groove. (2) forming a thermal oxide film on the corner of the semiconductor layer surface, and forming the thermal oxide film on the corner, and then filling the first groove and covering the second semiconductor layer. Forming a support film on the semiconductor substrate; and sequentially and selectively etching the support film, the second semiconductor layer, and the first semiconductor layer to form the first film from below the second semiconductor layer. Forming a second groove exposing the semiconductor layer; and Etching the first semiconductor layer through the second groove under a specific etching condition that allows the first semiconductor layer to be etched more easily than the body layer, so that the semiconductor substrate and the second semiconductor layer are The method includes a step of forming a cavity portion therebetween, and a step of forming an insulating layer in the cavity portion.

  With such a configuration, the corner of the surface of the second semiconductor layer located at the periphery of the first groove can be rounded by forming the thermal oxide film. Therefore, even when the gate electrode is disposed immediately above the corner of the second semiconductor layer, the electric field concentration at the corner can be reduced. As a result, the reliability of the gate insulating film can be increased, which can contribute to prevention of leakage current.

[Invention 2] The method for manufacturing a semiconductor device according to Invention 2 is the method for manufacturing a semiconductor device according to Invention 1, wherein in the step of forming the first groove, the second semiconductor layer and the second semiconductor layer are formed using the patterned photoresist film as a mask. In the step of etching the first semiconductor layer to form the first groove, and forming the thermal oxide film on the corner of the second semiconductor layer surface located at the periphery of the first groove, the photoresist film is formed Trimming to expose the corner from below the photoresist film, and then amorphizing the corner by ion implantation of impurities into the second semiconductor layer using the trimmed photoresist film as a mask, The thermal oxide film is formed on the amorphous corners by subjecting the semiconductor substrate to a thermal oxidation treatment. That.

Here, an amorphous semiconductor layer tends to react with oxygen (that is, easily oxidize) rather than a single crystal semiconductor layer.
According to the semiconductor device manufacturing method of the second aspect of the present invention, the thermal oxide film is formed only on the corner portion (that is, the amorphized portion) on the surface of the second semiconductor layer, and the second semiconductor layer (that is, the other region) It is possible to avoid forming a thermal oxide film as much as possible on the single crystal portion).

[Invention 3] The semiconductor device manufacturing method of Invention 3 is the semiconductor device manufacturing method of Invention 2, wherein the first semiconductor layer is silicon germanium (SiGe), and the second semiconductor layer is silicon (Si). The temperature of the thermal oxidation treatment is set to 750 ° C. or lower.
With such a configuration, it is possible to sufficiently suppress the diffusion of Ge from the first semiconductor layer to the semiconductor substrate or the second semiconductor layer side. For example, an unintended characteristic variation (due to Ge) of the transistor is caused. It is possible to prevent.

[Invention 4] A method of manufacturing a semiconductor device of Invention 4 includes a step of forming a single-crystal first semiconductor layer on a semiconductor substrate, and a step of forming a single-crystal second semiconductor layer on the first semiconductor layer; Forming a first groove through the second semiconductor layer and the first semiconductor layer to expose the semiconductor substrate, and filling the first groove and covering the second semiconductor layer. Forming a support film on the semiconductor substrate; and sequentially and selectively etching the support film, the second semiconductor layer, and the first semiconductor layer to form the first film from below the second semiconductor layer. A step of forming a second groove exposing the semiconductor layer, and the first semiconductor layer through the second groove under a specific etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer. By etching A step of forming a cavity between the conductor substrate and the second semiconductor layer; and a step of forming an insulating layer in the cavity, wherein the step of forming the first groove includes patterning a photoresist film. The second semiconductor layer is isotropically etched from the bottom of the second semiconductor layer to the extent that the first semiconductor layer is not exposed, and the second semiconductor layer and the mask are further masked using the photoresist film as a mask. The first groove is formed by anisotropically etching the first semiconductor layer.

  With such a configuration, in the process of forming the first groove, a portion corresponding to the corner of the surface of the second semiconductor layer located at the periphery of the first groove (hereinafter also referred to as “corner”). It can be formed into a tapered shape constituted by a gentle concave surface, not an angular shape. Therefore, even when the gate electrode is disposed immediately above the corner of the second semiconductor layer, the electric field concentration at the corner can be reduced. As a result, the reliability of the gate insulating film can be increased, which can contribute to prevention of leakage current.

Embodiments of the present invention will be described below with reference to the drawings.
(1) First Embodiment FIGS. 1 to 13 are schematic views showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. In detail, each figure (a) of Drawing 1-Drawing 13 is a schematic plan view, and each figure (b) is a schematic sectional view which meets an AA 'broken line in the figure (a). FIG. 14 is a schematic cross-sectional view taken along the line BB ′ in FIG.

1A and 1B, first, a silicon germanium (SiGe) layer 2 as a first semiconductor layer is formed on a silicon substrate 1 which is a bulk silicon wafer, and a second semiconductor layer is formed thereon. A silicon (Si) layer 3 is formed. Each of the silicon germanium layer 2 and the silicon layer 3 is a single crystal and is formed by epitaxial growth.
Next, a photoresist film 4 is formed on the silicon layer 3 so as to open a region for forming the support hole and cover the other region. Then, using the photoresist film 4 as a mask, the silicon layer 3 and the silicon germanium layer 2 are sequentially etched to expose the surface of the silicon substrate 1,
A support hole 5 is formed. As shown in FIG. 1A, in a plan view, a region sandwiched from both sides by the support hole 5 is a region for forming an element (that is, an element region).

  Although not shown, a base oxide film, an antioxidant film or the like may be formed on the silicon layer 3 before forming the photoresist film 4. The base oxide film is, for example, a silicon oxide film, and can be formed by thermal oxidation of the silicon layer. Further, the antioxidant film is, for example, a silicon nitride film, and can be formed by CVD (chemical vapor deposition). When the antioxidant film is a silicon nitride film, in addition to the function of preventing the silicon layer 3 from being oxidized, it can also function as a stopper layer for a planarization process by CMP (chemical mechanical polish).

Next, as shown in FIGS. 2A and 2B, the photoresist film 4 is trimmed (that is, thinned) by an ashing process using oxygen plasma or the like and positioned at the periphery of the support hole 5. The corner 6 on the surface of the silicon layer 3 is exposed from below the photoresist film 4.
Next, as shown in FIGS. 3A and 3B, for example, argon (Ar) is ion-implanted toward the surface of the silicon substrate 1 using the trimmed photoresist film 4 as a mask. As a result, argon is ion-implanted into the corner 6 exposed from below the photoresist film 4, and its crystal structure is made amorphous (ie, amorphous). The impurity to be ion-implanted in this amorphization process is not limited to argon, and may be silicon, for example.

Next, the photoresist film 4 is removed from the silicon substrate 1 by ashing using oxygen plasma or the like. 4A and 4B, the silicon substrate 1 is subjected to a thermal oxidation process to form a thermal oxide film (SiO ₂ film) 6a at the corners 6 on the surface of the silicon layer 3. Here, an amorphous silicon layer tends to oxidize more easily than a single crystal silicon layer. In the first embodiment, since only the corner portion 6 of the silicon layer 3 is amorphized, a thermal oxide film 6a is formed only on the corner portion 6, and a thermal oxide film is formed on the silicon layer 3 in other regions. Can be formed as little as possible.

  In the first embodiment, the processing temperature for forming the thermal oxide film 6a is preferably set to a low temperature of, for example, 400 ° C. or higher and 750 ° C. or lower. By selecting such a temperature range, the thermal diffusion of Ge from the silicon germanium layer 2 to the silicon substrate 1 or the silicon layer 3 side can be sufficiently suppressed. As a result, it is possible to prevent, for example, unintended characteristic fluctuations (due to Ge) of the transistor.

In FIG. 4B, when the (angular) corner portion of the silicon layer 3 is thermally oxidized, the corner portion becomes a thermal oxide film (SiO ₂ film) 6a and the volume is increased. The surface is fluidized to some extent. As a result, the angular shape of the corner becomes a shape that is rounded to some extent (that is, a gently curved shape). The square shape is a shape having a corner.

  Next, as shown in FIGS. 5A and 5B, a support film 7 is formed on the entire upper surface of the silicon substrate 1 so as to fill the support hole 5 and cover the silicon layer 3. The support film 7 is a silicon oxide film, for example, and is formed by, for example, CVD. Subsequently, as shown in FIGS. 6A and 6B, a photoresist film 8 is formed on the support film 7. The shape of the photoresist film 8 in plan view (that is, the planar shape) is, for example, a shape that covers the element region across the two support hole 5.

Next, as shown in FIGS. 7A and 7B, the support film 7, the silicon layer 3, and the silicon germanium layer 2 are sequentially dry etched using the photoresist film 8 as a mask. By this etching, a support 9 made of the support film 7 is formed on the silicon substrate 1, and a groove 13 having the silicon substrate 1 as a bottom surface is formed around the support 9. 7A and 7B, the side surface 15 (facing the groove 13) below the support 9 is an opening surface from which the silicon layer 3 and the silicon germanium layer 2 are exposed. Next, the photoresist film 8 is removed.

  Then, as shown in FIGS. 8A and 8B, an etching solution such as hydrofluoric acid is brought into contact with the silicon layer 3 and the silicon germanium layer 2 from the side surface 15 facing the groove portion 13 below the support 9. The silicon germanium layer 2 is selectively etched and removed. As a result, a cavity 10 is formed between the silicon substrate 1 and the silicon layer 3. In wet etching using hydrofluoric acid, silicon has a lower etching selectivity than silicon germanium (ie, silicon germanium is easier to etch than silicon), and only the silicon germanium layer is selectively etched leaving the silicon layer. And can be removed. As shown in FIGS. 8A and 8B, after the formation of the cavity 10, the silicon layer 3 is completely supported by the support 9.

Subsequently, as shown in FIGS. 9A and 9B, the silicon substrate 1 is thermally oxidized to form a buried insulating layer (BOX layer) 11 made of a SiO ₂ film in the cavity 10. The formation of the buried insulating layer 11 is not limited to the thermal oxidation of the silicon substrate 1, and can be performed by CVD.
Next, as shown in FIGS. 10A and 10B, an inter-element isolation insulating film 12 is formed on the entire upper surface of the silicon substrate 1. The groove 13 is buried by the formation of the insulating film 12. Further, when the filling in the cavity 10 by thermal oxidation or CVD (as described above) is insufficient, the filling in the cavity 10 is complemented by the formation of the insulating film 12.

Next, as shown in FIGS. 11A and 11B, the entire upper surface of the silicon substrate 1 is planarized by CMP or the like, and the insulating film 12 and a part of the support 9 are removed. As a result, a structure (SOI structure) in which the upper surface of the silicon layer 3 is exposed and the silicon layer 3 is element-isolated by the insulating film 12 and the buried insulating layer 11 is completed. As described above, when a silicon nitride film is formed as an antioxidant film on the silicon layer 3, the antioxidant film functions as a stopper layer in this planarization process. It is possible to prevent dishing that does not occur. Further, when a silicon nitride film is used as the stopper layer, it is removed by wet etching using, for example, hot phosphoric acid after the planarization process, and then the underlying oxide film (SiO 2) by wet etching using, for example, dilute hydrofluoric acid. ₍₂ films) may be removed.

Next, as shown in FIGS. 12A and 12B, the surface of the silicon layer 3 is thermally oxidized to form a gate insulating film 20. Then, a polycrystalline silicon layer is formed on the gate insulating film 20 by a method such as CVD. Then, the gate electrode 21 is formed on the gate insulating film 20 by patterning the polycrystalline silicon layer using a photolithography technique.
Next, in FIG. 13, impurities such as As, P, and B are ion-implanted into the silicon layer 3 using the gate electrode 21 as a mask, so that the low-concentration impurity introduction layers are respectively introduced into the silicon layer 3 on both sides of the gate electrode 21. LDD layers 23a and 23b are formed.

Further, an insulating layer is formed on the silicon layer 3 on which the LDD layers 23a and 23b are formed by a method such as CVD, and the insulating layer is etched back using dry etching such as RIE (reactive ion etching). As a result, as shown in FIG. 13, sidewalls 24 a and 24 b are formed on the sidewalls of the gate electrode 21. Then, impurities such as As, P, and B are ion-implanted into the silicon layer 3 using the gate electrode 21 and the sidewalls 24a and 24b as masks, so that the silicon layer 3 on both sides of the gate electrode 21 is respectively introduced from the high concentration impurity introduction layer. A source layer 25a and a drain layer 25b are formed. In this way, a transistor is completed on the SOI structure.

  Thus, according to the first embodiment of the present invention, the thermal oxide film 6a is formed on the corner 6 on the surface of the silicon layer 3 located at the periphery of the support hole 5, and then the support film 7 is formed. ing. By forming the thermal oxide film 6a, the corner 6 on the surface of the silicon layer 3 can be rounded. Therefore, even when the gate electrode 21 is arranged immediately above the corner portion 6, electric field concentration at the corner portion 6 can be reduced. Thereby, the reliability of the gate insulating film 20 can be improved, and it can contribute to prevention of leakage current.

  According to the first embodiment of the present invention, since the electric field concentration at the corner 6 can be relaxed, the gate electrode 21 can be disposed immediately above the corner 6 and can be arranged in any direction in the element region. The gate electrode 21 can be extended. That is, since the gate length direction can be set in an arbitrary direction, the gate electrode 21 can be laid out more freely, and the degree of freedom in designing the semiconductor device can be increased.

(2) Second Embodiment FIGS. 14A to 14C are schematic sectional views showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention. 14 (a) to 14 (c), parts having the same configurations as those in FIGS. 1 to 13 described in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. In this second embodiment, when forming the support hole, the silicon layer 3 is first etched halfway by isotropic etching, and then the remaining silicon layer 3 and the silicon germanium layer 2 are anisotropically etched. And etch.

  That is, in FIG. 14A, when the support hole is formed, the silicon layer 3 is wet-etched, for example, to an intermediate position in the thickness direction using the photoresist 4 as a mask. This wet etching is isotropic etching, and for example, any one of the following a) to c) or a combination thereof is used as an etchant. In the second embodiment, unlike the first embodiment, trimming of the photoresist is not performed.

a) hydrofluoric acid b) hydrofluoric acid + acetic acid c) hydrofluoric acid d) hydrofluoric acid + ammonium fluoride

  Next, using the photoresist 4 as a mask, the remaining silicon layer 3 and the silicon germanium layer 2 are sequentially removed by dry etching. This dry etching is anisotropic etching. Thereby, as shown in FIG.14 (b), support body hole 5 'is formed. The role of the support hole 5 ′ is the same as that of the support 5 described in the first embodiment. The subsequent steps are the same as those in the first embodiment. As shown in FIG. 14C, the support hole is finally filled with the support 9 and the insulating film 12.

  Thus, according to the second embodiment of the present invention, when forming the support hole 5 ′, the silicon layer 3 is first etched halfway by isotropic etching, and then anisotropic etching is performed. The remaining silicon layer 3 and silicon germanium layer 2 are etched. With such a configuration, in the process of forming the support hole 5 ′, a portion corresponding to the corner of the surface of the silicon layer 3 located at the periphery of the support hole 5 ′ (hereinafter also referred to as “corner”). .) It can be formed into a tapered shape constituted by a gentle concave surface instead of an angular shape 6 ′.

Therefore, even when the gate electrode is arranged just above the corner 6 'on the surface of the silicon layer 3,
Electric field concentration at the corner 6 'can be reduced. As a result, the reliability of the gate insulating film can be increased, which can contribute to prevention of leakage current.
In the second embodiment, as in the first embodiment, a base oxide film, an antioxidant film, or the like may be formed on the silicon layer 3 before the photoresist film 4 is formed. The base oxide film is, for example, a silicon oxide film, and the antioxidant film is, for example, a silicon nitride film. In the case where a base oxide film or an antioxidant film (hereinafter also referred to as “protective film”) is formed on the silicon layer 3, before starting the isotropic wet etching in FIG. These protective films may be removed by dry etching using the film 4 as a mask.

  In the first and second embodiments described above, the silicon substrate 1 corresponds to the “semiconductor substrate” of the present invention, the silicon germanium layer 2 corresponds to the “first semiconductor layer” of the present invention, and the silicon layer 3 corresponds to the present invention. To the “second semiconductor layer”. Still, the support hole 5, 5 'corresponds to the "first groove" of the present invention, and the groove portion 13 corresponds to the "second groove" of the present invention. Further, the buried insulating layer 11 corresponds to the “insulating layer” of the present invention.

  In the first and second embodiments, the “semiconductor substrate” is a bulk silicon wafer, the material of the “first semiconductor layer” is silicon germanium, and the “second semiconductor layer” is silicon. explained. However, the material of the “semiconductor substrate”, “first semiconductor layer”, and “second semiconductor layer” of the present invention is not limited to this. For example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, A combination selected from InP, GaP, GaN, ZnSe, or the like can be used.

FIG. 3 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 1). FIG. 6 is a diagram (No. 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 3A and 3B are diagrams illustrating the method for manufacturing a semiconductor device according to the first embodiment (No. 3). 4A and 4B are diagrams illustrating the method for fabricating a semiconductor device according to the first embodiment (No. 4). FIG. 5 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 5). 6A and 6B are diagrams illustrating the method for manufacturing a semiconductor device according to the first embodiment (No. 6). FIG. 7 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 7). FIG. 8 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 8). FIG. 9 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 9). FIG. 10 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 10). FIG. 11 is a view (No. 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 12 is a view (No. 12) illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 13 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 13). The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. The figure which shows a prior art example.

Explanation of symbols

  1 silicon (Si) substrate, 2 silicon germanium (SiGe) layer, 3 silicon (Si) layer, 4 photoresist film, 5 5 ′ support hole, 6, 6 ′ corner of silicon layer surface, 6a thermal oxide film , 7 Support film, 9 Support body, 10 Cavity, 11 Embedded insulating layer, 12 Insulating film, 13 Groove, 20 Gate insulating film, 21 Gate electrode, 23a, 23b LDD layer, 24a, 24b Side wall, 25a Source layer 25b Drain layer

Claims (4)

Forming a single-crystal first semiconductor layer on a semiconductor substrate;
Forming a single-crystal second semiconductor layer on the first semiconductor layer;
Forming a first groove through the second semiconductor layer and the first semiconductor layer to expose the semiconductor substrate;
Forming a thermal oxide film at a corner of the surface of the second semiconductor layer located at the periphery of the first groove;
Forming a support film on the semiconductor substrate after the thermal oxide film is formed at the corners, so that the first groove is embedded and the second semiconductor layer is covered;
Selectively etching the support film, the second semiconductor layer, and the first semiconductor layer sequentially to form a second groove that exposes the first semiconductor layer from under the second semiconductor layer;
The semiconductor substrate and the second semiconductor are etched by etching the first semiconductor layer through the second groove under a specific etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer. Forming a cavity between the layers;
And a step of forming an insulating layer in the cavity. In the step of forming the first groove,
Etching the second semiconductor layer and the first semiconductor layer using the patterned photoresist film as a mask to form the first groove,
In the step of forming the thermal oxide film at the corner of the surface of the second semiconductor layer located at the periphery of the first groove,
Trimming the photoresist film to expose the corner from below the photoresist film,
The corners are made amorphous by ion-implanting impurities into the second semiconductor layer using the trimmed photoresist film as a mask, and then
2. The method of manufacturing a semiconductor device according to claim 1, wherein the thermal oxide film is formed at the corner portion that has been amorphized by subjecting the semiconductor substrate to a thermal oxidation treatment. The first semiconductor layer is silicon germanium (SiGe), the second semiconductor layer is silicon (Si);
The method for manufacturing a semiconductor device according to claim 2, wherein the temperature of the thermal oxidation treatment is set to 750 ° C. or lower. Forming a single-crystal first semiconductor layer on a semiconductor substrate;
Forming a single-crystal second semiconductor layer on the first semiconductor layer;
Forming a first groove through the second semiconductor layer and the first semiconductor layer to expose the semiconductor substrate;
Forming a support film on the semiconductor substrate so that the first groove is embedded and the second semiconductor layer is covered;
Selectively etching the support film, the second semiconductor layer, and the first semiconductor layer sequentially to form a second groove that exposes the first semiconductor layer from under the second semiconductor layer;
The semiconductor substrate and the second semiconductor are etched by etching the first semiconductor layer through the second groove under a specific etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer. Forming a cavity between the layers;
Forming an insulating layer in the cavity,
In the step of forming the first groove,
Using the patterned photoresist film as a mask, isotropically etching the second semiconductor layer to the extent that the first semiconductor layer is not exposed from under the second semiconductor layer, and
The method of manufacturing a semiconductor device, wherein the first groove is formed by anisotropically etching the second semiconductor layer and the first semiconductor layer using the photoresist film as a mask.

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