JP2007311582A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2007311582A
JP2007311582A JP2006139675A JP2006139675A JP2007311582A JP 2007311582 A JP2007311582 A JP 2007311582A JP 2006139675 A JP2006139675 A JP 2006139675A JP 2006139675 A JP2006139675 A JP 2006139675A JP 2007311582 A JP2007311582 A JP 2007311582A
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Japan
Prior art keywords
wiring
plate
semiconductor device
silicon chip
solder
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JP2006139675A
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Japanese (ja)
Inventor
Shinya Kawakita
心哉 河喜多
Toshiaki Ishii
利昭 石井
Enjiyou Tsuyuno
円丈 露野
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Hitachi Ltd
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Hitachi Ltd
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Priority to JP2006139675A priority Critical patent/JP2007311582A/en
Publication of JP2007311582A publication Critical patent/JP2007311582A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with a plate metal used for the wiring of the upper surface electrode of a silicon chip excellent in the connection reliability of the bonding part between the upper surface electrode of the silicon chip and the wiring member, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device comprises a circuit board 8 with a wiring pattern formed on the surface of an insulating board, the silicon chip 4 mounted on the circuit board 8, the plate wiring for electrically connecting the upper electrode of the silicon chip 4 and the wiring pattern, and a sealing resin 10 for sealing at least the silicon chip 4 and the plate metal. The plate wiring is a metal having continuous holes, and solder having a melting point of not lower than 130°C nor higher than 500°C and the sealing resins 10 are filled in the holes. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、ＩＧＢＴやＭＯＳＦＥＴなどのシリコンチップ上面電極の配線に板状金属を用いた半導体装置に関する。   The present invention relates to a semiconductor device using a plate-like metal for wiring of an upper surface electrode of a silicon chip such as an IGBT or a MOSFET.

モータの制御装置用などの低圧系モジュールやインバータ用などの高圧系モジュールなどに代表される半導体装置においては、近年の小型化，高性能化の要求から、半導体装置中の電流容量は増加する傾向にある。半導体装置の高電流容量化に伴い、発熱量は増加するため、半導体装置の高放熱化、及び接合部の長寿命化がより重要となっている。   In semiconductor devices typified by low voltage modules for motor control devices and high voltage modules for inverters, etc., current capacity in semiconductor devices tends to increase due to recent demands for miniaturization and high performance. It is in. As the semiconductor device has a higher current capacity, the amount of heat generation increases, so it is more important to increase the heat dissipation of the semiconductor device and to extend the life of the junction.

接合部を長寿命化する技術の一つに、接合部のはんだ厚さの均一化がある。該はんだ厚さを均一化する手法として、はんだ中にニッケル（Ｎｉ）球を入れる方法が開示されている。   One technique for extending the life of a joint is to make the solder thickness of the joint uniform. As a method for making the solder thickness uniform, a method of putting nickel (Ni) spheres in the solder is disclosed.

しかし、前記シリコンチップ上面、または下面の少なくとも一方に、前記ニッケル
（Ｎｉ）球が一つだけ入った場合、前記シリコンチップが割れるという課題がある。また、前記ニッケル（Ｎｉ）球近傍にて応力が集中し、該ニッケル（Ｎｉ）球近傍からき裂が進展し、半導体装置が通電不良となる課題がある。 However, when only one nickel (Ni) ball enters at least one of the upper surface and the lower surface of the silicon chip, there is a problem that the silicon chip breaks. Further, there is a problem that stress concentrates in the vicinity of the nickel (Ni) sphere, cracks develop from the vicinity of the nickel (Ni) sphere, and the semiconductor device becomes poorly energized.

一方、半導体装置の高放熱化技術として、ＩＧＢＴやＭＯＳＦＥＴなどのシリコンチップ上面電極の配線に板状金属を用いる技術が開示されている（例えば、特許文献１）。前記シリコンチップ上面電極の配線にアルミ（Ａｌ）などのワイヤを用いて配線するのではなく、銅（Ｃｕ）や銅（Ｃｕ）合金などの板状金属を配線材として用いることにより、電気的な配線のほか、熱的にも配線される。その結果、配線材として前記板状金属を用いることで前記アルミ（Ａｌ）などのワイヤを用いた配線にはない、新たな放熱経路が設けられ、前記シリコンチップに通電することで発せられた熱を効率よく放熱することが可能である。   On the other hand, as a technique for increasing the heat dissipation of a semiconductor device, a technique using a plate-like metal for wiring of an upper surface electrode of a silicon chip such as IGBT or MOSFET is disclosed (for example, Patent Document 1). Rather than using a wire such as aluminum (Al) for the wiring of the upper electrode of the silicon chip, a plate-like metal such as copper (Cu) or a copper (Cu) alloy is used as a wiring material. In addition to wiring, it is also wired thermally. As a result, the use of the plate-like metal as a wiring material provides a new heat dissipation path that is not present in wiring using wires such as aluminum (Al), and heat generated by energizing the silicon chip. Can be efficiently dissipated.

特開２００３−２４３６０１号公報JP 2003-243601A

しかし、一般的に前記シリコンチップ上面電極は複数の電極パッドに分割されており、各パッド間にははんだが濡れず、空洞となっている。前記空洞部に熱応力が集中することなどの原因から、前記複数の電極パッドに分割された、シリコンチップ上面と前記板状金属の接合部は、前記シリコンチップ下面と回路基板間など他の接合部より寿命が短く、半導体装置の寿命を短くするという課題がある。   However, in general, the silicon chip upper surface electrode is divided into a plurality of electrode pads, and the solder is not wet between the pads, and is hollow. The joint between the silicon chip upper surface and the plate-like metal, which is divided into the plurality of electrode pads due to the concentration of thermal stress in the cavity, etc., is another joint such as between the silicon chip lower surface and the circuit board. There is a problem that the lifetime is shorter than that of the portion and the lifetime of the semiconductor device is shortened.

本発明は、上記課題を踏まえ、シリコンチップの上面電極の配線に板状金属を用いた半導体装置において、シリコンチップの上面電極と配線部材の接合部の接続信頼性に優れた半導体装置及びその製造方法を提供することを目的とする。   In view of the above-described problems, the present invention provides a semiconductor device using a plate-like metal for the wiring of the upper surface electrode of the silicon chip, and a semiconductor device excellent in connection reliability between the upper surface electrode of the silicon chip and the wiring member and its manufacture It aims to provide a method.

本発明の上記課題を解決するための第一の手段は、絶縁基板の表面に配線パターンが形成された回路基板と、前記回路基板に搭載されたシリコンチップと、前記シリコンチップの上面電極と前記配線パターンとを電気的に接続する板状配線と、少なくとも前記シリコンチップ及び板状配線を封止する封止樹脂とを有し、前記板状配線が連続した空孔を有する金属であり、前記空孔に融点が１３０℃以上５００℃以下のはんだと、前記封止樹脂が充填されている半導体装置を特徴とする。   A first means for solving the above-described problems of the present invention includes a circuit board having a wiring pattern formed on the surface of an insulating substrate, a silicon chip mounted on the circuit board, an upper surface electrode of the silicon chip, and the It has a plate-like wiring that electrically connects a wiring pattern, and a sealing resin that seals at least the silicon chip and the plate-like wiring, and the plate-like wiring is a metal having continuous pores, The semiconductor device is characterized in that the void is filled with solder having a melting point of 130 ° C. or higher and 500 ° C. or lower and the sealing resin.

また、本発明の第二の手段は、絶縁基板の表面に配線パターンが形成された回路基板と、前記回路基板に搭載されたシリコンチップと、前記シリコンチップの上面電極と前記配線パターンとを電気的に接続する板状配線と、少なくとも前記シリコンチップ及び板状配線を封止する封止樹脂とを有する半導体装置の製造方法であって、前記シリコンチップの上面電極と、連続した空孔を有する前記板状配線との間に融点が１３０℃以上５００℃以下のはんだを配置し、リフローにより前記空孔に前記はんだを含浸させ、前記はんだと前記板状配線を一体化させる工程と、少なくとも前記シリコンチップ及び板状配線を樹脂封止し、前記板状配線の前記はんだが含浸されていない空孔に樹脂を充填させる工程とを有する半導体装置の製造方法を特徴とする。   The second means of the present invention electrically connects a circuit board having a wiring pattern formed on the surface of an insulating substrate, a silicon chip mounted on the circuit board, an upper surface electrode of the silicon chip, and the wiring pattern. A method of manufacturing a semiconductor device having a plate-like wiring to be connected to each other and a sealing resin for sealing at least the silicon chip and the plate-like wiring, and having a top surface electrode of the silicon chip and a continuous hole A step of disposing a solder having a melting point of 130 ° C. or more and 500 ° C. or less between the plate-like wiring, impregnating the solder into the holes by reflow, and integrating the solder and the plate-like wiring; A method of manufacturing a semiconductor device, comprising: sealing a silicon chip and a plate-like wiring with resin, and filling the hole in the plate-like wiring not impregnated with the solder with a resin. To.

また、本発明の第三の手段は、連続した空孔を有する前記板状配線の前記シリコンチップの上面電極と接合される領域の空孔に融点が１３０℃以上５００℃以下のはんだを含浸させ、前記シリコンチップの上面電極上に前記板状配線を配置し、リフローにより前記空孔に含浸したはんだを介して、前記上面電極と前記板状配線とを接合する工程と、少なくとも前記シリコンチップ及び板状配線を樹脂封止し、前記板状配線の前記はんだが含浸されていない空孔に樹脂を充填させる工程とを有する半導体装置の製造方法を特徴とする。   The third means of the present invention is to impregnate a hole in a region where the upper surface electrode of the silicon chip of the plate-like wiring having continuous holes is joined with a melting point of 130 ° C. or more and 500 ° C. or less. Disposing the plate-like wiring on the upper surface electrode of the silicon chip, and joining the upper-surface electrode and the plate-like wiring via solder impregnated in the holes by reflow; and at least the silicon chip and A method of manufacturing a semiconductor device, comprising: sealing a plate-like wiring with resin and filling a resin into a hole of the plate-like wiring not impregnated with the solder.

このように、板状配線として、連続した空孔を有する金属を用いて、空孔内に融点が
１３０℃以上５００℃以下のはんだと樹脂を充填させた構造とすることによって、従来の板状配線を用いた半導体装置と比較して、接続信頼性を大幅に向上させることができる。 Thus, by using a metal having continuous pores as the plate-like wiring and having a structure in which the pores are filled with solder and resin having a melting point of 130 ° C. or higher and 500 ° C. or lower, Compared with a semiconductor device using wiring, connection reliability can be greatly improved.

本発明により、シリコンチップの上面電極の配線に板状金属を用いた半導体装置において、シリコンチップの上面電極と配線部材の接合部の接続信頼性に優れた半導体装置並びにその製造方法を提供することができる。   According to the present invention, in a semiconductor device using a plate-like metal for the wiring of the upper surface electrode of the silicon chip, a semiconductor device excellent in connection reliability between the upper surface electrode of the silicon chip and the wiring member and a manufacturing method thereof are provided. Can do.

以下、本発明の半導体装置について説明する。まず、本発明で用いる板状配線について説明する。融点が１３０℃以上５００℃以下のペーストはんだを、前記ペーストはんだより融点，熱伝導率、及び弾性率が高い金属で、かつ連続する空孔を有する金属に室温で充填し、望ましくは、シリコンチップ上面電極や回路基板などと配線しない、前記はんだを充填した連続する空孔を有する金属の表面にある余分な前記ペーストはんだを除去した、はんだと連続する空孔を有する金属からなる、板状配線材を作製しておく。次に、回路基板等にシリコンチップや板状配線材、その他の部材を搭載し、リフローを行うことで、該ペーストはんだと該連続する空孔を有する金属を一体化すると同時に、該配線材を前記シリコンチップ上面電極、及び前記回路基板等の被配線材に配線する。その後、絶縁樹脂にて封止し、前記配線材のはんだを含まない空孔に、前記絶縁樹脂組成物を含浸させる。   Hereinafter, the semiconductor device of the present invention will be described. First, the plate-like wiring used in the present invention will be described. A paste solder having a melting point of 130 ° C. or more and 500 ° C. or less is filled at room temperature with a metal having a higher melting point, thermal conductivity and elastic modulus than the paste solder and having continuous pores, and preferably a silicon chip. A plate-like wiring made of a metal having voids continuous with the solder, in which excess paste solder on the surface of the metal having continuous voids filled with the solder is removed, and is not wired with an upper surface electrode or a circuit board Prepare the material. Next, by mounting a silicon chip, a plate-like wiring material, or other members on a circuit board or the like, and reflowing, the paste solder and the metal having the continuous holes are integrated, and at the same time, the wiring material is Wiring is performed on the silicon chip upper surface electrode and the wiring material such as the circuit board. Thereafter, sealing is performed with an insulating resin, and the insulating resin composition is impregnated into the holes of the wiring member that do not contain solder.

融点が１３０℃以上５００℃以下の板はんだを、前記板はんだより融点，熱伝導率、及び弾性率が高い金属で、かつ連続する空孔を有する金属とシリコンチップなどの被配線材との間に設置する。次に、リフローを行い、該板はんだと、該連続する空孔を有する金属を一体化させると同時に、前記はんだと一体化した連続する空孔を有する金属を前記シリコンチップ上面電極、及び前記回路基板等に配線する。その後、絶縁樹脂にて封止し、前記はんだと一体化した連続する空孔を有する金属のはんだを含まない空孔に、前記絶縁樹脂組成物を含浸させる。   A sheet solder having a melting point of 130 ° C. or more and 500 ° C. or less is a metal having a higher melting point, thermal conductivity, and elastic modulus than the sheet solder, and between a metal having continuous pores and a wiring material such as a silicon chip. Install in. Next, reflow is performed to integrate the plate solder and the metal having continuous holes, and at the same time, connect the metal having continuous holes integrated with the solder to the top electrode of the silicon chip and the circuit. Connect to the substrate. Thereafter, the insulating resin composition is impregnated, and the insulating resin composition is impregnated into a hole that does not contain a metal solder having continuous holes integrated with the solder.

連続する空孔を有する金属としては、Ｃｕ，Ｃｕ合金、Ｎｉ，Ｎｉ合金、Ａｌ，Ａｌ合金、Ａｇ，Ａｕ，Ｐｔ，ステンレス鋼の中から選ばれた一つの金属で、該金属の空孔率が５０％以上９８％以下である金属を使用する。なお、連続する空孔を有する金属がステンレス鋼である場合は、該ステンレス鋼の表面をニッケル（Ｎｉ）メッキすることが好ましい。   The metal having continuous pores is one metal selected from Cu, Cu alloy, Ni, Ni alloy, Al, Al alloy, Ag, Au, Pt, and stainless steel, and the porosity of the metal. A metal having a ratio of 50% to 98% is used. In addition, when the metal which has a continuous void | hole is stainless steel, it is preferable to plate the surface of this stainless steel with nickel (Ni).

また、連続する空孔を有する金属は、室温における熱伝導率が７０Ｗ／ｍＫ以上の金属で、望ましくは室温における熱伝導率が２００Ｗ／ｍＫ以上である金属を用いることにより、前記はんだ，連続する空孔を有する金属，絶縁封止樹脂組成物からなる、配線材の熱伝達率を３０Ｗ／ｍＫ以上とすることができる。かかる結果、該配線材を有効な放熱経路として、該配線材と前記シリコンチップ上面電極間の接合部の長寿命化と高放熱化を同時に満足させる。   Further, the metal having continuous pores is a metal having a thermal conductivity of 70 W / mK or more at room temperature, and preferably by using a metal having a thermal conductivity of 200 W / mK or more at room temperature. The heat transfer coefficient of the wiring material made of a metal having holes and an insulating sealing resin composition can be set to 30 W / mK or more. As a result, the wiring material is used as an effective heat dissipation path, and a long life and high heat dissipation at the joint between the wiring material and the silicon chip upper surface electrode are satisfied at the same time.

配線材に用いる、連続する空孔を有する金属の空孔率は低くなるほど、該配線材の熱伝達率は高くなる。しかし、空孔率が低くなりすぎると、該配線材に含浸されるはんだと、該連続する空孔を有する金属が、硬くて脆い合金層を形成し、かつ熱伝導率が低くなる。そのため、本発明では、連続する空孔を有する金属の空孔率を５０％以上と規定する。   The lower the porosity of the metal having continuous pores used for the wiring material, the higher the heat transfer coefficient of the wiring material. However, if the porosity is too low, the solder impregnated in the wiring material and the metal having the continuous pores form a hard and brittle alloy layer, and the thermal conductivity becomes low. Therefore, in this invention, the porosity of the metal which has a continuous void | hole is prescribed | regulated as 50% or more.

また、き裂進展に関する観点からは、従来のはんだのみを用いて接合と比較して、前記連続する空孔を有する金属に、はんだが含浸させられているため、き裂進展経路が複雑化し、き裂進展速度が抑制される。さらに、はんだが被配線材の端部に濡れ広がることがないため、半導体装置の耐圧信頼性も向上する。   In addition, from the viewpoint of crack propagation, compared to joining using only conventional solder, the metal having continuous voids is impregnated with solder, so the crack propagation path is complicated, Crack growth rate is suppressed. Furthermore, since the solder does not spread over the end portion of the wiring material, the breakdown voltage reliability of the semiconductor device is also improved.

前記連続する空孔を有する金属に、前記金属より融点，熱伝導率、及び弾性率が低いはんだを含浸させる方法は前記の二種類に限定するのではなく、例えばはんだを溶融させた槽中に前記連続する空孔を有する金属を浸漬させて、はんだを含浸させてもよい。   The method of impregnating the metal having continuous pores with solder having a melting point, thermal conductivity, and elastic modulus lower than those of the metal is not limited to the above two types. For example, in a bath in which solder is melted The metal having continuous voids may be immersed and impregnated with solder.

本発明の配線材の効果は、以下である。まず、融点が１３０℃以上５００℃以下のはんだと、前記はんだより融点，熱伝導率、及び弾性率が高い金属で、かつ連続する空孔を有する金属を一体化することにより、電気的、及び熱的な配線が可能となる配線材が作製される。その後、絶縁樹脂にて封止することで、該配線材のはんだを含まない空孔に、前記絶縁樹脂組成物が含浸させられることで、前記絶縁樹脂組成物と該配線材が一体化させられる。前記絶縁樹脂組成物との一体化により、半導体装置を封止している絶縁樹脂と配線材の密着性が極めて高い配線材を提供できる。   The effects of the wiring material of the present invention are as follows. First, by integrating a solder having a melting point of 130 ° C. or more and 500 ° C. or less with a metal having a melting point, a thermal conductivity, and a modulus of elasticity higher than that of the solder and having continuous pores, A wiring material capable of thermal wiring is produced. Thereafter, the insulating resin composition and the wiring material are integrated by impregnating the hole without the solder of the wiring material with the insulating resin composition by sealing with an insulating resin. . Integration with the insulating resin composition can provide a wiring material with extremely high adhesion between the insulating resin sealing the semiconductor device and the wiring material.

絶縁封止樹脂は半導体装置内に搭載させている、回路基板やシリコンチップ等の部材を拘束することにより、前記部材間の線膨張係数差に起因する熱応力等によるひずみを抑制している。そのため、前記絶縁封止樹脂と、前記配線材とを一体化させることにより、前記シリコンチップ上面電極と前記配線材間も拘束される。かかる結果、前記シリコンチップ上面電極と前記配線材間の接合部を長寿命化できる。   The insulating sealing resin restrains distortion caused by thermal stress or the like due to a difference in linear expansion coefficient between the members by restraining members such as a circuit board and a silicon chip mounted in the semiconductor device. Therefore, by integrating the insulating sealing resin and the wiring material, the silicon chip upper surface electrode and the wiring material are also restrained. As a result, the life of the joint between the silicon chip upper surface electrode and the wiring member can be extended.

以下に本発明を具体化した、第一の実施例を図面に従って用いて説明する。図１は、本実施の形態における半導体装置の縦断面図である。   A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a longitudinal sectional view of a semiconductor device according to the present embodiment.

シリコンチップ（ＭＯＳＦＥＴ）４には、その上面にソース電極（図示せず）およびゲート電極（図示せず）が設けられ、下面にはドレイン電極（図示せず）が設けられている。図１において、シリコンチップ（ＭＯＳＦＥＴ）４のソース電極は配線材１、ドレイン電極は回路基板８に、それぞれ電気的，熱的に接続されている。また前記シリコンチップ（ＭＯＳＦＥＴ）４のゲート電極はアルミワイヤ３により電気的に回路基板８に接続されている。さらに、回路基板８の裏面側の銅薄板７は、はんだを介して放熱基板９と熱的に接続されている。   The silicon chip (MOSFET) 4 has a source electrode (not shown) and a gate electrode (not shown) on its upper surface, and a drain electrode (not shown) on its lower surface. In FIG. 1, a silicon chip (MOSFET) 4 has a source electrode electrically connected to a wiring material 1 and a drain electrode electrically and thermally connected to a circuit board 8. The gate electrode of the silicon chip (MOSFET) 4 is electrically connected to the circuit board 8 by an aluminum wire 3. Furthermore, the copper thin plate 7 on the back side of the circuit board 8 is thermally connected to the heat dissipation board 9 via solder.

本実施例では、空孔率が８７％の銅（Ｃｕ）の多孔質金属にペースト状のスズ（Ｓｎ）−銀（Ａｇ）―銅（Ｃｕ）からなるはんだ、及びエポキシ系絶縁封止樹脂組成物を含浸させた配線材を用いた。   In this example, a copper (Cu) porous metal having a porosity of 87% and paste solder (Tn (Sn) -silver (Ag) -copper (Cu)), and epoxy insulating sealing resin composition A wiring material impregnated with an object was used.

本実施例の半導体装置は、以下の方法で作成した。まず、セラミックス絶縁基板６の片面に銅配線５、他方の面に銅薄板７が形成された回路基板８の所定の位置にはんだ接合層２を介してシリコンチップ４を搭載する。次に、上面電極，銅配線５の表面にペースト状のスズ（Ｓｎ）−銀（Ａｇ）―銅（Ｃｕ）からなるペースト状はんだを形成し、上面電極と銅配線５が電気的に接続されるように配線材１を配置する。また、放熱基板９の上にはんだ接合材を介在させて、回路基板８の銅薄板７が対向するように配置する。この状態で、リフローすることで、放熱基板９と回路基板８，回路基板８とシリコンチップ４，配線材１とシリコンチップ４及び回路基板８とを一括で接合する。この際、配線材１の空孔にはんだが充填される。次に、配線材１，シリコンチップ４，回路基板８，放熱基板９を樹脂封止することで、図１の半導体装置を得た。ここで、樹脂封止の工程において、配線材１のはんだが充填されていない空孔に樹脂が充填された構造となる。   The semiconductor device of this example was produced by the following method. First, the silicon chip 4 is mounted via the solder bonding layer 2 at a predetermined position of the circuit board 8 in which the copper wiring 5 is formed on one surface of the ceramic insulating substrate 6 and the copper thin plate 7 is formed on the other surface. Next, paste solder made of paste tin (Sn) -silver (Ag) -copper (Cu) is formed on the surface of the upper electrode and the copper wiring 5, and the upper electrode and the copper wiring 5 are electrically connected. The wiring material 1 is arranged so as to be. In addition, a solder bonding material is interposed on the heat dissipation board 9 so that the copper thin plates 7 of the circuit board 8 face each other. By reflowing in this state, the heat dissipation board 9 and the circuit board 8, the circuit board 8 and the silicon chip 4, the wiring member 1, the silicon chip 4 and the circuit board 8 are bonded together. At this time, the voids of the wiring material 1 are filled with solder. Next, the wiring material 1, the silicon chip 4, the circuit board 8, and the heat dissipation board 9 were resin-sealed to obtain the semiconductor device of FIG. Here, in the resin sealing step, the structure is such that the holes of the wiring member 1 not filled with the solder are filled with the resin.

図２に公知の銅（Ｃｕ）製板状金属と、本発明の配線材について、弾性率と熱伝導率の関係を示す。図２に示すように、本発明の配線材は、銅（Ｃｕ）より弾性率の低いはんだを、銅（Ｃｕ）の多孔質金属に含浸させることで、銅（Ｃｕ）製板状金属より弾性率が低く、熱膨張率が高くなる。弾性率が低くなることで、封止樹脂の流動を阻害しにくくなる。一方、熱膨張率が高くなるが、樹脂にて拘束されるため、前記配線材と前記シリコンチップ上面間の接合部に作用する熱応力は増加しない。   FIG. 2 shows the relationship between the elastic modulus and thermal conductivity of a known copper (Cu) plate-like metal and the wiring material of the present invention. As shown in FIG. 2, the wiring material of the present invention is more elastic than a copper (Cu) plate metal by impregnating a copper (Cu) porous metal with a solder having a lower elastic modulus than copper (Cu). The rate is low and the coefficient of thermal expansion is high. By lowering the elastic modulus, it becomes difficult to inhibit the flow of the sealing resin. On the other hand, although the coefficient of thermal expansion is increased, the thermal stress acting on the joint between the wiring member and the upper surface of the silicon chip does not increase because it is constrained by the resin.

図３にシリコンチップ（ＭＯＳＦＥＴ）４のソース電極と本発明の配線材１の接合部縦断面を拡大表示する。図３に示すように、本実施例では、前記接合部の配線材断面積の
２０％以下に前記絶縁封止樹脂が含浸される。本実施例では、前記配線部位以外においても、はんだが含浸されているが、はんだが含浸されていなくてもよい。 FIG. 3 is an enlarged view of the longitudinal section of the junction between the source electrode of the silicon chip (MOSFET) 4 and the wiring member 1 of the present invention. As shown in FIG. 3, in this embodiment, the insulating sealing resin is impregnated in 20% or less of the wiring material cross-sectional area of the joint. In this embodiment, the solder is impregnated also at portions other than the wiring portion, but the solder may not be impregnated.

以上のごとく、はんだが、前記はんだより熱伝導率，弾性率、及び融点が高い金属で、かつ連続する空孔を有する金属に含浸させられた配線材を用いて、シリコンチップ上面電極と回路基板を配線した後、絶縁樹脂にて封止することで、従来の板状金属による配線後、絶縁樹脂にて封止した場合に比べ、絶縁封止樹脂との接着性を向上できる。その結果、シリコンチップと配線材との間の接合部に作用する応力が緩和される。また、公知の板状金属をはんだで接合する場合より、接合部のき裂進展経路が複雑になるため、き裂進展速度の抑制できる。かかる結果、接合部の長寿命化が実現する。   As described above, the solder is a metal having a higher thermal conductivity, elastic modulus, and melting point than the solder, and using a wiring material impregnated with a metal having continuous pores, the silicon chip upper surface electrode and the circuit board After wiring, the adhesiveness with the insulating sealing resin can be improved as compared with the case of sealing with the insulating resin after wiring with the conventional plate metal. As a result, the stress acting on the joint between the silicon chip and the wiring material is relaxed. In addition, since the crack propagation path of the joint becomes more complicated than when a known plate metal is joined by solder, the crack propagation speed can be suppressed. As a result, the life of the joint is increased.

本実施例では、配線材中に空孔率が８７％の銅（Ｃｕ）の多孔質金属を用いたが、前記金属の空孔率が低くなるほど、該配線材の熱伝達率は高くなる。   In this example, a copper (Cu) porous metal having a porosity of 87% was used in the wiring material. However, the lower the porosity of the metal, the higher the heat transfer coefficient of the wiring material.

さらに、接合部端部に着目すると、本発明の配線材を用いることで、はんだが該配線材に含浸させられているため、シリコンチップ上面電極などの被接合部位以外まで濡れ広がることがないため、半導体装置の耐圧信頼性も向上させうる。   Further, when attention is paid to the end portion of the joint portion, by using the wiring material of the present invention, since the solder is impregnated in the wiring material, it does not spread out to other than the bonded portion such as the silicon chip upper surface electrode. In addition, the breakdown voltage reliability of the semiconductor device can be improved.

なお、本実施例では、各部材を一括で搭載するプロセスとしたが、各はんだ材の融点に温度階層を持たせて、例えば、回路基板とシリコンチップ裏面電極（下面側）との接合、配線材とシリコンチップ上面電極，回路基板との接合，回路基板との放熱基板との接合の順で接合しても良い。   In this embodiment, each member is mounted in a batch process. However, the melting point of each solder material has a temperature hierarchy, for example, bonding between a circuit board and a silicon chip back electrode (lower surface side), wiring The material and the silicon chip upper surface electrode, the circuit board, and the circuit board and the heat dissipation board may be joined in this order.

以下に本発明を具体化した、第二の実施例を図面に従って用いて説明する。図４は、本実施の形態における半導体装置の縦断面図である。   A second embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a longitudinal sectional view of the semiconductor device according to the present embodiment.

シリコンチップ（ＭＯＳＦＥＴ）４には、その上面にソース電極（図示せず）およびゲート電極（図示せず）が設けられ、下面にはドレイン電極（図示せず）が設けられている。図４において、シリコンチップ（ＭＯＳＦＥＴ）４のソース電極は配線材１３、ドレイン電極は銅配線５に、それぞれ電気的，熱的に接続されている。また前記シリコンチップ（ＭＯＳＦＥＴ）４のゲート電極はアルミワイヤ３により電気的に銅配線５に接続されている。さらに銅配線５は樹脂絶縁層１４を介して放熱基板９と熱的に接続されている。   The silicon chip (MOSFET) 4 has a source electrode (not shown) and a gate electrode (not shown) on its upper surface, and a drain electrode (not shown) on its lower surface. In FIG. 4, the source electrode of the silicon chip (MOSFET) 4 is electrically and thermally connected to the wiring material 13 and the drain electrode to the copper wiring 5, respectively. The gate electrode of the silicon chip (MOSFET) 4 is electrically connected to the copper wiring 5 by an aluminum wire 3. Further, the copper wiring 5 is thermally connected to the heat dissipation substrate 9 through the resin insulating layer 14.

本実施例では、次の方法で配線材を作製した。まず、空孔率が８６％の連続する空孔を有するニッケル（Ｎｉ）とシリコンチップ（ＭＯＳＦＥＴ）４の間にスズ（Ｓｎ）−銀
（Ａｇ）―銅（Ｃｕ）からなる板はんだを設置する。他の部材を搭載する際のリフローにより、前記連続する空孔を有するニッケル（Ｎｉ）と溶融した前記板はんだを一体化させる。その後、絶縁樹脂にて半導体装置を封止することで前記はんだと一体化した連続する空孔を有するニッケル（Ｎｉ）中の空孔に、絶縁封止樹脂組成物が含浸される。かかる構成の部材を配線材１３とする。 In this example, a wiring material was produced by the following method. First, a plate solder made of tin (Sn) -silver (Ag) -copper (Cu) is placed between nickel (Ni) having a continuous porosity of 86% and a silicon chip (MOSFET) 4. . By reflow when other members are mounted, the nickel (Ni) having the continuous holes and the molten sheet solder are integrated. Thereafter, the insulating sealing resin composition is impregnated into holes in nickel (Ni) having continuous holes integrated with the solder by sealing the semiconductor device with insulating resin. The member having such a configuration is referred to as a wiring member 13.

以上のごとく、板はんだが、前記板はんだより熱伝導率，弾性率、及び融点が高い金属で、かつ連続する空孔を有する金属に含浸させられた配線材を用いて、シリコンチップ上面電極と回路基板を配線した後、絶縁樹脂にて封止することで、従来の板状金属により電気的に配線し、絶縁樹脂にて封止した場合と比べ、絶縁封止樹脂との接着性を向上できる。その結果、シリコンチップと配線材との間の接合部に作用する応力が緩和される。また、公知の板状金属をはんだで接合する場合より、き裂進展経路が複雑になるため、き裂進展速度の抑制できる。かかる結果、接合部の長寿命化が実現する。   As described above, the plate solder is a metal having a higher thermal conductivity, elastic modulus, and melting point than the plate solder, and using a wiring material impregnated with a metal having continuous pores, After wiring the circuit board, sealing with insulating resin improves the adhesion with insulating sealing resin compared to the case of electrical wiring with conventional plate metal and sealing with insulating resin it can. As a result, the stress acting on the joint between the silicon chip and the wiring material is relaxed. In addition, since the crack propagation path is more complicated than when a known plate metal is joined with solder, the crack propagation speed can be suppressed. As a result, the life of the joint is increased.

以下に本発明を具体化した、第三の実施例を図面に従って用いて説明する。図５は、本実施の形態における半導体装置の縦断面図である。   A third embodiment of the present invention will be described below with reference to the drawings. FIG. 5 is a longitudinal sectional view of the semiconductor device according to the present embodiment.

図５において、シリコンチップ（ＭＯＳＦＥＴ）４のソース電極、及びドレイン電極は、それぞれ配線材１６，銅配線５に、電気的に接続されている。また前記シリコンチップ（ＭＯＳＦＥＴ）４のゲート電極はアルミワイヤ３により電気的に銅配線５に接続されている。また銅配線５は樹脂絶縁層１４を介して放熱基板９と熱的に接続されている。また、シリコンチップ（ＭＯＳＦＥＴ）４の上部に位置する配線材１６の平坦部に第二の放熱板１５が樹脂絶縁層１４を介して熱的に接続されている。   In FIG. 5, the source electrode and the drain electrode of the silicon chip (MOSFET) 4 are electrically connected to the wiring material 16 and the copper wiring 5, respectively. The gate electrode of the silicon chip (MOSFET) 4 is electrically connected to the copper wiring 5 by an aluminum wire 3. The copper wiring 5 is thermally connected to the heat dissipation substrate 9 through the resin insulating layer 14. In addition, a second heat radiating plate 15 is thermally connected to a flat portion of the wiring material 16 located above the silicon chip (MOSFET) 4 via a resin insulating layer 14.

本実施例では、前記シリコンチップ（ＭＯＳＦＥＴ）４上面のソース電極と銅配線５との電気的接続に、空孔率が８７％の銅の多孔質金属にペースト状のスズ（Ｓｎ）−銀
（Ａｇ）−銅（Ｃｕ）からなるはんだを含浸させ、絶縁封止樹脂組成物を含浸させたものを配線材１６として用いた。 In this embodiment, for the electrical connection between the source electrode on the upper surface of the silicon chip (MOSFET) 4 and the copper wiring 5, a paste of tin (Sn) -silver (on a copper porous metal having a porosity of 87%) is used. A wiring material 16 was made by impregnating a solder composed of (Ag) -copper (Cu) and impregnating the insulating sealing resin composition.

通電によりシリコンチップ（ＭＯＳＦＥＴ）４から生じた熱量は、該シリコンチップ
（ＭＯＳＦＥＴ）４の下方向に伝導されるほか、該シリコンチップ（ＭＯＳＦＥＴ）４の上方向にある配線材１６、及び第二の放熱板１５に伝導され、半導体装置の放熱性が向上される。かかる結果、公知の板状金属を配線材に用いた場合の、シリコンチップと前記板状金属の間の接合層寿命より、本発明の配線材を用いた場合、接合層の長寿命化すると同時に高放熱化が同時に実現する。 The amount of heat generated from the silicon chip (MOSFET) 4 by energization is conducted in the downward direction of the silicon chip (MOSFET) 4, the wiring material 16 in the upward direction of the silicon chip (MOSFET) 4, and the second Conducted by the heat sink 15, the heat dissipation of the semiconductor device is improved. As a result, when the wiring material of the present invention is used rather than the life of the bonding layer between the silicon chip and the plate metal when a known plate metal is used for the wiring material, the life of the bonding layer is increased. High heat dissipation is realized at the same time.

本実施例の形態は、図７に示すように、放熱基板９，放熱板１５の少なくとも一つが、熱伝導グリスを介して、モータのアルミニウム（Ａｌ）製筐体１８に熱的に接続されていてもいい。また図８に示すように、前記放熱基板９，放熱板１５の少なくとも一つに放熱フィン１９が設けられ、直接冷却液にて冷却してもよい。   In the embodiment, as shown in FIG. 7, at least one of the heat radiating board 9 and the heat radiating plate 15 is thermally connected to the aluminum (Al) casing 18 of the motor through the heat conductive grease. It ’s okay. Further, as shown in FIG. 8, at least one of the heat radiating substrate 9 and the heat radiating plate 15 may be provided with heat radiating fins 19 and may be directly cooled with a cooling liquid.

本発明の配線材は電動パワーステアリング用モータの制御装置用などの低圧系モジュールや、インバータ用などの高圧系モジュールなどに代表される半導体装置のなかで、絶縁樹脂にて封止される半導体装置全般に適用可能である。   The wiring material of the present invention is a semiconductor device sealed with an insulating resin among semiconductor devices represented by a low voltage system module for an electric power steering motor control device, a high voltage system module for an inverter, etc. Applicable in general.

第一実施例に係る半導体装置の要部縦断面図である。It is a principal part longitudinal cross-sectional view of the semiconductor device which concerns on a 1st Example. 第一実施例に係る配線材の弾性率と熱膨張率の関係図である。It is a related figure of the elasticity modulus and thermal expansion coefficient of the wiring material which concerns on a 1st Example. 第一実施例に係る半導体装置のシリコンチップから配線材上端までの縦断面図である。It is a longitudinal cross-sectional view from the silicon chip of the semiconductor device which concerns on a 1st Example to the wiring material upper end. 第二実施例に係る半導体装置の要部縦断面図である。It is a principal part longitudinal cross-sectional view of the semiconductor device which concerns on a 2nd Example. 第三実施例に係る半導体装置の要部断面図である。It is principal part sectional drawing of the semiconductor device which concerns on a 3rd Example. 第三実施例に係る半導体装置のシリコンチップから配線材上端までの縦断面図である。It is a longitudinal cross-sectional view from the silicon chip of the semiconductor device which concerns on a 3rd Example to the wiring material upper end. アルミ筐体に熱的に接続した第三実施例に係る半導体装置の要部縦断面図である。It is a principal part longitudinal cross-sectional view of the semiconductor device which concerns on the 3rd Example thermally connected to the aluminum housing | casing. 放熱フィンに接続した第三実施例に係る半導体装置の要部縦断面図である。It is a principal part longitudinal cross-sectional view of the semiconductor device which concerns on the 3rd Example connected to the radiation fin.

符号の説明Explanation of symbols

１…銅（Ｃｕ）の多孔質体とはんだ、絶縁封止用の樹脂からなる配線材、２…はんだ接合層、３…ゲート電極配線用アルミワイヤ、４…シリコンチップ（ＭＯＳＦＥＴ）、５…銅配線、６…セラミクス絶縁層、７…銅薄板、８…回路基板、９…放熱基板、１０…樹脂、１１…配線材１中のはんだの含浸部位、１２…配線材１中の絶縁封止用樹脂の含浸部位、１３…ニッケル（Ｎｉ）の多孔質体とはんだ、絶縁封止用の樹脂からなる配線材、１４…樹脂絶縁層、１５…第二の放熱板、１６…シリコンチップ４の上面が両面配線可能に調整した、銅（Ｃｕ）の多孔質体とはんだ絶縁封止用の樹脂からなる配線材、１７…熱伝導グリス、１８…アルミ筐体、１９…放熱フィン。
DESCRIPTION OF SYMBOLS 1 ... The wiring material which consists of a porous body of copper (Cu), solder, resin for insulation sealing, 2 ... Solder joint layer, 3 ... Aluminum wire for gate electrode wiring, 4 ... Silicon chip (MOSFET), 5 ... Copper Wiring, 6 ... ceramic insulating layer, 7 ... copper thin plate, 8 ... circuit board, 9 ... heat dissipation board, 10 ... resin, 11 ... site of solder impregnation in wiring material 1, 12 ... for insulation sealing in wiring material 1 Resin-impregnated portion, 13 ... nickel (Ni) porous body and solder, wiring material made of resin for insulation sealing, 14 ... resin insulation layer, 15 ... second heat sink, 16 ... upper surface of silicon chip 4 Are a wiring material made of a copper (Cu) porous body and a resin for solder insulation sealing, 17... Thermal conductive grease, 18... Aluminum casing, and 19.

Claims (15)

絶縁基板の表面に配線パターンが形成された回路基板と、前記回路基板に搭載されたシリコンチップと、前記シリコンチップの上面電極と前記配線パターンとを電気的に接続する板状配線と、少なくとも前記シリコンチップ及び板状配線を封止する封止樹脂とを有し、
前記板状配線が連続した空孔を有する金属であり、前記空孔に融点が１３０℃以上500℃以下のはんだと、前記封止樹脂が充填されていることを特徴とする半導体装置。 A circuit board having a wiring pattern formed on a surface of an insulating substrate; a silicon chip mounted on the circuit board; a plate-like wiring that electrically connects an upper surface electrode of the silicon chip and the wiring pattern; A sealing resin for sealing the silicon chip and the plate-like wiring,
The semiconductor device, wherein the plate-like wiring is a metal having continuous holes, and the holes are filled with solder having a melting point of 130 ° C. or higher and 500 ° C. or lower and the sealing resin. 請求項１に記載の半導体装置において、前記板状配線を構成する金属は、前記はんだよりも融点，縦弾性係数、及び熱伝導率が高いことを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the metal constituting the plate-like wiring has a melting point, a longitudinal elastic modulus, and a thermal conductivity higher than those of the solder. 請求項１に記載の半導体装置において、前記板状配線を構成する金属の室温における熱伝導率が７０Ｗ／ｍＫ以上であることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the metal constituting the plate-like wiring has a thermal conductivity of 70 W / mK or more at room temperature. 請求項１に記載の半導体装置において、前記板状配線は、Ｃｕ，Ｃｕ合金、Ｎｉ，Ｎｉ合金、Ａｌ，Ａｌ合金、Ａｇ，Ａｕ，Ｐｔ、または、ステンレス鋼の中の一つから選ばれた、空孔率が５０％以上９８％以下の金属であることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the plate-like wiring is selected from one of Cu, Cu alloy, Ni, Ni alloy, Al, Al alloy, Ag, Au, Pt, or stainless steel. A semiconductor device characterized by being a metal having a porosity of 50% to 98%. 請求項１に記載の半導体装置において、前記板状配線を構成する金属がステンレス鋼であり、前記ステンレス鋼の表面にＮｉめっき層が形成されていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the metal constituting the plate-like wiring is stainless steel, and a Ni plating layer is formed on the surface of the stainless steel. 請求項１に記載の半導体装置において、前記回路基板と熱的に接続された放熱基板を有することを特徴とする半導体装置。   2. The semiconductor device according to claim 1, further comprising a heat dissipation board thermally connected to the circuit board. 請求項６に記載の半導体装置において、前記回路基板の配線パターンが形成された面とは反対側の面に形成された金属層を有し、前記放熱基板が接着剤を介して前記金属層と接続されていることを特徴とする半導体装置。   7. The semiconductor device according to claim 6, further comprising a metal layer formed on a surface opposite to the surface on which the wiring pattern of the circuit board is formed, wherein the heat dissipation substrate is connected to the metal layer via an adhesive. A semiconductor device which is connected. 請求項１に記載の半導体装置において、前記回路基板の配線パターンが形成された面とは反対側の面に接続された第１の放熱基板と、
前記板状配線のシリコンチップと接続された面とは反対側の面に絶縁層を介して接続された第２の放熱基板とを有し、
前記封止樹脂は、前記第１及び第２の放熱基板の少なくとも一部を外部に露出するように前記回路基板，シリコンチップ及び板状配線を封止していることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein a first heat dissipation substrate is connected to a surface opposite to the surface on which the wiring pattern of the circuit board is formed.
A second heat dissipating substrate connected via an insulating layer to a surface opposite to the surface connected to the silicon chip of the plate-like wiring;
The semiconductor device, wherein the sealing resin seals the circuit board, the silicon chip and the plate-like wiring so that at least a part of the first and second heat dissipation substrates is exposed to the outside. 前記第１または第２の放熱基板の露出部に熱伝導グリスを介して、請求項８に記載の半導体装置をＡｌ製筐体又は放熱フィンに搭載したことを特徴とする電子装置。   9. An electronic device comprising the semiconductor device according to claim 8 mounted on an Al casing or a heat radiating fin via heat conductive grease on an exposed portion of the first or second heat radiating substrate. 絶縁基板の表面に配線パターンが形成された回路基板と、前記回路基板に搭載されたシリコンチップと、前記シリコンチップの上面電極と前記配線パターンとを電気的に接続する板状配線と、少なくとも前記シリコンチップ及び板状配線を封止する封止樹脂とを有する半導体装置の製造方法であって、
前記シリコンチップの上面電極と、連続した空孔を有する前記板状配線との間に融点が１３０℃以上５００℃以下のはんだを配置し、リフローにより前記空孔に前記はんだを含浸させ、前記はんだと前記板状配線を一体化させる工程と、
少なくとも前記シリコンチップ及び板状配線を樹脂封止し、前記板状配線の前記はんだが含浸されていない空孔に樹脂を充填させる工程とを有することを特徴とする半導体装置の製造方法。 A circuit board having a wiring pattern formed on a surface of an insulating substrate; a silicon chip mounted on the circuit board; a plate-like wiring that electrically connects an upper surface electrode of the silicon chip and the wiring pattern; A method of manufacturing a semiconductor device having a silicon chip and a sealing resin for sealing a plate-like wiring,
A solder having a melting point of 130 ° C. or higher and 500 ° C. or lower is disposed between the upper surface electrode of the silicon chip and the plate-like wiring having continuous holes, and the holes are impregnated with the solder by reflow, And the step of integrating the plate-like wiring,
A method for manufacturing a semiconductor device, comprising: sealing at least the silicon chip and the plate-like wiring with resin, and filling the hole in the plate-like wiring not impregnated with the solder. 請求項１０に記載の半導体装置の製造方法において、前記はんだが板はんだであることを特徴とする半導体装置の製造方法。   11. The method of manufacturing a semiconductor device according to claim 10, wherein the solder is a plate solder. 請求項１０に記載の半導体装置の製造方法において、前記はんだがフラックス成分を含むペーストはんだであることを特徴とする半導体装置の製造方法。   11. The method of manufacturing a semiconductor device according to claim 10, wherein the solder is paste solder containing a flux component. 請求項１０に記載の半導体装置の製造方法において、前記板状配線に前記はんだよりも融点，縦弾性係数、及び熱伝導率が高い金属を用いることを特徴とする半導体装置の製造方法。   11. The method of manufacturing a semiconductor device according to claim 10, wherein a metal having a melting point, a longitudinal elastic modulus, and a thermal conductivity higher than that of the solder is used for the plate-like wiring. 絶縁基板の表面に配線パターンが形成された回路基板と、前記回路基板に搭載されたシリコンチップと、前記シリコンチップの上面電極と前記配線パターンとを電気的に接続する板状配線と、少なくとも前記シリコンチップ及び板状配線を封止する封止樹脂とを有する半導体装置の製造方法であって、
連続した空孔を有する前記板状配線の前記シリコンチップの上面電極と接合される領域の空孔部に融点が１３０℃以上５００℃以下のはんだを含浸させ、前記シリコンチップの上面電極上に前記板状配線を配置し、リフローにより前記空孔に含浸したはんだを介して、前記上面電極と前記板状配線とを接合する工程と、
少なくとも前記シリコンチップ及び板状配線を樹脂封止し、前記板状配線の前記はんだが含浸されていない空孔に樹脂を充填させる工程とを有することを特徴とする半導体装置の製造方法。 A circuit board having a wiring pattern formed on a surface of an insulating substrate; a silicon chip mounted on the circuit board; a plate-like wiring that electrically connects an upper surface electrode of the silicon chip and the wiring pattern; A method of manufacturing a semiconductor device having a silicon chip and a sealing resin for sealing a plate-like wiring,
The hole part of the area | region joined with the upper surface electrode of the said silicon chip of the said plate-shaped wiring which has a continuous void | hole is impregnated with the solder whose melting | fusing point is 130 degreeC or more and 500 degrees C or less, The said upper surface electrode of the said silicon chip is Placing plate-like wiring and joining the upper surface electrode and the plate-like wiring through solder impregnated in the holes by reflowing;
A method for manufacturing a semiconductor device, comprising: sealing at least the silicon chip and the plate-like wiring with resin, and filling the hole in the plate-like wiring not impregnated with the solder. 請求項１４に記載の半導体装置の製造方法において、前記板状配線に前記はんだよりも融点，縦弾性係数、及び熱伝導率が高い金属を用いることを特徴とする半導体装置の製造方法。   15. The method of manufacturing a semiconductor device according to claim 14, wherein a metal having a melting point, a longitudinal elastic modulus, and a thermal conductivity higher than that of the solder is used for the plate-like wiring.
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* Cited by examiner, † Cited by third party
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JP2013179744A (en) * 2012-02-28 2013-09-09 Denso Corp Semiconductor module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013179744A (en) * 2012-02-28 2013-09-09 Denso Corp Semiconductor module
US9006883B2 (en) 2012-02-28 2015-04-14 Denso Corporation Semiconductor module with switching elements

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