JP2002237556A - Power semiconductor device - Google Patents

Power semiconductor device

Info

Publication number
JP2002237556A
JP2002237556A JP2001033121A JP2001033121A JP2002237556A JP 2002237556 A JP2002237556 A JP 2002237556A JP 2001033121 A JP2001033121 A JP 2001033121A JP 2001033121 A JP2001033121 A JP 2001033121A JP 2002237556 A JP2002237556 A JP 2002237556A
Authority
JP
Japan
Prior art keywords
power semiconductor
metal plate
porous metal
semiconductor device
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001033121A
Other languages
Japanese (ja)
Inventor
Kenji Sawatani
賢二 澤谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2001033121A priority Critical patent/JP2002237556A/en
Publication of JP2002237556A publication Critical patent/JP2002237556A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Abstract

PROBLEM TO BE SOLVED: To provide a reliable power semiconductor device which has reduced thermal stress and thermal strain caused by the difference in the coefficient of linear expansion between members and which can dissipate efficiently and stably heat generated by a power semiconductor element through effective conduction of heat. SOLUTION: The bottom surface of an insulation substrate 11, having a small coefficient of linear expansion which is mounted with the power semiconductor element 10, and a metal base plate 15 having a large coefficient of linear expansion which will become a heat dissipation plate are bonded to each other via a heat-conductivity type porous metal plate 22, having through-holes into which columnar heat conductors 24 are inserted. By separating each columnar heat conductor 24 from the sidewall of each through-hole 23 by a very small gap 23a, thermal stress is lowered while at the same time the thermal conductivity is maintained.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、電力変換や電動
機駆動などに用いられるパワー半導体装置に関し、特に
複数の半導体素子が実装され、冷却機構を有するパワー
半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device used for power conversion, motor drive, and the like, and more particularly to a power semiconductor device having a plurality of semiconductor elements mounted thereon and having a cooling mechanism.

【0002】[0002]

【従来の技術】従来のパワー半導体装置の一例として、
汎用のIGBT(Insulated Gate Bipolar Transisto
r)モジュールを用いたパワー半導体装置の断面図を図
6に示す。図6において、1はパワーモジュールの一つ
であるIGBTモジュール、2はパワー半導体素子の一
つであるIGBT素子、3は両面に銅等の金属の箔が接
着された、アルミナや窒化アルミ等からなる絶縁基板、
4はモリブデンやタングステン等からなる放熱用金属ベ
ース板、5はヒートシンク等の冷却手段、6と7ははん
だ、8は熱伝導性グリース等のコンパウンドである。図
に示すように、複数のIGBT素子2は絶縁基板3を介
して放熱用金属ベース板4上に搭載され、図示しない樹
脂により覆われてIGBTモジュール1を構成する。ま
た、IGBT素子2は絶縁基板3上に、絶縁基板3は放
熱用金属ベース板4上にそれぞれはんだ6、7で接合さ
れ、放熱用金属ベース板4は冷却手段5にコンパウンド
8を介して圧接されている。IGBTモジュール1の運
転時、IGBT素子2で発生する熱は、絶縁基板3と放
熱用金属ベース板4を介して、冷却手段5に伝導し、冷
却される。また、パワーモジュールの他の構造として、
GTO(Gate Turn-Off Thyristor)等のパワーモジュ
ールの両面にヒートシンク等の冷却手段を取り付け、そ
れぞれの接続部は外部からの圧力で接続する圧接スタッ
ク型がある。
2. Description of the Related Art As an example of a conventional power semiconductor device,
General-purpose IGBT (Insulated Gate Bipolar Transisto)
r) A cross-sectional view of a power semiconductor device using a module is shown in FIG. In FIG. 6, reference numeral 1 denotes an IGBT module which is one of power modules, 2 denotes an IGBT element which is one of power semiconductor elements, and 3 denotes an IGBT element made of alumina, aluminum nitride, or the like having a metal foil such as copper bonded to both surfaces. An insulating substrate,
Reference numeral 4 denotes a heat-dissipating metal base plate made of molybdenum, tungsten, or the like, 5 denotes cooling means such as a heat sink, 6 and 7 denote solder, and 8 denotes a compound such as heat conductive grease. As shown in the figure, a plurality of IGBT elements 2 are mounted on a heat-dissipating metal base plate 4 via an insulating substrate 3 and are covered with a resin (not shown) to constitute an IGBT module 1. Further, the IGBT element 2 is bonded on the insulating substrate 3, and the insulating substrate 3 is bonded on the metal base plate 4 for heat radiation with solders 6 and 7, and the metal base plate 4 for heat radiation is pressed against the cooling means 5 via the compound 8. Have been. During operation of the IGBT module 1, heat generated in the IGBT element 2 is conducted to the cooling means 5 via the insulating substrate 3 and the metal base plate 4 for heat dissipation, and is cooled. Also, as another structure of the power module,
There is a press-contact stack type in which cooling means such as a heat sink is attached to both sides of a power module such as a GTO (Gate Turn-Off Thyristor) and each connection portion is connected by external pressure.

【0003】[0003]

【発明が解決しようとする課題】これらIGBTモジュ
ール1の内部構造では、運転時の温度変化による接合部
の熱応力を低減するために、主要部分には素子の線膨張
率に近い部材を使っている。IGBTモジュール1のI
GBT素子2の線膨張率はシリコンで約3×10 −6
K、絶縁基板3の線膨張率は窒化アルミで約4×10
−6/K、放熱用金属ベース板4の線膨張率はモリブデ
ンで約4.9×10−6/K、タングステンで約4.6
×10−6/Kである。また、ヒートシンク等の冷却手
段5には熱伝導率の高い金属、例えば銅やアルミが使用
されるが、一般に熱伝導率の高い金属は、線膨張率も高
くなり、線膨張率は銅で約17.1×10−6/K、ア
ルミで約24.4×10−6/KとIGBTモジュール
1の線膨張率との差が非常に大きい。このようにIGB
Tモジュール1と冷却手段5とでは、使用されている部
材の線膨張率の差が大きく、動作時の温度変化により熱
伸び差が発生する。このため、IGBTモジュール1と
冷却手段5との間は、はんだなどを用いず、コンパウン
ド8を介して圧接することにより、熱応力や熱歪みを緩
和していた。
SUMMARY OF THE INVENTION These IGBT modules
In the internal structure of the tool 1, the joints due to temperature changes during operation
In order to reduce the thermal stress of
Uses a material that is close to the rate. I of IGBT module 1
The linear expansion coefficient of the GBT element 2 is about 3 × 10 -6/
K, the coefficient of linear expansion of the insulating substrate 3 is about 4 × 10
-6/ K, the coefficient of linear expansion of the metal base plate 4 for heat radiation is molybdenum
About 4.9 × 10-6/ K, about 4.6 for tungsten
× 10-6/ K. In addition, cooling hand such as heat sink
Step 5 is made of metal with high thermal conductivity, such as copper or aluminum
However, metals with high thermal conductivity generally have a high coefficient of linear expansion.
And the coefficient of linear expansion is about 17.1 × 10-6/ K, A
About 24.4 × 10 in Lumi-6/ K and IGBT module
The difference from the coefficient of linear expansion of 1 is very large. Thus IGB
The parts used between the T module 1 and the cooling means 5
The difference in the coefficient of linear expansion of the material is large, and heat changes due to temperature changes during operation.
A difference in elongation occurs. Therefore, the IGBT module 1
Use no compound between the cooling means 5 and the compound.
Pressure contact through the metal 8 reduces thermal stress and thermal strain.
It was sum.

【0004】しかしながら、IGBTモジュール1と冷
却手段5との間に介在して両者を熱的に接続するコンパ
ウンド8は、熱伝導率が1〜数Watt/m・K程度と
低く、冷却性能が低い。また熱変形によりIGBTモジ
ュール1と冷却手段5との間の寸法が変化し冷却性能が
安定しないものであった。このような傾向は、高電圧・
大電流化や高サイクル化などの大容量化にともない半導
体素子からの発熱量が増加し、さらに長期信頼性の観点
から熱サイクル数も増大している近年では顕著であり、
IGBTモジュール1の発熱を安定して効率よく外部に
放出することが困難であった。
However, the compound 8, which is interposed between the IGBT module 1 and the cooling means 5 and thermally connects the two, has a low thermal conductivity of about 1 to several Watt / m · K and a low cooling performance. . Further, the dimensions between the IGBT module 1 and the cooling means 5 change due to thermal deformation, and the cooling performance is not stable. This tendency is due to high voltage
The amount of heat generated from the semiconductor element has increased with the increase in capacity such as the increase in current and cycle, and the number of heat cycles has also increased in recent years, from the viewpoint of long-term reliability.
It has been difficult to stably and efficiently release the heat generated by the IGBT module 1 to the outside.

【0005】この発明は、上記のような問題点を解消す
るために成されたものであって、部材間の線膨張率の差
による熱応力、熱歪みを低減すると共に、パワー半導体
素子の発熱を良好な熱伝導により安定して効率的に放熱
できる信頼性の高いパワー半導体装置を得ることを目的
とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is intended to reduce thermal stress and thermal strain caused by a difference in linear expansion coefficient between members and to generate heat of a power semiconductor element. It is an object of the present invention to obtain a highly reliable power semiconductor device capable of stably and efficiently dissipating heat by good heat conduction.

【0006】[0006]

【課題を解決するための手段】この発明に係る請求項1
記載のパワー半導体装置は、パワー半導体素子を搭載し
た絶縁基板の下面と熱伝導性金属放熱板とを、孔の面内
占有率が30〜80%である熱伝導性ポーラス金属板を
介在して接合したものである。
Means for Solving the Problems Claim 1 according to the present invention.
In the power semiconductor device described above, the lower surface of the insulating substrate on which the power semiconductor element is mounted and the heat conductive metal radiator plate are interposed with a heat conductive porous metal plate having a hole occupancy of 30 to 80%. They are joined.

【0007】またこの発明に係る請求項2記載のパワー
半導体装置は、請求項1において、熱伝導性ポーラス金
属板の孔は、球状あるいは上記ポーラス金属板の面に対
してほぼ垂直方向に延びた形状の空洞である。
According to a second aspect of the present invention, there is provided the power semiconductor device according to the first aspect, wherein the hole of the heat conductive porous metal plate is spherical or extends substantially perpendicular to the surface of the porous metal plate. It is a cavity of a shape.

【0008】またこの発明に係る請求項3記載のパワー
半導体装置は、パワー半導体素子を搭載した絶縁基板の
下面と熱伝導性金属放熱板とを、熱伝導性ポーラス金属
板を介在して接合し、上記ポーラス金属板は該ポーラス
金属板の面に対してほぼ垂直方向に貫通した空洞を備
え、該空洞内に該ポーラス金属板の一面から他面まで貫
通する柱状の熱伝導性金属を該空洞側壁と微細な空隙で
離間して配設したものである。
According to a third aspect of the present invention, there is provided a power semiconductor device, wherein a lower surface of an insulating substrate on which a power semiconductor element is mounted and a heat conductive metal radiating plate are joined via a heat conductive porous metal plate. The porous metal plate includes a cavity penetrating in a direction substantially perpendicular to a surface of the porous metal plate, and a columnar heat conductive metal penetrating from one surface of the porous metal plate to another surface is formed in the cavity. It is disposed apart from the side wall by a minute gap.

【0009】またこの発明に係る請求項4記載のパワー
半導体装置は、請求項3において、常温からパワー半導
体素子の動作温度までの範囲において、空洞内の熱伝導
性金属と該空洞側壁との間で、空隙が確保されて離間状
態が継続するものである。
A power semiconductor device according to a fourth aspect of the present invention is the power semiconductor device according to the third aspect, wherein the power semiconductor device is provided between the heat conductive metal in the cavity and the side wall of the cavity in a range from room temperature to the operating temperature of the power semiconductor element. Thus, the gap is secured and the separated state continues.

【0010】またこの発明に係る請求項5記載のパワー
半導体装置は、請求項4において、空洞内の熱伝導性金
属は、ポーラス金属板の金属材料に比して低融点かつ線
膨張率が高い材料から成り、溶融含浸法により上記空洞
内に充填されて形成したものである。
According to a fifth aspect of the present invention, in the power semiconductor device according to the fourth aspect, the heat conductive metal in the cavity has a lower melting point and a higher linear expansion coefficient than the metal material of the porous metal plate. It is made of a material, and is formed by filling the above cavity by a melt impregnation method.

【0011】またこの発明に係る請求項6記載のパワー
半導体装置は、請求項1〜5のいずれかにおいて、ポー
ラス金属板の孔(空洞)による開口率は、該金属板の中
心部よりも外周部で大きいものである。
According to a sixth aspect of the present invention, there is provided the power semiconductor device according to any one of the first to fifth aspects, wherein the aperture ratio of the hole (cavity) of the porous metal plate is more outer than the center of the metal plate. It is big in part.

【0012】またこの発明に係る請求項7記載のパワー
半導体装置は、請求項1〜6のいずれかにおいて、ポー
ラス金属板の絶縁基板側にモリブデンあるいはタングス
テンから成る緩衝板を接合して用いたものである。
A power semiconductor device according to a seventh aspect of the present invention is the power semiconductor device according to any one of the first to sixth aspects, wherein a buffer plate made of molybdenum or tungsten is joined to the insulating substrate side of the porous metal plate. It is.

【0013】またこの発明に係る請求項8記載のパワー
半導体装置は、請求項7において、ポーラス金属板と緩
衝板との接合は、クラッドによる接合である。
According to an eighth aspect of the present invention, in the power semiconductor device according to the seventh aspect, the bonding between the porous metal plate and the buffer plate is performed by cladding.

【0014】またこの発明に係る請求項9記載のパワー
半導体装置は、パワー半導体素子を搭載した絶縁基板の
下面と熱伝導性金属放熱板とを、多数の柱状熱伝導性金
属を微細な空隙で互いに離間させて上記絶縁基板に対し
て垂直方向に配設した層を介在して接合したものであ
る。
According to a ninth aspect of the present invention, there is provided the power semiconductor device, wherein the lower surface of the insulating substrate on which the power semiconductor element is mounted and the heat conductive metal radiating plate are formed by forming a large number of columnar heat conductive metals with fine gaps. The insulating substrate is joined to the insulating substrate via a layer that is vertically separated from the insulating substrate.

【0015】[0015]

【発明の実施の形態】実施の形態1.以下、この発明の
実施の形態を図について説明する。図1は、この発明の
実施の形態1によるパワー半導体装置の断面図である。
図1において、9はパワーモジュールの一つであるIG
BTモジュール、10はパワー半導体素子としてのIG
BT素子、11は両面に銅等の金属の箔が接着された、
アルミナや窒化アルミ等からなる絶縁基板、12はモリ
ブデンやタングステン等からなる緩衝板、13は銅やア
ルミニウムなどからなる熱伝導性ポーラス金属板、14
はポーラス金属板13に設けられた空洞としての貫通孔
でポーラス金属板13の表面から裏面に抜ける方向に貫
通する。また、15は銅板やアルミニウム板などからな
る熱伝導性金属放熱板としての金属ベース板、16は銅
やアルミニウムなどからなるヒートシンクなどの冷却手
段である。また、17〜20は接合のためのはんだ、2
1は緩衝板12とポーラス金属板13との間のクラッド
接合部である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a power semiconductor device according to Embodiment 1 of the present invention.
In FIG. 1, reference numeral 9 denotes an IG which is one of the power modules.
BT module, 10 is IG as power semiconductor element
The BT element 11 has a metal foil such as copper adhered to both sides thereof,
An insulating substrate made of alumina or aluminum nitride, 12 a buffer plate made of molybdenum or tungsten, 13 a heat conductive porous metal plate made of copper or aluminum, 14
Is a through hole as a cavity provided in the porous metal plate 13 and penetrates in a direction from the surface of the porous metal plate 13 to the back surface. Reference numeral 15 denotes a metal base plate as a heat conductive metal radiating plate made of a copper plate or an aluminum plate, and 16 denotes a cooling means such as a heat sink made of copper or aluminum. 17 to 20 are solder for joining, 2
Reference numeral 1 denotes a clad joint between the buffer plate 12 and the porous metal plate 13.

【0016】図に示すように、複数のIGBT素子10
は絶縁基板11を介して金属ベース板15上に搭載され
るが、絶縁基板11と金属ベース板15とは、緩衝板1
2と所定の面内占有率で貫通孔14を有する熱伝導性ポ
ーラス金属板13とを介在して接合される。また、金属
ベース板15上の構造物は、図示しない樹脂により覆わ
れてIGBTモジュール9を構成する。また、IGBT
素子10は絶縁基板11上に、絶縁基板11は緩衝板1
2上にそれぞれはんだ17、18で接合され、緩衝板1
2とポーラス金属板13とは、異なる材料の金属を界面
で強固に圧接接合するクラッド接合21により接合され
ている。また、ポーラス金属板13は金属ベース板15
上にはんだ19で接合され、さらに金属ベース板15は
冷却手段16にはんだ20で接合されている。
As shown in the drawing, a plurality of IGBT elements 10
Is mounted on the metal base plate 15 via the insulating substrate 11. The insulating substrate 11 and the metal base plate 15
2 and a thermally conductive porous metal plate 13 having through holes 14 with a predetermined in-plane occupancy. The structure on the metal base plate 15 is covered with a resin (not shown) to form the IGBT module 9. Also, IGBT
The element 10 is on the insulating substrate 11, and the insulating substrate 11 is
2 are joined by solders 17 and 18, respectively,
The metal plate 2 and the porous metal plate 13 are joined by a clad joint 21 which strongly joins metals of different materials by pressure at the interface. Further, the porous metal plate 13 is a metal base plate 15.
The metal base plate 15 is joined to the cooling means 16 by solder 20.

【0017】このように構成されるパワー半導体装置で
は、動作時にパワー半導体素子10で発生した熱は熱伝
導によって絶縁基板11、緩衝板12、ポーラス金属板
13、金属ベース板15を順次経て冷却手段16に伝導
されて冷却される。この熱伝導経路において、上述した
ように、シリコンなどから成るパワー半導体素子10お
よび窒化アルミニウムなどから成る絶縁基板11の線膨
張率は小さく、銅やアルミニウムなどから成る冷却手段
16は線膨張率が大きい。この実施の形態では、冷却手
段16上の金属ベース板15を銅やアルミなど、線膨張
率の大きな熱伝導性金属で構成し、この線膨張率の大き
な金属ベース板15と線膨張率の小さな絶縁基板11と
の間に、緩衝板12およびポーラス金属板13を挿入し
た。
In the power semiconductor device configured as described above, the heat generated in the power semiconductor element 10 during operation passes through the insulating substrate 11, the buffer plate 12, the porous metal plate 13, and the metal base plate 15 by heat conduction in order, and the cooling means. It is conducted to 16 and cooled. In this heat conduction path, as described above, the power semiconductor element 10 made of silicon or the like and the insulating substrate 11 made of aluminum nitride or the like have a small coefficient of linear expansion, and the cooling means 16 made of copper or aluminum has a large coefficient of linear expansion. . In this embodiment, the metal base plate 15 on the cooling means 16 is made of a thermally conductive metal having a large linear expansion coefficient such as copper or aluminum. The buffer plate 12 and the porous metal plate 13 were inserted between the insulating substrate 11.

【0018】ポーラス金属板13は銅やアルミニウムな
どの熱伝導率及び線膨張率の大きな熱伝導性金属で構成
され、図2に示すように、ポーラス金属板13の面に対
してほぼ垂直方向に貫通する貫通孔14を有する。この
貫通孔14は、径寸法が1μ〜5mm程度、面内占有率
は30〜80%程度であり、この比較的大きな面内占有
率を有する貫通孔14のためにポーラス金属板13は剛
性が低くたわみ易くなっている。このため、動作時の温
度変化により図3に示すようにたわみ、線膨張率の大き
な金属ベース板15と線膨張率の小さな絶縁基板11と
の熱伸び差を吸収し、応力を緩和できる。また、ポーラ
ス金属板13の絶縁基板11側に挿入する緩衝板12
は、モリブデンやタングステンなど、線膨張率が小さく
て剛性が高い材料を使用したため、絶縁基板11への熱
応力の影響をさらに緩和できると共に、緩衝板12と絶
縁基板11との間のはんだによる接合部に発生する熱応
力を低減して長期信頼性を向上する。また、この緩衝板
12の材料は、熱伝導性も良好(モリブデンの熱伝導
率;138Watt/m・K)である。さらに、緩衝板
12はポーラス金属板13とクラッドにより界面で強固
に接合されているため、接合部21の信頼性が高く、ま
た緩衝板12とポーラス金属板13との間で、安定して
良好な熱伝導性が得られる。
The porous metal plate 13 is made of a heat conductive metal having a high thermal conductivity and a high coefficient of linear expansion, such as copper and aluminum, and is substantially perpendicular to the surface of the porous metal plate 13 as shown in FIG. It has a through hole 14 that penetrates. The diameter of the through hole 14 is about 1 μm to 5 mm and the in-plane occupancy is about 30 to 80%. The porous metal plate 13 has rigidity because of the through hole 14 having the relatively large in-plane occupancy. It is low and easy to bend. For this reason, as shown in FIG. 3 due to a temperature change during operation, the difference in thermal expansion between the metal base plate 15 having a large linear expansion coefficient and the insulating substrate 11 having a small linear expansion coefficient can be absorbed, and the stress can be reduced. Further, a buffer plate 12 inserted into the insulating substrate 11 side of the porous metal plate 13 is provided.
Is made of a material having a low linear expansion coefficient and high rigidity such as molybdenum and tungsten, so that the effect of thermal stress on the insulating substrate 11 can be further reduced, and the bonding between the buffer plate 12 and the insulating substrate 11 by soldering The thermal stress generated in the part is reduced to improve long-term reliability. The material of the buffer plate 12 has good thermal conductivity (molybdenum thermal conductivity; 138 Watt / mK). Furthermore, since the buffer plate 12 is firmly bonded at the interface with the porous metal plate 13 and the clad, the reliability of the bonding portion 21 is high, and the buffer plate 12 and the porous metal plate 13 are stable and good. High thermal conductivity is obtained.

【0019】このように、緩衝板12およびポーラス金
属板13により金属ベース板15と絶縁基板11との間
の線膨張率の差による熱応力が緩和できると共に、IG
BT素子10の発熱を良好な熱伝導により安定して効率
的に放熱できる。
As described above, the buffer plate 12 and the porous metal plate 13 can alleviate the thermal stress caused by the difference in the coefficient of linear expansion between the metal base plate 15 and the insulating substrate 11, and can reduce the IG.
The heat generated by the BT element 10 can be stably and efficiently radiated by good heat conduction.

【0020】ところで、上述したようなポーラス金属板
は、液体金属中でガス原子の溶解度が大きく凝固して固
体に変態するとガス原子の固溶度が小さい材料を、高圧
ガス(水素あるいは酸素)雰囲気で溶解し凝固させるこ
とによって形成するもので、ポア(孔)の径寸法が1μ
〜5mm程度、面内占有率は30〜80%程度である。
また、形成時に型に流し込んだ溶融金属を、例えば下方
から、あるいは側面から一方向凝固させると、ポア
(孔)の成長方向を自由に制御できる。また、溶融温
度、凝固冷却速度、ガス圧力等の制御パラメータを制御
することにより、ポアサイズ、面内占有率も制御でき
る。このように形成されたポーラス金属板は、機械的強
度が比較的強く、また大きな面内占有率(30〜80%
程度)のポアが形成されて、機械的性質を維持しつつた
やみ易いため、上記の様に効果的に熱応力が緩和でき
る。また、熱伝導性金属を用いて構成したため、熱伝導
性も優れている。なお、鋳造法、メッキ法等により形成
されるポーラス金属では、80%を越える面内占有率の
ポアを有するものがあるが、機械的強度が低い、ポア形
成の制御が十分に行えない、さらに面内占有率が大き過
ぎて熱伝導性が悪くなる等のため、適さない。
By the way, the porous metal plate as described above is made of a material in which the solubility of gas atoms is large in a liquid metal and which solidifies when transformed into a solid and has a low solid solubility of gas atoms, in a high-pressure gas (hydrogen or oxygen) atmosphere. It is formed by dissolving and coagulating in a pore.
55 mm, and the in-plane occupancy is about 30-80%.
In addition, when the molten metal poured into the mold at the time of forming is unidirectionally solidified, for example, from below or from the side, the growth direction of the pores (holes) can be freely controlled. Further, by controlling control parameters such as melting temperature, solidification cooling rate, and gas pressure, the pore size and the in-plane occupancy can be controlled. The porous metal plate thus formed has relatively high mechanical strength and a large in-plane occupancy (30 to 80%).
) Pores are formed and are easily flexible while maintaining mechanical properties, so that thermal stress can be effectively reduced as described above. In addition, since it is configured using a heat conductive metal, the heat conductivity is also excellent. Some porous metals formed by a casting method, a plating method, or the like have pores having an in-plane occupancy of more than 80%. However, the mechanical strength is low, and the formation of pores cannot be sufficiently controlled. It is not suitable because the in-plane occupancy is too large and the thermal conductivity deteriorates.

【0021】上記実施の形態では、貫通孔14を有する
ポーラス金属板13を用いたが、ポアは貫通していなく
ても良く、上記ポーラス金属板13の面に対してほぼ垂
直方向に延びた形状の空洞、あるいは球状孔であっても
良い。これにより、金属ベース板15と絶縁基板11と
の間に生じる面方向の熱伸び差による応力を効果的に低
減できる。また、ポーラス金属板13のポアによる開口
率は、中心部よりも外周部で大きくすると、外周部での
柔軟性が大きくなり効果的にたわみを発生させることが
できると共に、中心部の熱伝導量を大きくでき、放熱効
果を向上できる。
In the above embodiment, the porous metal plate 13 having the through-holes 14 is used, but the pores do not have to penetrate, and the porous metal plate 13 extends in a direction substantially perpendicular to the surface of the porous metal plate 13. Or a spherical hole. Thereby, stress due to a difference in thermal expansion in the plane direction generated between the metal base plate 15 and the insulating substrate 11 can be effectively reduced. When the aperture ratio of the porous metal plate 13 due to the pores is larger at the outer peripheral portion than at the central portion, the flexibility at the outer peripheral portion is increased and the deflection can be generated effectively, and the heat conduction amount at the central portion can be increased. And the heat radiation effect can be improved.

【0022】また、上記実施の形態では、緩衝板12は
ポーラス金属板13とクラッドにより接合したが、熱伝
導性、および強度の観点から劣るものであるが、はんだ
により接合しても良い。さらに、緩衝板12を設けずに
ポーラス金属板13のみを金属ベース板15と絶縁基板
11との間に介在させてもよく、熱応力の緩和効果を得
ることができる。
In the above embodiment, the cushioning plate 12 is joined to the porous metal plate 13 by cladding. However, it is inferior in terms of thermal conductivity and strength, but may be joined by soldering. Further, only the porous metal plate 13 may be interposed between the metal base plate 15 and the insulating substrate 11 without providing the buffer plate 12, and an effect of reducing thermal stress can be obtained.

【0023】さらにまた、金属ベース板15を設けず、
熱伝導性放熱板となる冷却手段16をIGBTモジュー
ル9のベース板に用い、これにポーラス金属板13を直
接接合して用いることもできる。
Furthermore, without providing the metal base plate 15,
The cooling means 16 serving as a heat conductive heat radiating plate may be used as the base plate of the IGBT module 9 and the porous metal plate 13 may be directly bonded to the base plate.

【0024】実施の形態2.次に、この発明の実施の形
態2を図4に基づいて説明する。上記実施の形態1で
は、貫通孔14を有するポーラス金属板13を用いた
が、この実施の形態2では、図4に示すように、熱伝導
性ポーラス金属板22の空洞としての貫通孔23内に柱
状の熱伝導性金属としての柱状熱伝導体24を挿入した
ものを用いる。熱伝導性ポーラス金属板22の母材を例
えば銅で構成し、貫通孔23内に、銅よりも低融点で線
膨張率の高い金属材料である、例えばアルミニウムから
成る柱状熱伝導体24を、貫通孔23の側壁と微細な空
隙23aで離間させて挿入する。なお、ポーラス金属板
22以外の構成は、上記実施の形態1と同様である。
Embodiment 2 FIG. Next, a second embodiment of the present invention will be described with reference to FIG. In the first embodiment, the porous metal plate 13 having the through holes 14 is used. In the second embodiment, however, as shown in FIG. In this case, a columnar heat conductor 24 as a columnar heat conductive metal is inserted. The base material of the heat conductive porous metal plate 22 is made of, for example, copper, and a columnar heat conductor 24 made of, for example, aluminum, which is a metal material having a lower melting point and a higher linear expansion coefficient than copper, is formed in the through hole 23. It is inserted away from the side wall of the through hole 23 by a minute gap 23a. The configuration other than the porous metal plate 22 is the same as that of the first embodiment.

【0025】このようなポーラス金属板22は、上記実
施の形態1と同様に貫通孔23を有するポーラス金属板
22を形成し、その後、柱状熱伝導体24の融点とポー
ラス金属板の母材21の融点との間の温度に加熱してポ
ーラス金属板22の貫通孔23に溶融状態の柱状熱伝導
体24を含浸させる、いわゆる溶融含浸法によって製作
する。上記のように、例えば、ポーラス金属板22の母
材に融点が1357.6Kの銅、柱状熱伝導体24に融
点が933.5Kのアルミニウムを使用することがで
き、しかもアルミニウムの線膨張率は銅の線膨張率より
大きいので、常温に近い動作温度まで冷却すると貫通孔
23側壁と柱状熱伝導体24との間に微小な空隙23a
ができる。また、この空隙23aは、常温からパワー半
導体装置の動作温度までの範囲で確保されて、貫通孔2
3の側壁と柱状熱伝導体24とは確実に離間される。
The porous metal plate 22 forms a porous metal plate 22 having a through hole 23 in the same manner as in the first embodiment, and thereafter, the melting point of the columnar heat conductor 24 and the base material 21 of the porous metal plate are formed. Is manufactured by a so-called melt impregnation method in which the through-holes 23 of the porous metal plate 22 are impregnated with the molten columnar heat conductor 24 by heating to a temperature between the melting points of the porous metal plates 22. As described above, for example, copper having a melting point of 1357.6 K can be used for the base material of the porous metal plate 22, and aluminum having a melting point of 933.5 K can be used for the columnar heat conductor 24. Since it is larger than the linear expansion coefficient of copper, when it is cooled to an operating temperature close to room temperature, a minute gap 23 a is formed between the side wall of the through hole 23 and the columnar heat conductor 24.
Can be. The space 23a is secured in a range from room temperature to the operating temperature of the power semiconductor device, and the through hole 2a is formed.
The side wall 3 and the columnar heat conductor 24 are surely separated from each other.

【0026】この実施の形態2では、貫通孔23内に柱
状熱伝導体24を挿入したため、ポーラス金属板22の
母材だけでなく、柱状熱伝導体24によっても熱伝導が
為され、熱伝導性能が高くなる。また、常温からパワー
半導体装置の動作温度までの範囲で貫通孔23側壁と柱
状熱伝導体24との間の空隙23aが確保されているた
め、ポーラス金属板24がたわむ際に、ポーラス金属板
22の母材と柱状熱伝導体24とが互いに干渉せず、た
わみによる効果を妨げることがない。このため、動作時
の温度変化により図5に示すようにたわみ、線膨張率の
大きな金属ベース板15と線膨張率の小さな絶縁基板1
1との熱伸び差を吸収し、上記実施の形態1と同様の熱
応力緩和効果を有すると共に、熱伝導性がさらに良くな
るため、放熱効果が向上する。
In the second embodiment, since the columnar heat conductor 24 is inserted into the through hole 23, heat is conducted not only by the base material of the porous metal plate 22 but also by the columnar heat conductor 24, and the heat conduction is performed. High performance. Further, since the gap 23a between the side wall of the through hole 23 and the columnar heat conductor 24 is secured in the range from room temperature to the operating temperature of the power semiconductor device, when the porous metal plate 24 bends, Does not interfere with each other, and does not hinder the effect of bending. Therefore, the metal base plate 15 having a large linear expansion coefficient and the insulating substrate 1 having a small linear expansion coefficient are bent as shown in FIG.
In addition to absorbing the difference in thermal elongation from the first embodiment and having the same thermal stress relaxation effect as in the first embodiment, the thermal conductivity is further improved, so that the heat radiation effect is improved.

【0027】なお、柱状熱伝導体24を機械加工によっ
て貫通孔23よりごくわずかに小さく製作して挿入して
も良く、その場合は、柱状熱伝導体24の材料をポーラ
ス金属板22の母材よりも低融点で線膨張率の高いもの
とする必要はなく、共に熱伝導性の良い材料で、常温か
らパワー半導体装置の動作温度までの範囲で貫通孔23
側壁と柱状熱伝導体24との間の空隙23aが確保でき
ればよい。
Note that the columnar heat conductor 24 may be manufactured to be slightly smaller than the through hole 23 by machining and inserted. In this case, the material of the columnar heat conductor 24 is changed to the base material of the porous metal plate 22. It is not necessary to use a material having a lower melting point and a higher coefficient of linear expansion than the material.
It is sufficient that a gap 23a between the side wall and the columnar heat conductor 24 can be secured.

【0028】また、上記実施の形態2において、ポーラ
ス金属板22の母材がない状態、即ち、多数の柱状熱伝
導体24を微細な空隙で互いに離間させて配設した層
を、ポーラス金属板22の替わりに用いると、熱応力の
緩和効果がさらに向上する。この場合、多数の柱状熱伝
導体24を支持する支持板を下層の金属ベース板15
側、あるいは、上下両側に設けても良い。
In the second embodiment, the porous metal plate 22 has no base material, that is, a layer in which a number of columnar heat conductors 24 are spaced apart from each other by fine voids. When used in place of 22, the effect of reducing thermal stress is further improved. In this case, the support plate for supporting the large number of columnar heat conductors 24 is replaced with the lower metal base plate 15.
It may be provided on the side, or both upper and lower sides.

【0029】[0029]

【発明の効果】以上のように、この発明に係る請求項1
記載のパワー半導体装置は、パワー半導体素子を搭載し
た絶縁基板の下面と熱伝導性金属放熱板とを、孔の面内
占有率が30〜80%である熱伝導性ポーラス金属板を
介在して接合したため、絶縁基板と熱伝導性金属放熱板
との間での熱応力、熱歪みを低減すると共に、パワー半
導体素子の発熱を良好な熱伝導により安定して効率的に
放熱できる。
As described above, the first aspect of the present invention is as follows.
In the power semiconductor device described above, the lower surface of the insulating substrate on which the power semiconductor element is mounted and the heat conductive metal radiator plate are interposed with a heat conductive porous metal plate having a hole occupancy of 30 to 80%. Because of the bonding, thermal stress and thermal distortion between the insulating substrate and the heat conductive metal heat radiating plate can be reduced, and the heat generated by the power semiconductor element can be stably and efficiently radiated by good heat conduction.

【0030】またこの発明に係る請求項2記載のパワー
半導体装置は、請求項1において、熱伝導性ポーラス金
属板の孔は、球状あるいは上記ポーラス金属板の面に対
してほぼ垂直方向に延びた形状の空洞であるため、絶縁
基板と熱伝導性金属放熱板との間に生じる面方向の熱伸
び差による応力を効果的に低減できる。
According to a second aspect of the present invention, there is provided the power semiconductor device according to the first aspect, wherein the hole of the heat conductive porous metal plate is spherical or extends substantially perpendicular to the surface of the porous metal plate. Due to the shape of the cavity, the stress caused by the difference in thermal expansion in the plane direction generated between the insulating substrate and the heat conductive metal radiating plate can be effectively reduced.

【0031】またこの発明に係る請求項3記載のパワー
半導体装置は、パワー半導体素子を搭載した絶縁基板の
下面と熱伝導性金属放熱板とを、熱伝導性ポーラス金属
板を介在して接合し、上記ポーラス金属板は該ポーラス
金属板の面に対してほぼ垂直方向に貫通した空洞を備
え、該空洞内に該ポーラス金属板の一面から他面まで貫
通する柱状の熱伝導性金属を該空洞側壁と微細な空隙で
離間して配設したため、絶縁基板と熱伝導性金属放熱板
との間での熱応力、熱歪みを低減すると共に、パワー半
導体素子の発熱をさらに良好な熱伝導により、一層効率
的に放熱できる。
According to a third aspect of the present invention, in the power semiconductor device, the lower surface of the insulating substrate on which the power semiconductor element is mounted and the heat conductive metal radiating plate are joined via the heat conductive porous metal plate. The porous metal plate includes a cavity penetrating in a direction substantially perpendicular to a surface of the porous metal plate, and a columnar heat conductive metal penetrating from one surface of the porous metal plate to another surface is formed in the cavity. Since it is arranged apart from the side wall with a minute gap, thermal stress and thermal distortion between the insulating substrate and the heat conductive metal heat sink are reduced, and the heat generation of the power semiconductor element is further improved by better heat conduction. Heat can be dissipated more efficiently.

【0032】またこの発明に係る請求項4記載のパワー
半導体装置は、請求項3において、常温からパワー半導
体素子の動作温度までの範囲において、空洞内の熱伝導
性金属と該空洞側壁との間で、空隙が確保されて離間状
態が継続するため、安定して信頼性の高い放熱性能が得
られる。
According to a fourth aspect of the present invention, there is provided the power semiconductor device according to the third aspect, wherein the power semiconductor device is provided between the heat conductive metal in the cavity and the side wall of the cavity in a range from room temperature to the operating temperature of the power semiconductor element. As a result, the gap is secured and the separated state continues, so that stable and reliable heat radiation performance can be obtained.

【0033】またこの発明に係る請求項5記載のパワー
半導体装置は、請求項4において、空洞内の熱伝導性金
属は、ポーラス金属板の金属材料に比して低融点かつ線
膨張率が高い材料から成り、溶融含浸法により上記空洞
内に充填されて形成したため、空洞内の熱伝導性金属と
該空洞側壁との間に微細な空隙が制御性良く容易に確保
でき、安定して信頼性の高い放熱性能が容易に得られ
る。
According to a fifth aspect of the present invention, in the power semiconductor device according to the fourth aspect, the heat conductive metal in the cavity has a lower melting point and a higher linear expansion coefficient than the metal material of the porous metal plate. It is made of a material and formed by filling the cavity by the melt impregnation method, so that a fine gap can be easily secured with good controllability between the heat conductive metal in the cavity and the side wall of the cavity, and the reliability is stable. High heat dissipation performance can be easily obtained.

【0034】またこの発明に係る請求項6記載のパワー
半導体装置は、請求項1〜5のいずれかにおいて、ポー
ラス金属板の孔(空洞)による開口率は、該金属板の中
心部よりも外周部で大きいため、効果的に熱応力が緩和
できると共に、放熱効果を向上できる。
According to a sixth aspect of the present invention, there is provided the power semiconductor device according to any one of the first to fifth aspects, wherein the aperture ratio of the hole (cavity) of the porous metal plate is more outer than the center of the metal plate. Since it is large in the portion, the thermal stress can be effectively reduced and the heat radiation effect can be improved.

【0035】またこの発明に係る請求項7記載のパワー
半導体装置は、請求項1〜6のいずれかにおいて、ポー
ラス金属板の絶縁基板側にモリブデンあるいはタングス
テンから成る緩衝板を接合して用いたため、絶縁基板及
びパワー半導体素子への熱応力の影響をさらに低減でき
る。
According to a seventh aspect of the present invention, in the power semiconductor device according to any one of the first to sixth aspects, a buffer plate made of molybdenum or tungsten is joined to an insulating substrate side of the porous metal plate. The influence of thermal stress on the insulating substrate and the power semiconductor element can be further reduced.

【0036】またこの発明に係る請求項8記載のパワー
半導体装置は、請求項7において、ポーラス金属板と緩
衝板との接合は、クラッドによる接合であるため、強固
で信頼性が高く、また熱伝導性が良好な接合が形成でき
る。
In the power semiconductor device according to the present invention, since the bonding between the porous metal plate and the buffer plate is performed by cladding, the power semiconductor device is strong, has high reliability, and has high thermal conductivity. A junction having good conductivity can be formed.

【0037】またこの発明に係る請求項9記載のパワー
半導体装置は、パワー半導体素子を搭載した絶縁基板の
下面と熱伝導性金属放熱板とを、多数の柱状熱伝導性金
属を微細な空隙で互いに離間させて上記絶縁基板に対し
て垂直方向に配設した層を介在して接合したため、絶縁
基板と熱伝導性金属放熱板との間での熱応力、熱歪みを
一層低減できると共に、パワー半導体素子の発熱を良好
な熱伝導により安定して効率的に放熱できる。
According to a ninth aspect of the present invention, in the power semiconductor device, the lower surface of the insulating substrate on which the power semiconductor element is mounted and the heat conductive metal radiating plate are formed by forming a large number of columnar heat conductive metals with fine gaps. Since the layers are vertically separated from the insulating substrate and are bonded to each other with an interval therebetween, thermal stress and thermal distortion between the insulating substrate and the heat conductive metal radiating plate can be further reduced, and the power The heat generated by the semiconductor element can be stably and efficiently radiated by good heat conduction.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 この発明の実施の形態1によるパワー半導体
装置の構造を示す断面図である。
FIG. 1 is a sectional view showing a structure of a power semiconductor device according to a first embodiment of the present invention.

【図2】 この発明の実施の形態1によるポーラス金属
板を示す斜視図である。
FIG. 2 is a perspective view showing a porous metal plate according to Embodiment 1 of the present invention.

【図3】 この発明の実施の形態1によるポーラス金属
板の動作時のたわみを説明する図である。
FIG. 3 is a diagram for explaining deflection of the porous metal plate during operation according to the first embodiment of the present invention.

【図4】 この発明の実施の形態2によるパワー半導体
装置の構造を示す断面図である。
FIG. 4 is a sectional view showing a structure of a power semiconductor device according to a second embodiment of the present invention;

【図5】 この発明の実施の形態2によるポーラス金属
板の動作時のたわみを説明する図である。
FIG. 5 is a diagram for explaining deflection of the porous metal plate during operation according to the second embodiment of the present invention.

【図6】 従来のパワー半導体装置の構造を示す断面図
である。
FIG. 6 is a cross-sectional view showing a structure of a conventional power semiconductor device.

【符号の説明】[Explanation of symbols]

10 パワー半導体素子としてのIGBT素子、11
絶縁基板、12 緩衝板、13 熱伝導性ポーラス金属
板、14 空洞としての貫通孔、15 放熱板としての
金属ベース板、16 放熱板としての冷却手段、21
クラッド接合部、22 熱伝導性ポーラス金属板、23
空洞としての貫通孔、23a 空隙、24 柱状の熱
伝導性金属としての柱状熱伝導体。
10 IGBT element as power semiconductor element, 11
Insulating substrate, 12 buffer plate, 13 heat conductive porous metal plate, 14 through hole as cavity, 15 metal base plate as heat sink, 16 cooling means as heat sink, 21
Clad joint, 22 heat conductive porous metal plate, 23
Through holes as cavities, 23a voids, 24 columnar heat conductors as columnar heat conductive metals.

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 パワー半導体素子を搭載した絶縁基板の
下面と熱伝導性金属放熱板とを、孔の面内占有率が30
〜80%である熱伝導性ポーラス金属板を介在して接合
したことを特徴とするパワー半導体装置。
1. The method according to claim 1, wherein the lower surface of the insulating substrate on which the power semiconductor element is mounted and the heat conductive metal radiating plate have a hole occupancy of 30%.
A power semiconductor device characterized by being joined by interposing a thermally conductive porous metal plate of up to 80%.
【請求項2】 熱伝導性ポーラス金属板の孔は、球状あ
るいは上記ポーラス金属板の面に対してほぼ垂直方向に
延びた形状の空洞であることを特徴とする請求項1記載
のパワー半導体装置。
2. The power semiconductor device according to claim 1, wherein the hole of the heat conductive porous metal plate is a cavity having a spherical shape or a shape extending substantially perpendicular to the surface of the porous metal plate. .
【請求項3】 パワー半導体素子を搭載した絶縁基板の
下面と熱伝導性金属放熱板とを、熱伝導性ポーラス金属
板を介在して接合し、上記ポーラス金属板は該ポーラス
金属板の面に対してほぼ垂直方向に貫通した空洞を備
え、該空洞内に該ポーラス金属板の一面から他面まで貫
通する柱状の熱伝導性金属を該空洞側壁と微細な空隙で
離間して配設したことを特徴とするパワー半導体装置。
3. A lower surface of an insulating substrate on which a power semiconductor element is mounted and a heat conductive metal radiator plate are joined with a heat conductive porous metal plate interposed therebetween, and the porous metal plate is connected to a surface of the porous metal plate. A hollow which penetrates the porous metal plate from one side to the other side is provided in the cavity, and a columnar heat conductive metal is arranged in the cavity so as to be separated from the side wall of the hollow by a minute gap. Power semiconductor device characterized by the above-mentioned.
【請求項4】 常温からパワー半導体素子の動作温度ま
での範囲において、空洞内の熱伝導性金属と該空洞側壁
との間で、空隙が確保されて離間状態が継続することを
特徴とする請求項3記載のパワー半導体装置。
4. A space is maintained between the heat conductive metal in the cavity and the side wall of the cavity in a range from room temperature to the operating temperature of the power semiconductor element, and the separated state is continued. Item 4. The power semiconductor device according to Item 3.
【請求項5】 空洞内の熱伝導性金属は、ポーラス金属
板の金属材料に比して低融点かつ線膨張率が高い材料か
ら成り、溶融含浸法により上記空洞内に充填されて形成
したものであることを特徴とする請求項4記載のパワー
半導体装置。
5. The heat conductive metal in the cavity is made of a material having a lower melting point and a higher linear expansion coefficient than the metal material of the porous metal plate, and is formed by filling the cavity by a melt impregnation method. The power semiconductor device according to claim 4, wherein:
【請求項6】 ポーラス金属板の孔(空洞)による開口
率は、該金属板の中心部よりも外周部で大きいことを特
徴とする請求項1〜5のいずれかに記載のパワー半導体
装置。
6. The power semiconductor device according to claim 1, wherein an aperture ratio of the porous metal plate due to a hole (cavity) is larger at an outer peripheral portion than at a central portion of the metal plate.
【請求項7】 ポーラス金属板の絶縁基板側にモリブデ
ンあるいはタングステンから成る緩衝板を接合して用い
たことを特徴とする請求項1〜6のいずれかに記載のパ
ワー半導体装置。
7. The power semiconductor device according to claim 1, wherein a buffer plate made of molybdenum or tungsten is bonded to an insulating substrate side of the porous metal plate.
【請求項8】 ポーラス金属板と緩衝板との接合は、ク
ラッドによる接合であることを特徴とする請求項7記載
のパワー半導体装置。
8. The power semiconductor device according to claim 7, wherein the bonding between the porous metal plate and the buffer plate is performed by cladding.
【請求項9】 パワー半導体素子を搭載した絶縁基板の
下面と熱伝導性金属放熱板とを、多数の柱状熱伝導性金
属を微細な空隙で互いに離間させて上記絶縁基板に対し
て垂直方向に配設した層を介在して接合したことを特徴
とするパワー半導体装置。
9. A lower surface of an insulating substrate on which a power semiconductor element is mounted and a heat conductive metal radiator are separated from each other by a plurality of columnar heat conductive metals with minute gaps so as to be perpendicular to the insulating substrate. A power semiconductor device, wherein the power semiconductor device is joined with an interposed layer.
JP2001033121A 2001-02-09 2001-02-09 Power semiconductor device Pending JP2002237556A (en)

Priority Applications (1)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Publications (1)

Publication Number Publication Date
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Family

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Country Status (1)

Country Link
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