JP2007311448A5 - - Google Patents
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- JP2007311448A5 JP2007311448A5 JP2006137281A JP2006137281A JP2007311448A5 JP 2007311448 A5 JP2007311448 A5 JP 2007311448A5 JP 2006137281 A JP2006137281 A JP 2006137281A JP 2006137281 A JP2006137281 A JP 2006137281A JP 2007311448 A5 JP2007311448 A5 JP 2007311448A5
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- 239000004065 semiconductor Substances 0.000 claims 28
- 238000009792 diffusion process Methods 0.000 claims 6
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Claims (23)
上記第１電流密度よりも小さな第２電流密度の第２電流が流れるようにされた第２トランジスタと、
ＭＯＳＦＥＴにより構成された増幅回路と、
第１抵抗素子と、
電流源回路と、
第３トランジスタ及び第２抵抗素子とを備え、
上記第１トランジスタのベースと上記第２トランジスタのベースは、共通に接続されて上記増幅回路の出力電圧に対応した電圧が供給され、
上記第１トランジスタのエミッタは、第１電源電圧端子に接続され、
上記第１抵抗素子は、上記第２トランジスタのエミッタと上記第１電源電圧端子との間に接続されて基準電流を形成し、
上記増幅回路は、上記第１トランジスタと第２トランジスタのコレクタ電圧の差電圧に対応した出力電圧を形成し、
上記電流源回路は、上記基準電流に対応した電流を上記第１、第２、第３トランジスタに供給し、
上記第３トランジスタは、そのベースとコレクタとが共通接続され、
上記第２抵抗素子は、上記第３トランジスタと上記第１電源電圧端子又は第２電源電圧端子側に直列形態に接続され、
上記第３トランジスタのサイズ、上記第１及び第２抵抗素子の抵抗値の設定により、上記第３トランジスタと第２抵抗素子の直列回路で発生する電圧を基準電圧とする基準電圧発生回路を有する半導体集積回路装置。 A first transistor configured to flow a first current having a first current density;
A second transistor configured to flow a second current having a second current density smaller than the first current density;
An amplifier circuit composed of a MOSFET;
A first resistance element;
A current source circuit;
A third transistor and a second resistance element;
The base of the first transistor and the base of the second transistor are connected in common and supplied with a voltage corresponding to the output voltage of the amplifier circuit,
An emitter of the first transistor is connected to a first power supply voltage terminal;
The first resistance element is connected between the emitter of the second transistor and the first power supply voltage terminal to form a reference current,
The amplifier circuit forms an output voltage corresponding to a voltage difference between collector voltages of the first transistor and the second transistor,
The current source circuit supplies a current corresponding to the reference current to the first, second, and third transistors,
The third transistor has a base and a collector connected together,
The second resistance element is connected in series to the third transistor and the first power supply voltage terminal or the second power supply voltage terminal side,
Said third transistor sizes, by setting the resistance value of the first and second resistive element, a semiconductor having a reference voltage generating circuit as a reference voltage a voltage generated by the series circuit of the third transistor and the second resistor element Integrated circuit device.
第３抵抗素子を更に備え、
上記第３抵抗素子は、上記第３トランジスタと第２抵抗素子との直列回路に対して並列に接続されていることを特徴とする半導体集積回路装置。 In claim 1,
A third resistance element;
The third resistor element, a semiconductor integrated circuit device, characterized in that connected in parallel with the series circuit between the third transistor and the second resistor element.
上記第１トランジスタと第３トランジスタは、同じエミッタ面積を備え、
上記第１トランジスタのエミッタ面積は、上記第２トランジスタのエミッタ面積よりも大きく形成され、第１乃至第３トランジスタには同じ電流値の電流が流れるようにされる半導体集積回路装置。 In claim 2,
The first transistor and the third transistor have the same emitter area,
A semiconductor integrated circuit device, wherein an emitter area of the first transistor is formed larger than an emitter area of the second transistor, and currents of the same current value flow through the first to third transistors.
上記第１、第２、第３トランジスタは、差動増幅回路を構成するＣＭＯＳ回路のプロセスで形成される半導体領域を利用して構成される半導体集積回路装置。 In claim 3,
The first , second, and third transistors are semiconductor integrated circuit devices configured using a semiconductor region formed by a CMOS circuit process that forms a differential amplifier circuit.
上記増幅回路は、上記第１トランジスタと第２トランジスタのコレクタ電圧を受ける差動増幅回路であり、
上記電流源回路は、上記第２トランジスタのコレクタ電流を入力電流とするＭＯＳＦＥＴで構成された電流ミラー回路である半導体集積回路装置。 In claim 3,
The amplifier circuit is a differential amplifier circuit that receives collector voltages of the first transistor and the second transistor,
The semiconductor integrated circuit device, wherein the current source circuit is a current mirror circuit composed of a MOSFET having the collector current of the second transistor as an input current.
上記増幅回路は、上記第１トランジスタと第２トランジスタのコレクタ電圧を受ける差動増幅回路であり、
上記電流源回路は、
上記第２トランジスタのコレクタ電流を入力電流として上記第１トランジスタのコレクタ電流を形成するＭＯＳＦＥＴで構成された電流ミラー回路と、
上記第１トランジスタとベース，エミッタが共通接続され、同じエミッタサイズに形成された第４トランジスタとを含む半導体集積回路装置。 In claim 3,
The amplifier circuit is a differential amplifier circuit that receives collector voltages of the first transistor and the second transistor,
The current source circuit is
A current mirror circuit composed of a MOSFET that forms the collector current of the first transistor using the collector current of the second transistor as an input current;
A semiconductor integrated circuit device including the first transistor and a fourth transistor having a base and an emitter connected in common and having the same emitter size.
上記増幅回路は、上記第１トランジスタと第２トランジスタのコレクタ電圧を受ける差動増幅回路であり、
上記電流源回路は、ソースが第２電源電圧端子に接続され、ゲートに上記差動増幅回路の出力電圧が供給された第１乃至第３ＭＯＳＦＥＴであり、
上記第１乃至第３ＭＯＳＦＥＴのドレイン電流は、上記第１乃至第３トランジスタにそれぞれ供給され、
上記第１及び第２トランジスタのベースは、上記第１又は第２トランジスタのコレクタ電圧がゲートに供給された第４ＭＯＳＦＥＴを通して、上記第２電源電圧端子からベース電流が供給される半導体集積回路装置。 In claim 3,
The amplifier circuit is a differential amplifier circuit that receives collector voltages of the first transistor and the second transistor,
The current source circuit includes first to third MOSFETs having a source connected to a second power supply voltage terminal and a gate supplied with the output voltage of the differential amplifier circuit,
The drain currents of the first to third MOSFETs are supplied to the first to third transistors, respectively.
The base of the first and second transistors is a semiconductor integrated circuit device in which a base current is supplied from the second power supply voltage terminal through a fourth MOSFET to which the collector voltage of the first or second transistor is supplied to the gate.
上記増幅回路は、
上記第２トランジスタのコレクタ電圧を受け、ソースが上記第２電源電圧端子に接続された増幅ＭＯＳＦＥＴと、
上記増幅ＭＯＳＦＥＴのドレインと第１電源電圧端子との間に設けられ、ダイオード形態にされた第５トランジスタからなり、
上記第１及び第２トランジスタのベースは、上記第５トランジスタの共通接続されたベース，コレクタに接続され、
上記電流源回路は、上記第２トランジスタのコレクタ電流を入力電流とする第５乃至第７ＭＯＳＦＥＴで構成された電流ミラー回路である半導体集積回路装置。 In claim 3,
The amplifier circuit is
An amplification MOSFET that receives the collector voltage of the second transistor and has a source connected to the second power supply voltage terminal;
A fifth transistor in the form of a diode provided between the drain of the amplification MOSFET and the first power supply voltage terminal;
The bases of the first and second transistors are connected to the commonly connected base and collector of the fifth transistor,
The semiconductor integrated circuit device, wherein the current source circuit is a current mirror circuit composed of fifth to seventh MOSFETs having the collector current of the second transistor as an input current.
上記増幅回路は、上記第１トランジスタと第２トランジスタのコレクタ電圧を受ける第１差動増幅回路であり、
上記電流源回路は、
同じ抵抗値にされた第４ないし第６抵抗素子と、
第８ＭＯＳＦＥＴと、
第２差動増幅回路とを有し、
上記第４、第５抵抗素子は、上記第１、第２トランジスタのコレクタと上記第２電源電圧端子との間に設けられ、
上記第８ＭＯＳＦＥＴのソースと上記第２電源電圧端子との間に上記第６抵抗素子が接続され、
上記第２差動増幅回路は、上記第１トランジスタ又は第２トランジスタのコレクタ電圧と、上記第６抵抗素子で発生した電圧が等しくなるよう上記第８ＭＯＳＦＥＴのゲート電圧を形成する半導体集積回路装置。 In claim 3,
The amplifier circuit is a first differential amplifier circuit that receives collector voltages of the first transistor and the second transistor,
The current source circuit is
Fourth to sixth resistance elements having the same resistance value;
An eighth MOSFET;
A second differential amplifier circuit;
The fourth and fifth resistance elements are provided between the collectors of the first and second transistors and the second power supply voltage terminal,
The sixth resistance element is connected between the source of the eighth MOSFET and the second power supply voltage terminal,
The semiconductor integrated circuit device, wherein the second differential amplifier circuit forms a gate voltage of the eighth MOSFET so that a collector voltage of the first transistor or the second transistor is equal to a voltage generated by the sixth resistance element.
上記増幅回路は、上記第１トランジスタのコレクタ電圧と、所定のバイアス電圧とを受ける第１差動増幅回路であり、その出力電圧を上記第１及び第２トランジスタのベースに供給し、
上記電流源回路は、
第９ないし第１１ＭＯＳＦＥＴと、
第２差動増幅回路とを有し、
上記第９乃至第１１ＭＯＳＦＥＴは、ゲートが共通に接続され、上記第２電源電圧端子にソースが接続され、上記第１、第２及び第３トランジスタに供給する電流を形成し、
上記第２差動増幅回路は、上記第２トランジスタのコレクタ電圧と、上記所定のバイアス電圧とを受けて、その出力電圧を上記第９乃至第１１ＭＯＳＦＥＴのゲートに供給する半導体集積回路装置。 In claim 3,
The amplifier circuit is a first differential amplifier circuit that receives the collector voltage of the first transistor and a predetermined bias voltage, and supplies the output voltage to the bases of the first and second transistors,
The current source circuit is
Ninth to eleventh MOSFETs;
A second differential amplifier circuit;
The ninth to eleventh MOSFETs have gates connected in common, a source connected to the second power supply voltage terminal, and a current supplied to the first, second, and third transistors,
The semiconductor integrated circuit device, wherein the second differential amplifier circuit receives the collector voltage of the second transistor and the predetermined bias voltage and supplies the output voltage to the gates of the ninth to eleventh MOSFETs.
上記増幅回路は、上記第１トランジスタと第２トランジスタのコレクタ電圧を受ける差動増幅回路であり、
上記電流源回路は、
上記差動増幅回路の出力電圧がベースに供給された上記第１トランジスタ及び第２トランジスタ及び上記第１トランジスタとベース，エミッタが共通接続され、同じエミッタサイズに形成された第４トランジスタであり、
上記第１トランジスタ、第２トランジスタのコレクタと第２電源電圧端子との間には同じ抵抗値にされた抵抗手段が設けられた半導体集積回路装置。 In claim 3,
The amplifier circuit is a differential amplifier circuit that receives collector voltages of the first transistor and the second transistor,
The current source circuit is
The differential output voltage of the amplifier circuit is supplied to the base of the first transistor and the second transistor and the first transistor and the base, emitter are commonly connected, a fourth transistor formed on the same emitter size,
A semiconductor integrated circuit device in which resistance means having the same resistance value is provided between a collector of the first transistor and the second transistor and a second power supply voltage terminal.
上記バイアス電圧は、上記第１電源電圧端子と上記第２電源電圧端子との間に直列形態に設けられた電流源と抵抗手段からなるバイアス電圧発生回路で形成される半導体集積回路装置。 In claim 10,
The semiconductor integrated circuit device, wherein the bias voltage is formed by a bias voltage generating circuit comprising a current source and a resistance means provided in series between the first power supply voltage terminal and the second power supply voltage terminal.
上記バイアス電圧は、上記第１電源電圧端子と上記第２電源電圧端子との間に設けられたＮチャネルＭＯＳＦＥＴとＰチャネルＭＯＳＦＥＴの電流ミラー回路の出力電流が相互に入力電流とされるカレントミラー回路で形成される半導体集積回路装置。 In claim 10,
The bias voltage is a current mirror circuit in which an output current of a current mirror circuit of an N-channel MOSFET and a P-channel MOSFET provided between the first power supply voltage terminal and the second power supply voltage terminal is used as an input current. A semiconductor integrated circuit device formed of
上記バイアス電圧は、
上記第１差動増幅回路の出力電圧がベース，コレタクに供給され、エミッタが上記第１電源電圧端子に接続された第６トランジスタと、上記第２差動増幅回路の出力電圧がゲートに供給され、ソースが上記第２電源電圧端子に接続された第１２ＭＯＳＦＥＴとの直列回路で形成される半導体集積回路装置。 In claim 10,
The bias voltage is
The output voltage of the first differential amplifier circuit is supplied to the base and collector, the sixth transistor whose emitter is connected to the first power supply voltage terminal, and the output voltage of the second differential amplifier circuit is supplied to the gate. A semiconductor integrated circuit device formed of a series circuit with a twelfth MOSFET whose source is connected to the second power supply voltage terminal.
上記第１電流密度よりも小さな第２電流密度の第２電流が流れるようにされた第２トランジスタと、
ＭＯＳＦＥＴにより構成された第１及び第２差動増幅回路と、
第１乃至第４抵抗素子と、
第１乃至第３ＭＯＳＦＥＴとを備え、
上記第１トランジスタと第２トランジスタのベースは共通接続され、
上記第１トランジスタのエミッタは、第１電源電圧端子に接続され、
上記第２トランジスタのエミッタと上記第１電源電圧端子間に上記第１抵抗素子が接続され、
上記第２抵抗素子は、上記第１トランジスタのコレクタ，エミッタとの間に並列接続され、
上記第３抵抗素子は、上記第２トランジスタのコレクタ，エミッタとの間に並列接続され、
上記第１ないし第３ＭＯＳＦＥＴは、ソースが上記第２電源電圧端子に接続され、ゲートが共通に接続され、
上記第１差動増幅回路は、上記第１トランジスタのコレクタ電圧と所定のバイアス電圧とを受けて出力電圧を上記第１、第２トランジスタのベースに供給し、
上記第２差動増幅回路は、上記第２トランジスタのコレクタ電圧と上記所定のバイアス電圧とを受けて出力電圧を上記第１乃至第３ＭＯＳＦＥＴのゲートに供給し、
上記第１ＭＯＳＦＥＴのドレインは、上記第１トランジスタのコレクタに接続され、
上記第２ＭＯＳＦＥＴのドレインは、上記第２トランジスタのコレクタに接続され、
上記第４抵抗素子は、上記第３ＭＯＳＦＥＴのドレインと上記第１電源電圧端子との間に設けられた基準電圧発生回路を含む半導体集積回路装置。 A first transistor configured to flow a first current having a first current density;
A second transistor configured to flow a second current having a second current density smaller than the first current density;
First and second differential amplifier circuits configured by MOSFETs;
First to fourth resistance elements;
First to third MOSFETs,
The bases of the first transistor and the second transistor are connected in common,
An emitter of the first transistor is connected to a first power supply voltage terminal;
The first resistance element is connected between the emitter of the second transistor and the first power supply voltage terminal;
The second resistance element is connected in parallel between the collector and emitter of the first transistor,
The third resistance element is connected in parallel between the collector and emitter of the second transistor,
The first to third MOSFETs have a source connected to the second power supply voltage terminal, a gate connected in common,
The first differential amplifier circuit receives the collector voltage of the first transistor and a predetermined bias voltage, and supplies an output voltage to the bases of the first and second transistors,
The second differential amplifier circuit receives the collector voltage of the second transistor and the predetermined bias voltage, and supplies an output voltage to the gates of the first to third MOSFETs.
The drain of the first MOSFET is connected to the collector of the first transistor,
The drain of the second MOSFET is connected to the collector of the second transistor,
The semiconductor integrated circuit device, wherein the fourth resistance element includes a reference voltage generation circuit provided between a drain of the third MOSFET and the first power supply voltage terminal.
上記バイアス電圧は、上記第１電源電圧端子と上記第２電源電圧端子との間に直列形態に設けられた電流源と抵抗手段からなるバイアス電圧発生回路で形成される半導体集積回路装置。 In claim 15,
The semiconductor integrated circuit device, wherein the bias voltage is formed by a bias voltage generating circuit comprising a current source and a resistance means provided in series between the first power supply voltage terminal and the second power supply voltage terminal.
第３トランジスタ、第５抵抗素子及び第４ＭＯＳＦＥＴを更に備え、
上記第３トランジスタは、コレクタ及びベースが上記第１、第２トランジスタのベースと共通に接続され、エミッタが上記第１電源電圧端子に接続され、
上記第５トランジスタは、上記第３トランジスタのコレクタ，エミッタとの間に並列接続され、
上記第４ＭＯＳＦＥＴは、ソースが上記第２電源電圧端子に接続され、ゲートが上記第１乃至第３ＭＯＳＦＥＴのゲートと共通に接続され、ドレインが上記第３トランジスタのコレクタと接続され、
上記第３トランジスタのコレクタから上記所定のバイアス電圧を得る半導体集積回路装置。 In claim 15,
A third transistor, a fifth resistor element, and a fourth MOSFET;
The third transistor has a collector and a base connected in common with the bases of the first and second transistors, an emitter connected to the first power supply voltage terminal,
The fifth transistor is connected in parallel between the collector and emitter of the third transistor,
The fourth MOSFET has a source connected to the second power supply voltage terminal, a gate connected in common with the gates of the first to third MOSFETs, and a drain connected to the collector of the third transistor,
A semiconductor integrated circuit device for obtaining the predetermined bias voltage from the collector of the third transistor.
上記第１、第２及び第５抵抗素子は、上記第１乃至第３トランジスタのコレクタ電圧をそれぞれ分圧する分圧抵抗回路からなり、
上記各分圧抵抗回路で形成された上記第１乃至第３トランジスタのコレクタ電圧が上記第１及び第２差動増幅回路の入力信号とされる半導体集積回路装置。 In claim 17,
The first, second, and fifth resistance elements are voltage dividing resistor circuits that divide the collector voltages of the first to third transistors, respectively.
A semiconductor integrated circuit device in which collector voltages of the first to third transistors formed by the voltage dividing resistor circuits are used as input signals of the first and second differential amplifier circuits.
上記第１及び第２差動増幅回路の出力端子と交流的接地電位点との間に設けられ、抵抗とキャパシタからなる位相補償回路を更に備えてなる半導体集積回路装置。 In claim 10,
A semiconductor integrated circuit device further comprising a phase compensation circuit comprising a resistor and a capacitor provided between the output terminals of the first and second differential amplifier circuits and an AC ground potential point.
上記第１及び第２トランジスタのコレクタと交流的接地電位点との間に設けられ、抵抗とキャパシタからなる位相補償回路を更に備えてなる半導体集積回路装置。 In claim 10,
A semiconductor integrated circuit device further comprising a phase compensation circuit provided between a collector of the first and second transistors and an AC ground potential point, and comprising a resistor and a capacitor.
上記ＭＯＳＦＥＴは、第１導電型の半導体基板に形成された第２導電型ウェル領域及び第１導電型ウェル領域と、上記第２導電型領域に形成された第１導電型ＭＯＳＦＥＴと、上記第１導電型ウェル領域に形成された第２導電型ＭＯＳＦＥＴからなり、
上記第１トランジスタと第２トランジスタは、上記ＭＯＳＦＥＴを構成する第２導電型ＭＯＳＦＥＴのソース，ドレイン拡散層を形成する工程で形成された拡散層をコレクタ及びエミッタとし、上記コレクタとエミッタとしての拡散層が形成される第１導電型ウェル領域をベースとして動作する横型構造のバイポーラトランジスタである半導体集積回路装置。 In claim 4,
The MOSFET includes a second conductivity type well region and a first conductivity type well region formed in a first conductivity type semiconductor substrate, a first conductivity type MOSFET formed in the second conductivity type region, and the first conductivity type. A second conductivity type MOSFET formed in the conductivity type well region;
In the first transistor and the second transistor, the diffusion layer formed in the step of forming the source and drain diffusion layers of the second conductivity type MOSFET constituting the MOSFET is used as a collector and an emitter, and the diffusion layer as the collector and the emitter is used. A semiconductor integrated circuit device, which is a lateral bipolar transistor that operates on the basis of a first conductivity type well region in which is formed.
上記ＭＯＳＦＥＴは、第１導電型の半導体基板に形成された第２導電型ウェル領域及び第１導電型ウェル領域と、上記第２導電型ウェル領域に形成された第１導電型ＭＯＳＦＥＴと、上記第１導電型領域に形成された第２導電型ＭＯＳＦＥＴからなり、上記第２導電型ＭＯＳＦＥＴが形成された第１導電型ウェル領域を上記第１導電型の半導体基板から電気的に分離するための深い深さの第２導電型ウェル領域を有し、
上記第１トランジスタと第２トランジスタは、上記第１導電型ＭＯＳＦＥＴのソース，ドレイン拡散層を形成する工程で形成された第２導電型拡散層をエミッタとし、上記エミッタを構成する第２導電型拡散層が形成された第１導電型ウェル領域をベートとし、上記ベースを構成する第１導電型ウェル領域を上記第１導電型の半導体基板から電気的に分離するために設けられた深い深さの第２導電型ウェル領域をコレクタとして用いる縦型構造のバイポーラトランジスタである半導体集積回路装置。 In claim 4,
The MOSFET includes a second conductivity type well region and a first conductivity type well region formed in a first conductivity type semiconductor substrate, a first conductivity type MOSFET formed in the second conductivity type well region, and the first conductivity type MOSFET. A second conductivity type MOSFET formed in a first conductivity type region, for deeply isolating the first conductivity type well region in which the second conductivity type MOSFET is formed from the first conductivity type semiconductor substrate; A second conductivity type well region having a depth;
The first transistor and the second transistor have a second conductivity type diffusion layer formed in the step of forming a source / drain diffusion layer of the first conductivity type MOSFET as an emitter, and a second conductivity type diffusion that constitutes the emitter. The first conductivity type well region in which the layer is formed is used as a bait, and the first conductivity type well region constituting the base is deeply provided to electrically isolate the first conductivity type well region from the first conductivity type semiconductor substrate. A semiconductor integrated circuit device which is a bipolar transistor having a vertical structure using a second conductivity type well region as a collector.
上記第１トランジスタは、１つのトランジスタから構成され、
上記第２トランジスタは、上記第１トランジスタに対応した単位トランジスタを複数個並列接続して構成される半導体集積回路装置。 In claim 22,
The first transistor is composed of one transistor,
The second transistor is a semiconductor integrated circuit device configured by connecting a plurality of unit transistors corresponding to the first transistor in parallel.
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| US8149047B2 (en) * | 2008-03-20 | 2012-04-03 | Mediatek Inc. | Bandgap reference circuit with low operating voltage |
| JP2012044108A (en) * | 2010-08-23 | 2012-03-01 | Mitsumi Electric Co Ltd | Semiconductor integrated circuit, switching power supply equipped with that circuit and control system equipped with that power supply |
| JP5962788B2 (en) * | 2015-01-27 | 2016-08-03 | ミツミ電機株式会社 | Semiconductor integrated circuit |
| JP6416020B2 (en) | 2015-03-09 | 2018-10-31 | 株式会社東芝 | Active load circuit and semiconductor integrated circuit |
| JP6767330B2 (en) | 2017-09-20 | 2020-10-14 | 株式会社東芝 | Regulator amplifier circuit |
| JP6413005B2 (en) * | 2017-11-06 | 2018-10-24 | ルネサスエレクトロニクス株式会社 | Semiconductor device and electronic system |
| CN111837341A (en) * | 2018-03-19 | 2020-10-27 | 神话公司 | System and method for mixed signal computation |
| DE102018113145B4 (en) * | 2018-06-01 | 2020-06-04 | Infineon Technologies Ag | RECTIFIER DEVICE |
| CN114299872B (en) * | 2022-01-04 | 2023-07-18 | 京东方科技集团股份有限公司 | Driving circuit, driving method thereof and display device |
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