JP5057358B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique that is effective when applied to a semiconductor integrated circuit device using a silicon bandgap and incorporating a low-voltage reference voltage generation circuit.

FIG. 63 shows a circuit diagram of a band gap reference voltage generation circuit for low voltage output previously proposed by the applicant of the present application. Since the gates of insulated gate field effect transistors (hereinafter simply referred to as MOSFETs) M1, M2 and M0 are connected in common, the same current Io flows if the sizes of the MOSFETs M0 to M2 are equal. The differential amplifier circuit (op-amp) AMP forms an output voltage Vc such that the difference between the input voltages Vc1 and Vc2 becomes zero and transmits it to the gates of the MOSFETs M0 to M2. A voltage equal to the difference voltage between the base-emitter voltage VBE1 of the bipolar transistor (hereinafter simply referred to as transistor) Q1 and the base-emitter voltage VBE2 of the bipolar transistor Q2 is applied to the resistor R1. The difference voltage is proportional to the thermal voltage V _T , that is, the absolute temperature T. The output potential Vc of the differential amplifier circuit AMP is formed so that the current Io maintains this state. The output unit can obtain a low voltage output by flowing the current Io determined by the voltage Vc through the series circuit of the transistor Q0 diode-connected to the resistor Ra and the resistor Rb connected in parallel thereto. Since the base-emitter voltage VBE0 of the transistor Q0 decreases as the temperature T rises, the reference voltage VbgrL obtained by adding the terminal voltage of the resistor Ra to the voltage VBE0 is increased by the resistors Ra and Rb whose resistance value increases as the temperature rises. A desired voltage having no temperature dependence can be obtained. Such a reference voltage generating circuit is disclosed in Japanese Patent Application Laid-Open No. 2004-206633.
JP 2004-206633 A

  For example, the miniaturization process of about 0.2 μm or less lowers the breakdown voltage of the MOSFET, and the power supply voltage VDD that can be supplied also decreases to about 1.5 V or less. Thus, when the power supply voltage VDD is 1.5V, the allowable lower limit operating voltage is reduced to 1.35V. Therefore, in a conventional reference voltage generation circuit that generates a reference voltage in the vicinity of 1.2 V corresponding to the silicon band gap, it is possible to secure an operating voltage in the differential amplifier circuit to which the 1.2 V reference voltage is input. It has a problem that it cannot be done. In the reference voltage generating circuit shown in FIG. 63, the input voltage Vc1 (Vc2) of the differential amplifier circuit can be made as low as the base-emitter voltage VBE1 of the transistor Q1 by the above configuration. The differential amplifier circuit AMP can operate even with the power supply voltage VDD.

  However, in the MOSFET formed by the above-described miniaturization process of 0.2 μm or less, the variation of the threshold voltage becomes large due to the short channel effect or the like. Such a variation in the threshold voltage of the MOSFET also occurs in the differential MOSFET constituting the differential amplifier circuit AMP, and an offset voltage Vos that cannot be ignored is generated. In the reference voltage generating circuit of FIG. 63, it has been found that the offset voltage Vos as described above greatly fluctuates the reference voltage VbgrL. That is, the current Io when the differential amplifier circuit AMP has the offset voltage Vos varies (Vos / R1) from the current Io when there is no offset voltage Vos. In the circuit of FIG. 63, since the current Io is passed through the output transistor Q0 and the resistors Ra and Rb to form the reference voltage VbgrL, the reference voltage VbgrL also varies in accordance with the variation of the current Io. For example, when setting VbgrL = 0.8V, if the offset voltage Vos is about 10 mV, it will fluctuate beyond 0.8V ± 10%, such as 0.8V ± 0.1V. It cannot be used as a circuit reference voltage. For example, when the reference voltage VbgrL (= 0.8V) is multiplied by 1.5 to form an internal step-down voltage VDL such as 1.2V, it becomes 1.2V ± 0.15V, and the allowable fluctuation range is ± 10%. Therefore, it becomes unusable as a power supply circuit.

Incidentally, the influence of the offset voltage Vos is quantitatively described as follows.
In the circuit of FIG. 63, the amplifier circuit AMP operates so that Vc2−Vc1 = Vos. For this reason, the current Io flowing through the resistor R1 changes by Vos / R1, which causes the reference voltage VbgrL to fluctuate. VT = kT / q (where T is the absolute temperature, k is the Boltzmann coefficient, q is the elementary charge, and Is is the reverse saturation current of the bipolar transistor, VBE1 and VBE2 are expressed as 2 (Equation 2).

The relationship between the two input voltages Vc1 and Vc2 of the differential amplifier AMP and the offset voltage Vos is Vc1 = VBE1 and Vc2 = VBE2 + Io × R1. Can be represented.

On the other hand, with respect to the reference voltage VbgrL, the following equation 4 (Equation 4) is established, and when VbgrL is arranged, the following equation 5 (Equation 5) is obtained.

Here, when the formula 3 (formula 3) is substituted, the following formula 6 (formula 6) is obtained. The rate of change of VbgrL due to Vos is a value obtained by differentiating Equation 5 (Equation 5) with Vos, and the following Equation 7 (Equation 7) can be obtained. The offset voltage Vos is expressed by the following Equation 7 (Equation 7). As shown in FIG. 4, the voltage is amplified by the resistors Ra, Rb and R1, and appears in the reference voltage VbgrL.

  An object of the present invention is to provide a semiconductor integrated circuit device in which a reference voltage generation circuit suitable for a miniaturized MOSFET is mounted. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. The base of the first transistor through which the current of the first current density flows and the base of the second transistor through which the current of the second current density smaller than the first current density are connected in common to supply a voltage corresponding to the output voltage of the amplifier circuit To do. A reference current is formed by applying a voltage difference between the emitter and base of the first and second transistors to the first resistance element. The amplifier circuit forms an output voltage corresponding to a differential voltage between collector voltages of the first transistor and the second transistor. A current source circuit supplies a current corresponding to the reference current to the first, second and third transistors. The base and collector of the third transistor are connected in common, and the second resistance element is connected in series with the third transistor. Depending on the setting of the size of the third transistor and the resistance values of the first and second resistance elements, the voltage generated in the third transistor and the second resistance element may be changed with respect to the first and second power supply voltages and the temperature change. So that the reference voltage is constant.

  It is possible to obtain a reference voltage that can operate up to a low voltage and that is less affected by the offset voltage of the differential amplifier circuit.

  FIG. 1 is a circuit diagram showing one embodiment of a reference voltage generating circuit according to the present invention. Each circuit element shown in the figure is formed on a single semiconductor substrate such as single crystal silicon together with other circuit elements (not shown) by a known CMOS integrated circuit manufacturing technique.

  The output voltage Vc of the differential amplifier circuit AMP is supplied to the bases of the transistors Q1 and Q2. A resistor R1 is connected to the emitter of the transistor Q2 and the ground potential point VSS of the circuit. The collector voltages Vc1 and Vc2 of the transistors Q1 and Q2 are controlled by the differential amplifier circuit AMP so that the difference is zero, that is, the same voltage, and each MOSFET M1, M2 is controlled by a current mirror circuit including p-channel MOSFETs M2, M1, and M0. The drain currents of M2 and M0 are all set to the current Io. In other words, the gate and drain of the MOSFET M2 are connected to form a diode, and the current Io formed by the resistor R1 is supplied to the MOSFET M2. To. Then, the size of the transistor Q2 is formed to be n times larger than that of the transistor Q1, and the current density of the transistor Q2 is reduced to 1 / n with respect to the current density of the transistor Q1.

When the operational amplifier circuit AMP does not have the offset voltage Vos, the same current Io flows through the transistors Q1 and Q2. Since the same current Io flows through the transistors Q1 and Q2, the difference voltage between the base-emitter voltage VBE1 of the transistor Q1 and the base-emitter voltage VBE2 of the transistor Q2 is applied to the resistor R1 corresponding to the current density difference. Applied. This differential voltage is proportional to the thermal voltage V _T , ie the absolute temperature T. The differential amplifier circuit AMP forms the output voltage Vc so that the current Io maintains this state. The output unit can obtain the reference voltage VbgrL by copying the current Io by the current mirror of the MOSFETs M2 and M0 and flowing the current Io through the series circuit of the diode Q-connected transistor Q0 and the resistor Rb connected in parallel thereto. Since the base-emitter voltage VBE0 of the transistor Q0 decreases as the temperature rises, the output voltage VbgrL obtained by adding the terminal voltage of the resistor Ra to the voltage VBE0 becomes a desired voltage having no temperature dependence by the resistors Ra and Rb. can do.

  The principle that the influence of the offset voltage Vos (difference between Vc1 and Vc2) of the differential amplifier circuit AMP in the circuit of FIG. 1 can be made smaller than that of the circuit of FIG. 63 will be described in a simplified manner as follows. gm is the MOSFET current gain, gmb is the transistor current gain, rds is the MOSFET drain-source resistance, and rce is the transistor collector-emitter resistance. When the differential amplifier circuit AMP has an offset voltage Vos, the output voltage Vc of the differential amplifier circuit AMP changes, and ΔVc1 / ΔVc = gmb × (rds // rce), ΔVc2 / ΔVc≈1 / (gm × r1) To Vc1 mainly changes.

  Therefore, the change in the output voltage Vc with respect to the offset voltage = | ΔVc1−ΔVc2 | ≈ | ΔVc1 | is reduced to 1 / gmb × (rds // rce). Therefore, the current Io varies by Vos / (rds // rce) with respect to the offset voltage Vos. As a result, the fluctuation of the current Io with respect to the offset voltage Vos is much smaller than (Vos / r1) in FIG. Since this is sent to the output part by the current mirror circuit of the p-channel MOSFETs M2 and M0, a reference voltage VbgrL strong against the offset voltage Vos of the differential amplifier circuit AMP is obtained. That is, a band gap circuit that is resistant to offset of the differential amplifier circuit AMP is realized by adopting a circuit configuration in which the offset voltage Vos of the differential amplifier circuit AMP does not enter the portion where the positive temperature characteristic (VBE1−VBE2) is generated. be able to.

Incidentally, the influence of the offset voltage Vos is quantitatively described as follows. Similarly to the above, the differential amplifier circuit AMP operates so that Vc2-Vc1 = Vos. The base-emitter voltages VBE1 and VBE2 of the transistors Q1 and Q2 are obtained from the following formula 8 (formula 8) and formula 9 (formula 9).

Further, the output voltage Vc, which is a control voltage, is expressed by the following equation 10 (Equation 10). When VBE1 and VBE2 are eliminated from Equation 10 (Equation 10), the following Equation 11 (Equation 11) is obtained, and when arranged, Equation 12 (Equation 12) is obtained.

Here, it is considered that Vos is sufficiently small and Vos / Io × rds << 1 holds. Therefore, it can be transformed as the following equation 13 (Equation 13), and can be rewritten as the following equation 14 (Equation 14).

In order to see the change of Io with respect to Vos, the following equation 15 (Equation 15) is obtained by differentiation with Vos, and the following equation 16 (Equation 16) is obtained when rearranged.

Since the reference voltage VbgrL is formed by passing a current copied from the current Io through a series circuit of the resistor Ra and the transistor Q0 and the resistor Rb connected in parallel thereto, the following equation 17 (Equation 17) and Equation 18 (Equation 18). The change of the reference voltage VbgrL with respect to the offset voltage Vos can be expressed by the following equation 19 (Equation 19).

Here, since the previous term Ra.Rb / (Ra + Rb) R1 on the right side is the value of the circuit of FIG. 63, if the subsequent term is the following equation 20 (Equation 20), the influence of the offset can be reduced. Since rds is the resistance between the drain and source of the MOSFET and is generally very large, the change of the reference voltage VbgrL with respect to the offset voltage Vos can be greatly reduced.

  In this embodiment, when the offset voltage Vos of the differential amplifier circuit AMP is present, the offset voltage Vos is generated at the collector terminals of the transistors Q1 and Q2 (corresponding to the outputs of the grounded transistor amplifiers Q1 and Q2). The impact on is small. As described above, the influence of the offset voltage Vos generated in the differential amplifier circuit AMP on the reference voltage VrefL can be reduced to (1 / gain of the band gap generator).

  FIG. 2 is a circuit diagram showing one embodiment of the reference voltage generating circuit according to the present invention. This embodiment has a circuit configuration in which the circuit of FIG. 1 is simplified, and an amplification MOSFET M3 is used instead of the differential amplifier circuit AMP. In this embodiment, a diode-like transistor Q3 is provided at the drain of the current mirror circuit and the amplifying MOSFET M3 using the same MOSFETs M0 to M2, and the transistors Q1 and Q2 are connected in a current mirror form. Feedback is performed by current mirror circuits above and below the power supply voltages VDD and VSS, and the current Io formed by (VBE1−VBE2) / R1 is passed through the transistors Q1 to Q3 in the same manner as described above. In this embodiment as well, the circuit configuration is such that the reference voltage VbgrL does not vary with respect to the difference between the collector voltages Vc1 and Vc2 of the transistors Q1 and Q2 as in the embodiment of FIG. In this embodiment, since the differential amplifier circuit AMP is not used, the circuit configuration becomes simple, the design is easy, and the rise time when the power is turned on is shortened.

  FIG. 3 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. In the reference voltage generating circuit of FIGS. 1 and 2, the operation at the power supply voltage VDD in a relatively low and narrow range of about 2V to 3V, for example, such that the drain-source voltages Vds of the MOSFETs M1 and M0 are substantially equal. In some cases, the drain currents Io are all substantially equal, and operate as a low power supply voltage bandgap reference voltage generation circuit considering the offset voltage of the differential amplifier circuit AMP in FIG. 1 and the differential voltage between the collector voltages Vc1 and Vc2 as shown in FIG. be able to. However, considering the application of the power supply voltage VDD to a semiconductor integrated circuit in a wide voltage range such as 2 V to 6 V, for example, a deviation occurs in the drain-source voltage Vds of the MOSFETs M1 and M2 and M0 in FIGS. Accordingly, the MOSFETs M1, M2 and the M0 drain current Io are not equal to each other corresponding to the difference between the drain-source voltage Vds. Thus, for example, the reference voltage VbgrL when the power supply voltage VDD becomes a high voltage such as 6V fluctuates as compared with the case where the power supply voltage VDD is as low as 2 to 3V, and a wide power supply such as 2 to 6V. The operation of the semiconductor integrated circuit device in the voltage range becomes difficult.

  FIG. 3 is devised so that a circuit can be applied in a wide power supply voltage range. In the embodiment shown in FIGS. 1 and 2, npn-type bipolar transistors are used. In this embodiment, pnp-type bipolar transistors Q1 to Q3 are used. The output voltage Vc of the differential amplifier circuit AMP is supplied to the bases of the transistors Q1, Q2, and Q3, and a resistor R1 is connected between the emitter of the transistor Q2 and the power supply voltage VDD. The collector voltages Vc1 and Vc2 of the transistors Q1 and Q2 are determined by the resistors Rc1 and Rc2 through which the current Io formed by the transistors Q1 and Q2 flows corresponding to the output voltage Vc of the differential amplifier circuit AMP. Also in this configuration, a circuit configuration in which the reference voltage VgrL does not vary with respect to the difference between the input voltages Vc1 and Vc2 of the differential amplifier circuit AMP is the same as the embodiment of FIGS.

The operation principle of this embodiment circuit is as follows. Since the same current Io flows through the transistors Q1 and Q2, a voltage equal to the difference between the base-emitter voltage VBE1 of the transistor Q1 and the base-emitter voltage VBE2 of the transistor Q2 is generated in the resistor R1. This difference voltage is proportional to the thermal voltage V _T , that is, proportional to the absolute temperature T. The output potential Vc of the differential amplifier circuit AMP is determined so that the current Io maintains this state. The output section can obtain a low-voltage reference voltage VbgrL by flowing a current Io determined by the output voltage Vc through a circuit in which a resistor Ra and a diode-connected transistor Q0 are connected in series and a resistor Rb. Since the base-emitter voltage VBE0 of the transistor Q0 decreases as the temperature rises, the reference voltage VbgrL obtained by adding the both-ends voltage of the resistor Ra to the base-emitter voltage VBE0 is not desired depending on the resistors Ra and Rb. Can be voltage. If the reference voltage VbgrL is not lowered, the resistor Rb need not be connected.

  In this embodiment, the current mirror type MOSFETs M1 and M2 which are problematic in FIGS. 1 and 2 are eliminated, and the input voltages Vc1 and Vc2 of the differential amplifier circuit are Vc1 = Io × Rc1 and Vc2 by the differential amplifier circuit AMP. = Io × Rc2 is determined based on the ground potential VSS (0 V). Therefore, the collector-emitter voltage VCE of the transistors Q1, Q2 and Q3 does not deviate greatly in a wide voltage range where the power supply voltage VDD is 2 to 6V. Therefore, the transistors Q1 to Q3 pass the same current Io corresponding to the output voltage Vc formed by the differential amplifier circuit AMP. As a result, the reference voltage generation circuit of this embodiment can form the same reference voltage VbgrL even if it corresponds to a wide power supply voltage range such as 2 to 6V.

  FIG. 4 shows a circuit diagram of another embodiment of the reference voltage generating circuit according to the present invention. This embodiment is a modification of FIG. 1 and includes differential amplifier circuits AMP1 and AMP2. The differential amplifier circuit AMP1 corresponds to the differential amplifier circuit AMP in FIG. That is, a differential amplifier circuit AMP2 is newly added to form the gate voltages of the p-channel MOSFETs M1 to M0. In the differential amplifier circuits AMP1 and AMP2, an appropriate bias voltage VB is supplied to the inverting input terminal (−), and input voltages Vc1 and Vc2 are supplied to the non-inverting input terminal (+), respectively. Thus, the bias voltage VB and the input voltages Vc1 and Vc2 are controlled to be equal by the amplification operation of the differential amplifier circuits AMP1 and AMP2. With this circuit configuration, there is no diode-connected MOSFET M2 as shown in FIGS. 1 and 2, and the input voltages Vc1 and Vc2 are given an appropriate bias voltage VB with reference to the ground potential VSS. Therefore, even if the power supply voltage VDD fluctuates, the drain-source voltage Vds of the MOSFETs M1, M2 and M0 does not deviate greatly. Therefore, for example, as described above, it is possible to cope with a wide power supply voltage range VDD such as 2 to 6V.

  FIG. 5 shows a circuit diagram of another embodiment of the reference voltage generating circuit according to the present invention. The circuit of the embodiment so far is based on the assumption that there are no transistor variations in MOSFETs M1, M2 and M0. Therefore, if the gate-source voltage Vgs and the drain-source voltage Vds of the p-channel MOSFET are equal, the drain currents Io are equal to each other. However, it is impossible to make the MOSFETs M1, M2, and M0 completely the same during the manufacturing process, and it is considered that the drain currents Io are different even when the MOSFETs M1, M2, and M0 are in the same bias state.

  As described above, there is a variation in the threshold voltage Vth as one of the variations in the p-channel MOSFETs M1, M2, and M0. That is, if the p-channel MOSFETs M1, M2, and M0 have variations and the respective threshold voltages Vth vary, the respective currents Io vary by the square with respect to the variations in the threshold voltage Vth. Furthermore, when MOSFETs M1, M2 and M0 are operating in the weak inversion region, the current Io fluctuates exponentially. As a result, the reference voltage VbgrL varies.

  The embodiment circuit of FIG. 5 is devised so that the reference voltage VbgrL is stabilized against such variations in the threshold voltage Vth of the MOSFETs M1, M2 and M0. In this embodiment, MOSFETs M1, M2, and M0 are all replaced with a resistor R0 having the same resistance value. Then, the differential amplifier circuit AMP1 is used to control the input voltages Vc1 and Vc2 to be equal. The differential amplifier circuit AMP2 receives the source potential Vc0 of the p-channel MOSFET M0 to which the resistor R0 is connected and the input voltage Vc1, and feeds back the output signal Vcb to the gate of the MOSFET M0 so that the input voltage Vc1 The above Vc0 is made equal. Thus, the same current Io can be caused to flow through the resistors R0 having the same resistance value. By eliminating the MOSFETs M1, M2 and M0 constituting the current mirror circuit as described above, the variation in the reference voltage VbgrL due to the variation in the threshold voltage Vth of the p-channel MOSFETs M1, M2 and M0 is eliminated in principle.

  The variation of the reference voltage VbgrL considered in the embodiment of FIG. 5 is caused by the offset voltage Vos of the differential amplifier circuits AMP1 and AMP2. The fluctuation of the current Io caused by the offset voltage Vos is (Vos / R0), and fluctuates only to the first power with respect to the offset voltage Vos. Assuming that the offset Vos of the differential amplifier circuits AMP1 and AMP2 and the threshold voltage Vth variation of the p-channel MOSFET are the same, the variation of the reference voltage VbgrL can be made smaller in the configuration of the embodiment circuit of FIG. . Since the circuit configuration can be designed such that R0> R1, the variation of the reference voltage VbgrL with respect to the difference between the input voltages Vc1 and Vc2 is smaller than that of the circuit of FIG.

  FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. This embodiment circuit has a simple configuration as compared with the embodiment circuits shown in FIGS. 4 and 5 and can comprise a single differential amplifier circuit. That is, the output voltage Vc of the differential amplifier circuit AMP is supplied to the gates of the p-channel MOSFETs M1, M2 and M0, and a constant current Io is formed by the MOSFETs M1, M2 and M0 so as to flow through the transistors Q1, Q2 and Q0. To do. A base current is supplied to the transistors Q1 and Q2 through the MOSFET MB2 to which the input voltage Vc1 is supplied to the gate. In this embodiment, it is necessary to make the power supply voltage VDD larger than the voltage VBE1 + Vgs obtained by adding the base-emitter voltage VBE1 of the transistor Q1 and the gate-source voltage Vgs of the MOSFET Mb2. However, as compared with the circuit of the embodiment shown in FIGS. 4 and 5, a single differential amplifier circuit can be provided, so that the structure is simple, the design is easy, and the rise time immediately after power-on is shortened. Also, there is no diode-connected MOSFET M2 (M1) which has been a problem in the embodiment circuit of FIGS. 1 and 2, and the input voltages Vc1 and Vc2 are set to VBE1 + Vgs with respect to the ground potential VSS of the circuit. Even if the power supply voltage VDD fluctuates, the drain-source voltage Vds of the MOSFETs M1, M1 and M0 does not greatly deviate. Therefore, it is possible to correspond to a wide power supply voltage range.

  FIG. 7 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the resistor Rb in FIG. 1 is omitted. In this configuration, since the base-emitter voltage VBE0 of the transistor Q0 decreases as the temperature rises, the terminal voltage of the resistor Ra is added to the voltage VBE0 to form a reference voltage VrefL having no temperature dependence. Therefore, the formed reference voltage VbgrL is increased by the voltage generated by the base-emitter voltage VBE0 of the transistor Q0, the resistor Ra, and the current Io, which is useful when a high voltage of about 1.2V is required. It is. The configuration in which the resistor Rb is omitted and the relatively high reference voltage is formed can be similarly applied to the embodiments of FIGS. 2 to 6 and the reference voltage generation circuit described below.

  FIG. 8 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the npn transistors Q1, Q2, and Q0 of the embodiment circuit of FIG. 1 are replaced with pnp transistors Q1, Q2, and Q0, and the p-channel MOSFETs M1, M2, and M0 are replaced with n-channel MOSFETs M1, M2, and M0, respectively. It is supposed to be. Further, the reference voltage VbgrL based on the power supply voltage VDD is obtained by replacing the conductivity type of the transistor and MOSFET.

  FIG. 9 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the npn transistors Q1, Q2, Q3, and Q0 of the embodiment circuit of FIG. 2 are replaced with pnp transistors Q1, Q2, Q3, and Q0, and the p-channel MOSFETs M1, M2, M3, and M0 are replaced with n-channel MOSFETs M1, M2 , M3 and M0, respectively. Further, the reference voltage VbgrL based on the power supply voltage VDD is obtained by replacing the conductivity type of the transistor and MOSFET.

  FIG. 10 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the pnp transistors Q1, Q2, Q3 and Q0 in the embodiment circuit of FIG. 3 are replaced with npn transistors Q1, Q2, Q3 and Q0, respectively. Further, the reference voltage VbgrL based on the power supply voltage VDD is obtained by replacing the conductivity type of the transistor.

  FIG. 11 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, a differential amplifier circuit AMPb, resistors Rb1 and Rb2, and a p-channel MOSFET Mb1 are added to the reference voltage generating circuit shown in FIG. 10, and a reference voltage VrefL based on the power supply voltage VDD is added to the circuit. The reference voltage VrefLb is converted with reference to the ground potential VSS. That is, the reference voltage VrefL is supplied to the input terminal (+) of the differential amplifier circuit AMPb, and the source potential of the p-channel MOSFET Mb1 receiving the output voltage at the gate is fed back to the input terminal (−). A resistor Rb1 is connected between the input terminal (-) and the power supply voltage VDD to form a current Ib1. This current Ib1 is passed through the MOSFET Mb1 to the resistor Rb2 and connected to the circuit ground potential VSS. In this way, the reference voltage VbgrL based on the power supply voltage VDD can be converted into the reference voltage VbgrLb based on the circuit ground potential VSS. Further, the reference voltage VbgrLb can be set to a desired reference voltage by the ratio of the resistors Rb1 and Rb2. Such an additional circuit composed of the differential amplifier circuit AMPb, the resistors Rb1, Rb2, and the p-channel MOSFET Mb1 can be similarly applied to FIGS. 8 and 9 which are based on the power supply voltage VDD as described above. it can.

  FIG. 12 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the resistors Rc1 and Rc2 which determine the potentials of the input voltages Vc1 and Vc2 of the embodiment circuit of FIG. 3 are replaced with a current mirror circuit comprising n-channel MOSFETs M1 and M2. This embodiment is stronger than the offset voltage Vos of the differential amplifier circuit AMP than the embodiment of FIG. In the embodiment circuit configuration of FIG. 3, the current Io varies by Vos / Rc1, whereas in this embodiment circuit, the current Io decreases to a variation of Vos / (rds // rce). Therefore, the variation of the reference voltage VbgrL is reduced.

  FIG. 13 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the pnp transistors Q1, Q2, Q3 and Q0 in the embodiment circuit of FIG. 12 are replaced with npn transistors Q1, Q2, Q3 and Q0, and the n-channel MOSFETs M1 and M2 are replaced with p-channel MOSFETs M1 and M2, respectively. It is assumed. Further, the reference voltage VbgrL based on the power supply voltage VDD is obtained by replacing the conductivity type of the transistor.

  FIG. 14 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the npn transistors Q1, Q2, and Q0 of the embodiment circuit of FIG. 4 are replaced with pnp transistors Q1, Q2, and Q0, and the p-channel MOSFETs M1, M2, and M0 are replaced with n-channel MOSFETs M1, M2, and M0, respectively. It is assumed. Further, the reference voltage VbgrL based on the power supply voltage VDD is obtained by replacing the conductivity type of the transistor.

  FIG. 15 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the npn transistors Q1, Q2 and Q0 in the embodiment circuit of FIG. 5 are replaced with pnp transistors Q1, Q2 and Q0, and the p-channel MOSFET M0 is replaced with an n-channel MOSFET M0. Further, the reference voltage VbgrL based on the power supply voltage VDD is obtained by replacing the conductivity type of the transistor.

  FIG. 16 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the npn transistors Q1, Q2 and Q0 in the embodiment circuit of FIG. 6 are replaced with pnp transistors Q1, Q2 and Q0, and the p-channel MOSFETs M1, M2 and M0 are replaced with n-channel MOSFETs M1, M2 and M0, respectively. It is assumed. The MOSFET Mb2 is a p-channel MOSFET for setting the input voltages Vc1 and Vc2 to a voltage based on the power supply voltage VDD of the circuit. By replacing the conductivity type of the transistor, a reference voltage VbgrL based on the power supply voltage VDD is obtained.

  FIG. 17 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, a current Ic is formed by a current source provided on the power supply voltage VDD side, and is passed through a resistor R3 provided on the circuit ground potential VSS side, so that a bias voltage VB based on the circuit ground potential VSS is used. Is generated. By using such a bias voltage VB, the drain-source voltage Vds of the MOSFETs M1, M2 and M0 does not greatly deviate even when the power supply voltage VDD fluctuates as described in FIG. Thus, it becomes possible to cope with a wide power supply voltage range VDD such as 2 to 6V.

  FIG. 18 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the npn transistors Q1, Q2, and Q0 of the embodiment circuit of FIG. 17 are replaced with pnp transistors Q1, Q2, and Q0, and the p-channel MOSFETs M1, M2, and M0 are replaced with n-channel MOSFETs M1, M2, and M0, respectively. It is supposed to be. Further, the reference voltage VbgrL based on the power supply voltage VDD is obtained by replacing the conductivity type of the transistor and MOSFET. Therefore, a current Ic is formed by a current source provided on the ground potential VSS side of the circuit, and flows through a resistor R3 provided on the power supply voltage VDD side, thereby generating a bias voltage VB based on the power supply voltage VDD.

  FIG. 19 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the resistor R3 in FIG. 17 is replaced with a diode-connected n-channel MOSFET M4. Thus, the same effect as described above can be obtained by using the gate-source voltage Vgs of the n-channel MOSFET M4.

  FIG. 20 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the resistor R3 in FIG. 18 is replaced with a diode-connected p-channel MOSFET M4. Thus, the same effect as described above can be obtained by using the gate-source voltage Vgs of the p-channel MOSFET M4.

  FIG. 21 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the diode-connected n-channel MOSFET M4 in FIG. 19 is replaced with a diode-connected npn transistor Q4. By using the base-emitter voltage VBE4 of the npn transistor Q4 as described above, the same effect as described above can be obtained.

  FIG. 22 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the diode-connected p-channel MOSFET M4 in FIG. 20 is replaced with a diode-connected pnp transistor Q4. Thus, by using the base-emitter voltage VBE4 of the pnp transistor Q4, the same effect as described above can be obtained.

  FIG. 23 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the bias voltage VB shown in FIG. 4 is formed by using a Wideler current mirror circuit. A threshold voltage Vth of a diode-shaped n-channel MOSFET M5 provided on the ground potential VSS side of the circuit is applied to the gate of the n-channel MOSFET M6, and a resistor R5 is connected between the source and the circuit ground potential VSS. The difference voltage of the threshold voltage Vth between the MOSFETs M5 and M6 is applied to the resistor R5 to form a constant current, and through a current mirror circuit composed of p-channel MOSFETs M7 and M8 provided on the power supply voltage VDD side, Return to the diode-connected n-channel MOSFET M5. A bias voltage VB corresponding to the threshold voltage Vth of the MOSFET M5 is formed by such a wideler current mirror circuit.

  FIG. 24 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the current circuit of the wider shown in FIG. 23 is combined with the embodiment circuit of FIG. Since this embodiment obtains the reference voltage VbgrL based on the power supply voltage VDD, the bias voltage VB corresponding to the threshold voltage Vth of the p-channel MOSFET M7 provided on the power supply voltage VDD side is formed.

  FIG. 25 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, a gate of a p-channel MOSFET M6 whose source is supplied with a power supply voltage VDD and a gate of a diode-type p-channel MOSFET M5 having a resistor R5 connected between the source and the power supply voltage VDD are connected in common. Is fed back as a drain current of the p-channel MOSFET M5 through a current mirror circuit composed of n-channel MOSFETs M7 and M8 provided on the ground potential VSS side of the circuit to constitute a wideler current mirror circuit. A bias voltage VB corresponding to the threshold voltage Vth is formed.

  FIG. 26 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the current mirror circuit of the wider shown in 25 is combined with the embodiment circuit of FIG. Since this embodiment obtains the reference voltage VbgrL based on the power supply voltage VDD, the bias voltage VB corresponding to the gate and drain voltages of the p-channel MOSFET M5 provided on the power supply voltage VDD side is formed.

  FIG. 27 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, a gate-emitter voltage VBE4 of a diode-connected npn transistor Q4 provided on the ground potential VSS side of the circuit is used as a circuit for forming the bias voltage VB of the embodiment circuit of FIG. In order to equalize the drain currents of the MOSFETs M1, M2, and M4, the base of the transistor Q4 is also connected to the output terminal of the differential amplifier circuit AMP1, and the base currents of the transistors Q1, Q2, and Q4 are supplied by the differential amplifier circuit AMP1. To do.

  FIG. 28 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the npn transistors Q1, Q2, Q0, and Q4 of the embodiment circuit of FIG. 27 are replaced with pnp transistors Q1, Q2, Q0, and Q4, and the p-channel MOSFETs M1, M2, M0, and M4 are replaced with n-channel MOSFETs M1, M2 , M0 and M4, respectively. Further, the reference voltage VbgrL based on the power supply voltage VDD is obtained by replacing the conductivity type of the transistor and MOSFET. Therefore, the base-emitter voltage VBE4 of the transistor Q4 provided on the power supply voltage VDD side is used as the bias voltage VB.

  FIG. 29 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the bias voltage VB is realized by the diode connection of the transistor Q4 as in FIG. 21, and resistors R3 and R2 for making a current proportional to the base-emitter voltage VBE4 of the transistor Q4 are respectively connected in parallel. It is the structure added to. By adding a current I + having a positive temperature characteristic flowing through the transistors Q1 and Q2 and a current I− having a negative temperature characteristic flowing through the resistors R3 and R2, a current Io having no temperature dependency is created. A low voltage bandgap reference voltage VbgrL having no temperature dependence is generated by flowing a current proportional to the resistance Ra into the resistor Ra. In this embodiment, the reference voltage VbgrL can be made lower than the base-emitter voltage VBE1 of the transistor Q1. The inputs of the differential amplifier circuits AMP1 and AMP2 are determined by the base-emitter voltage VBE1 of the transistor Q1. Therefore, the differential amplifier circuits AMP1 and AMP2 can operate at about 1V by using low threshold MOSFETs.

  FIG. 30 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the npn transistors Q1, Q2 and Q4 of the embodiment circuit of FIG. 29 are replaced with pnp transistors Q1, Q2 and Q4, and the p-channel MOSFETs M1, M2 and M0 are replaced with n-channel MOSFETs M1, M2 and M0, respectively. It is supposed to be. Further, the reference voltage VbgrL based on the power supply voltage VDD is obtained by replacing the conductivity type of the transistor and MOSFET. Therefore, the base-emitter voltage VBE4 of the transistor Q4 provided on the power supply voltage VDD side is used as the bias voltage VB.

  FIG. 31 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the bias voltage VB is realized by the base-emitter voltage VBE4 of the diode-connected transistor Q4 in the same manner as in FIG. 27, and the potential Vcb in the reference voltage generation circuit considering the offset is also used as the gate. This is realized by the supplied p-channel MOSFET M4. Similarly to FIG. 29, resistors R3 and R2 for generating currents proportional to the base-emitter voltages VBE1 and VBE2 of the transistors Q1 and Q2 are added in parallel. By adding a current I + having a positive temperature characteristic flowing through the transistors Q1 and Q2 and a current I− having a negative temperature characteristic flowing through the resistors R3 and R2, a current Io having no temperature dependency is created. A low voltage bandgap reference voltage VbgrL having no temperature dependence is generated by flowing a current proportional to the resistance Ra into the resistor Ra. Accordingly, a resistor R4 is connected in parallel to the transistor Q4 that forms the bias voltage VB so that a current Io having no temperature dependence flows from the MOSFET M4. Also in this embodiment, the reference voltage VbgrL can be made lower than the base-emitter voltage VBE1 of the transistor Q1, and the inputs of the differential amplifier circuits AMP1 and AMP2 are determined by the base-emitter voltage VBE4 of the transistor Q4. . Therefore, the differential amplifier circuits AMP1 and AMP2 can operate at about 1V by using low threshold MOSFETs.

  FIG. 32 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, the npn transistors Q1, Q2, and Q4 of the embodiment circuit of FIG. 31 are replaced with pnp transistors Q1, Q2, and Q4, and the p-channel MOSFETs M1, M2, M0, and M4 are replaced with n-channel MOSFETs M1, M2, M0, and M4. Respectively. Further, the reference voltage VbgrL based on the power supply voltage VDD is obtained by replacing the conductivity type of the transistor and MOSFET. Therefore, the base-emitter voltage VBE4 of the transistor Q4 provided on the power supply voltage VDD side is used as the bias voltage VB.

  FIG. 33 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. This embodiment is a modification of FIG. The resistor R2 provided in parallel with the transistor Q2 is replaced with a series circuit of R21 and R22. Similarly, the resistor R3 provided in parallel with the transistor Q1 is replaced with a series circuit of R31 and R32, and the resistor R4 provided in parallel with the transistor Q4 is replaced with a series circuit of R41 and R42. The input voltages Vc1 and Vc2 of the differential amplifier circuits AMP1 and AMP2 are the feedback voltages of the differential amplifier circuits AMP1 and AMP2, and the base-emitter voltage VBE4 of the transistor Q4 is divided by the resistors R41 and R42. Therefore, it operates on the same principle of operation as in FIG. In this embodiment, the input voltages Vc1 and Vc2 of the differential amplifier circuits AMP1 and AMP2 can be reduced. For example, by using a p-channel MOSFET as the differential input MOSFET, the differential amplifier circuits AMP1 and AMP2 are configured. The operation at a low voltage of about 1V can be realized without using a low threshold n-channel MOSFET. The reference voltage VbgrL based on the power supply voltage VDD may be obtained by replacing the conductivity types of the transistors and MOSFETs in FIG.

  FIG. 34 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, an example of a current supply circuit of the differential amplifier circuits AMP1 and AMP2 shown in FIG. 4 is shown. As described in FIG. 4, the current Io determined by (VBE1-VBE2) / R1 is passed through the p-channel MOSFET M4 and the n-channel MOSFET M5. By connecting the MOSFETs M6 and M7 to the MOSFET M4 in a current mirror, a bias current to be supplied to the differential amplifier circuits AMP1 and AMP2 is formed by the MOSFETs M6 and M7.

  FIG. 35 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, an example in which a phase compensation circuit is added is shown. The circuit shown in FIG. 4 is applied to the reference voltage generation circuit. The differential amplifier circuit AMP1 is connected with a resistor Rp1 and a capacitor Cp1 connected in series between the output terminal and the ground potential VSS of the circuit, and performs pole-zero phase compensation on the feedback path. A resistor Rp2 and a capacitor Cp2 connected in series are connected between the output terminal and the power supply voltage VDD in the differential amplifier circuit AMP2, and pole zero phase compensation is performed on the feedback path. In this embodiment, mirror compensation is not used in consideration of the PSRR characteristic of the reference voltage VbgrL, and the resistor Rp2 and the capacitor Cp2 are connected to the power supply voltage VDD instead of the circuit ground potential VSS.

  FIG. 36 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, a modification of the phase compensation circuit is shown. The connection method of the resistor Rp2 is changed between the gate of the MOSFET M2 and the gate of the MOSFET M0. Since no direct current is generated at the gate of the MOSFET M0, there is no voltage drop due to the resistor Rp2. Further, since the impedance of the gate of MOSFET M0 is very large, it is considered that the gate is open in terms of alternating current, and the phase compensation effect is exactly the same as in FIG. Since the low-pass filter filter can be formed by the resistor Rp2 and the capacitor Cp2, the PSRR characteristic is improved as compared with FIG.

  FIG. 37 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, a further modification of the phase compensation circuit is shown. A resistor Rp1 and a capacitor Cp1 in series are connected between the input terminal (+) of the differential amplifier circuit AMP1 and the ground potential VSS of the circuit, and pole-zero phase compensation is performed by a feedback path. A resistor Rp2 and a capacitor Cp2 in series are connected between the input terminal (+) of the differential amplifier circuit AMP2 and the ground potential VSS of the circuit, and pole-zero phase compensation is performed on the feedback path. By providing the input terminals (+) of the differential amplifier circuits AMP1 and AMP2 in this way, a phase compensation capacitor is not connected to the output terminal of the differential amplifier circuit AMP2, so that the rising characteristics are better than those shown in FIGS. can do.

  FIG. 38 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, an example in which a startup circuit is added to the embodiment circuit of FIG. 4 is shown. If there is no start-up circuit, the reference voltage generating circuit of FIG. 4 may become stable when the reference voltage VrefL is 0 V when the power is turned on. In this case, since no current flows in the bipolar section, activation is performed by forcing the current to flow. The start-up circuit can generate the reference voltage without error when turning on the current and releasing the sleep. Even if there is a disturbance during operation, it can be recovered immediately and the reference voltage can be generated stably.

  A current Io is formed by the p-channel MOSFET M15 to charge the capacitor C11. At this time, the p-channel MOSFETs M11 to M14 operate as MOS resistors and discharge current from the capacitor C11 at a constant rate. By comparing the current Io for charging the capacitor C11 and the resistance current by the MOSFETs M11 to M14 for discharging, it is determined whether or not the current flows in the bipolar part. When no current flows in the bipolar portion, the output voltage Vca of the differential amplifier circuit AMP1 = 0V and the output voltage Vcb of the differential amplifier circuit AMP2 = VDD. Therefore, the current Io charged from the p-channel MOSFET M15 to the capacitor C11 is small, the discharge currents from the MOSFETs M11 to M14 are larger, and the holding voltage of the capacitor C11 is reduced to 0V.

  The holding voltage of the capacitor C11 is amplified by a CMOS inverter circuit composed of an n-channel MOSFET M16 and a p-channel MOSFET M17, and is transmitted to the cascade circuits of similar CMOS inverter circuits (M18, M19) and (M20, M21). As a result, the p-channel MOSFETs M32 and M33 are turned on, the n-channel MOSFETs M30 and M31 are turned on, the input voltage Vca is the power supply voltage VDD, Vcb is the circuit ground potential VSS, the input voltage Vc1 is the power supply voltage VDD, The input voltage Vc2 is set to the circuit ground potential VSS, and a current flows forcibly through the bipolar section. When a normal current flows through the bipolar section, the current Io flowing through the p-channel MOSFET M15 increases, and the current charging the capacitor C11 becomes larger than the current discharged by the MOSFETs M11 to M14, and the holding voltage of the capacitor C11 is Rise toward VDD. In response to this, the CMOS inverter circuit inverts, the p-channel MOSFETs M32 and M33 are turned off, and the n-channel MOSFETs M30 and M31 are turned off. In this way, the startup circuit is disconnected and the reference voltage generating circuit enters normal operation.

  FIG. 39 is a circuit diagram showing another embodiment of a startup circuit used in the reference voltage generating circuit according to the present invention. The generation circuit of the bias voltage VB is a wideler current mirror circuit (M24 to M27 and R11) as shown in FIGS. 23 to 26, and the startup circuit shown in FIG. 38 is combined therewith. That is, when the current mirror circuit of the wider is not operating normally, the p-channel MOSFET M22 is turned on by the output signal in the start-up circuit, the voltage Vbn is set to the power supply voltage VDD, the n-channel MOSFET M23 is turned on, and the voltage Vbp is set. The circuit is set to the ground potential VSS so that a current flows through the current mirror circuit of the wider. When a normal current flows through the current mirror circuit of the wideler, the current Io flowing through the p-channel MOSFET M15 increases, and the current charging the capacitor C11 becomes larger than the current discharged by the MOSFETs M11 to M14. The holding voltage of C11 increases toward VDD. In response to this, the CMOS inverter circuit inverts, the p-channel MOSFET M22 is turned off, and the n-channel MOSFET M23 is switched to the off state. In this way, the startup circuit is disconnected and the current mirror circuit enters normal operation.

  FIG. 40 is a circuit diagram showing one embodiment of the differential amplifier circuit used in the present invention. N-channel MOSFETs M41 and M42 are connected in a differential configuration. A current source including an n-channel MOSFET M40 is provided between the common source of the MOSFETs M41 and M42 and the circuit ground potential VSS. Between the drains of the differential MOSFETs M41 and M42 and the power supply voltage VDD, p-channel MOSFETs M43 and M44 are connected in the form of a parallel mirror as a load circuit. This differential amplifier circuit can be configured with a simple circuit.

  FIG. 41 shows a circuit diagram of another embodiment of the differential amplifier circuit used in the present invention. In the differential amplifier circuit of this embodiment, diode-like p-channel MOSFETs M43 and M44 are provided at the drains of the same differential MOSFETs M41 and M42, and p-channel MOSFETs M45 and M46 are provided in a current mirror form. A diode-type n-channel MOSFET M47 is provided between the drain of the MOSFET M45 and the circuit ground potential VSS, and an n-channel MOSFET M48 is provided in a current mirror form. The drains of the p-channel MOSFET M46 and the n-channel MOSFET M48 are commonly connected to obtain an output signal Vout having a full amplitude.

  FIG. 42 is a circuit diagram showing still another embodiment of the differential amplifier circuit used in the present invention. In the differential amplifier circuit of this embodiment, diode-type p-channel MOSFETs M43 and M44 are provided as load elements between the drains of the differential MOSFETs M41 and M42 and the power supply voltage VDD. The MOSFET M43 is provided with a MOSFET M49 in the form of a current mirror. A MOSFET M50 as a current source is provided as a load between the drain of the MOSFET M49 and the circuit ground potential VSS. As a result, a full amplitude output signal Vout can be obtained. Since the differential amplifier circuit has a smaller gain than the differential amplifier circuit shown in FIG. 41, phase compensation can be simplified. However, the gain decreases accordingly, and the input error (offset voltage) of the differential amplifier circuit cannot be reduced. However, the band gap configuration of the above embodiment has no problem because the circuit configuration is not affected by the error.

  The differential amplifier circuit AMP shown in FIG. 3, the differential amplifier circuit AMP2 shown in FIG. 4, the differential amplifier circuit AMP2 shown in FIG. In the differential amplifier circuit AMP shown in FIG. 6, the differential amplifier circuit shown in FIG. 41 or FIG. 42 is suitable when considering low voltage characteristics. 40 to 42, the p-channel MOSFET and the n-channel MOSFET may be interchanged. In all the embodiment circuits shown in FIGS. 1 to 5, the optimum configuration selection between the n-channel differential MOSFET and the p-channel differential MOSFET, the size of the MOSFET, and the like, without using the low threshold voltage MOSFET, It is possible to operate up to a low voltage (about 1V) by the optimum design of the resistance value. Further, in the embodiment circuit of FIG. 6, the optimum configuration selection of the n-channel differential MOSFET and the p-channel differential MOSFET and the optimum design of the size and resistance value of the MOSFET are possible without using the low threshold voltage MOSFET. Can operate up to a low voltage (about 1.2 V).

  FIG. 43 shows an overall circuit diagram of an embodiment of the reference voltage generating circuit according to the present invention. This embodiment corresponds to the embodiment of FIG. 38, and comprises a start-up circuit STRT, a bandgap reference section BGR, and differential amplifier circuits AMP1 and AMP2, as shown by the dotted line in FIG. The start-up circuit STRT and the band gap reference part BGR are the same as those in FIG. 38, but phase compensation circuits (Rp1, Cp1) (Rp2, Cp2) as shown in FIG. 35 are added thereto. As the differential amplifier circuit AMP1, a circuit as shown in FIG. 40 is used. However, for low voltage operation, the differential MOSFET and the current source MOSFET are composed of p-channel MOSFETs, and the current mirror circuit as a load circuit is composed of an n-channel MOSFET. As the differential amplifier circuit AMP2, a circuit as shown in FIG. 42 is used. However, for the low voltage operation as described above, the differential MOSFET and the current source MOSFET are composed of p-channel MOSFETs, and the load element and the amplifying element of the differential circuit are composed of n-channel MOSFETs.

  FIG. 44 shows a layout of an embodiment of an npn-type bipolar transistor and an n-channel MOSFET and a p-channel MOSFET constituting a differential amplifier circuit AMP used in the reference voltage generating circuit according to the present invention and an explanatory diagram of the element structure. It is shown. In the figure, the above-described two MOSFETs and one transistor are exemplarily shown as representatives. This transistor is a partial unit transistor that constitutes the transistor Q1, the transistor Q2, or the transistor Q0.

  The npn-type bipolar transistor is not particularly limited, but has a lateral (lateral) structure. An n-type deep well dwel is formed on the p-type semiconductor substrate (p-sub), and a p-type well pwel is formed on the deep well dwel. In the p-type well pwel, an n + type emitter E (n +) is formed at the center, and a p + type base B (p +) is formed so as to surround the periphery. An n + type collector C (n +) is formed so as to further surround the base B (p +). The p-type well pwel is interposed between the emitter E and the collector C and functions as a substantial base region. An insulating layer SGI is provided and separated between the semiconductor regions n + and p +.

  Although not particularly limited, an n-type well is formed around the p-type well pwel, which is joined to the deep well dwel, and the power supply voltage is supplied via an n + region provided in the n-well. A bias voltage such as VCC is applied. As a result, each semiconductor region constituting the npn-type bipolar transistor is electrically isolated from the p-type semiconductor substrate (p-sub).

  An n-channel MOSFET (nMOS) constituting a CMOS circuit has an n + region formed in a p-type well region pwel formed on the semiconductor substrate p-sub as a source and drain region, and is sandwiched between the source and drain. A gate electrode G (nMOS) is formed through the gate insulating film. The p-type well pwel is supplied with a circuit ground potential VSS as a bias voltage from the p + region. A p-channel MOSFET (pMOS) uses a p + region formed in an n-type well region nwel formed on the semiconductor substrate p-sub as a source and drain region, and a gate insulating film is sandwiched between the source and drain. Through this, a gate electrode G (pMOS) is formed. The n-type well nwel is supplied with the power supply voltage VCC as a bias voltage from the n + region. A bias voltage such as a circuit ground potential VSS is applied to the semiconductor substrate p-sub through the p-type well region pwel and the p + region.

  The p-type well region pwel and n + region for forming the source and drain regions for forming the n-channel MOSFET constituting the CMOS circuit, and the p-type well region pwel, emitter and collector for forming the npn bipolar transistor are constituted. The n + region to be formed is formed by the same process. The p + region constituting the source and drain regions of the p-channel MOSFET constituting the CMOS circuit and the p + region constituting the base for forming the npn bipolar transistor are formed by the same process.

  The transistor Q1 (Q2) of the band gap generating portion of this embodiment is a device formed by a CMOS process. Thus, by forming the transistors Q1 and Q2 by the CMOS process, the reference voltage generation circuit is the same CMOS as the digital CMOS circuit such as another microcomputer formed on the same semiconductor substrate without using the bipolar process. Can be formed in the process. The substrate potential VSS of the semiconductor substrate p-sub is stabilized by arranging the guard band or the guard ring including the deep well dwel, the n-type well nwel and the n + region as described above around or between the bipolar portion and the CMOS portion. , Noise propagation can be suppressed. By forming the npn bipolar transistor in the deep well dwel in this way, the influence of noise propagating from other circuit modules via the substrate p-sub can be suppressed.

  FIG. 45 shows the layout of an npn-type bipolar transistor used in the reference voltage generating circuit according to the present invention and the n-channel MOSFET and p-channel MOSFET constituting the differential amplifier circuit AMP, and the element structure thereof. The figure is shown. In the npn-type bipolar transistor of this embodiment, the collector is formed in a vertical (vertical) structure using an n-type deep well dwel. 44. Similarly to the embodiment of FIG. 44, the base B (p +) is formed around the emitter E (n +) as the center, and the n-type well nwel and n + region for taking out the collector C (n +) are surrounded by the periphery. Place. In this structure, the emitter (n + region) -base (p-type well pwel) -collector (n-type deep well dwel) has a vertical structure.

  The vertical npn bipolar transistor of this embodiment has a higher current amplification factor hfe of the bipolar transistor and a higher gain of the bipolar portion than the horizontal bipolar transistor of FIG. 44. Therefore, as described in the embodiment of FIG. In addition, the effect of generating a highly accurate reference voltage by suppressing the influence of the offset voltage of the amplifier circuit becomes higher. In this embodiment, the CMOS circuit is also provided with an n-type deep well dwel, and the p-type well pwel portion is surrounded by the n-type well nwel and electrically separated from the semiconductor substrate p-sub. . Thereby, the potential of the p-type well pwel in which the n-channel MOSFET is formed can be freely set regardless of the bias voltage VSS applied to the semiconductor substrate p-sub. Therefore, it is possible to cope with a digital circuit in which the bias VBB applied to the p-type well pwel is pulled to a negative voltage.

  FIG. 46 shows the layout of an npn-type bipolar transistor used in the reference voltage generating circuit according to the present invention and the n-channel MOSFET and p-channel MOSFET constituting the differential amplifier circuit AMP and the element structure thereof. An illustration is shown. In this embodiment, an n-type semiconductor substrate n-sub is used. When the n-type semiconductor substrate n-sub is used in this way, unlike the embodiment of FIG. 44, an npn bipolar transistor is configured with a CMOS double well structure. That is, the base B (p +), the emitter E (n +), and the collector C (n +) are formed in the p-type well pwel. As in the embodiment of FIG. 44, the emitter E is arranged around the base B and the collector B so as to surround the base B and the collector C. With this configuration, a lateral npn bipolar transistor can be formed with a structure that does not form a deep well dwel as in the embodiment of FIG. 44 (an nMOS is formed in a p-type well pwel and a pMOS is formed in an n-type well). .

  When an n-type semiconductor substrate n-sub is used as in this embodiment, a deep well dwel for separating the substrate and the collector is not necessary, and a CMOS double well structure can be formed. Process steps can be reduced.

  In the reference voltage generation circuit of this embodiment, it is possible to obtain a highly accurate reference voltage that is not easily affected by the offset of the CMOS differential amplifier circuit. Trimming to reduce the influence of offset can be eliminated. For example, for power supply circuits of ROMless products that are difficult to trim such as air-bag microcomputers, high-precision reference voltage generation that does not require trimming circuits It can be useful as a circuit.

  FIG. 47 shows a layout diagram of another embodiment of an npn-type bipolar transistor used in the reference voltage generating circuit according to the present invention. Although not particularly limited, the collector C (n +) is formed in the vertical direction (vertical structure) using the n-type deep well dwel as in the embodiment of FIG. The emitter E (n +) is surrounded by a base B (p +) in a U-shape, and its periphery is surrounded by the collector C (n +). This layout configuration can also be applied to the lateral transistor shown in FIG.

  FIG. 48 shows a layout diagram of still another embodiment of an npn-type bipolar transistor used in the reference voltage generating circuit according to the present invention. In this embodiment, similarly to the embodiment of FIG. 44, the base B (p +), the emitter E (n +), and the collector C (n +) are formed in the p-type well pwel and separated by the power supply voltage VCC. Surround with a mold deep well dwel. And it is set as the horizontal structure which arrange | positions the collector C (n +), base B (p +), and emitter E (n +) in parallel. The vertical structure of the CMOS shown in FIGS. 44 and 45 and the layout of the bipolar transistors shown in FIGS. 44 to 48 can be realized by arbitrarily combining them.

  In the reference voltage generation circuit of this embodiment, the band gap generation unit is configured such that the size ratio of the transistors Q1 (Q0) and Q2 is 1 to n. Transistors Q1 and Q2 are formed on separate n-type deep wells dwel.

  FIG. 49 shows a layout diagram of one embodiment of npn-type bipolar transistors Q1 and Q2 used in the reference voltage generating circuit according to the present invention. The transistor Q0 is similar to the transistor Q1. In this embodiment, although not particularly limited, a case where the collector is formed in the vertical direction using an n-type deep well dwel is shown as an example. In this embodiment, transistors Q1 (Q0) and Q2 are surrounded by an n-type deep well dwel. The deep well dwel of the transistor Q1 (Q0) having a small size is formed to be small corresponding to the size. On the other hand, the n-type deep well dwel of the large transistor Q2 has a large size corresponding to the eight transistors Q1. In this configuration, the size ratio between the transistors Q1 and Q2 is set to 1: 8.

  FIG. 50 shows a layout diagram of another embodiment of npn-type bipolar transistors Q1 (Q0) and Q2 used in the reference voltage generating circuit according to the present invention. In this embodiment, unlike the embodiment of FIG. 49, the n-type deep well dwel constituting the collectors of the two transistors Q1 (Q0) and Q2 are formed to have the same size. Thus, by forming the n-type deep well dwel constituting the collector in the same size, the influence of the noise propagating from the substrate by capacitive coupling is made equal, and can be canceled as in-phase noise.

  FIG. 51 shows a layout diagram of another embodiment of npn-type bipolar transistors Q1 (Q0) and Q2 used in the reference voltage generating circuit according to the present invention. In this embodiment, the transistors Q1 (Q0) and Q2 are formed as a small transistor Q1 (Q0) in addition to the n-type deep well dwel having the same size as in the embodiment of FIG. In the deep well dwel, eight transistors including dummy transistors are arranged to have the same configuration as the transistor Q2. The size ratio is set as Q1 / Q2 = 1/8 by wiring one of the eight transistors. Thus, by setting it as the same pattern, the influence of processing dimension dispersion | variation can be reduced.

  FIG. 52 shows a layout diagram of still another embodiment of npn-type bipolar transistors Q1 (Q0) and Q2 used in the reference voltage generating circuit according to the present invention. In this embodiment, a transistor having a lateral structure as shown in FIG. 48 in which the base B, the emitter E, and the collector C are formed on the same p-type well pwel is used. As in the transistor of FIG. 48, an n + region for power supply for stabilizing the n-type deep well dwel and an n-type are provided around the n-type deep well dwel in which the transistor Q1 (Q0) or Q2 is formed. A well nwel (not shown) is provided. In this embodiment, the size ratio is Q1 / Q2 = 1/9, and the transistor Q1 (Q0) is composed of one transistor and eight dummy transistors. When the number of transistors Q2 is a power such as nine as in this embodiment, the influence of the dimensional variation can be further reduced by taking the center part of the transistors in which the same number of transistors Q1 (Q0) are arranged. .

  In any of the shapes shown in FIGS. 49 to 52, the lateral structure formed on the same well is used when the bipolar transistor collector is formed in a vertical structure using an n-type deep well in the vertical direction. It can be applied to any of the above.

  FIG. 53 shows a layout of one embodiment of a pnp bipolar transistor used in the reference voltage generating circuit according to the present invention and an explanatory diagram of its element structure. In this embodiment, the conductivity type is opposite to that shown in FIG. That is, in the pnp bipolar transistor, a p-type deep well dwel is formed on an n-type semiconductor substrate (n-sub), and an n-type well nwel is formed on the deep well dwel. In the n-type well pwel, a p + type emitter E (p +) is formed at the center, and an n + type base B (n +) is formed so as to surround the periphery. A p + type collector C (p +) is formed so as to further surround the base B (n +). The n-type well nwel is interposed between the emitter E and the collector C and functions as a substantial base region. An insulating layer SGI is provided and separated between the semiconductor regions p + and n +.

  FIG. 54 shows a layout of another embodiment of a pnp bipolar transistor used in the reference voltage generating circuit according to the present invention and an explanatory diagram of its element structure. In this embodiment, the conductivity type is opposite to that shown in FIG. In the pnp bipolar transistor of this embodiment, the collector is formed in a vertical (vertical) structure using a p-type deep well dwel. Similarly to the embodiment of FIG. 53, the base B (n +) is formed around the emitter E (p +) as the center, and the p-type well nwel and p + region for taking out the collector C (p +) so as to surround the periphery. Place. In such a structure, the emitter (p + region) -base (n-type well pwel) -collector (p-type deep well dwel) has a vertical structure.

  FIG. 55 shows a layout of another embodiment of a pnp bipolar transistor used in the reference voltage generating circuit according to the present invention and an explanatory diagram of its element structure. In this embodiment, a p-type semiconductor substrate p-sub is used. When the p-type semiconductor substrate p-sub is used in this way, unlike the embodiment of FIG. 53, a pnp bipolar transistor is configured with a CMOS double well structure. That is, the base B (n +), the emitter E (p +), and the collector C (p +) are formed in the n-type well nwel. As in the embodiment of FIG. 53, the emitter E is arranged around the base B and the base B and the collector C so as to surround it. With this configuration, a lateral pnp bipolar transistor can be formed with a structure that does not form a deep well dwel as in the embodiment of FIG. 53 (a pMOS is formed in an n-type well nwel and an nMOS is formed in a p-type well). .

  FIG. 56 shows an element structure diagram of one embodiment of a resistance element provided in the semiconductor integrated circuit device according to the present invention. In the example of FIG. 56A, an n + diffusion layer formed in a p-type well is used as a resistor. In the example of FIG. 56B, a polysilicon layer p + poly formed on the isolation insulating layer SGI is used as a resistance element. The example of FIG. 56C uses a p-type well pwel formed in an n-type deep well dwel as a resistance element. The p-type well pwel is electrically isolated from the substrate p-sub by the deep well dwel and the n-type well nwel and n + region provided around the deep well dwel. Any of the resistance elements (A) to (C) can be constituted by a standard CMOS process (double well or triple well structure).

  FIG. 56 (A) uses the resistance value between n + diffusions (or the resistance value between p + diffusions in the n well), and the p well pwel in which it is formed is stabilized by p + diffusion. Is given a bias. A high resistance can be obtained in a relatively small area, the resistance has a high accuracy, and can be formed with a double well or triple well CMOS structure.

  The polysilicon resistance in FIG. 56B is the resistance value between the terminals of p + polysilicon formed on the isolation region SGI in the p-type well pwel (or n + polysilicon formed on the SGI in the n-type well nwel). The resistance value between silicon terminals) is utilized, a high resistance can be obtained in a relatively small area, the resistance accuracy can be increased, and a double well or triple well CMOS structure can be formed.

  FIG. 56 (C) uses a resistance value between terminals of the p-type well pwel formed on the n-type deep well dwel (terminals are provided on the p + diffusion), and has a small area and high resistance. Is obtained. It can be formed with a triple well CMOS structure.

  FIG. 57 shows an element structure diagram of an embodiment of a capacitive element provided in the semiconductor integrated circuit device according to the present invention. The example of FIG. 24A is formed by providing two layers of polysilicon over an insulating layer SGI in the p-type well pwel with an interlayer insulating film interposed therebetween. The example of FIG. 24B uses MOS capacitance, and uses the capacitance between the gate (polysilicon) and the source and drain of the p-channel MOSFET in the n-type well nwel (source and drain are short-circuited). It is. The n-type well nwel is stabilized at a higher potential than the power supply or p-sub through the n + layer on the well. (An nMOS in a p-well on an n-sub can be similarly configured with a MOS capacitor. Both the capacitor elements (A) and (B) described above are formed by a standard CMOS process (double well or triple well structure). Can be configured.

  FIG. 58 shows a circuit diagram of an embodiment of a power supply circuit using the reference voltage generating circuit according to the present invention. The reference voltage VrefL generated by the reference voltage generating circuit as shown in FIGS. 1 to 37 according to the present invention is leveled to the desired power supply voltage vo1 by the buffer circuit comprising the amplifier A1 and the negative feedback resistors R5 and R6. It is converted and output as internal voltages VO1 and VO1 supplied to the internal circuit through a regulator circuit composed of voltage follower circuits A3 and A4. On the other hand, the reference voltage VrefL is level-converted to a desired power supply voltage vo2 different from the voltage vo1 by a buffer circuit including an amplifier A2 and negative feedback resistors R5 ′ and R6 ′, and voltage follower circuits A5 and A6. The voltage is output as internal voltages VO2 and VO2 supplied to other internal circuits through a regulator circuit consisting of

  In this embodiment, a plurality of regulator circuits are provided corresponding to a plurality of functional blocks, and are arranged in the vicinity of individual circuit modules (functional blocks), so that the circuit between the regulator circuit and the circuit module is provided. The wiring resistance value can be reduced, and the power supply voltage level can be prevented from lowering even when there is a relatively large load current flowing through the circuit module.

  FIG. 59 is an overall block diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention. This embodiment is not particularly limited, but is directed to a system LSI having a built-in power supply circuit. The power supply circuit of this embodiment includes a reference voltage generating circuit, a reference voltage buffer circuit, a series regulator (main power supply: main regulator and standby power supply: subregulator), and a power supply control unit. These power supply circuits operate by receiving a power supply voltage supplied from an external terminal Vext, and form an internal voltage Vint obtained by stepping down the power supply voltage, thereby forming a CPU (central processing unit), registers, and nonvolatile memory constituting the system LSI. The operating voltage of the element and other peripheral circuits is formed.

  The power supply controller performs level conversion of the buffer circuit, designation of activation of each block, and the like by the control signals cnt1 to cnt4. The semiconductor integrated circuit device is provided with an input / output circuit. The input / output circuit operates in response to the power supply voltage supplied from the external terminal Vext, and includes an input circuit for shifting the level of the external signal supplied from the external terminal to match the level of the internal circuit, and the internal circuit And an output circuit that converts the signal level to be output from the external terminal. Although not particularly limited, Vext is a wide range power supply voltage such as 2 to 6V, and the internal voltage Vint is a low voltage such as 1.0 to 1.5V.

  As described above, the input / output circuit and the power supply circuit are operated by the power supply voltage supplied from the external terminal Vext. This input / output circuit inputs and outputs control signals from the power supply circuit and the CPU. The internal voltage Vint is an internal power supply voltage output from the power supply circuit, and is supplied to the CPU, registers, nonvolatile memory elements, and other peripheral circuits. In this embodiment, by determining the internal power supply voltage Vint based on the reference voltage Vref of the reference voltage generating circuit, a constant internal power supply voltage can be obtained regardless of external factors such as fluctuations in the external power supply voltage Vext and temperature changes. Vint can be supplied.

  FIG. 60 is an overall block diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention. This embodiment is not particularly limited, but is directed to an LCD driver circuit having a built-in power supply circuit. The LCD driver circuit of this embodiment is based on a reference voltage generating circuit, a booster circuit, a RAM (random access memory) for storing display data, a source driver, a gate driver, a VCOM driver and an output voltage VrefL of the reference voltage generating circuit. The circuit includes a circuit for generating a voltage for driving each driver (RAM step-down circuit, source voltage generation circuit, gate voltage generation circuit, VCOM voltage generation circuit) and a driver control circuit.

  The source voltage generation circuit generates gradation voltages VS0 to VSn corresponding to display data supplied to pixels of an LCD (liquid crystal) panel. The gate voltage generation circuit generates gate voltage selection / non-selection voltages VGH and VGL for selecting a pixel. The VCOM voltage generates common voltages VCOMH and VCOML applied to the common electrode of the liquid crystal panel. The source driver outputs one voltage Si among the gradation voltages VS0 to VSn corresponding to the display data. The gate driver receives a selection signal corresponding to the scanning operation and outputs a pixel selection / non-selection signal Gj. The VCOM driver switches the voltage VCOM corresponding to a positive voltage field and a negative voltage field in order to AC drive the liquid crystal pixels.

  In this embodiment LCD driver circuit, the external power supply voltage Vci is provided by applying voltages VDL, VS0 to VSn, VGH, VGL, VCOMH, VCOML, etc. for driving each driver circuit based on the reference voltage VrefL of the reference voltage generating circuit. Regardless of external factors such as fluctuations in temperature and temperature changes, signals can be supplied to the LCD panel by driving each driver stably without performing trimming.

  FIG. 61 is a block diagram for explaining an application example of the reference voltage generating circuit according to the present invention. This embodiment is directed to an application to an analog / digital converter (ADC). Based on the reference voltage VrefL formed by the reference voltage generating circuit according to the present invention, the voltage is converted into a desired voltage by the amplifier circuit A10, the voltage conversion circuit comprising the output MOSFET M10 and the feedback resistors R10 and R11, and the maximum voltage VRT and the minimum A voltage VRB is formed and divided by a resistor dividing circuit to form a plurality of reference voltages, and compared with the analog input AIN to form digital outputs D0 to Dn. In this embodiment, it is not necessary to supply the reference voltage VrefL from the outside of the chip of the semiconductor integrated circuit device incorporating the ADC. By setting the reference voltage VrefL to about 0.8V, the power supply voltage VCC can be operated at a low voltage of about 1V.

  FIG. 62 is a block diagram for explaining another application example of the reference voltage generating circuit according to the present invention. This embodiment is directed to an application to a digital / analog converter (DAC). Based on the reference voltage VrefL formed by the reference voltage generating circuit according to the present invention, a desired reference current Iref (= VrefL / R12) is obtained by a voltage-current conversion circuit including an amplifier circuit A11, an output MOSFET M11, and a feedback resistor R12. The analog output voltage AOUT is obtained by forming a current having a binary weight based on the reference current Iref, synthesizing the current corresponding to the digital input signals D0 to Dn, and flowing the current through a resistor. it can. Also in this embodiment, it is not necessary to supply the reference voltage VrefL from the outside of the chip of the semiconductor integrated circuit device incorporating the DAC. Similarly to the above, by setting the reference voltage VrefL to about 0.8V, it is possible to operate with the power supply voltage VCC as low as about 1V.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, the transistors Q1 and Q2 may be made to have the same current flow and a current density difference depending on the area ratio, but the transistors Q1 and Q2 may have the same size and the emitter current may flow at a constant ratio. . Also, a combination of area ratio and current ratio may be used. The present invention incorporates a constant voltage generation circuit or a reference voltage generation circuit mounted on a semiconductor integrated circuit device formed by a CMOS process, and can be widely used for a semiconductor integrated circuit device formed by a CMOS process.

1 is a circuit diagram showing an embodiment of a reference voltage generating circuit according to the present invention. FIG. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. It is a circuit diagram which shows another Example of the startup circuit used for the reference voltage generation circuit based on this invention. It is a circuit diagram which shows one Example of the differential amplifier circuit used for this invention. It is a circuit diagram which shows another Example of the differential amplifier circuit used for this invention. It is a circuit diagram which shows another Example of the differential amplifier circuit used for this invention. 1 is an overall circuit diagram showing an embodiment of a reference voltage generating circuit according to the present invention. FIG. 2 is an explanatory diagram of a layout and an element structure showing one embodiment of an npn-type bipolar transistor and an n-channel MOSFET and a p-channel MOSFET constituting a differential amplifier circuit used in the reference voltage generating circuit according to the present invention. FIG. 6 is an explanatory diagram of a layout and an element structure showing another embodiment of an npn-type bipolar transistor and an n-channel MOSFET and a p-channel MOSFET constituting a differential amplifier circuit used in the reference voltage generating circuit according to the present invention. It is explanatory drawing of the layout which shows further another Example of the npn type | mold bipolar transistor used for the reference voltage generation circuit which concerns on this invention, and n channel MOSFET which comprises a differential amplifier circuit, and p channel MOSFET, and its element structure. FIG. 6 is a layout diagram showing another embodiment of an npn-type bipolar transistor used in the reference voltage generating circuit according to the present invention. FIG. 10 is a layout diagram showing still another embodiment of an npn-type bipolar transistor used in the reference voltage generating circuit according to the present invention. FIG. 5 is a layout diagram showing one embodiment of npn-type bipolar transistors Q1 (Q0) and Q2 used in the reference voltage generating circuit according to the present invention. FIG. 7 is a layout diagram showing another embodiment of npn-type bipolar transistors Q1 (Q0) and Q2 used in the reference voltage generating circuit according to the present invention. FIG. 7 is a layout diagram showing another embodiment of npn-type bipolar transistors Q1 (Q0) and Q2 used in the reference voltage generating circuit according to the present invention. FIG. 11 is a layout diagram showing still another embodiment of npn-type bipolar transistors Q1 (Q0) and Q2 used in the reference voltage generating circuit according to the present invention. FIG. 3 is an explanatory diagram of a layout and an element structure showing an embodiment of a pnp bipolar transistor used in the reference voltage generation circuit according to the present invention. It is explanatory drawing of the layout which shows another Example of the pnp-type bipolar transistor used for the reference voltage generation circuit which concerns on this invention, and its element structure. It is explanatory drawing of the layout which shows another Example of the pnp-type bipolar transistor used for the reference voltage generation circuit which concerns on this invention, and its element structure. 1 is an element structure diagram showing one embodiment of a resistance element provided in a semiconductor integrated circuit device according to the present invention. 1 is an element structure diagram showing one embodiment of a capacitive element provided in a semiconductor integrated circuit device according to the present invention. 1 is a circuit diagram showing an embodiment of a power supply circuit using a reference voltage generating circuit according to the present invention. 1 is an overall block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention. It is a whole block diagram which shows another Example of the semiconductor integrated circuit device based on this invention. It is a block diagram for demonstrating the application example of the reference voltage generation circuit which concerns on this invention. It is a block diagram for demonstrating the other application example of the reference voltage generation circuit which concerns on this invention. It is a circuit diagram which shows an example of the conventional reference voltage generation circuit.

Explanation of symbols

  Q0, Q1-Q3 ... transistor, M0-M48 ... MOSFET, Ra, Rb, R1-R52 ... resistor, C11, Cp1, Cp2 ... capacitor, Rp1, Rp2 ... resistor, AMP, AMP1, AMP2 ... differential amplifier circuit, STRT ... start-up circuit, BGR ... band gap part, C (n +) ... collector, B (p +) ... base, E (n +) ... emitter, dwel ... n-type deep well, pwel ... p-type well, nwel ... n-type well, SGI: insulating layer (element isolation), n + ... semiconductor region, p + ... semiconductor region, G ... gate, M1 to M24 ... MOSFET, SW ... switch, CMP ... voltage comparison circuit, A1-A6, A11, A12 ... amplification circuit, ADC: analog / digital conversion circuit, DAC: digital / analog conversion circuit.

Claims (14)

A first transistor having an emitter connected to a first power supply voltage terminal ;
A second transistor having an emitter area larger than that of the first transistor ;
A third transistor having an emitter connected to the first power supply voltage terminal and a base and a collector commonly connected;
A first amplifier circuit configured by a MOSFET and supplied with the collector voltage of the first transistor and the collector voltage of the second transistor ;
A first resistance element connected between the emitter of the second transistor and the first power supply voltage terminal ;
A current source circuit for supplying a predetermined current to the first, second and third transistors ;
A second resistance element;
The base of the first transistor and the base of the second transistor are connected in common and supplied with a voltage corresponding to the output voltage of the first amplifier circuit,
Upper Symbol second resistance element is connected to the third transistor and the first power supply voltage terminal or series configuration to a second power supply voltage terminal side,
The semiconductor integrated circuit device having a reference voltage generating circuit as a reference voltage a voltage generated by the series circuit of the upper Symbol third transistor and the second resistor element. A first transistor having an emitter connected to a first power supply voltage terminal;
A second transistor having an emitter area larger than that of the first transistor;
A third transistor having an emitter connected to the first power supply voltage terminal and a base and a collector commonly connected;
An amplification MOSFET in which the collector voltage of the second transistor is supplied to the gate and the source is connected to the second power supply voltage terminal;
A current source circuit for supplying a predetermined current to the first, second and third transistors;
A first resistance element connected between the emitter of the second transistor and the first power supply voltage terminal;
A second resistance element;
A fourth transistor provided between the drain of the amplification MOSFET and the first power supply voltage terminal and having a base and a collector commonly connected;
The bases of the first, second and fourth transistors are connected in common,
The second resistance element is connected in series to the third transistor and the first power supply voltage terminal or the second power supply voltage terminal side,
A semiconductor integrated circuit device having a reference voltage generation circuit using a voltage generated in a series circuit of the third transistor and the second resistance element as a reference voltage. A first transistor having an emitter connected to a first power supply voltage terminal;
A second transistor having an emitter area larger than that of the first transistor;
A third transistor having an emitter connected to the first power supply terminal and a base and a collector commonly connected;
A first amplifier circuit configured by a MOSFET and supplied with a collector voltage of the first transistor and a predetermined bias voltage;
A current source circuit for supplying a predetermined current to the first, second and third transistors;
A first resistance element connected between the emitter of the second transistor and the first power supply voltage terminal;
A second resistance element;
The base of the first transistor and the base of the second transistor are connected in common and supplied with a voltage corresponding to the output voltage of the first amplifier circuit,
The second resistance element is connected in series to the third transistor and the first power supply voltage terminal or the second power supply voltage terminal side,
A semiconductor integrated circuit device having a reference voltage generation circuit using a voltage generated in a series circuit of the third transistor and the second resistance element as a reference voltage. In claims 1 to 3 ,
A third resistance element;
The third resistor element, a semiconductor integrated circuit device characterized by being connected in parallel to the series circuit. In claims 1 to 3 ,
The first transistor and the third transistor, with the same emitter area,
The above first to third transistor semiconductor integrated circuit device which is to flow a current having the same current value. In claim 1 or 3 ,
The first, second, and third transistors are semiconductor integrated circuit devices configured using a semiconductor region formed by a process of a CMOS circuit that constitutes the first amplifier circuit. In claims 1 to 3 ,
Upper SL current source circuit, the semiconductor integrated circuit device is a current mirror circuit composed of MOSFET to the input current to the collector current of the first or second transistor. In claims 1 to 3,
The current source circuit is
A plurality of MOSFETs;
A second amplifier circuit,
The semiconductor integrated circuit device, wherein the second amplifier circuit is supplied with the collector voltage of the second transistor and supplies the output voltage to the gates of the plurality of MOSFETs. In claim 3 ,
The semiconductor integrated circuit device, wherein the bias voltage is formed by a bias voltage generating circuit comprising a current source and a resistance means provided in series between the first power supply voltage terminal and the second power supply voltage terminal. In claim 3 ,
The bias voltage is a current mirror circuit in which an output current of a current mirror circuit of an N-channel MOSFET and a P-channel MOSFET provided between the first power supply voltage terminal and the second power supply voltage terminal is used as an input current. A semiconductor integrated circuit device formed of In claim 8 ,
The bias voltage is
The output voltage of the first amplification circuit base, is supplied to Koretaku, a fifth transistor having an emitter connected to said first power supply voltage terminal, the output voltage of the second amplification circuit is supplied to the gate, source There semiconductor integrated circuit device formed by a series circuit of the M OSFET connected to said second power supply voltage terminal. In claim 6 ,
The MOSFET includes a second conductivity type well region and a first conductivity type well region formed in a first conductivity type semiconductor substrate, a first conductivity type MOSFET formed in the second conductivity type region, and the first conductivity type. A second conductivity type MOSFET formed in the conductivity type well region;
In the first transistor and the second transistor, the diffusion layer formed in the step of forming the source and drain diffusion layers of the second conductivity type MOSFET constituting the MOSFET is used as a collector and an emitter, and the diffusion layer as the collector and the emitter is used. A semiconductor integrated circuit device, which is a lateral bipolar transistor that operates on the basis of a first conductivity type well region in which is formed. In claim 6 ,
The MOSFET includes a second conductivity type well region and a first conductivity type well region formed in a first conductivity type semiconductor substrate, a first conductivity type MOSFET formed in the second conductivity type well region, and the first conductivity type MOSFET. A second conductivity type MOSFET formed in a first conductivity type region, for deeply isolating the first conductivity type well region in which the second conductivity type MOSFET is formed from the first conductivity type semiconductor substrate; A second conductivity type well region having a depth;
The first transistor and the second transistor have a second conductivity type diffusion layer formed in the step of forming a source / drain diffusion layer of the first conductivity type MOSFET as an emitter, and a second conductivity type diffusion that constitutes the emitter. The first conductivity type well region in which the layer is formed is used as a bait, and the first conductivity type well region constituting the base is deeply provided to electrically isolate the first conductivity type well region from the first conductivity type semiconductor substrate. A semiconductor integrated circuit device which is a bipolar transistor having a vertical structure using a second conductivity type well region as a collector. In claim 13 ,
The first transistor is composed of one transistor,
The second transistor is a semiconductor integrated circuit device configured by connecting a plurality of unit transistors corresponding to the first transistor in parallel.

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