JP2009265954A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit for generating reference voltage suited for low-voltage operation while reducing influence due to process unevenness. <P>SOLUTION: The circuit includes a first transistor (hereinafter, Tr) and a second Tr having a large emitter area. The base currents of the first and second Trs are formed such that the base voltage and the collector voltage of the first Tr are made equal by a first amplifier circuit. A first resistance is provided between the emitter of the second Tr and the reference potential and applied with a band gap voltage. A second resistance is provided between the emitter of a third Tr and VSS, and a third resistance is provided between the collector and base of the third Tr and VSS. The reference voltage output from the collector and base of the third Tr is temperature-compensated according to a ratio between the first and second resistances. A second amplifier circuit forms gate voltages of a first to third MOS such that the collectors of the first and second Tr are made equal, and forms the collector currents of the first to third Trs. A fourth to sixth resistances are provided source sides of the first to third MOS, respectively. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique that is effective for use in a device having a reference voltage generation circuit formed by a CMOS process having a triple well structure.

As a band gap reference voltage generation circuit of a CMOS process, for example, 2007 Sympsium on VLSI Circuits Digest of Technical Papers pp. 96-97 (A Trimmig-Free CMOS Bandgap-Reference Circuit with Sub-1-V-Supply Voltage Operation) is available. FIG. 10 shows a reference voltage generating circuit of the same document. The reference voltage generation circuit shown in the figure uses the differential amplifier circuits A1 and A2 to suppress the influence of the offset voltage of the differential amplifier circuit A1 on the reference voltage Vref. In this configuration, by operating in the activation region where the collector currents of the bipolar transistors Q1 and Q3 are almost independent of the collector potential, it is difficult to suppress the influence of the offset voltage in the differential input portion of the differential amplifier circuit A1.
2007 Sympsium on VLSI Circuits Digest of Technical Papers pp.96-97 (A Trimmig-Free CMOS Bandgap-Reference Circuit with Sub-1-V-Supply Voltage Operation)

  The inventor of the present application has found that the reference voltage generation circuit shown in Non-Patent Document 1 has the following problems due to process variations of elements accompanying element miniaturization and the like. In order to realize a low-voltage, high-accuracy reference voltage (bandgap reference) using a CMOS process, it is important to suppress the influence of offset voltage in pair elements such as differential (arithmetic) amplifier circuits and current mirror circuits It is. FIG. 11 shows the equivalent circuit of FIG. 10 studied by the present inventors. It can be seen that the offset voltage V1 due to the differential MOSFET pair element constituting the differential amplifier circuit A1 has been improved as in the characteristics of the offset voltage V1 and the reference voltage Vref shown in FIG.

  However, as shown in the equivalent circuit of FIG. 11, in the reference voltage generating circuit of FIG. 10, in addition to the differential elements of the differential amplifier circuit A1, P-channel MOSFETs QP1 to QP4 that constitute a current mirror circuit are used. Even in such a pair element, there should be offset voltages V2 to V5, respectively. When the influence of the offset voltages V2 to V5 on the reference voltage Vref is examined by computer simulation by the inventors of the present application, it has been found that the characteristics V2 to V5 in FIG. 12 are obtained.

  In FIG. 12, it is assumed that the threshold voltages of the MOSFETs QP1 to QP4 have fluctuated in the range of −10 mV to +10 mV with respect to the target value (0 mV), and the offset voltages V2 to V5 are the reference voltages Vref. This is a verification of the impact on From FIG. 12, the threshold voltage variation (offset voltage V2) of the MOSFET QP1 has the greatest influence on the reference voltage Vref, and then the influence of the variation of the threshold voltage of the MOSFET QP2 (V3) is large, and the threshold of the MOSFET QP4. It can be seen that the influence of the value voltage variation (V5) is slight. That is, in the reference voltage generating circuit of FIG. 10, the reference voltage Vref fluctuates greatly due to variations in threshold voltages (V2 to V4) of the P-channel MOSFETs QP1 to QP3 constituting these current mirror circuits. Have

  In the reference voltage generating circuit shown in FIG. 10, no consideration is given to the process variation of the current amplification factor β of the bipolar transistor formed by the CMOS process. The bipolar transistors Q1 to Q3 are formed as vertical NPN transistors by using a semiconductor region for forming an N-channel MOSFET having a triple (triple) well structure as shown in the same document. In this transistor structure, a diffusion layer for forming the source and drain of an N-channel MOSFET is used as an emitter, a P-type well region in which the source and drain regions are formed is used as a base region, and the P-type well is formed from a P-type substrate. A deep N-type well for electrical isolation is used as a collector region.

  For this reason, the current amplification factor β of the transistors Q1 to Q3 formed by the CMOS process largely fluctuates as compared with a transistor formed by a normal bipolar transistor manufacturing process. For example, it is predicted that a large variation such as a range of half (β × 0.5) to twice (β × 2) with respect to the design value β is exhibited. When the influence of the variation β × 0.5 to β × 2 on the reference voltage Vref due to the variation of the current amplification factor β is examined by computer simulation by the inventor, the characteristic β × 0.5 to β × 2 in FIG. It has been found that the reference voltage Vref varies.

  One object of the present invention is to provide a semiconductor integrated circuit device having a reference voltage generation circuit in which the influence of process variations of elements is suppressed. Another object of the present invention is to provide a reference voltage generation circuit which is formed by a CMOS process, suppresses the influence of device process variations, and is suitable for low voltage operation. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  One embodiment disclosed in the present application is as follows. A reference voltage generation circuit formed in a semiconductor integrated circuit device has a first transistor and a second transistor having a larger emitter area. The first differential amplifier circuit forms the base currents of the first transistor and the second transistor so that the base and collector voltages of the first transistor are equal. The first resistance element is provided between the emitter of the second transistor and a reference potential, and is applied with a silicon band gap voltage generated corresponding to the emitter current density of the first transistor and the second transistor. . In the third transistor, a collector and a base are coupled, a second resistance element is provided between the emitter and the reference potential, and a third resistance element is disposed between the coupled collector and base and the reference potential. Provided. The second differential amplifier circuit receives the voltages of the collectors of the first and second transistors, and sets the gate voltages of the first to third MOSFETs that respectively form the collector currents of the first to third transistors so that they are equal. Control. The first resistance element and the second resistance element are set to have a resistance ratio such that the reference voltage output from the collector and base combined with the third transistor does not have temperature dependence. Fourth to sixth resistance elements are provided on the source sides of the first to third MOSFETs, respectively.

  Another embodiment disclosed in the present application is as follows. A reference voltage generating circuit formed in a semiconductor integrated circuit device includes a first transistor and a second transistor having a larger emitter area. The first differential amplifier circuit forms base currents for the first and second transistors so that the base and collector voltages of the first transistor are equal. The first resistance element is provided between the emitter of the second transistor and a reference potential, and is applied with a silicon band gap voltage generated corresponding to the emitter current density of the first transistor and the second transistor. . In the third transistor, a collector and a base are coupled, a second resistance element is provided between the emitter and the reference potential, and a third resistance element is disposed between the coupled collector and base and the reference potential. Provided. The second differential amplifier circuit receives the voltages of the collectors of the first and second transistors, and sets the gate voltages of the first to third MOSFETs that respectively form the collector currents of the first to third transistors so that they are equal. Control. The second resistance element and the third resistance element are output from the collector and base combined with the third transistor. The first resistance element and the second resistance element are set to a resistance ratio such that the reference voltage does not have temperature dependence. The base currents of the first and second transistors are formed by the drain current of the fourth MOSFET to which the output voltage of the first differential amplifier circuit is supplied to the gate, and are detected by the fourth MOSFET. A current mirror circuit is provided for increasing the current supplied to the collector of the third transistor in response to the base current.

  The influence of the offset voltage generated in the first to third MOSFETs can be suppressed by the fourth to sixth resistance elements provided on the source side of the first to third MOSFETs. The current mirror circuit increases the current supplied to the collector of the third transistor in response to the base currents of the first and second transistors, thereby suppressing the influence of variations in the current amplification factor in the third transistor. can do.

  FIG. 1 is a circuit diagram showing one embodiment of a reference voltage generating circuit according to the present invention. The reference voltage generating circuit of this embodiment is not particularly limited, but is mounted in a semiconductor integrated circuit device in which a known CMOS circuit having a triple well structure is formed.

  The transistors Q1 to Q3 are NPN bipolar transistors formed using a CMOS circuit having a triple well structure. For example, as in Non-Patent Document 1, a deep N-type well region formed on a P-type substrate is used as a collector, and a P-type well region formed in the deep N-type well region is used as a base. The vertical structure has an N-type region formed in the P-type well region as an emitter.

  When the emitter area of the transistor Q3 is 1 (× 1), the emitter area of the transistor Q1 is formed as large as N times (× N). The bases of the transistors Q1 and Q3 are connected in common. The emitter of the transistor Q3 is supplied with the circuit ground potential (0 V) VSS, and a resistor R1 is provided between the emitter of the transistor Q1 and the reference potential VSS. The currents flowing through the transistors Q1 and Q3 are the same, and a band gap voltage (base-emitter voltage difference between the transistors Q1 and Q3) corresponding to the difference between the emitter current densities of the transistors Q1 and Q3 flows through the resistor R1.

  In order to allow the same current to flow through the transistors Q1 and Q3, differential amplifier circuits A1 and A2 and P-channel MOSFETs QP1 to QP3 are provided. The collector voltage and base voltage of the transistor Q3 are supplied to the positive phase input (+) and the negative phase input (−) of the differential amplifier circuit A1. The output current of the differential amplifier circuit A1 is the base current of the transistors Q1 and Q3. Thereby, the differential amplifier circuit A1 forms base currents of the transistors Q1 and Q3 so that the collector and base of the transistor Q3 have the same potential.

  The collector voltage of the transistor Q1 and the collector voltage of the transistor Q1 are supplied to the positive phase input (+) and the negative phase input (−) of the differential amplifier circuit A2. The output voltage of the differential amplifier circuit A2 is supplied to the gates of the P-channel MOSFETs QP1 to QP3. The drain currents of the P-channel MOSFETs QP1 and QP3 are supplied to the collectors of the transistors Q1 and Q3. As a result, the differential amplifier circuit A2 and the MOSFETs QP1 and QP3 form the gate voltages of the MOSFETs QP1 and QP3 so that the collectors of the transistors Q1 and Q3 have the same potential. The MOSFETs QP1 to QP3 are formed to have the same size, and a constant current corresponding to the band gap voltage flows through the resistor R1, and the differential amplifier circuits A1 and A2 and the P channel MOSFETs QP1 to QP3 correspond to this. The bases, collector voltages and collector currents of the transistors Q1 and Q3 are set to be equal.

  In this embodiment, although not particularly limited, the MOSFET QP4 and the transistor Q4 of the reference voltage generation circuit of FIG. 10 shown in Non-Patent Document 1 are omitted in order to reduce the number of circuit elements and current consumption. In the circuit of FIG. 10, the differential amplifier circuit A1 has the same configuration as that of the transistor Q3, and operates so that the base voltage of the transistor Q4 to which the collector and base are connected and the collector voltage of the transistor Q1 are received and become equal. is doing. Focusing on this, in the embodiment of FIG. 1, the collector current and the base voltage of the transistor Q1 are directly input to the differential amplifier circuit A1, so that the base currents of the transistors Q1 and Q3 are made to coincide with each other. To form.

  A transistor Q2, resistors R2 and R3, and a P-channel MOSFET QP2 are provided for temperature compensation of the constant current formed by the resistor R1, in other words, for temperature compensation of the output reference voltage Vref. The transistor Q2 has a collector and a base connected to each other, and a reference voltage Vref is output from the connection point. The resistor R2 is provided between the emitter of the transistor Q2 and the reference potential VSS. A resistor R3 is provided between the collector and base to which the transistor Q2 is connected and the reference potential VSS. The drain current of the P-channel MOSFET QP2 is supplied to the collector of the transistor Q2. The resistors R2 and R3 are set to a resistance ratio so that the reference voltage Vref does not have temperature dependency in order to compensate the temperature of the reference voltage Vref.

  In the circuit of this embodiment, in order to suppress the fluctuation of the reference voltage Vref due to the offset voltage (V2 to V4 shown in FIG. 4 described later) corresponding to the variation of the threshold voltage in the P channel MOSFETs QP1 to QP3, Resistors R4 to R6 are respectively provided between the voltage VDD.

  FIG. 2 is a circuit diagram showing another embodiment of the reference voltage generating circuit according to the present invention. This embodiment is a reference voltage generating circuit having transistors Q1 to Q3, resistors R1 to R3, differential amplifiers A1 and A2 and P channel MOSFETs QP1 to QP3 having the same configuration as that shown in FIG. P channel MOSFETs QP5 and QP6 and N channel MOSFETs QN1 to QN3 are provided to suppress fluctuations in the reference voltage Vref due to variations in the current amplification factor β.

  In the P-channel MOSFET QP5, the output voltage of the differential amplifier circuit A1 is supplied to the gate, the power supply voltage VDD is applied to the source, and the drain current is supplied to the bases of the transistors Q1 and Q3. As a result, the MOSFET QP5 operates as a detection element for the combined base current flowing through the transistors Q1 and Q3. The P-channel MOSFET QP6 is the same size as the MOSFET QP5, and the P-channel MOSFET QP5 is connected to the gate and the source in common to form a current mirror so that the same current flows. This current is input to a current mirror circuit composed of N-channel MOSFETs QN1 to QN3 provided on the reference potential VSS side.

  That is, the drain current of the P-channel MOSFET QP6 is supplied to the drain of the diode-connected N-channel MOSFET QN1. The N-channel MOSFET QN1 and the N-channel MOSFETs QN2 and QN3 in the form of a current mirror are set to 1/2 the size of the MOSFET QN1 so that half the current of the MOSFET QN1 flows. The drain of the MOSFET QN2 is connected to the collector of the transistor Q1. The drain of the MOSFET QN3 is connected to the collector of the transistor Q3.

  FIG. 3 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. In this embodiment, in the reference voltage generating circuit of FIG. 2, the fluctuation of the reference voltage Vref due to the offset voltage corresponding to the variation of the threshold voltage in the P-channel MOSFETs QP1 to QP3 as in the embodiment of FIG. 1 is suppressed. In addition, resistors R4 to R6 are provided between the source and the power supply voltage VDD, respectively. That is, by combining the embodiment of FIG. 1 and the embodiment of FIG. 2, the influence of the offset voltage on the reference voltage Vref due to the process variation in the MOSFETs QP1 to QP3 and the influence of the process variation of the current amplification factor in the transistors Q1 to Q3, respectively. It is to suppress.

  FIG. 4 is an equivalent circuit diagram for explaining the present invention. This figure shows offset voltages V1 to V4 for verifying process variations of differential elements and process variations of current mirror MOSFETs QP1 to QP3 in the differential amplifier circuit corresponding to the embodiment of FIG.

  FIG. 5 is a characteristic diagram showing the influence of the offset voltages V1 to V4 on the reference voltage Vref. FIG. 5 shows the influence of the offset voltages V1 to V4 on the reference voltage Vref by a computer simulation by the inventor of the present application. As in FIG. 12, the threshold voltages of the MOSFETs QP1 to QP3 are set to target values ( 0 mV), the influence of each offset voltage V1 to V4 on the reference voltage Vref was verified by assuming that it fluctuated in the range of −10 mV to +10 mV. FIG. 5 shows that the threshold voltage variation (offset voltage V2) of the MOSFET QP1 that has the greatest influence on the reference voltage Vref is also greatly suppressed.

This can be explained quantitatively as follows. For example, in FIG. 4, the MOSFET QP2 will be described. When the gate voltage is VG, the offset voltage V3 is VOS, and the resistor R5 provided at the source is generalized as R, the drain current is I _DS. 1 can be expressed as follows, and ∂I _DS / ∂V _OS can be calculated as shown in Equation 2 below. The same applies to the offset voltages V2 and V4 for the other MOSFETs QP1 and QP3.

In the above equation 2, ∂I _DS / ∂V _OS is an equation (≈2 / R) that is inversely proportional to the resistance R without depending on the size ratio W / L of the channel width and channel length of the MOSFET and the offset voltage V _OS. It will appear. Since the drain current I _DS is supplied to the transistor Q2 to form the reference voltage Vref, Equation 2 (∂I _DS / ∂V _OS ) does not depend on the offset voltage V _OS because the reference voltage Vref is the offset voltage V _This means that it can be made unaffected by _OS variations. When the resistance value of the resistor R is increased to some extent, the influence of variation in the resistance R can be reduced. In this configuration, since W / L can be reduced, the circuit is advantageous for low voltage operation.

Incidentally, when there is no resistance as in the circuit of FIG. 10, the drain current I _DS can be expressed by the following equation 3, and ∂I _DS / ∂V _OS is obtained by the following equation 4. Can be expressed as: From Equation 4, the offset voltage dependency of the current is proportional to the size ratio W / L and the offset voltage V _OS . Reducing the size ratio W / L means reducing the amount of fluctuation, but on the other hand, it causes another adverse effect that makes low-voltage operation difficult.

  FIG. 6 is a characteristic diagram of the influence on the reference voltage Vref due to process variations of the current amplification factor β of the transistors Q1 to Q3 corresponding to the embodiment of FIGS. FIG. 6 shows a reference voltage Vref due to a large variation in the range of half (β × 0.5) to twice (β × 2) with respect to the design value (center value) β of the current amplification factor of the transistors Q1 to Q3. This is a result of a computer simulation conducted by the inventor of the present application. From FIG. 6, it can be seen that the fluctuation range due to the variation of the current amplification factor β with respect to the reference voltage Vref is greatly suppressed.

This can be explained qualitatively as follows. In FIG. 2, the base currents I _B1 and I _B3 of the transistors Q1 and Q3 are detected by the MOSFET QP5 and added to the current I _OUT supplied to the transistors Q1 and Q3 via the MOSFETs QP6-QN1-QN2 and QN3. Is done. Therefore, the current I _OUT supplied from the collector of the transistor Q2 corresponds to the collector current I _C1 and the base current I _B1 of the transistor Q1. Accordingly, the collector current I _C2 of the transistor Q2 is equal to the collector current I _C1 of the transistor Q1, and the base current I _B2 of the transistor Q2 can be equal to the base current I _B1 of the transistor Q1. The process variation in the current amplification factor β of these transistors Q1 and Q2 means that the base currents I _B1 and I _B2 can be changed because the current on the collector side is made constant as described above. In this circuit, the collector current and the base current flowing in the transistors Q1 and Q2 are the same regardless of variations in the current amplification factor β, and the amount of change in the collector current of the transistor Q2 when the current amplification factor β varies can be suppressed. Therefore, fluctuations in the reference voltage Vref can be suppressed.

This can be explained quantitatively as follows. For example, in FIG. 2, the drain current of P-channel MOSFETs QP1 to QP3 is I _OUT , the collector current of transistor Q1 is I _C1 , the base current is I _B1 , the collector current of transistor Q2 is I _C2 , and the base current is I and _B2, based, to-emitter voltage and V _bE, the resistor R1 and R _1, the resistor R2 and R _2, the resistor R3 and R _3, the drain current I _OUT may be expressed by the following equation 5 The reference voltage reference voltage Vref can be expressed as in the following equation (6).

In Equation 6, the reference voltage Vref does not depend on the current amplification factor β, and the temperature dependence of V _BE can be canceled by the resistance ratio R ₂ / R ₁ .

Incidentally, in the reference voltage generation circuit of FIG. 10, the current I _OUT supplied from the P-channel MOSFET QP2 to the transistor Q2 can be expressed by the following equation 7, and the reference voltage Vref is expressed by the following equation 8. Can do. In the above formulas 7 and 8, it can be seen that both depend on the current amplification factor β.

To explain qualitatively, since the base current I _B1 is supplied from the differential amplifier circuit A1 to the transistor Q1, the collector current I _C1 is supplied as it is to the collector side of the transistor Q2 as the current I _OUT through the P-channel MOSFET QP2. However, in the transistor Q2, the collector and the base are connected, and the current I _OUT supplied from the P-channel MOSFET QP2 is distributed and flows like the collector current I _C2 and the base current I _B2 of the transistor Q2. Become. The distribution ratio between the currents I _C2 and I _B2 is determined by the current amplification factor β, and the collector current I _C2 varies. As a result, the reference voltage Vref varies as described above.

  FIG. 7 is an explanatory diagram of the present invention. 7 compares the worst fluctuation amount due to the offset voltage generated by the process variation of the P-channel MOSFETs QP1 to QP3 in the reference voltage generation circuit of FIG. 10 and FIG. 1, and FIG. The worst fluctuation amount in the reference voltage generating circuit is shown, and the fluctuation amount of the reference voltage Vref becomes about 120 mV. On the other hand, FIG. 7B shows the worst fluctuation amount in the reference voltage circuit of FIG. 1, and the fluctuation amount of the reference voltage Vref is suppressed to 20 mV or less, which is an improvement of 85% compared to the circuit of FIG. it can.

  FIG. 8 shows another explanatory view of the present invention. FIG. 8 is a comparison of worst fluctuation amounts due to variations in the current amplification factors β of the transistors Q1 to Q3 in the reference voltage generation circuit of FIG. 10 and FIG. 1, and FIG. The worst fluctuation amount in the voltage generation circuit is shown, and the fluctuation amount of the reference voltage Vref becomes about 75 mV. On the other hand, FIG. 8B shows the worst fluctuation amount in the reference voltage circuit of FIG. 2, and the fluctuation amount of the reference voltage Vref is suppressed to about 3 mV, which is an improvement of about 97% compared to the circuit of FIG. Can do.

  In the embodiment circuit of FIG. 3, both the offset voltage of the MOSFETs QP1 to QP3 and the variation of the current amplification factor β of the transistors Q1 to Q3 are improved as described above. That is, in the circuit of FIG. 10, 120 mV varies due to variations in the offset voltage of MOSFETs QP1 to QP3, and 70 mV varies due to variations in the current amplification factor β. Therefore, it is necessary to consider variations in the reference voltage Vref as much as 190 mV. On the other hand, in the embodiment circuit of FIG. 3, since both are only about 20 mV, it is possible to obtain a reference voltage generation circuit in which the influence of the process variation of the elements is greatly suppressed.

FIG. 9 is a circuit diagram showing still another embodiment of the reference voltage generating circuit according to the present invention. This embodiment is a modification of the embodiment circuit of FIG. 3, and the drain currents of the P-channel MOSFET QP5 for detecting the base currents of the transistors Q1 and Q3 and the P-channel MOSFET QP6 in the form of a current mirror are directly applied to the transistor Q2. It is supplied to the collector and base connection points. Since the P-channel MOSFET QP5 allows the base currents of the two transistors Q1 and Q3 to flow, the size of the P-channel MOSFET QP6 is halved compared to the size of the MOSFET QP5 in the same manner as in the embodiment of FIG. The collector current I _C1 and the base current I _B1 of the transistor Q1 can be supplied to the collector and base connection point of the transistor Q2. Thus, as in the embodiment of FIG. 3, the collector current I _C2 of the transistor Q2 is equal to the collector current I _C1 of the transistor Q1, and the base current I _B2 of the transistor Q2 is equal to the base current I _B1 of the transistor Q1. it can.

  In this embodiment, since the P channel MOSFETs QP5 and QP6 have the same circuit configuration as the MOSFETs QP1 to QP3, the offset voltage in the P channel MOSFETs QP5 and QP6 is considered to affect the reference voltage Vref. Therefore, in order to suppress this, resistors R7 and R8 similar to the resistors R4 to R6 provided on the source side of the P channel MOSFETs QP1 to QP3 are also provided on the source side of the P channel MOSFETs QP5 and QP6. In this embodiment, the number of current paths is reduced as compared with the embodiment of FIG. 3, leading to low power consumption and a small area.

  The semiconductor integrated circuit device on which the reference voltage generating circuit is formed is preferably composed of a CMOS circuit. In this case, since it is possible to make the circuit unaffected by the process variation of the element, the circuit is effective for the SOC mounted memory and the microprocessor. This is because these semiconductor integrated circuit devices have a high need for a low voltage and require a highly accurate reference voltage. In addition, since redesign corresponding to different β is not required depending on the process, it becomes an effective technology when used for a hardware IP (Intellectual Propety) core. Furthermore, products that are difficult to trim, such as processors, are effective because the amount of variation in the reference voltage due to variations in the MOSFET threshold voltage and current amplification factor β is small, and it is not necessary to prepare a trimming circuit. .

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, the transistors Q1 to Q3 can be variously modified such as a transistor using a lateral structure bipolar transistor in addition to a semiconductor region formed by a CMOS process having a triple well structure as described above. When the negative voltage is used as the power supply voltage, the conductivity type of the transistor or MOSFET may be reversed. Since the resistors R4 to R8 and the like need to have relatively high resistance values as described above, a polysilicon resistor or the like can be used.

  The present invention can be widely used as a reference voltage generating circuit mounted on a semiconductor integrated circuit device composed of MOSFETs, has a high need for lowering the voltage, and also requires a highly accurate reference voltage and a microprocessor mounted with an SOC. It is effective for use in hardware IP core products, various semiconductor integrated circuit devices that are difficult to trim.

1 is a circuit diagram of one embodiment of a reference voltage generating circuit according to the present invention. FIG. It is a circuit diagram of another embodiment of the reference voltage generating circuit according to the present invention. FIG. 6 is a circuit diagram of still another embodiment of the reference voltage generating circuit according to the present invention. It is an equivalent circuit diagram for explaining the present invention. FIG. 2 is a characteristic diagram illustrating an influence on a reference voltage due to variations in offset voltage of the MOSFET of FIG. 1. FIG. 3 is a characteristic diagram illustrating an influence on a reference voltage due to variations in current amplification factors of the transistors in FIG. 2. It is explanatory drawing of this invention. It is another explanatory drawing of this invention. FIG. 6 is a circuit diagram of still another embodiment of the reference voltage generating circuit according to the present invention. It is a circuit diagram of a conventional reference voltage generation circuit. It is the equivalent circuit of FIG. 10 examined by this inventor. FIG. 11 is a characteristic diagram illustrating an influence on a reference voltage due to variations in offset voltage of the MOSFET of FIG. 10. FIG. 11 is a characteristic diagram illustrating the influence on the reference voltage due to variations in the current amplification factor of the transistor of FIG. 10.

Explanation of symbols

  A1, A2 ... differential amplifier circuit, Q1-Q4 ... transistor, QP1-QP6 ... P-channel MOSFET, QN1-QN3 ... N-channel MOSFET, R1-R8 ... resistor,

Claims (10)

A reference voltage generation circuit;
The reference voltage generation circuit is
A first transistor;
A second transistor configured to have a larger emitter area than the first transistor;
A first differential amplifier circuit for forming a base current of the first transistor and the second transistor so that a base voltage and a collector voltage of the first transistor are equal;
A first resistance element provided between the emitter of the second transistor and a reference potential, to which a silicon bandgap voltage generated corresponding to the emitter current density of the first transistor and the second transistor is applied;
A collector and a base are coupled, a second resistance element is provided between the emitter and the reference potential, and a third resistance element is provided between the coupled collector and base and the reference potential. A transistor,
A second differential amplifier circuit receiving a voltage of the collector of the first transistor and the collector of the second transistor;
First to third MOSFETs that are supplied to the gate of the output voltage of the second differential amplifier circuit and form collector currents of the first to third transistors, respectively.
The first resistance element and the second resistance element are set to a resistance ratio such that a reference voltage output from a collector and a base coupled to the third transistor does not have temperature dependence.
A semiconductor integrated circuit device having fourth to sixth resistance elements on the source side of the first to third MOSFETs, respectively. In claim 1,
The semiconductor integrated circuit device, wherein the fourth to sixth resistance elements have a large resistance value that is less affected by variations of the fourth to sixth resistance elements. In claim 1 or 2,
The first differential amplifier circuit receives a collector voltage and a base voltage of the first transistor and supplies an output current to the bases of the first transistor and the second transistor. In any of claims 1 to 3,
The first to third transistors have a deep N-type well region formed on a P-type substrate as a collector and a P-type well region formed in the deep N-type well region as a base. The N-type region formed in the P-type well region is used as an emitter,
The first to third MOSFETs are P-channel MOSFETs in which a P-type source and drain are formed in an N-type well region formed on the P-type substrate or the deep N-type well region. Integrated circuit device. A reference voltage generation circuit;
The reference voltage generation circuit is
A first transistor;
A second transistor having an emitter area larger than that of the first transistor;
A first differential amplifier circuit for forming base currents of the first and second transistors so that the base and collector voltages of the first transistor are equal;
A first resistance element provided between the emitter of the second transistor and a reference potential, to which a silicon bandgap voltage generated corresponding to the emitter current density of the first transistor and the second transistor is applied;
A collector and a base are coupled, a second resistance element is provided between the emitter and the reference potential, and a third resistance element is provided between the coupled collector and base and the reference potential. A transistor,
A second differential amplifier circuit receiving a voltage of the collector of the first transistor and the collector of the second transistor;
First to third MOSFETs that form currents such that the output voltage of the second differential amplifier circuit is supplied to the gate and the currents supplied to the collectors of the first to third transistors are equal to each other;
The first resistance element and the second resistance element are set to a resistance ratio such that a reference voltage formed from a collector collector and a base combined with the third transistor does not have temperature dependence,
The base currents of the first and second transistors are formed by the drain current of the fourth MOSFET in which the output voltage of the first differential amplifier circuit is supplied to the gate,
A semiconductor integrated circuit device further comprising a current mirror circuit for increasing a current supplied to a collector of the third transistor corresponding to the base currents of the first and second transistors detected by the fourth MOSFET. In claim 5,
The current mirror circuit is
A fifth MOSFET in which the fourth MOSFET, the gate and the source are connected in common, and a half current of the fourth MOSFET flows;
A semiconductor integrated circuit device having sixth to eighth MOSFETs that add a base current to the drain currents of the first and second MOSFETs using the current flowing through the fifth MOSFET as an input current. In claim 5,
The current mirror circuit is
The fourth MOSFET, the gate and the source are connected in common, and has a fifth MOSFET that flows a half of the current of the fourth MOSFET,
A semiconductor integrated circuit device in which a drain current of the fifth MOSFET is supplied to a collector of the third transistor. In claim 6 or 7,
A semiconductor integrated circuit device having fourth to sixth resistance elements on the source side of the first to third MOSFETs, respectively. In claim 8,
The semiconductor integrated circuit device, wherein the fourth to sixth resistance elements have a large resistance value that is less affected by variations of the fourth to sixth resistance elements. In any of claims 6 to 9,
The first to third transistors have a deep N-type well region formed on a P-type substrate as a collector and a P-type well region formed in the deep N-type well region as a base. The N-type region formed in the P-type well region is used as an emitter,
The first to fifth MOSFETs are P-channel MOSFETs in which a P-type source and drain are formed in an N-type well region formed on the P-type substrate or the deep N-type well region. Integrated circuit device.

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