JP2007299116A - Image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate processing overhead due to the notification of an interrupting request for of DMA transfer accompanying the reading and writing processing of image data for every image processing. <P>SOLUTION: An image processor 101 stores scan data for one page in a page memory. A DMAC control circuit 104b of a bus bridge 104 performs parameter setting to a DMAC 105a of an image processor 105. The DMAC 105a of the image processor 105 transfers data for one band from a page memory 106. The image processor 105 supplies an interrupting request to a bus bridge 104 each time each stream ends. A DMAC control circuit 104b of the bus bridge 104 controls a DMAC 105a of the image processing processor 105, and issues an instruction to transfer the next band data or stream, and transfers interruption to a host CPU 101 side only when one page processing completes. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an image processing apparatus, and intends to efficiently perform DMA transfer when image processing is repeatedly performed on image data.

  FIG. 1 shows a conventional image processing apparatus. In this figure, an image processing apparatus 10 includes a host CPU 11 and an image processing processor 12. The host CPU 11 performs general data processing, and the image processor 12 performs data processing dedicated to image processing. The host CPU 11 and the image processor 12 are connected to an expansion bus (network) 13 and can transfer data via the expansion bus 13 by DMA. The host CPU 11 uses the page memory 14, and the image processor 12 uses the buffer memory 15.

  The image processor 12 writes the image data to be processed into the buffer memory 15 and performs a plurality of image processing by, for example, pipeline processing. First, the image data written in the buffer memory 15 is read, the first image processing is performed, and the processing result is written in the buffer memory 15. Thereafter, the processing result of the first image processing is read from the buffer memory 15 and the second image processing is performed. Thereafter, the processing result of the last image processing is written in the buffer memory 15 in the same manner, and then output. This processing is typically performed in band units, but may be performed in page units. The buffer memory 15 is typically composed of a DDR memory.

  By the way, whenever the image processor 12 reads / writes data from / to the buffer memory 15 by DMA, it is necessary to generate an interrupt signal and notify the host CPU 11 to perform DMA setting. There was overhead.

  The reason why the image processor 12 generates an interrupt signal to the host CPU 11 will be described next. The image processor 12 has a built-in DMAC, and an intermediate stream on the buffer memory can be freely read and written by this DMAC. However, this address control is complicated in band unit processing, and a general-purpose CPU used as the host CPU 11 is easier to program than processing by a dedicated processor for image processing (for example, a SIMD type processor). Therefore, the host CPU 11 sets the intermediate stream address calculated in response to the interrupt signal of the image processing processor in the DMAC of the image processing processor.

  In addition, the reason why the image processor 12 generates an interrupt signal to the host CPU 11 is to input / output data to / from the host CPU 11 when the image processing in the image processor 12 is completed.

  Note that there is Patent Document 1 as a prior art related to the present invention.

  In Patent Document 1, when an expansion PCI bus is connected to the main body PCI bus via a bus adapter, and an interrupt signal is generated from the input / output device connected to the expansion PCI bus, the input signal from which the bus adapter receives the interrupt signal It has been proposed to notify the CPU whether or not the error has occurred.

However, as in this proposal, the probability that an interrupt signal is generated to the host CPU each time the system is expanded is nothing but a decrease in the performance of the entire system.
Japanese Patent Laid-Open No. 10-21182

  The present invention has been made in consideration of the above circumstances, and eliminates the processing overhead of the host CPU due to the notification of an interrupt signal at the time of DMA transfer accompanying the read / write process of image data for each of a plurality of image processes. It is aimed. In other words, the object is to improve the performance of the entire system by reducing the number of interrupts to the host CPU and generating only the really necessary interrupts.

  According to this invention, in order to achieve the above-mentioned object, the configuration as described in the claims is adopted. Here, prior to describing the invention in detail, supplementary explanations of the claims will be given.

  That is, according to one aspect of the present invention, in order to achieve the above object, an image processing apparatus includes: a first bus; a host processor with a DMAC (DMA controller) connected to the first bus ( A first image memory connected to the first bus; a second bus; an image processor with a DMAC connected to the second bus; and the second CPU. A second image memory connected to the bus; a bus bridge connecting the first bus and the second bus; and the image processor reads image data from the second image memory The pipeline processing is performed by DMA transfer to perform image processing and the processing result is written to the second image memory, and the bus bridge allocates the DMA transfer for the pipeline processing. By decoding only request performs setting of the DMAC of the image processor, and the interrupt request to not notified to the host processor side.

  In this configuration, an interrupt request is not notified to the host processor for each DMA transfer of each stream in pipeline processing, and the overhead of the host processor is reduced.

  In this configuration, typically, the image data of the first image memory is transferred as image processing target image data to the second image memory and subjected to pipeline processing.

  Further, image data generated by scanning by the image reading apparatus may be transferred as image processing target image data from the image reading apparatus to the second image memory.

  The bus bridge includes, for example, a decoding unit that decodes an interrupt request from the image processing processor, and the decoding unit receives a DMAC control unit that receives a decoding result from the decoding unit. The DMAC controller prohibits the interrupt request for the DMA transfer to be notified to the host processor side, and the DMAC control means determines the DMAC of the image processor based on the interrupt request for the DMA transfer of the pipeline processing. Set up.

  Typically, the host processor is notified of an interrupt request for DMA transfer of page unit image data input to the image processor side or page unit image data output from the image processor side. To do. Further, an interrupt request may be notified to the host processor in order to perform DMA transfer of band-unit image data input to the image processor or band-unit image data output from the image processor. Good.

  The above and other aspects of the invention are set forth in the appended claims and will be described in detail using the following examples and the like.

  According to the present invention, an interrupt request is not notified to the host processor for each DMA transfer of each stream in pipeline processing, and the overhead of the host processor is reduced. That is, the above-described bus bridge generates an interrupt related to data input / output between the host CPU and the image processor from the image processor to the host CPU, but an interrupt related to DMA transfer only on the image processor side is not notified to the host by the bridge. .

  Examples of the present invention will be described below.

  FIG. 2 shows the overall configuration of an image processing apparatus according to an embodiment of the present invention. In FIG. 2, the image processing apparatus 100 according to the embodiment includes a host CPU 101, a page memory 102 for the host CPU 101, a bus 103, and a bus bridge. 104, an image processor 105, and a page memory 106 for the image processor. The host CPU 101 and the image processor 106 incorporate DMACs 101a and 105a, respectively. The bus bridge 104 is for coupling the bus 103 to the bus on the image processing side, and further includes a decoder 104a and a DMAC control circuit 104b.

  The decoder 104a notifies the host CPU 101 of an interrupt request when image processing for one page is completed, and the interrupt request when processing for one band is completed and the interrupt request when processing of each stream is completed are the host. The CPU 101 is not notified. Also, an interrupt request when processing for one band is completed and an interrupt request when processing of each stream is completed are decoded and supplied to the DMAC control circuit 104b. The DMAC control circuit 104b sets the DMAC 105a of the image processor 105 based on the decoding result.

  Next, the operation of the embodiment will be described.

  Note that the image data to be processed is scan data (1) from the image reading apparatus and image data (2) from the page memory 102 on the host CPU 101 side, and this is the page memory on the image processing processor 105 side by DMA transfer. 106 is written.

  Hereinafter, scan data processing will be described, but image data on the host CPU 101 side is similarly processed.

[Step S1]: The image processor 101 stores one page of scan data in the page memory.
[Step S2]: The DMAC control circuit 104b of the bus bridge 104 sets parameters in the DMAC 105a of the image processor 105.
[Step S3]: The DMAC 105a of the image processor 105 transfers data for one band from the page memory 106.
[Step S4]: The image processor 105 starts processing, and supplies an interrupt request to the bus bridge 104 every time each stream (flow of image data) ends.
[Step S5]: The bus bridge 104 decodes the interrupt request and transfers the interrupt to the host CPU 101 side only when one page processing is completed.
[Step S6] When the processing for one page has not been completed and when it is recognized that the end of one band or the processing of each stream has been completed, the DMAC control circuit 104b of the bus bridge 104 displays the image processor 105. The DMAC 105a is controlled to issue an instruction to transfer the next band data or stream.

  FIG. 3 schematically shows a flow of a series of processes. As shown in FIG. 3, image data in units of pages is input, and the image processor 105 performs pipeline processing for each band, and processes each stream in the order of processing A, B, and C (processing is A, B, and B). , C is shown, but the number is not limited to this). When the processing is completed for all the bands and processed image data for one page is generated, for example, an interrupt request is notified to the host CPU 101, and the image data for one page is output by DMA.

  By doing so, as shown in FIG. 4, an interrupt request for DMA of each stream passes through the bus bridge 104, and when the last one page of data is output, it passes through the bus bridge 104 to the host. The CPU is notified and the image data for one page is DMA-transferred to the host CPU 101 side.

  Conventionally, as shown in FIG. 5, an interrupt request is supplied to the host CPU for each stream, which is an overhead of the CPU.

  In this way, by decoding and processing the interrupt with the bus bridge (hardware), it is not necessary for the host CPU to process the interrupt, the load is reduced, and other applications can be processed accordingly. Also, the bus bridge (hardware) performs interrupt processing, so that interrupt processing is shortened and productivity is improved. It is particularly suitable for overlap processing and rotation processing.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the invention. For example, in the above example, when processing of image data for one page is completed, an interrupt request is notified to the host CPU to perform DMA transfer, but when processing of image data for one band is completed. Alternatively, an interrupt request may be notified to the host CPU. Of course, one band may be supplied to the image processor as a processing unit. The bus bridge may be a dedicated circuit (= hardware) or a circuit incorporating a CPU core. Furthermore, a configuration without a host CPU, that is, a stand-alone image processor system can be configured by this bus bridge. An image processing apparatus includes: a first bus; a first image memory connected to the first bus; a second bus; an image processor with a DMAC connected to the second bus. A second image memory connected to the second bus; a bus bridge connecting the first bus and the second bus; and the image processor includes the second image memory Pipeline processing that reads image data from the image memory, performs image processing, and writes the processing result to the second image memory is performed by DMA transfer; the bus bridge issues an interrupt request for DMA transfer of the pipeline processing May be decoded to set the DMAC of the image processor.

It is a block diagram explaining the conventional image processing apparatus. 1 is a block diagram showing an entire image processing apparatus according to an embodiment of the present invention. It is a figure explaining the flow of processing of the above-mentioned example. It is a figure explaining the range where the interruption request | requirement reaches of the above-mentioned Example. It is a figure explaining the range which the interruption request | requirement reaches of a prior art example.

Explanation of symbols

10 Image processing apparatus 11 Host CPU
12 image processor 13 expansion bus 14 page memory 15 buffer memory 100 image processing apparatus 101 host CPU
102 page memory 103 bus 104 bus bridge 104a decoder 104b DMAC control circuit 105 image processor 106 page memory

Claims (7)

The first bus,
A host processor with DMAC connected to the first bus;
A first image memory connected to the first bus;
A second bus,
An image processor with DMAC connected to the second bus;
A second image memory connected to the second bus;
A bus bridge connecting the first bus and the second bus;
The image processor reads out image data from the second image memory, performs image processing, performs pipeline processing to write the processing result in the second image memory by DMA transfer,
The bus bridge decodes the interrupt request for the DMA transfer of the pipeline processing, sets the DMAC of the image processor, and does not notify the host processor of the interrupt request. A featured image processing apparatus.   The image processing apparatus according to claim 1, wherein the image data in the first image memory is transferred to the second image memory as image data to be processed.   The image processing apparatus according to claim 1, wherein the image data generated by scanning by the image reading apparatus is transferred from the image reading apparatus to the second image memory as image data to be processed.   The bus bridge includes a decoding unit that decodes an interrupt request from the image processor, and the decoding unit receives a DMAC control unit that receives a decoding result from the decoding unit, and the decoding unit performs DMA transfer of the pipeline processing. The DMAC control means sets the DMAC of the image processor based on the interrupt request for DMA transfer of the pipeline processing. Item 4. The image processing device according to any one of Items 1 to 3.   5. An interrupt request is notified to the host processor for DMA transfer of page unit image data input to the image processor side or page unit image data output from the image processor side. The image processing apparatus according to any one of the above.   5. An interrupt request is notified to the host processor for DMA transfer of band-unit image data input to the image processor or band-unit image data output from the image processor. The image processing apparatus according to any one of the above. The first bus,
A first image memory connected to the first bus;
A second bus,
An image processor with DMAC connected to the second bus;
A second image memory connected to the second bus;
A bus bridge connecting the first bus and the second bus;
The image processor reads out image data from the second image memory, performs image processing, performs pipeline processing to write the processing result in the second image memory by DMA transfer,
An image processing apparatus, wherein the bus bridge decodes an interrupt request for DMA transfer of the pipeline processing and sets the DMAC of the image processing processor.