丄幻2623 ?年Qb (‘日修正替巧] 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種資料處理系統，且特 種具有多條匯流排之資料處理系統及方法。'1有關於一 【先前技術】 磁碟陣列（Disk Array)的技術可以用來增加 速度以及防止資料因磁碟的故障而遺失。^ ’碟的存取 個磁碟纽成—個陣列，當作單_磁碟一碟陣列是把多 列中的資料係以分段(Striping)的方式來二使用。磁碟陣 :中。當存取資料時，陣列之中的相關磁碟的磁碟 大幅降低資料的存取時間。 〃 起動作， 磁碟陣列所利用的不同的技術 陣列等級(漏Leve丨），如RAID G =社磁碟多重 架構中，由於資料树段 :;車列中的每-個磁碟都可以獨立動作==: 土=同時進行讀寫，從而提高資料存取的效率。另外碟 :某些獨立磁碟多重陣列等級中，如繼5架構中除 :育料可以利用分段的方式來儲存在不同的磁碟之中，還 需要對相應資料進行處以獲得相應之同位#訊，並儲存 至磁碟陣财之—特定存儲區域中。當儲存-資料分段之 磁碟故障時，可以透過其他資料分段與此同位資訊來回復 故障磁碟中之資料分段。 在習知之應用RAID 5架構之精簡指令集運算(RISC) 0608-A40830TWF1 5 1332623 系統中，通常是通過軟体程式來對資料區塊進行各種運算 處理，例如互斥或運算處理，這無疑增加了 RISC系統之 中央處理單元的負擔，影響整個系統之效能。另一方面， 大多數適用於RISC系統之匯流排，例如進階高效能匯流 排，具有相對較小的帶寬而無法以較快的速度傳輸大量的 資料。 【發明内容】 • 本發明實施例之資料處理系統，包括：至少一寫入匯 流排；至少一讀取匯流排；一處理單元，產生一組態資料； 一存取控制器；以及一資料加速單元，與該寫入匯流排及 該讀取匯流排耦接，用以依據該組態資料致使該讀取匯流 排至一儲存裝置讀取至少一資料區塊，處理該資料區塊， 並將一處理后之結果藉該寫入匯流排傳輸至該儲存裝置。 本發明實施例之資料處理系統，包括一第一匯流排、 一第二匯流排、一第三匯流排、一處理單元，用以產生一 • 組態資料、一存取控制器、以及一資料加速單元。資料加 速單元包括一暫存器與一資料處理單元。暫存器透過第一 匯流排接收組態資料。資料處理單元透過第二匯流排與第 三匯流排致使存取控制器依據組態資料由一儲存裝置讀取 一第一資料區塊與一第二資料區塊，將該第一資料區塊與 第二資料區塊進行處理，從而產生一結果，並透過該第一 匯流排致使該存取控制器依據該組態資料將該結果寫入至 該儲存裝置。 0608-A40830TWF1 6 1332623 p年1月ίί日修正替換黃j • 本發明實施例之資料處理之方法，適用於一具有複數 匯流排之資料處理系統，包括：驅使一第一讀取匯流排與 一第二讀取匯流排至一儲存裝置中並行讀取複數資料區 塊；處理該複數資料區塊以得到一處理后之結果；以及將 該處理后之結果藉由一寫入匯流排寫入該儲存裝置。 為使本發明之上述目的、特徵和優點能更明顯易懂， 下文特舉實施例，並配合所附圖示，詳細說明如下。 • 【實施方式】 本發明提供一種資料處理系統，其適用於精簡指令集 運算(RISC)系統平台，且提供有一資料加速單元，用於讀 取資料區塊並對資料區塊進行相應的處理，從而使得處理 早元不需要參與資料區塊的處理。 在本發明中，資料處理系統包括複數個匯流排，且透 過這些匯流排對於儲存裝置進行讀寫作業。其中，資料處 理系統對於儲存裝置的讀取與寫入操作係各自獨立的。換 鲁 言之，讀取操作係透過至少一讀取匯流排，而寫入操作係 透過至少一個獨立於讀取匯流排之寫入匯流排。 第1圖顯示依據本發明實施例之資料處理系統。在此 實施例中，資料處理系統包括兩個匯流排，其分別用於資 料之讀取操作與寫入操作。 依據本發明實施例之資料處理系統200包括一第一匯 流排210與一第二匯流排220、一中央處理單元230、一資 料加速單元240、一存取控制器250、以及至少一儲存裝置 0608-A40830TWF1 7 ^32623 月K日修正替換頁 260 ’如SDRAM、DDR、DDRII。在本實施例中第一匯 流排210與第二匯流排220可以是適用於Risc平臺之進 階高效能匯流排，但不限定於此。中央處理單元23=決定 資料處理所需的組態資料。於本實施例中，料可以 為一存儲於儲存裝置之摇述符列表之基址（ baseaddress)，透過該描述符基址資訊可獲得複數已存儲 於儲存裝置細内之描述符。每-描述符包括，但不限於 至少-資料區塊於儲存裝置26”的源位址（― memory block address )、將資料區塊處理後所得到之纟士果 =儲存至儲存裝置26G中的位址（即目標位址，編&論 a dress)、對相應之資料區塊進行何種處理以及 符之位址。 資料加速單元240包括一從動(slave)匯流排介面 ϋ、人一第一主動(Μ_Γ)匯流排介*⑽、一第二主動匯 =排以243、與—資料處理單元冰。其中，從動匯流排 "面冰與第一主動匯流排介面242輕接至第一匯流排 =0’第二主動匯流排介面243輕接至第二匯流排⑽。注 意的是，在進階高效能匯流排(AHB)系統中，每一主機可 以是主動端或是從動端。進階高魏統的定義與 主動端及從動端的操作為本領域普通知識麵熟知，其相 關細節在此省略。從動匯流排介面241中具有一暫ς器 245,用以透過第—匯流排21()由中央處理單/元聊接收: 儲存組態資料。 資料處理單元244包括-直接記憶體存取（dma)控 0608-A40830TWF1 8 月修止替換頁 月修止替換頁丄 2 2623 年 Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1About [Prior Art] Disk Array technology can be used to increase the speed and prevent data from being lost due to disk failure. ^ 'Disk access to a disk into an array, as Single-disk array is to use the data in multiple columns in striping mode. Disk array: Medium. When accessing data, the disk of the relevant disk in the array is large. Reduce the access time of the data. 〃 Action, the different technology array levels used by the disk array (leak Leve丨), such as RAID G = social disk multiple architecture, due to the data tree segment:; - A disk can be independently operated ==: Soil = simultaneous reading and writing, thereby improving the efficiency of data access. In addition, some independent disk multiple array levels, such as the following 5 architecture: Segmented way to store on different disks In the middle, the corresponding data needs to be obtained to obtain the corresponding co-located information, and stored in the specific storage area of the disk array. When the storage-data segmentation disk fails, the data can be segmented by other data. The same information to reply to the data segmentation in the failed disk. In the conventional application of the RAID 5 architecture reduced instruction set operation (RISC) 0608-A40830TWF1 5 1332623 system, usually through the software program to perform various operations on the data block For example, mutual exclusion or arithmetic processing, which undoubtedly increases the burden on the central processing unit of the RISC system and affects the performance of the entire system. On the other hand, most bus bars suitable for RISC systems, such as advanced high-performance busbars, have The data processing system of the embodiment of the present invention includes: at least one write bus; at least one read bus; and a processing unit. Generating a configuration data; an access controller; and a data acceleration unit, the write bus and the read bus Connecting, according to the configuration data, causing the read bus to a storage device to read at least one data block, processing the data block, and transmitting a processed result to the storage by the write bus The data processing system of the embodiment of the present invention includes a first bus bar, a second bus bar, a third bus bar, and a processing unit for generating a configuration data, an access controller, and a data acceleration unit includes a register and a data processing unit. The register receives configuration data through the first bus. The data processing unit causes the access controller to pass through the second bus and the third bus. Reading a first data block and a second data block by a storage device according to the configuration data, processing the first data block and the second data block, thereby generating a result, and transmitting the first The bus bar causes the access controller to write the result to the storage device based on the configuration data. 0608-A40830TWF1 6 1332623 p january ίί 日 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改 改The second read bus is read into a storage device to read the plurality of data blocks in parallel; the complex data block is processed to obtain a processed result; and the processed result is written by the write bus Storage device. The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] The present invention provides a data processing system suitable for a reduced instruction set computing (RISC) system platform, and provides a data acceleration unit for reading a data block and performing corresponding processing on the data block. Therefore, the processing of the early element does not need to participate in the processing of the data block. In the present invention, the data processing system includes a plurality of bus bars through which the reading and writing operations are performed on the storage device. Among them, the data processing system is independent of the reading and writing operations of the storage device. In other words, the read operation is through at least one read bus, and the write operation is through at least one write bus independent of the read bus. Figure 1 shows a data processing system in accordance with an embodiment of the present invention. In this embodiment, the data processing system includes two bus bars for reading and writing operations of the data, respectively. The data processing system 200 according to the embodiment of the present invention includes a first bus bar 210 and a second bus bar 220, a central processing unit 230, a data acceleration unit 240, an access controller 250, and at least one storage device 0608. -A40830TWF1 7 ^32623 Month K Day Correction Replacement Page 260 'SDRAM, DDR, DDRII. In the present embodiment, the first bus bar 210 and the second bus bar 220 may be advanced high-performance bus bars suitable for the Risc platform, but are not limited thereto. The central processing unit 23 = determines the configuration data required for data processing. In this embodiment, the material may be a base address stored in the address list of the storage device, and the descriptor base address information may be used to obtain a plurality of descriptors stored in the storage device. Each descriptor includes, but is not limited to, a source block ("memory block address" of the data block 26", a gentleman's fruit obtained after processing the data block, and is stored in the storage device 26G. Address (ie, target address, edit & a dress), what kind of processing is performed on the corresponding data block, and the address of the symbol. The data acceleration unit 240 includes a slave bus interface, and a person The first active (Μ _ Γ) bus 介 * (10), a second active sink = 243, and - data processing unit ice, wherein the driven bus " face ice and the first active bus interface 242 are lightly connected to The first bus bar =0' the second active bus bar interface 243 is lightly connected to the second bus bar (10). Note that in the advanced high efficiency bus bar (AHB) system, each host can be the active end or the slave The definition of the advanced Gao Wei system and the operation of the active end and the slave end are well known in the art, and the related details are omitted here. The slave bus interface 241 has a buffer 245 for transmitting The first - bus bar 21 () is received by the central processing unit / yuan chat: storage configuration . Data processing unit 244 comprises a feed - direct memory access (DMA) controller, August 0608-A40830TWF1 modifications are to replace the page replacement sheet dated modifications are to
第二主動匯流排介面243由第 DMA控制器2441通過接 獲得描述符基址，從而透過 一匯流排220致使存取控制 器250依據描述符基址由儲存裝置耀讀取至少一描述 符。其後，圓A㈣器2441對描述符進行解碼以獲取將 要讀取之資料區塊之位址、對f料進行何種處理以及目標 位址’並透過第二主動匯流排介φ 243自第二匯流排22〇 致使存取控制器250依據資料塊之位址由儲存裝置26〇讀 取相應之資料區塊。處理模組2442隨後依據描述符資訊對 DMA控制|§ 2441讀取之一個或複數資料區塊進行處理， 如互斥或(XOR)運算處理、比較運算處理或是無零判斷處 理’從而得到處理後之結果。f要注意岐，只有對兩個 或兩個以上資料塊方可進行互斥或運算處理，因而本實施 例之處理模組2442可設置一資料暫存器，在接受一定數量 之資料區塊後再對該等資料區塊進行互斥或運算處理並輪 出一處理後之結果至DMA控制器2441。之後，DMA控制 器2441透過第一主動匯流排介面242由第一匯流排21〇 致使存取控制器250依據描述符中之目標位址將處理後之 結果寫入至儲存裝置260中。 在一些對於獨立磁碟多重陣列存取之資料處理系統之 實施例中’由於系統中讀取操作的需求大於寫入操作，因 此’一些相關的周邊裝置可以耦接至第一匯流排21〇中， 使得第一匯流排220的頻寬可以使用於資料之讀取操作。 第2圖顯示依據本發明實施例之資料處理方法。 0608-A40830TWF1 1332623 正替換ϋ 月丨(a修The second active bus interface 243 is coupled to the descriptor base by the first DMA controller 2441, such that the access controller 250 causes the access controller 250 to read at least one descriptor from the storage device based on the descriptor base. Thereafter, the circle A (four) device 2441 decodes the descriptor to obtain the address of the data block to be read, what kind of processing is performed on the f material, and the target address is transmitted through the second active bus φ 243 from the second The bus bar 22 causes the access controller 250 to read the corresponding data block from the storage device 26 based on the address of the data block. The processing module 2442 then processes one or multiple data blocks read by the DMA control |§ 2441 according to the descriptor information, such as mutual exclusion or (XOR) operation processing, comparison operation processing, or zero-free determination processing, thereby being processed. After the result. It should be noted that only two or more data blocks can be mutually exclusive or processed. Therefore, the processing module 2442 of the embodiment can be configured with a data temporary register, after accepting a certain number of data blocks. The data blocks are mutually exclusive or arithmetically processed and a processed result is rotated to the DMA controller 2441. Thereafter, the DMA controller 2441 is caused by the first bus bar interface 242 through the first bus bar interface 242 to cause the access controller 250 to write the processed result to the storage device 260 according to the target address in the descriptor. In some embodiments of a data processing system for multiple disk multiple array accesses, 'since the need for read operations in the system is greater than the write operation, some associated peripheral devices may be coupled to the first bus bar 21〇. The bandwidth of the first bus bar 220 can be used for data reading operations. Figure 2 shows a data processing method in accordance with an embodiment of the present invention. 0608-A40830TWF1 1332623 is replacing ϋ 丨 丨 (a repair
首先，如步驟S302，中央處理單元23〇產生且透過第 一匯流排210將組態資料傳送至從動匯流排介面241。其 中，組態資料可以為一存儲於儲存裝置26〇之描述符列表 之基址（descriptor base address )，透過該描述符基址資訊 可獲得複數已存儲於儲存裝置26〇内之描述符。每一描述 符包括，但不限於至少一資料區塊於儲存裝置26〇中的位 址（即源位址，source memory bl〇ck address )、將資料區 塊處理後所得到之結果欲儲存至儲存裝置26〇中的位址 (即目標位址，destination address )、對相應之資料區塊 進行何種處理以及下一描述符之位址。如步驟S3〇4 ,從動 匯流排介面241接收組態資料且將組態資料儲存至暫存琴 245。之後，如步驟S306，資料處理單元244之DMA控制 器2441由暫存器245取得組態資料並依據組態資料發出一 讀取描述符指令至第二主動匯流排介面243。First, in step S302, the central processing unit 23 generates and transmits the configuration data to the slave bus interface 241 through the first bus 210. The configuration data may be a descriptor base address stored in the storage device 26's descriptor list, and the descriptors stored in the storage device 26 may be obtained through the descriptor base information. Each descriptor includes, but is not limited to, an address of at least one data block in the storage device 26 (ie, source memory bl〇ck address), and the result obtained by processing the data block is to be stored to The address in the storage device 26 (ie, the destination address), what processing is performed on the corresponding data block, and the address of the next descriptor. In step S3〇4, the slave bus interface 241 receives the configuration data and stores the configuration data to the temporary memory 245. Then, in step S306, the DMA controller 2441 of the data processing unit 244 retrieves the configuration data from the temporary memory 245 and issues a read descriptor instruction to the second active bus interface 243 according to the configuration data.
如步驟S308，第二主動匯流排介面243透過第二匯流 排220將讀取描述符指令傳送至存取控制器25〇。如步驟 S310,存取控制器250依據讀取描述符指令由儲存裝置26〇 讀取一描述符，並如步驟S312，透過第二匯流排22〇與第 二主動匯流排介面243將描述符回傳至資料處理單元244 的DMA控制器2441。如步驟S314,資料處理單元244對 5買取之描述符進行解碼操作，以獲知源位址、目標位址及 資料處理資訊，並如步驟S316，依據上述描述符資訊發出 一言買取資料指令至第二主動匯流排介面243。如步驟 S318’第一主動匯流排介面243透過第二匯流排220將讀 0608-A40830TWF1In step S308, the second active bus interface 243 transmits the read descriptor instruction to the access controller 25 through the second bus 220. In step S310, the access controller 250 reads a descriptor from the storage device 26 according to the read descriptor instruction, and returns the descriptor through the second bus bar 22 and the second active bus interface 243 in step S312. The DMA controller 2441 is passed to the data processing unit 244. In step S314, the data processing unit 244 performs a decoding operation on the 5-buy descriptor to obtain the source address, the target address, and the data processing information, and, according to the step S316, sends a message to the first instruction according to the descriptor information. Two active bus interface 243. In step S318, the first active bus interface 243 will read 0608-A40830TWF1 through the second bus 220.
-I 1332623 _ __ "] 滅日修正替换ϋ 取資料指令傳送至存取控制器25G。隨後，如步驟S320,-I 1332623 _ __ "] The annihilation correction replacement ϋ fetch data command is transmitted to the access controller 25G. Subsequently, as step S320,
存取控制裔依據讀取資料指令由儲存農置260讀取一 資料區塊，並如步驟S322，透過第二匯流排-與第二主 動匯流排介面243將資料區塊回傳至資料處理單元244。 之後，如步驟S324 ’資料處理單元-對於資料區塊進行 相關處理’如互斥或運算處理或是計算同位資訊，從而得 到處理後之結果’並如步驟S326，發出—寫人資料指令至 第-主動匯流排介面242。如步驟S328，第一主動匯 介面242 if過第:匯流排21〇將處理所得之資料區塊依據 寫入資料指令傳达至存取控制器25〇。如步驟S33G，存取 控制器250依據寫入指令將處理結果寫入至儲存裝置 第3圖顯示依據本發明另一實施例之資料處理系統。 在此實施财，資料處理系統包括三個匯流排，其中兩個 匯流排用於資料之讀取操作，一個匯流排用於資料之寫入 操作。注意的是’第3圖與第！圖中相同的元件使用相同 的標號。 依據本發明實施例之資料處理系統4〇〇包括一第一匯 流排210、一第二匯流排220與一第三匯流排270、一中央 處理單元230、一資料加速單元240、一存取控制器25〇、 以及至少一儲存裝置260。類似地，儲存裝置260可以是 DDR、DDRII、SDRAM。此外，第一匯流排21〇、第二匯 流排220與第二匯流排270可以是進階高效能匯流排，但 不限定於此。中央處理單元230決定資料處理所需的組態 資料’如欲讀取之特定資料區塊於儲存裝置中的位址，以 0608-A40830TWF1 11 —______ ㈣月“日修正替換頁 =:;=::;欲;一”的 260之描述符列表之如〜、f4可以為—存儲於儲存裝置 已”於儲錢置^内之描=描述符基址資訊可獲得 動匯流排介面241盥 /、节’從 匯流排210,第二w 動匯流排介面242輕接至第— 220,第一主動「一匯流排介面243耦接至第二匯流排 ^ 中具有一暫存器245，用以透過第一匯 "丨L _⑺由中央處理單元23〇接收且儲存組態資料。 貝料處理單70 244包括一 DMA控制器2441及一處理 模，、且2442。DMA控制器2441依據接收之組態資料透過第 二，匯流排介面243或第三主動匯流排介面施4 = 匯流排220或第三匯流排27〇致使存取控制器25〇由儲存 裝置260讀取—描述符。其後，DMA控制器2441通過解 碼描述符獲取將要讀取之資料區塊之位址，並分別透過第 一主動匯流排介面243與第三主動匯流排介面246由第 二、第三匯流排220’270致使存取控制器250由儲存裝置 260讀取一第一資料區塊及一第二資料區塊。處理模組 2442對讀出之第一、第二資料區塊進行處理，如互斥或運 真處理、無零判斷（non_zero)、比較（compare)運算或 是計算同位資訊，從而得到處理後之結果。之後，DMA控 0608-A40830TWF1 1332623 月ίί日修正替換頁 制器2441透過第一主動匯流排介面242由第一匯流排210 致使存取控制器250依據相應描述符之目標地址將處理後 之結果寫入至儲存裝置260中。 由以上描述可知，本實施例之資料處理系統設置有兩 條讀取匯流排220，270與一條寫入匯流排21〇，以加快讀 寫資料到存取裝置的傳輸速度。這樣，本發明之資料處理 系統具有較大的資料傳輸帶寬’因而可適用於高端之RISC 應用平臺’並具有良好的資料處理性能。根據應用的情形， • 本實施例之資料處理系統也可設置三條或者更多的讀取匯 流排，而寫入匯流排亦可相應增加以平衡讀取與寫入資料 傳輸的帶寬。另一方面’中央處理單元230僅需要將組態 資料傳輸給資料加速單元，而不需要參與數據的傳輸及處 理，這使得本實施例之資料處理系統具有較高的運行速度。 第4圖顯示依據本發明另一實施例之資料處理方法。 在此實施例中’資料處理系統400需要由儲存裝置260讀 取兩個資料區塊。 鲁 首先，如步驟S502 ’中央處理單元230產生且透過第 一匯流排210將組態資料傳送至從動匯流排介面241。其 中，於本實施例中，組態資料為一存儲於儲存裝置26〇之 描述符列表之基址（descriptor base address )。如步驟 S504，從動匯流排介面241接收組態資料且將組態資料儲 存至暫存器245。 之後，如步驟S506，資料處理單元244之DMA控制 器2441由暫存器245取得組態資料，並依據該組態資料發 0608-A40830TWF1 13 !332623 .___ ㈣月K日修正替換頁 出一讀取描述符指令至第二匯流排220。每一描述符包 括’但不限於至少一資料區塊於儲存裝置260中的位址（即 源位址，source memory block address )、將資料區塊處理 後所得到之結果欲儲存至儲存裝置260中的位址（即目標 位址，destination address)、對相應之資料區塊進行何種 處理以及下一描述符之位址。 如步驟S508，第二主動匯流排介面243透過第二匯流 排220將讀取描述符指令傳送至存取控制器250。如步驟 S510,存取控制器250依據讀取描述符指令由儲存裝置260 讀取一描述符，並如步驟S512，透過第二匯流排220與第 二主動匯流排介面243將描述符回傳至資料處理單元244 的DMA控制器2441。如步驟S514，資料處理單元244對 讀取之描述符進行解碼操作，以獲知複數資料區塊之源位 址、目標位址及資料處理資訊。如步驟S516，資料處理單 元244依據上述描述符資訊發出一對應于第一資料區塊的 第一讀取資料指令至第二主動匯流排介面243，以及一對 應于第二資料區塊的第二讀取資料指令至第三主動匯流排 介面246。如步驟S518及步驟S520，第二、第三主動匯流 排介面243 ’ 246分別透過第二匯流排220與第三匯流排 270將第一、第二讀取資料指令傳送至存取控制器250。如 步驟S522’存取控制器250依據接收之第一、第二讀取資 料指令由儲存裝置260讀取一第一資料區塊及一第二資料 區塊。如步驟S524，存儲控制器250透過第二匯流排220 將第一資料區塊回傳至資料處理單元244。如步驟S526， 0608-A40830TWF1 1332623 ffV?月細正替換肓 ' 存儲控制器250透過第三匯流排270將第二資料區塊回傳 至資料處理單元244。之後，如步驟S528，資料處理單元 244對第一、第二資料區塊進行相關處理，如互斥或運算 處理或是計算同位資訊，從而得到處理後之資料區塊。其 中，若對第一、第二資料區塊進行互斥或運算處理，則僅 可獲得一個處理後之資料區塊，若對第一、第二資料區塊 分別進行獨立的處理，如全零運算，則可獲得兩個相應的 處理結果。如步驟S530，資料處理單元244隨後發出一寫 • 入資料指令至第一主動匯流排介面242，以將處理結果傳 輸至第一主動匯流排介面242。如步驟S532，第一主動匯 流排介面242透過第一匯流排210將處理所得之資料區塊 依據寫入資料指令傳送至存取控制器250。如步驟S534， 存取控制器250依據寫入指令將處理結果寫入至儲存裝置 260 ° 本發明之方法，或特定型態或其部份，可以以程式碼 的型態包含於實體媒體，如軟碟、光碟片、硬碟、或是任 • 何其他機器可讀取（如電腦可讀取)儲存媒體，其中，當程 式碼被機器，如電腦載入且執行時，此機器變成用以參與 本發明之裝置。本發明之方法與裝置也可以以程式碼型態 透過一些傳送媒體，如電線或電纜、光纖、或是任何傳輸 型態進行傳送，其中，當程式碼被機器，如電腦接收、載 入且執行時，此機器變成用以參與本發明之裝置。當在一 般用途處理器實作時，程式碼結合處理器提供一操作類似 於應用特定邏輯電路之獨特裝置。 0608-A40830TWF1 15 1332623 ㈣月((日修正替換ι| 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟悉此項技藝者，在不脫離本發明之精 神和範圍内，當可做些許更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖為一示意圖係顯示依據本發明一實施例之資料 處理系統。 • 第2圖為一流程圖係顯示依據本發明一實施例之資料 處理方法。 第3圖為一示意圖係顯示依據本發明另一實施例之資 料處理系統。 第4圖為一流程圖係顯示依據本發明另一實施例之資 料處理方法。 【主要元件符號說明】 200、400〜資料處理系統； 210〜第一匯流排； 220〜第二匯流排； 230〜中央處理單元； 240〜資料加速單元； 241〜從動匯流排介面； 242〜第一主動匯流排介面； 243〜第二主動匯流排介面； 0608-A40830TWF1 16 1332623 作年勹月,½修正替換頁 • 244〜資料處理單元； 2441-DMA控制器； 2442〜處理模組； 245〜暫存器； 246〜第三主動匯流排介面； 250〜存取控制器； 260〜儲存裝置； 270〜第三匯流排； • S302、S304、…、S330〜步驟； S502、S504、…、S534〜步驟。The access control person reads a data block from the storage farm 260 according to the read data command, and returns the data block to the data processing unit through the second bus bar and the second active bus bar interface 243 according to step S322. 244. Then, as in step S324, the data processing unit performs correlation processing on the data block, such as mutual exclusion or arithmetic processing, or calculates the parity information, thereby obtaining the processed result 'and, as in step S326, issuing a write data command to the first - Active bus interface 242. In step S328, the first active interface 242 if: the bus bar 21 transmits the processed data block to the access controller 25 according to the write data command. In step S33G, the access controller 250 writes the processing result to the storage device in accordance with the write command. Fig. 3 shows a data processing system in accordance with another embodiment of the present invention. In this implementation, the data processing system includes three bus bars, two bus bars for data read operations and one bus bar for data write operations. Note that 'Fig. 3 and the first! The same elements in the figures have the same reference numerals. The data processing system 4 of the embodiment of the present invention includes a first bus bar 210, a second bus bar 220 and a third bus bar 270, a central processing unit 230, a data acceleration unit 240, and an access control. And 25 at least one storage device 260. Similarly, storage device 260 can be DDR, DDRII, SDRAM. Further, the first bus bar 21A, the second bus bar 220, and the second bus bar 270 may be advanced high-efficiency bus bars, but are not limited thereto. The central processing unit 230 determines the configuration data required for data processing, such as the address of the specific data block to be read in the storage device, to 0608-A40830TWF1 11 —______ (four) month “day correction replacement page=:;=: :; want; a "260 of the list of descriptors such as ~, f4 can be - stored in the storage device has been in the storage of the ^ description = descriptor base information can be obtained by the bus interface 241 盥 /, The section 'from the bus bar 210, the second w bus bar interface 242 is lightly connected to the first 220, the first active "one bus bar interface 243 is coupled to the second bus bar ^ has a register 245 for transmitting The first sink "丨L_(7) is received by the central processing unit 23〇 and stores the configuration data. The bedding processing unit 70 244 includes a DMA controller 2441 and a processing module, and 2442. The DMA controller 2441 is based on the received group. The state data is transmitted through the second, bus interface 243 or third active bus interface 4 = bus bar 220 or third bus bar 27, causing the access controller 25 to read the descriptor from the storage device 260. Thereafter, The DMA controller 2441 obtains the data block to be read by decoding the descriptor The address, and the second active bus interface 246 and the third active bus interface 246 are respectively caused by the second and third bus bars 220 270 to cause the access controller 250 to read a first data block from the storage device 260. And a second data block. The processing module 2442 processes the read first and second data blocks, such as mutual exclusion or transmission processing, non-zero determination (non_zero), comparison (compare operation) or calculation The same information, so as to obtain the processed result. Thereafter, the DMA control 0608-A40830TWF1 1332623 month ίί correction replacement pager 2441 is caused by the first bus bar interface 242 to cause the access controller 250 according to the corresponding description through the first bus bar interface 242 The target address of the symbol is written into the storage device 260. As can be seen from the above description, the data processing system of the embodiment is provided with two read bus bars 220, 270 and one write bus bar 21〇, Accelerate the transmission speed of reading and writing data to the access device. Thus, the data processing system of the present invention has a large data transmission bandwidth 'and thus can be applied to a high-end RISC application platform' and has good Data processing performance. Depending on the application, • The data processing system of this embodiment can also set three or more read bus bars, and the write bus bar can be increased accordingly to balance the read and write data transmission. On the other hand, the central processing unit 230 only needs to transfer the configuration data to the data acceleration unit without participating in the data transmission and processing, which makes the data processing system of the embodiment have a higher running speed. The figure shows a data processing method according to another embodiment of the present invention. In this embodiment, the data processing system 400 needs to read two data blocks from the storage device 260. First, the central processing unit 230 generates and transmits the configuration data to the slave bus interface 241 through the first bus 210 as in step S502. In this embodiment, the configuration data is a descriptor base address stored in the storage device 26〇. In step S504, the slave bus interface 241 receives the configuration data and stores the configuration data to the register 245. Then, in step S506, the DMA controller 2441 of the data processing unit 244 obtains the configuration data from the temporary storage unit 245, and sends 0608-A40830TWF1 13 !332623 .___ according to the configuration data. (4) The monthly K-correction replacement page is read out. The descriptor instruction is fetched to the second bus 220. Each descriptor includes, but is not limited to, an address of at least one data block in the storage device 260 (ie, a source memory block address), and the result obtained by processing the data block is to be stored in the storage device 260. The address in the address (ie destination address), what processing is performed on the corresponding data block, and the address of the next descriptor. In step S508, the second active bus interface 243 transmits the read descriptor instruction to the access controller 250 through the second bus 220. In step S510, the access controller 250 reads a descriptor from the storage device 260 according to the read descriptor instruction, and returns the descriptor to the second active bus interface 243 via the second bus 220 and the second active bus interface 243 according to step S512. The DMA controller 2441 of the data processing unit 244. In step S514, the data processing unit 244 performs a decoding operation on the read descriptor to obtain the source address, the target address, and the data processing information of the complex data block. In step S516, the data processing unit 244 issues a first read data instruction corresponding to the first data block to the second active bus interface interface 243 according to the descriptor information, and a second corresponding to the second data block. The data command is read to the third active bus interface 246. In step S518 and step S520, the second and third active bus interface interfaces 243' 246 transmit the first and second read data instructions to the access controller 250 through the second bus bar 220 and the third bus bar 270, respectively. In step S522, the access controller 250 reads a first data block and a second data block from the storage device 260 according to the received first and second read data commands. In step S524, the storage controller 250 transmits the first data block back to the data processing unit 244 through the second bus bar 220. In step S526, 0608-A40830TWF1 1332623 ffV monthly replacement 肓 ' The memory controller 250 transmits the second data block back to the data processing unit 244 through the third bus 270. Then, in step S528, the data processing unit 244 performs related processing on the first and second data blocks, such as mutual exclusion or arithmetic processing or calculation of the parity information, thereby obtaining the processed data block. Wherein, if the first and second data blocks are mutually exclusive or processed, only one processed data block can be obtained, and if the first and second data blocks are separately processed, such as all zeros Operation, you can get two corresponding processing results. In step S530, the data processing unit 244 then issues a write data command to the first active bus interface 242 to transfer the processing result to the first active bus interface 242. In step S532, the first active bus interface 242 transmits the processed data block to the access controller 250 according to the write data command through the first bus 210. In step S534, the access controller 250 writes the processing result to the storage device 260 according to the write command, or the specific type or part thereof, may be included in the physical medium in the form of a code, such as A floppy disk, a disc, a hard disk, or any other machine readable (eg, computer readable) storage medium in which the machine becomes used when the code is loaded and executed by a machine, such as a computer. Participating in the device of the invention. The method and apparatus of the present invention can also be transmitted in a code format through some transmission medium such as a wire or cable, an optical fiber, or any transmission type, wherein the code is received, loaded, and executed by a machine such as a computer. At this time, the machine becomes a device for participating in the present invention. When implemented in a general purpose processor, the code in conjunction with the processor provides a unique means of operating similar to the application specific logic. </ RTI> </ RTI> <RTIgt; In the scope of the invention, the scope of protection of the present invention is defined by the scope of the appended claims. [FIG. 1 is a schematic diagram showing an implementation according to the present invention. Example of a data processing system. Fig. 2 is a flow chart showing a data processing method according to an embodiment of the present invention. Fig. 3 is a schematic view showing a data processing system according to another embodiment of the present invention. A data processing method according to another embodiment of the present invention is shown in a flowchart. [Main component symbol description] 200, 400~ data processing system; 210~ first bus bar; 220~ second bus bar; 230~ central processing Unit; 240~ data acceleration unit; 241~ slave bus interface; 242~ first active bus interface; 243~ second active bus interface; 0608-A40830TWF1 16 1332623 Year of the year, 1⁄2 correction replacement page • 244~ data processing unit; 2441-DMA controller; 2442~ processing module; 245~ scratchpad; 246~ third active bus interface; 250~ access control 260~ storage device; 270~third busbar; • S302, S304, ..., S330~ steps; S502, S504, ..., S534~ steps.
0608-A40830TWF10608-A40830TWF1