JP2001350461A - Picture processing method and picture processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a picture processor bringing no hindrance to displaying even when a bus bandwidth temporarily runs short, and a method therefor. SOLUTION: The picture processor holds a signal, which indicates that a write address has become larger than a read address, in an overflow detecting circuit 35 in a picture fetching device 6, and creates a signal that can be released by a horizontal or vertical synchronizing signal obtained from a camera signal processing circuit 31. Moreover, write and read controllers 33, 34 for FiFo memory stop read or write operation to the FiFo memory and also initialize the memory by the held overflow signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image processing apparatus such as a portable still image recording apparatus and the like, which has a function of capturing and displaying a moving image in real time.

[0002]

2. Description of the Related Art For example, a portable still image recording apparatus having a function of capturing and displaying a moving image in real time has been known. FIG. 5 shows real-time moving image capture,
FIG. 2 is a diagram illustrating an example of a general still image recording device that can be displayed. In FIG. 5, reference numeral 501 denotes a central control unit (CPU) that controls the entire apparatus, 502 denotes a CPU memory connected to a CPU bus 504, and 503 denotes recorded still image data such as a flash card. External device controller for recording in an external storage element, 50
Reference numeral 5 denotes a bridge circuit that connects the CPU bus 504 and the image bus 510.

Further, reference numeral 506 denotes an image capturing device for capturing a moving image, 507 denotes a display device capable of displaying the moving image, and 508 temporarily records the moving image captured by the image capturing device 506. Image memory circuit, 50
Reference numeral 9 denotes a compression / expansion circuit for compressing / expanding the captured image as a still image.

FIG. 6 shows a more detailed block diagram of the image capturing device 506. In the figure, reference numeral 131 denotes a camera signal processing circuit that processes analog or digitized image data from an area sensor (not shown) into a camera signal, and 132 denotes a camera signal processing circuit in the camera signal processing circuit 131. This is a FIFO memory for absorbing a difference between the clock rate and the clock rate used in the image bus 510.

[0005] A 133 is initialized by an external reset signal, and based on a clock rate used by the camera signal processing circuit 131, a FIFO memory 132.
A write address controller 134 for generating an address for writing image data to the memory is initialized by an external reset signal, and a read address controller 135 for generating a read address based on the clock rate of the image data bus. A data transfer request to the image memory is issued to the bus interface from the address and the read address value,
This is an overflow detection circuit that detects an overflow and outputs an overflow signal. More specifically, the overflow detection circuit includes two magnitude comparators. Also, 1
A bus interface 36 issues a bus right request to the image bus based on a transfer request from the overflow detection circuit 135.

The operation of a conventional still image recording apparatus capable of capturing and displaying a real-time moving image will now be described. The image data captured from the image capturing device 506 in FIG. 5 is temporarily stored in the image memory 508. The image memory 508 has an OS for an on-screen display.
D data is also stored.

On the other hand, the display device 507 includes the image memory 50.
The image data is read from the memory 8 and displayed, and at the same time, the overlay display is performed using the OSD data for the on-screen display stored in the image memory 508.

[0008]

However, in the above-described conventional still image recording apparatus capable of capturing and displaying a real-time moving image, it is necessary to sufficiently satisfy the data transfer rate and rewrite the OSD data depending on the situation.
Regarding the bus bandwidth for transferring image data,
It must be set high enough to satisfy the bandwidth required for OSD data transfer.

For this purpose, it is necessary to set a high clock rate of the bus or a wide data bit width of the bus. As a result, it leads to an increase in power consumption or an increase in the size of the apparatus, and still image recording is performed. There is a problem that it is difficult to mount a conventional device as it is on a basic small portable device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to reduce the bus data transfer rate to a minimum bandwidth required for capturing and displaying a moving image, and By providing an image processing apparatus and an image processing method that do not hinder display even when another device accesses the image bus and a shortage of bus bandwidth occurs temporarily. is there.

[0011]

According to the present invention, there is provided an image processing apparatus comprising: a first address for writing image data to a memory; and a second address for reading the image data from the memory. Address generating means for generating an address of the following, and the first and second addresses:
Capturing means for controlling writing and reading of image data to and from the memory to capture the image data; and determining whether or not the memory is in an overflow state based on a result of comparison between the first address and the second address. Determining means for determining; interrupting means for interrupting the capture of the image data by the capture means when the memory is determined to be in an overflow state; and a predetermined synchronization signal used for capture of the image data. And a resuming means for resuming the image data fetching process by the fetching means.

According to another aspect of the present invention, there is provided an image processing method comprising: a first address for writing image data to a memory; and a second address for reading the image data from the memory. An address generating step of generating an address of: and the first and second addresses,
A fetching step of controlling writing and reading of image data to and from the memory to fetch the image data; and determining whether the memory is in an overflow state based on a result of comparison between the first address and the second address. A determining step of determining, an interrupting step of interrupting the capturing of the image data in the capturing step when the memory is determined to be in an overflow state, and a predetermined synchronization signal used for capturing the image data. And a resuming step of resuming the image data taking process in the taking step.

[0013]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a schematic configuration of a still image recording device capable of displaying a moving image using the moving image data transfer device according to the present embodiment. In FIG. 1, reference numeral 1 denotes a central controller (hereinafter, CPU) for controlling the entire apparatus, 2 denotes a memory connected to a CPU bus 4, and 3 denotes an external storage element (for example, An external device controller 5 for recording data on a flash card or the like is a bridge circuit that connects the CPU bus 4 and the image bus 10.

Reference numeral 6 denotes an image capturing device for capturing a moving image, 7 denotes a display device capable of displaying a moving image, and 8 denotes an image for temporarily recording the moving image captured by the image capturing device 6. The memory 9 is a compression / expansion circuit for compressing / expanding the captured image as a still image.

FIG. 7 shows the arrangement of image data on the memory 8 at this time.
Is written to. In FIG. 7, the memory configuration is horizontal 1
024 pixels and 1024 pixels vertically, and the current area sensor output is shown as 640 pixels horizontally and 480 pixels vertically. In FIG. 7, an area 121 is the entire memory, and an area 122 is a display area in which image data that is currently captured and being displayed is stored. In the present embodiment, 640 pixels in the horizontal direction and 480 pixels in the vertical direction are used. It is shown.

Further, an area 123 shown in FIG. 7 is an OSD area for storing OSD data which is overlaid on the display screen at the time of display, and an area 124 is an area for storing image data to be compressed or expanded by the compression / expansion circuit 9. This is the compression area to be stored.

FIG. 2 is a block diagram schematically showing the internal configuration of the image capturing device 6 of FIG. In the image capturing device 6 shown in the figure, reference numeral 31 denotes a camera signal processing circuit for performing signal processing on a digitized output from an area sensor (not shown) or an analog output which is not digitized. This is a first-in first-out (Fifo) circuit for converting the digitized camera signal output from the circuit 31 to an image bus (image data bus) 10 after converting the signal into a certain signal amount.

Reference numeral 33 denotes a write address controller for generating a write address for writing data to the FIFO 32 in synchronization with a digital signal output from the camera signal processing circuit 31, and 34 acquires the bus right of the image bus 10. Sometimes, the read address controller generates an address for reading data from the FIFO 32 at a timing synchronized with the image bus 10.

The reference numeral 35 compares the write address of the write address controller 33 with the read address of the read address controller 34, and a state occurs where the write address overtakes the read address (that is, a state where overflow occurs). This is an overflow detection circuit for detecting whether or not there is an error.

FIG. 3 shows the overflow detection circuit 3 of FIG.
5 is a block diagram showing a specific example of No. 5. FIG. In FIG.
1 is an RS flip-flop, 42 is a subtraction circuit, 43 is a comparator, and 45 is '1' when the address is “0”.
Are output from the NAND circuit. In this detection circuit, the write address WA (multiple bits) from the write address controller 33 in FIG. 2 and the read address RA from the read address controller 34 in FIG.
(WA-RA) is performed in the subtraction circuit 42 on the (multiple bits). The write address WA and the read address RA are input to the subtraction circuit 42 and also to the NAND circuit 45 at the same time. NAND
The circuit 45 is set to output “1” when each input address is “0” (all bits are 0), and the output of the NAND circuit for the WA address is R.
The S input of the S flip-flop 41 and the output of the NAND circuit for the RA address are connected to the R input of the same RS flip-flop. Thus, when the WA address exceeds the upper limit of the counter and returns to "0", the RS flip-flop output (CA) is set to "1". The subtraction is performed as a bit (that is, if the upper limit of the counter is 63, the subtraction circuit performs 64+
WA-RA is being executed). On the other hand, when the read address RA returns to “0” exceeding the upper limit value of the counter, the output (CA) of the RS flip-flop previously set is reset to “0” and the normal subtraction (WA) is performed. -RA).

The above calculation result is compared with a predetermined value (the value indicated by Fix D in FIG. 3 and the number of one transaction on the image bus 10) by the comparator 43, and the WA-RA If the number is larger than the number, the output Q of the comparator 43, that is, the request signal (REQ) of the bus transaction becomes “1”. This signal is transmitted to the bus interface 36 of FIG. 2, and the bus interface 36 starts operating to generate a bus transaction.

On the other hand, the operation result of the subtraction circuit 42 is FI
If the number of stages is equal to or greater than the number of stages of the FO, it is determined that an overflow has occurred in the detection circuit, and the BR output of the subtraction circuit 42 becomes “1”. As a result, the output of the RS flip-flop 41 connected to this output becomes “1”, and this signal (OVR) is finally transmitted to the interrupt controller of the CPU as a signal indicating “overflow”.

At the same time, a signal that is the logical sum (OR) of the signal (OVR) indicating the overflow and the RESET signal (active High) supplied from the outside is sent to the write address controller 33 of FIG. Reset signal of controller 34 (RST)
Supplied as

Signal indicating "overflow" (OVR)
Is set by the BR signal from the subtraction circuit 42 as described above, and an external RESET signal (active H
high) and a horizontal synchronizing signal pulse HD (active high) supplied from the camera signal processing circuit 31 of FIG.
h) is reset. For this reason, Fifo32
Even when the overflow occurs, the reset signal of the write address controller 33 and the read address controller 34 is reset (that is, released) by the signal “HD pulse” from the camera signal processing circuit 31 to start supplying the signal of the next line. Then, both the write address controller 33 and the read address controller 34 can resume the normal transfer operation from the new line.

FIGS. 4A and 4B are timing charts showing the above-described operations in time series. In FIG.
LK is a video clock used in camera signal processing,
WA sets the write address controller 33 to Fif.
write address signal, BCLK
Is a bus clock used in the image bus 10, and RA is
The read address Diff output from the read address controller 34 of Fifo 32 is the result of subtracting the read address from the write address (WA-R
An AB signal indicating A), OVR is a signal indicating an overflow of Fifo 32, and HD is a camera signal processing circuit 3.
1 is a horizontal synchronizing signal, Valid is a signal indicating that the data obtained from the camera signal processing circuit 31 is valid, and REQ is data that can be transferred to Fifo 32 as much as possible and a bus transaction occurs. To the bus interface.

In FIGS. 4A and 4B, the fixed value for generating the REQ signal is 8 (transaction is 8 beats), and the number of stages of Fifo 32 is 64.

Hereinafter, with reference to FIGS. 4A and 4B, Fif
The operation at the time of overflow of o32 and the return operation will be described. Here, it is assumed that a considerable amount of data has already been stored in the Fifo 32, and the timing t1 in the drawing.
Then, the overflow of Fifo32 occurs and OVR
The signal becomes '1', and based on the result, the read address RA at the timing t2 and the write address WA at the timing t3 at the next valid clock.
Are reset, and each is returned to “0”.

Thereafter, since the OVR signal is held at "1", both WA and RA maintain "0". Thereafter, when the HD signal supplied from the camera signal processing circuit 31 becomes “1”, the OVR signal is reset to “0” (timing t4). Then, as valid pixel data is supplied from the camera signal processing circuit 31, the write address WA is incremented by "1".

On the other hand, the read address RA is
32, data cannot be transferred until a certain amount of data is accumulated. Therefore, the actual start of increment is because the above-mentioned address difference signal Diff is the number of transactions of 8
And the bus right after the timing t5 at which the REQ signal requesting the bus interface 36 to generate a bus transaction becomes “1” is obtained.

As described above, in the moving image data transfer apparatus according to the present embodiment, the data transfer rate of the bus is suppressed to the minimum bandwidth required for capturing and displaying moving images, and other devices are used. When accessing the image bus and there is a temporary shortage of bus bandwidth, the display-side bus data transfer is performed more than the capture-side bus transfer so as not to interfere with the display. Strongly set.

At the same time, if the bus transfer rate becomes insufficient on the fetch side and the data to be written to the memory becomes abnormal, the data transfer is immediately stopped and the data in the transfer FIFO memory is deleted. After clearing, using the next synchronization signal at the time of capturing, the moving image capturing operation is restarted.

Therefore, a signal indicating that the write address has become larger than the read address is held in the overflow detection circuit 35 in the image capturing device 6, and the held signal is transferred to the camera signal processing circuit 31.
And an RS flip-flop circuit for generating a signal that can be released by a horizontal or vertical synchronization signal obtained from the RS. Further, the write / read address controller for the FIFO memory has a function of stopping and initializing the write or read operation to the FIFO memory by the overflow signal thus held.

As described above, according to this embodiment, even if the Fifo overflows due to the lack of the bus right, the transfer of the image data to the memory is stopped by the overflow signal. The data in the image memory retains data having a high temporal correlation immediately before, so that there is an effect that display is not hindered.

In other words, even if the bus transfer rate is kept to the minimum necessary and the bus capacity temporarily becomes insufficient, the bus right cannot be obtained on the moving picture fetching side and the At the moment of the overflow,
By temporarily stopping the image capturing device from making a bus request, it is possible to improve the shortage of the bus capacity.

Further, by restarting the image data transfer process using the horizontal synchronization signal obtained from the camera signal processing circuit, the portion where the transfer of the image data has failed is minimized. Can also be prevented from being written into the memory, so that the display device can minimize discomfort on the screen for the viewer by using the previously captured moving image data as the display data.

[Modification] In the above-described embodiment, the Fi
The horizontal synchronizing signal from the camera signal processing circuit is used to recover from the overflow of fo. However, the present invention is not limited to this. For example, the recovery from the overflow of Fifo may be performed using a vertical signal. In this case, when a device connected to an image data bus other than the camera signal processing circuit and the display circuit performs a bus access (for example, rewriting OSD data) that requires a certain data transfer period, it takes one vertical period. The bus access from the camera signal processing circuit can be restricted.

As a result, the transfer processing of the devices connected to the image data bus other than the camera signal processing circuit and the display circuit can be completed quickly, and as a result, the sense of discomfort given to the display is reduced. The device configuration in this case is as follows:
It can be easily realized by replacing the horizontal synchronizing signal HD described in the above embodiment with the vertical synchronizing signal VD.

[0038]

[Other Embodiments] Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus (for example, a copying machine) Machine, facsimile machine, etc.).

Another object of the present invention is to provide a storage medium (or a recording medium) storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer for the system or the apparatus. Needless to say, this can also be achieved by (or a CPU or MPU) reading and executing the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. As a storage medium for supplying the program code, for example, a floppy disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, and the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the operating system (OS) running on the computer based on the instruction of the program code. ) May, of course, include a case where some or all of the actual processing is performed, and the processing realizes the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instructions of the program code, It goes without saying that the CPU included in the function expansion board or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0043]

As described above, according to the present invention,
Even if the memory device overflows due to the lack of the bus right and a temporary shortage of the bus capacity occurs, the process of transferring the image data to the memory device by the overflow signal is stopped by the overflow signal. The above data retains data having a high temporal correlation immediately before, and thus does not hinder display.

Further, according to the present invention, by restarting the image data transfer process using the horizontal synchronization signal or the vertical synchronization signal obtained from the data capturing device, the portion where the image data transfer has failed can be minimized. It is possible to minimize discomfort on the display screen.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a still image recording device capable of displaying a moving image using a moving image data transfer device according to the present embodiment.

FIG. 2 is a block diagram schematically showing an internal configuration of the image capturing device according to the embodiment.

FIG. 3 is a block diagram illustrating a specific example of an overflow detection circuit according to the embodiment;

FIG. 4A is a timing chart showing the operation of the overflow detection circuit in a time series.

FIG. 4B is a timing chart showing the operation of the overflow detection circuit in a time series.

FIG. 5 is a block diagram showing an example of a conventional still image recording device.

FIG. 6 is a detailed block diagram of a conventional image capturing device.

FIG. 7 is a diagram showing an arrangement of image data on a memory.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06T 1/60 450 G06T 1/60 450G G09G 5/36 510 G09G 5/36 510M

Claims (11)

[Claims] 1. An address generating means for generating a first address for writing image data to a memory and a second address for reading the image data from the memory, and the first and second addresses, Capturing means for controlling writing and reading of image data to and from the memory to capture the image data; and determining whether the memory is in an overflow state based on a result of comparison between the first address and the second address. Determining means for determining; interrupting means for interrupting the capturing of the image data by the capturing means when the memory is determined to be in an overflow state; and a predetermined synchronization signal used for capturing the image data. And a resuming means for resuming the image data fetching process by the fetching means. 2. The information processing apparatus according to claim 1, further comprising: a generating unit configured to generate a predetermined state signal indicating the overflow state when the memory is determined to be in an overflow state by the determining unit. 2. The image processing apparatus according to claim 1, further comprising: resetting an address generation unit, initializing the contents of the memory, and interrupting the acquisition of the image data by the acquisition unit. 3. The image processing apparatus according to claim 1, wherein the resuming unit resumes the capture of the image data using a next horizontal synchronization signal at the time of the capture related to the interruption. 4. The image processing apparatus according to claim 1, wherein the resuming unit resumes the capture of the image data using a next vertical synchronization signal at the time of the capture related to the interruption. 5. The image processing apparatus according to claim 1, further comprising display means for displaying and outputting image data read from said memory in accordance with said second address. 6. An address generation step of generating a first address for writing image data to a memory and a second address for reading the image data from the memory, and the first and second addresses A capturing step of controlling writing and reading of image data to and from the memory to capture the image data; and determining whether or not the memory is in an overflow state based on a result of comparison between the first address and the second address. A determining step of determining; an interrupting step of interrupting the capturing of the image data in the capturing step if the memory is determined to be in an overflow state; and a predetermined synchronization signal used for capturing the image data. And a resuming step of resuming the image data capturing process by the capturing step. 7. If the memory is determined to be in an overflow state by the determining step, the memory further includes a generating step of generating a predetermined state signal indicating the overflow state. 7. The image processing method according to claim 6, further comprising resetting an address generation step, initializing the contents of the memory, and interrupting the capture of the image data in the capture step. 8. The image processing method according to claim 6, wherein in the resuming step, the resumption of the capture of the image data is performed using a next horizontal synchronization signal at the time of the capture related to the interruption. 9. The image processing method according to claim 6, wherein in the resuming step, the resumption of the capture of the image data is performed using a next vertical synchronization signal at the time of the capture related to the interruption. 10. The image processing method according to claim 6, further comprising a display step of displaying and outputting image data read from said memory according to said second address. 11. A storage medium for storing a control program for causing a computer to execute the method according to claim 6. Description: