JP3742066B2 - Camera image processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for efficiently transferring data in a camera image processing apparatus while reducing the size of a camera memory in the apparatus. For example, the present invention provides a technique applicable to a mobile phone with a built-in camera.
[0002]
[Prior art]
In a camera image processing apparatus in which a frame rate differs between input and output, such as inputting a camera-captured image and outputting the same image by a CPU, conventionally, one frame or two frames are used for capturing input data. A memory is required (see, for example, Patent Document 1 and Patent Document 2).
[0003]
[Patent Document 1]
Japanese Patent No. 3347064
[Patent Document 2]
JP-A-8-163493
[0004]
[Problems to be solved by the invention]
In the conventional image processing apparatus, a memory having a capacity of one frame or two frames is required as a camera memory, and when the memory is mounted on an LSI, a large area must be secured. is there.
[0005]
In addition, when a CODEC engine is installed in a conventional image processing apparatus and image compression such as JPEG is performed on a captured camera image, a memory dedicated to the CODEC engine is newly required. Problems can arise.
[0006]
Further, when data is read from the camera memory by direct transfer or DMA transfer by the CPU, arbitration processing is performed on the memory in the memory control connected to the camera memory. Here, the “arbitration process” is a process in which priority is given to a memory access request, and memory access is sequentially performed from a request with a high priority. As a matter of course, a request with a low priority is You will have to wait. For this reason, normally, when accessing by DMA, one access is possible at the maximum speed of 2 clocks, but a delay of 2 clocks or more and several clocks occurs, and it is said that efficient data transfer cannot be performed. There are also problems.
[0007]
The present invention is intended to solve the above-described problems, and enables efficient data transfer in data reading while reducing the camera memory and CODEC memory mounted on the LSI. An object of the present invention is to provide a camera image processing device that can be used. In other words, an object of the present invention is to propose a technique that can efficiently transfer and compress a camera-captured image with a small memory capacity.
[0008]
[Means for Solving the Problems]
For example, in Patent Document 1 (Japanese Patent No. 3347064), when the frame rate differs between input and output, an overtaking state occurs at the time of writing / reading the memory, so that the memory for two frames is stored. It has been proposed that it is necessary. However, it is possible to avoid the occurrence of the overtaking state by providing rate limiting on the input side and the output side. In this case, there is no need to provide a memory for two frames.
[0009]
From this point of view, the subject of the present invention proposes the adoption of the solution described below.
[0010]
That is, the camera image processing apparatus according to the present invention includes an interface circuit for capturing a camera-captured image for one frame, a camera memory having a plurality of storage areas having a storage capacity of one frame or less, A memory control circuit that controls data writing to the camera memory and data reading from the camera memory in accordance with a write request and a read request while performing an arbitration process; and the camera incorporated from the interface circuit A block data transfer / write control unit that divides a captured image into a plurality of blocks and sequentially transfers image data of all pixels included in the block to the memory control circuit together with the write request for each block. And the memory control circuit includes the write request. In response to receipt of the request, each of the image data in one block transferred is sequentially written to one write target storage area that is not currently being read out of the plurality of storage areas in the camera memory. In accordance with the display memory for temporarily holding the camera-captured image to display the camera-captured image on a display device, and the completion timing of the write operation in the write-target storage area, The read request instructing to sequentially read each of the image data in one block from the write target storage area is transferred to the memory control circuit, and the one block image data read from the write target storage area Are sequentially transferred to the display memory, so that all of the image data in one block is displayed. A block data read / transfer control unit for writing to the memory, wherein the memory control circuit responds to the read request at a timing when the memory control circuit starts the data read operation from the write target storage area. Accordingly, all the pixel data belonging to the next block following the block is sequentially written in the plurality of storage areas in which the all pixel data belonging to the block is already written. It is characterized by writing in one storage area other than the above.
[0011]
The subject matter of the present invention will be described below with reference to the drawings showing embodiments thereof. Describe specifically.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
FIG. 1 is a block diagram showing a camera image processing apparatus according to the present embodiment. The core part of the apparatus is a circuit part that transfers a camera captured image to a display memory. In the figure, a camera module 1 (an imaging device such as a CCD camera) outputs a captured image for one frame obtained by photographing a subject. On the other hand, the interface circuit (referred to as an I / F circuit) 2 captures the captured image of the raster data format output from the camera module 1 in the transfer circuit.
[0013]
The write address generation circuit 3 writes a camera captured image (data for each imaging pixel) received from the I / F circuit 2 in the camera memory 5 (here, the maximum number of pixels in one block). Assuming an arbitrary value n, write address values 0, 1, 2,..., N−1 are generated for one block, and n, n + 1, n + 2,. 1 is generated sequentially, and the write address signal (write request signal) is connected to the memory control circuit 6 together with the corresponding pixel data of the camera-captured image divided into blocks. Output to the bus.
[0014]
The block transfer control circuit 4 has an output terminal connected to the write address generation circuit 3 and the interrupt signal generation circuit 15. Divided into a plurality of blocks (at least two blocks), and for each block, the image data of all pixels belonging to the block are transferred to the memory control circuit 6 side together with the write address signal for the image data. This is a circuit section that performs control for causing the write address generation circuit 3 to perform “operation to perform”.
[0015]
For example, assuming that the maximum number of pixels in one block is an arbitrary value n, the block transfer control circuit 4 detects the number of pixel data in the raster data format received by the write address generation circuit 3 and the value is “reception”. When it indicates that the image data corresponds to the nth pixel, the control signal (for example, the FLAG signal shown in FIG. 3) is sent to the write address generation circuit 3 and the interrupt signal generation circuit 15 at the detection timing. Output.
[0016]
In this example, even if the write address generation circuit 3 receives the FLAG signal at this timing, the write address generation circuit 3 does not reset the value of the write address from “n−1” to “0”, and the n addresses belonging to the next block By sequentially incrementing from “n” to “2n−1”, n write address values are generated and output. When the block transfer control circuit 4 issues a FLAG signal again, the write address generation circuit 3 immediately changes the write address value “2n−1” at that time to “0” according to the FLAG signal reception timing. After resetting to “0” and setting the write address value of the next received image data to “0”, the received image data is set as the first image data belonging to the next block, and the write address value “0” Then, the data is transferred to the memory control circuit 6 side. Such an operation is continued in both circuit portions 3 and 4.
[0017]
Therefore, in the present embodiment, the part composed of both circuits 3 and 4 is generically referred to as a “block data transfer / write control unit”.
[0018]
The memory control circuit 6 performs arbitration (arbitration processing) for a write request (write address signal) to the camera memory 5 and a read request (read address signal) from the memory 5 for the camera-divided camera image divided into blocks. This is a control circuit unit to be performed.
[0019]
Here, the camera memory 5 is a storage device having a storage area (size) in which image data for one frame (one screen) or less can be stored as a total storage capacity, and includes a plurality of storage areas. For example, when the number of blocks m in the above-described block transfer control is the minimum value 2, the total storage capacity of the camera memory 5 is one frame (one screen) of the maximum value.
[0020]
On the other hand, the read address generation circuit 7 performs a camera for each read access request from the CPU 9 or the DMAC 10 in accordance with the reception timing of a transfer timing signal (for example, the FLAG INT signal in FIG. 3) from the CPU 9 or the DMAC 10 to be described later. 1 block image data (that is, each of all image data belonging to one block already written in the storage area to be read) from the corresponding storage area in the storage memory 5 sequentially. Is a circuit unit that generates read addresses (0, 1, 2,..., N−1) for reading data, and outputs each read address signal to the memory control circuit 6 as a read request (signal).
[0021]
Note that the case where the circuit 7 executes the pre-reading described later when performing DMA transfer will be described in detail later.
[0022]
Further, the interrupt signal generation circuit 15 responds to reception of the FLAG signal (see FIG. 3) generated by the block transfer control circuit 4 (transfer of the last pixel data belonging to one block / writing completion timing in the corresponding storage area). An interrupt signal is immediately generated and output to the CPU 9 or the DMAC 10.
[0023]
On the other hand, the CPU 9 is a part that performs control management of data reading and writing in the plurality of memories 5, 11, and 13 through the CPU bus. For example, when the CPU 9 instructs reading of the image data from the corresponding storage area of the camera-side memory 5 and start of transfer, the CPU 9 receives a transfer timing signal (for example, the FLAGINT signal in FIG. 3) to receive the interrupt signal. In response to this, the transfer timing signal is immediately generated and transferred to the read address generation circuit 7 via the CPU bus. After that, the CPU 9 issues a read access request to the read address generation circuit 7. The CPU 9 also controls data writing to the display memory 11.
[0024]
The DMA controller (hereinafter referred to as DMAC) 10 is a core part that performs control when performing DMA transfer of image data read from the corresponding storage area of the camera memory 5, and its operation is started by the CPU 9, for example. Or is started by another dedicated hardware. Then, the DMAC 10 generates a transfer timing signal (for example, the FLAG INT signal in FIG. 3) according to the reception timing of the interrupt signal, and sends the transfer timing signal to the read address generation circuit 7 via the CPU bus. Forward. Then, the DMAC 10 issues a read access request to the read address generation circuit 7.
[0025]
Further, the memory prefetch control circuit 8 performs the DMA transfer of one block image data stored in the camera memory 5 from the corresponding storage area of the camera memory 5 prior to receiving the read access request from the DMAC 10. The circuit unit is responsible for operation control for prefetching image data corresponding to several pixels in the one-block image data.
[0026]
Therefore, in the present embodiment, the part composed of the circuit parts 7, 9 or 10 connected via the CPU bus, or the part composed of the circuit parts 10, 7, 8 is designated as “block data read / read Collectively referred to as “transfer control unit”.
[0027]
The display memory 11 described above temporarily stores the captured image for one frame in order to display a camera captured image on a liquid crystal display device (hereinafter referred to as LCD) 12 which is an example of a display device. A storage device for storage.
[0028]
Further, the storage memory 13 is a storage device for storing the camera-captured image for each frame compressed by the CODEC engine 14.
[0029]
Here, the CODEC engine 14 uses the camera memory 5 as a dedicated memory for compression processing with respect to the camera captured image data once captured in the memory 11 on the CPU 9 side, thereby performing image compression processing (for example, JPEG And MPEG).
[0030]
The transfer circuit having the above-described configuration is controlled by the block transfer control circuit 4 when transferring the camera-captured image (raster data format) for one frame captured from the I / F circuit 2 to the display memory 11. The block transfer of the camera captured image is executed.
[0031]
A camera-captured image for one screen imaged by the camera module 1 is an arbitrary number m (m ≧ 2) by an address value generating operation in the write address generating circuit 3 performed under the control of the block transfer control circuit 4. It is divided into blocks and transferred. At this time, a storage area capable of storing image data for at least two blocks out of m blocks may be prepared in the camera memory 5. In this case, regarding the block division for one screen, the size of one block, that is, the number of pixels n included in one block may be set to any size (therefore, n is an arbitrary number). In addition, the camera-captured image for one screen may be divided into blocks in a convenient number. In particular, when it is desired to reduce the storage capacity of each storage area of the camera memory 5 as much as possible, as long as the input rate of the image captured by the camera and the readout rate of one block image data by the CPU 9 or DMAC 10 match each other, It is also possible to divide the captured image into blocks in units of one line. In this case, each storage area of the camera memory 5 corresponds to a line memory.
[0032]
Here, FIG. 2 is a diagram schematically showing an image of the block transfer method. Hereinafter, an operation sequence of the block transfer method and a direct image data read / transfer operation sequence by the CPU 9 will be described with reference to FIGS. 1 and 2.
[0033]
First, as shown in FIG. 2, it is assumed that a camera-captured image of one screen is divided into m blocks each having n pixel data belonging to each block. For this purpose, the storage area in the camera memory 5 is composed of two storage areas A and B each having a capacity sufficient to write all image data corresponding to n pixels. In this case, a code A or B alternately assigned to each of the first to mth blocks 1, 2, 3,..., M is a storage area A or B in the camera memory 5 corresponding to the code. Furthermore, all the image data belonging to the block i (1 ≦ i ≦ m) is sequentially transferred / stored from the image data of the first pixel to the image data of the nth pixel. . In addition, although it refuses again, the capacity | capacitance of each area | region A and B is an arbitrary value.
[0034]
Step 1:
Each of all the n pieces of image data belonging to the first block 1 is sequentially transferred and written to the first storage area A in the camera memory 5 ((1) in FIG. 2).
[0035]
This block division / transfer process is executed by the control of the write address value generation by the block transfer control circuit 4 as described above. That is, the block transfer control circuit 4 continues to detect the raster data sequentially received by the write address generation circuit 3, that is, the reception of the image data of each pixel positioned sequentially on each scanning line in one frame, When it is detected that the detection result has reached the number n of pixels in one block, a pulse signal for instructing that transfer of all image data belonging to the first block is completed, for example, the FLAG signal in FIG. To the write address generation circuit 3 and the interrupt signal generation circuit 15.
[0036]
As a result, all the n pieces of image data belonging to the first block 1 are transferred to the memory control circuit 6 together with the corresponding write address values 0, 1, 2,..., N−1 in that order. The As a result, the circuit 6 sequentially receives each of all n pieces of image data belonging to the first block 1 to the corresponding addresses of the write address values 0, 1, 2,..., N−1. In response to the write request, data is sequentially written to the corresponding address in the first storage area A of the camera memory 5.
[0037]
Step 2:
At the time when the last image data (●) in the block 1 is written to the nth address in the first storage area A (A area read timing t1), the CPU 9 generates based on the FLAG signal and the interrupt signal. Read / transfer start signal FLAG INT is output to read address circuit 7. Then, in response to the read access request from the CPU 9, the read address circuit 7 generates and outputs a read address signal as a read request by the increment processing, and in response to the read request of each read address signal, the memory control The circuit 6 sequentially reads out each image data in the block 1 from the area A of the camera memory 5 and transfers it to the read address circuit 7 side, and the CPU 9 transfers each image data in the block 1 to the display memory 11. ((2) in FIG. 2).
[0038]
At this time, the writing of 1-block image data in the next block 2 to the camera memory 5 is continuously performed on the other B area which is an empty area.
[0039]
Step 3:
The CPU 9 ends the transfer operation at the stage where all the 1-block image data in the area A has been taken into the display memory 11 (end (2) in FIG. 2).
[0040]
At this time, the memory control circuit 6 continues the operation of writing one block image data in the block 2 to the second storage area B ((3) in FIG. 2).
[0041]
Step 4:
When the memory control circuit 6 writes the last image (●) in the block 2 to the nth address in the second storage area B (B area read timing t2) (end of (3) in FIG. 2) The CPU 9 starts the transfer operation of each block image data in the block 2 in the B area to the read / display memory 11 in the same manner as the data read / transfer operation from the A area ((4) in FIG. 2). ▼).
[0042]
At this time, as described above, the write address generation circuit 3 resets the write address value to “0” in response to the command of the FLAG signal and corresponds to each of the n pixel data belonging to the next block 3. The write address signal (the values are 0, 1, 2, 3,..., N−1) are transferred to the memory control circuit 6 side together with each image data. As a result, the memory control circuit 6 returns to the beginning and writes each of the n pieces of pixel data belonging to the block 3 in the first storage area A of the camera memory 5 ((1) in FIG. 2).
[0043]
Step 5:
The image data of the last pixel belonging to the (m−1) th block within one screen of the camera-captured image is read from one storage area of the camera memory 5 and transferred. The series of operations described above is executed until the image data at the last pixel belonging to the block m is written into the other storage area of the camera memory 5. As soon as the image data at the last pixel belonging to the last block m is written into the other storage area of the camera memory 5, the CPU 9 reads each block image data belonging to the last block m.・ Transition to transfer operation.
[0044]
Since the last pixel of the camera image does not necessarily match the last pixel stored in the area A or B, the CPU 9 performs the final writing at the timing when the last pixel of the camera captured image is written to the camera memory 5. Start data read / transfer operation.
[0045]
Specifically, the block transfer control circuit 4 detects the timing at which the image data of the final pixel is transferred to the storage areas A and B to be stored, and the toggle signal (the FLAG signal in FIG. And the transfer timing by the CPU 9 is achieved at the timing of the rising edge / falling edge of the FLAG signal.
[0046]
As a reference example, the FLAG signal and the transfer timing of the CPU 9 or DMA are shown in the timing chart of FIG. In the figure, when the level of the FLAG signal is 'H', data is written to the A region and data is read from the B region. When the level of the FLAG signal is 'L', the data is read from the A region and the B region. Write data to. However, the pixel data belonging to the first block of one frame is written only in the A area, and the pixel data belonging to the last block of one frame is read from the A area when the block number m is an odd number. When the block number m is an even number, data is read from the B area.
[0047]
Here, regarding the reading / transfer of the image data from the camera memory 5, the CPU 9 may not read directly but the DMA controller 10 may perform such reading by DMA transfer. In this case, unlike the random read access request issued by the CPU 9, the DMAC 10 issues a read access request in which the address value to be read is defined in order from '0'. As described above, it is possible to realize a modification that can overcome the problem of delay time generation caused by arbitration processing. This improvement will be described below with reference to FIG.
[0048]
Normally, when there is a direct read access request from the CPU 9 or a read access request from the DMAC 10, a delay of several clocks occurs due to the arbitration process in the memory control circuit 6, and as a result, the CPU 9 or the DMAC 10 May cause a situation in which efficient transfer cannot be performed. Actually, in the case of a direct read access request by the CPU 9, since the read access request is at random, even if a read access request is transmitted from the CPU 9 to the read address generation circuit 7, a separate waiting time is provided. A generation circuit (not shown) waits for the CPU 9 to issue the next read access request for a period of several clocks.
[0049]
However, in the case of DMA transfer, the addresses defined by the read access requests issued from the DMAC 10 are in order, so that the read address generation circuit 7 receives “0” every time the read access request is received. The read address value can be generated by incrementing by “1” in order.
[0050]
Therefore, when reading each image data by DMA transfer from the target storage area of the camera memory 5 in which one block image data is stored by the current block transfer, the address value at the time of reading is “0”, “ .., “0”, and so on, before waiting for the read access request from the DMAC 10, the read address signal (pre-read read address) is set to “0”. The number of pixels corresponding to the delay time due to the arbitration process (several pixels) is pre-read from the target storage area of the camera memory 5 in advance by automatically generating several pixels in order from '. Then, the read address generation circuit 7 receives the read access request from the DMAC 10 for image data corresponding to the number of pixels corresponding to the delay time read in advance by the memory control circuit 6 according to the read ahead read address. During this period, the data is temporarily stored in the internal storage unit (for example, a register: not shown). Then, according to the timing when the read access request is made from the DMAC 10, the read address generation circuit 7 transfers the pre-read image data for several pixels to the CPU bus side without delay. With such an improvement, data can be transferred efficiently.
[0051]
For example, if the image data can be output from the camera memory 5 after the time of 3 clocks after the read access request by the arbitration process, the read address generation circuit 7 prefetches the data for 3 pixels. Keep it.
[0052]
Regarding the prefetch timing of the image data, the prefetching may be started when the FLAG INT signal in FIG. 3 is generated, and the DMAC 10 is activated when the prefetching of the required number of pixels is completed.
[0053]
A circuit responsible for such pre-reading control is the memory pre-reading control circuit 8, which is generated and outputted by the “read-ahead read for reading out several pixels of image data in advance from the write target storage area of the camera memory 5. The read address generation circuit 7 automatically generates the read address for prefetching in response to the prefetch control signal for instructing to generate an address.
[0054]
Next, consider a case where the image data stored in the display memory 11 is compressed by the CODEC engine 14 and the compressed image data is transferred to the storage memory 13. In this case, since the operator of the apparatus saves the image data after previewing the image data stored in the display memory 11, the camera is operated during the period when the CODEC engine 14 is operating. There is no need to preview the captured image. For this reason, once the camera-captured image is transferred to the display memory 11 for preview display, the image data in the camera memory 5 is not necessary.
[0055]
Therefore, by using the camera memory 5 as a dedicated memory for the CODEC engine 14, a dedicated CODEC memory is not provided, and the number of memories in the apparatus can be reduced.
[0056]
Therefore, in the present apparatus shown in FIG. 1, the CODEC engine 14 is also connected to the camera memory 5 so that signals can be exchanged with the camera memory 5 via the arbitration bus. Yes.
[0057]
Here, although the size of the camera memory 5 can be arbitrarily set according to the size of the block division, the size of the camera memory 5 is set to the memory size required for the CODEC engine 14 (of course, one frame). The capacity of minutes is not necessary). Then, an efficient memory size can be realized.
[0058]
<Advantages of this embodiment>
The advantages can be summarized as follows.
[0059]
(1) Since the camera-captured image is divided into a plurality of blocks and transferred, the storage capacity of the camera image memory 5 can be reduced to one frame or less.
[0060]
(2) Since the image data is pre-read from the memory 5 in advance before the data read request to the camera memory 5 is made, the image is immediately captured when the read request is made later. Image data can be transferred, and efficient data transfer from the camera memory 5 to the display memory 11 can be realized.
[0061]
(3) Since the camera memory 5 is used as a dedicated memory for the CODEC engine 14, the dedicated memory for the CODEC engine 14 can be reduced.
[0062]
(Appendix)
While the embodiments of the present invention have been disclosed and described in detail above, the above description exemplifies aspects to which the present invention can be applied, and the present invention is not limited thereto. In other words, various modifications and variations to the described aspects can be considered without departing from the scope of the present invention.
[0063]
For example, the number n of pixels included in each block divided by the block transfer control circuit 4 may be an arbitrary value for each block.
[0064]
The display device may be another flat display instead of the LCD, such as an organic EL display.
[0065]
Moreover, this apparatus is applicable to PDA (personal digital assistant) other than a mobile phone.
[0066]
The write address generation circuit may perform an operation of resetting the current write address value “n−1” to “0” every time the FLAG signal is received.
[0067]
【The invention's effect】
According to the subject of the present invention, since the camera-captured image is divided into a plurality of blocks and transferred to the camera memory, there is an effect that the capacity of the camera memory can be reduced to one frame or less.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a camera image processing apparatus according to Embodiment 1 of the present invention.
FIG. 2 is an image diagram showing an operation of the camera image processing apparatus according to the first embodiment.
FIG. 3 is a timing chart showing a block transfer operation in the camera image processing apparatus according to the first embodiment.
[Explanation of symbols]
1 camera module, 2 interface circuit, 3 write address generation circuit, 4 block transfer control circuit, 5 camera memory, 6 memory control circuit, 7 read address generation circuit, 8 memory prefetch control circuit, 9 CPU, 10 DMAC, 11 display Memory, 12 display LCD, 13 storage memory.

Claims (3)

An interface circuit for capturing an image captured by the camera for one frame;
A camera memory having a plurality of storage areas that together have a storage capacity of one frame or less;
A memory control circuit that controls data writing to the camera memory and data reading from the camera memory while performing arbitration processing in response to a write request and a read request, respectively;
The camera-captured image captured from the interface circuit is divided into a plurality of blocks, and image data of all pixels included in the block are sequentially transferred to the memory control circuit together with the write request for each block. Block data transfer / write control unit
In response to receipt of the write request, the memory control circuit is transferred to one write target storage area that is not currently being read out of the plurality of storage areas in the camera memory. Execute the operation to write each image data sequentially,
A display memory for temporarily holding the camera-captured image in order to display the camera-captured image on a display device;
The read request for instructing to sequentially read the image data in one block from the write target storage area is transferred to the memory control circuit according to the completion timing of the write operation in the write target storage area. At the same time, by sequentially transferring each of the image data in one block read from the write target storage area to the display memory, block data reading / writing to write all of the image data in one block to the display memory is performed. A transfer control unit,
The memory control circuit receives all pixel data belonging to the next block immediately following the block in accordance with the timing at which the memory control circuit starts the data read operation from the write target storage area in response to the read request. In this case, the plurality of storage areas are sequentially written in one storage area other than the write target storage area in which all the pixel data belonging to the block is already written.
Camera image processing device. The camera image processing apparatus according to claim 1,
The block data read / transfer controller is
A DMA controller that controls DMA transfer according to the completion timing of the write operation in the write target storage area;
In response to the completion timing of the write operation, the DMA controller sends a pre-read control signal instructing to generate a pre-read read address for pre-reading image data for several pixels from the write target storage area of the camera memory. A memory prefetch control circuit that outputs to the read address generation circuit in response to reception of a transfer timing signal generated by
In response to receiving the prefetch control signal, the prefetch read address is generated and the prefetch read address is output to the memory control circuit as the read request, and the memory control circuit is configured based on the prefetch read address. The image data for the several pixels read in advance from the write target storage area is held until a read access request is received from the DMA controller, and held in advance as soon as the read access request is received. A read address generation circuit that transfers the image data for the several pixels to the DMA controller side.
Camera image processing device. The camera image processing device according to claim 1 or 2,
Further comprising a CODEC engine that compresses the image data captured in the display memory while diverting the camera memory as a dedicated memory.
Camera image processing device.

Images