JP2005141637A - Memory management device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the disadvantage that, although virtual memory control can improve memory use efficiency, in an image processing apparatus with a plurality of processors, a load concentrates at a CPU performing the virtual memory control, and page mapping delays memory access to pose a fault in real time processing. <P>SOLUTION: A memory management device of improved memory use efficiency suitable for real time parallel processing has an interface for every processor to prevent a load concentration, has an exclusive register separate from the interfaces to ensure page mapping in a fixed time, and gives the interfaces a function of requesting page mapping to the register to allocate and release a page without the intervention of a CPU 5. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a memory management device.

  The following is an example of the conventional memory management device, which is the MMU described in Patent Document 1. FIG. 5 shows a simplified configuration of the image processing apparatus according to Patent Document 1. In FIG. 5, 11 is an image processing apparatus, 12 is a host computer, 13 is a CPU, 14 is an input buffer, 15 is an image compression circuit, 16 is an image expansion circuit, 17 is an MMU, 18 is a RAM, and 19 is an output buffer.

  The operation of the conventional configuration example will be briefly described below. Image data output from the host CPU 12 to the image processing apparatus 11 is temporarily stored in the input buffer 14. The CPU 13 reads the image data from the input buffer 14 and inputs it to the image compression circuit 17. The image compression circuit 17 performs compression conversion on the input image data to form compressed data. The CPU extracts the compressed data from the image compression circuit 17 and stores it in the RAM 18 via the MMU 17. When outputting an image, the CPU 17 reads the compressed data from the RAM 18 via the MMU 17 and inputs the compressed data to the image expansion circuit 16. The image decompression circuit 16 decompresses the compressed data and restores the original image data. The CPU extracts the image data from the image expansion circuit and stores it in the RAM 18 via the MMU 17. Further, the CPU reads out image data from the RAM 18 via the MMU 17 in accordance with a signal from the output buffer 19 and transfers it to the output buffer 19. Since the output buffer 19 outputs a signal corresponding to the amount of image data to be stored to the CPU, the CPU can adjust the transfer speed of the image data in accordance with the output speed of the output buffer 19.

  In this series of operations, the address output by the CPU 13 is a virtual address, the address input to the RAM 18 is a real address, and the role of the MMU 17 is to convert the virtual address into a real address. The mechanism of this address translation will be described with reference to FIG. FIG. 6 shows the correspondence between virtual addresses and real addresses. In FIG. 6, 20 is a virtual address, 21 is a real address, 22 is a lower bit, 23 is a virtual page number, and 24 is a real page number. The memory is managed for each page in units of 2 N bytes, and a page number is assigned to each of the virtual page and the real page. The (N + 1) th bit or more of the virtual address is the virtual page number 23, and the (N + 1) th bit or more of the real address is the real page number 24. The lower bit 22 is the same for the virtual address and the real address, and the conversion from the virtual address to the real address is performed by replacing the virtual page number with the real page number.

  Next, application of address translation in the conventional example and its effect will be described with reference to FIG. FIG. 7 is a diagram showing the relationship between the pages in the virtual address space and the pages in the real address space associated with each other by the MMU address translation table. In FIG. 7, 30 is a virtual memory space, 31 is a real memory space, 32 is a page management table, 33 is a virtual page, and 34 is a real page. The page management table 11 is a table that stores the presence / absence of a real page corresponding to each virtual page and the number of the real page, if any. The address conversion is performed by taking out the virtual page number from the virtual address, obtaining the corresponding real page number by referring to the page management table, and replacing the upper bits of the address with the real page number.

  The management and update of the page management table is the role of the CPU. When accessing a new virtual page, the CPU checks the presence or absence of a corresponding real page by accessing the page management table, and if not, searches for a real page that does not correspond to the virtual page and finds the actual page found. The page number is registered at the position of the new virtual page number in the page management table. Then, the virtual page becomes accessible from this point. Conversely, when the CPU deletes the registration of the position of a virtual page number in the page management table, the virtual page becomes inaccessible, and the corresponding real page is released and can be reassigned to another virtual page. .

  Of the virtual memory space, only virtual pages with corresponding real pages are actually accessible. Conversely, a real page does not have to correspond to a virtual page that is not accessed. When this is applied to a conventional image processing apparatus, only the portion that is output to the printer at each point of time needs to be accessed as image data, and the other portions are compressed data whenever necessary. Can be read and decompressed and written back to the real memory, the part of the image data that has been output to the printer is not accessed, and the part of the image data that has not yet been input from the host CPU is also accessed. Therefore, the required capacity of the real memory space may be smaller than the capacity for storing the entire image data.

In this way, by using the MMU, it is possible to make it appear that a memory having a larger capacity than the actual memory exists from the viewpoint of the CPU, and signal processing that requires a large memory capacity can be performed with a relatively small capacity. It can be executed using memory.
JP-A-5-227444

  An imaging device such as a digital still camera or a digital video camera requires a memory for storing the image data in the process from processing the image data photoelectrically converted by the imaging circuit to further compressing and recording the data. However, in recent years, with the improvement of image quality, it has become increasingly necessary to accommodate large amounts of memory to accommodate image data, and this can be efficiently accommodated in small-capacity memory using virtual memory technology. For example, a significant cost reduction can be realized. However, there is a great difficulty in using the conventional configuration for an imaging device.

  In the conventional configuration, there are an image compression circuit 5 and an image expansion circuit 6 as signal processing circuits in addition to the CPU 3. However, since the CPU 3 performs all data input / output of these signal processing circuits, a large load is concentrated on the CPU 3. . Further, since the processing speed of each signal processing circuit is limited by the input / output speed performed by the CPU 3, there is a problem that even if the performance of each signal processing circuit is improved, the overall processing performance is not directly improved. There is.

  Further, since the management and update of the page management table is the role of the CPU, it takes time to search for a free real page when accessing a new virtual page, and the entire processing stops during this time. There is also a problem.

  In a system such as a computer peripheral device described in Patent Document 1, since the transfer speed is determined on the data receiving side, the system does not fail even if the overall processing speed is low. In addition, since the data transfer is performed by a handshake procedure in the host interface and the printer interface, no data is lost even if the entire system is temporarily stopped due to the update of the page management table. However, an imaging apparatus such as a digital still camera or a digital video camera needs to process image data every few tens of nanoseconds and process it at high speed without delay. In a memory control system that stops, correct operation cannot be expected.

  The present invention is a memory management device that performs virtual memory management by paging to solve the above-described problem, and includes an arbitration circuit, a corresponding registration circuit, and a plurality of processor interfaces. The processor interface includes an address conversion buffer, and the address The conversion buffer has a function of storing a correspondence between at least a pair of real pages and virtual pages, and converts a virtual address into a real address according to the correspondence, and the correspondence registration circuit includes all real pages and virtual pages. The processor interface has a function of requesting access to the correspondence registration circuit, and the arbitration circuit gives an access right to one of the requested processor interfaces. When the access right is obtained Is intended to access the register circuit, a memory management unit, characterized in that a plurality of processors can access the virtual memory space.

  The corresponding registration device can always complete the operation within a certain time for a request for corresponding reference or deletion, and can complete the operation within a certain time as long as there is an empty page for the registration request. . Therefore, the memory management device of the present invention can be applied to processing with extremely high real-time characteristics where delay is not allowed, such as taking in data from an imaging circuit, and used real pages are released without delay by each processor interface. Therefore, the memory can be used efficiently.

  The invention according to claim 1 of the present invention is a memory management device that performs virtual memory management by paging, comprising an arbitration circuit, a corresponding registration circuit, and a plurality of processor interfaces, wherein the processor interface comprises an address translation buffer, The address conversion buffer has a function of storing a correspondence between at least a pair of real pages and virtual pages, and converts a virtual address into a real address according to the correspondence, and the correspondence registration circuit includes all real pages. A function of storing a correspondence with a virtual page, the processor interface has a function of requesting access to a correspondence registration circuit, and the arbitration circuit gives an access right to one of the requested processor interfaces; When the processor interface gains the access right, Since it is a memory management device that accesses the corresponding registration circuit and has a feature that a plurality of processors can access the virtual memory space, the address conversion load is distributed to the processor interface for each processor, so the address It has the effect that conversion does not become a bottleneck.

  The invention according to claim 2 of the present invention is the memory management device according to claim 1, wherein at least one processor interface stores a function of storing a virtual page number accessed by the processor in the past, and the stored virtual A function of comparing a page number and a virtual page number requested by the processor, and a function of accessing the correspondence registration circuit according to the comparison result and registering a correspondence between the real page and the virtual page Since the processor interface registers the correspondence between the real page and the virtual page by itself, it is not necessary to wait for the registration of the correspondence by the specific processor, so that the correspondence between the real page and the virtual page can be reduced. It has the effect that registration does not become a bottleneck.

  According to a third aspect of the present invention, in the memory management device according to the first or second aspect, at least one processor interface accesses the correspondence registration circuit according to the detection result, and in particular, the processor has accessed in the past. The memory management device has a function of deleting the correspondence between the virtual page and the real page, and the real page is unnecessarily restrained because the processor interface immediately releases the real page that has been accessed. Has the effect of eliminating.

  The invention according to claim 4 of the present invention is the memory management device according to any one of claims 1 to 3, wherein the correspondence registration circuit includes at least a page management table and a page search device, and the page management table includes all of the page management tables. The memory management device stores a correspondence between a real page and a virtual page, and the page search device has a function of accessing a page management table and searching for a real page having no corresponding virtual page. In addition, by integrating the page search device with the page management table, the total of circuits for page search can be reduced and the search speed can be increased.

The invention according to claim 5 of the present invention is the memory management device according to claim 4, wherein the page search device accesses the page management table during a period when there is no access from the processor interface, and the corresponding virtual page. A memory management device characterized by having a function of searching for a real page with no page, and using a period when there is no access from the processor interface, there is no corresponding virtual page prior to a request from the processor interface, By searching for a real page, it is possible to immediately respond with a real page number when a search for a free real page is requested from the processor interface, and registering the correspondence between the real page and the virtual page The time that the processor interface waits at the time of Having.
(Embodiment)
Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a digital still camera using a memory management device according to the present invention. In FIG. 1, 1 is an imaging circuit, 2 is a YC processing circuit, 3 is a compression processing circuit, 4 is a recording circuit, 5 is a CPU, 6 is an MMU, and 7 is a memory circuit, of which the MMU 6 is a memory management device according to the present invention. It is. Each of the circuits 1 to 5 has a function of accessing the memory circuit 7, and all accesses to the memory circuit 7 are performed via the MMU 6.

  Hereinafter, the operation as a digital still camera will be briefly described with reference to FIG. The imaging circuit 1 includes a photoelectric conversion element such as a CCD, and converts an incident light image into input image data. Input image data output from the imaging circuit 1 is stored in the memory circuit 7 via the MMU 6. The YC processing circuit 2 reads input image data from the memory circuit 7 via the MMU 6, converts it into YC data suitable for compression, and writes it back to the memory circuit 7 again via the MMU 6. The compression processing circuit 3 reads the YC data from the memory circuit 7 via the MMU 6 and performs compression conversion, and writes the generated compressed file back to the memory circuit 7 via the MMU 6 again. The recording circuit 4 reads the compressed file from the memory circuit 7 via the MMU 6 and stores it in the flash memory. The CPU controls the circuits 1 to 4 in FIG. 1 and accesses the memory circuit 7 via the MMU 6 to operate the header portion of the compressed file. The circuits 1 to 4 in FIG. 1 can operate independently of the CPU. In particular, the imaging circuit 1, the YC processing circuit 2, and the compression processing circuit 3 can execute processing for one screen without intervention of the CPU. The MMU 6 performs address conversion at the time of access, holds the address relay for the time required for address conversion, and relays the access to the memory circuit 7 only when the address conversion is successful. The memory circuit 7 is a memory system that can accept a plurality of access requests, and the circuits 1 to 4 in FIG. 1 can access the memory independently and in parallel.

  FIG. 2 is a block diagram illustrating the configuration of the MMU and particularly the role of the arbitration circuit. In FIG. 2, reference numerals 40 to 44 denote processor interfaces, 45 denotes an arbitration circuit, and 46 denotes a correspondence registration circuit. Hereinafter, the role of the arbitration circuit will be described with reference to FIG.

  In this configuration, the same number of processor interfaces as the number of processors accessing the memory are provided, each having a function of performing address conversion and a function of accessing the corresponding registration device. Since each processor operates independently, access to the corresponding registration device may occur simultaneously. In such a case, it is the role of the arbitration circuit to arbitrate a plurality of requests and execute access one at a time. In FIG. 2, arrows from the processors 40, 41, and 43 to the arbitration circuit are indicated by solid lines, and this represents a case where three requests are generated simultaneously. There are various methods for controlling the priority in the arbitration circuit. In this embodiment, the method of fixing the priority of the processor interface is adopted, and the highest priority among the requested processor interfaces is accessed. It is controlled to give the right. In FIG. 2, an arrow from the arbitration circuit 45 to the processor interface 41 is indicated by a solid line, and this indicates that an access right is granted. The example of FIG. 2 shows a state in which only the processor interface 41 obtains the access right and accesses the correspondence registration device 46 as a result of the arbitration.

  FIG. 3 is a diagram showing a configuration example of the processor interface. In FIG. 3, 50 is a processor, 51 is one processor interface, 52 is an arbitration circuit, 53 is a corresponding registration device, 54 is a memory device, 55 is an address valid signal of a virtual address, 56 is a low-order address bit, and 57 is a high-order virtual address Bit, 58 is a control circuit, 59, 60 and 63 are registers, 61 is an upper bit of the real address, 62 is an address valid signal of the real address, 64 is a selector, and 65 is a real page number.

  Hereinafter, the operation accompanying the address conversion of the processor interface will be described with reference to FIG. The control circuit 58 of the processor interface monitors the address valid signal of the virtual address output from the processor 50, and if the address is valid, compares the virtual address upper bit 57 with the virtual page number stored in the register 59. The register 59 stores the virtual address upper bits 57 in the previous access as a virtual page number under the control of the control circuit 58. Therefore, when the comparison result is coincident, the virtual address upper bits are the same as the previous access. The register 60 stores the actual page number in the previous access under the control of the control circuit 58 and outputs this as the actual address upper bits 61. Therefore, if the comparison result is coincident, the effective signal 62 of the actual address is immediately output. Output. As a result, the memory circuit 54 accesses the real address.

  If the previous comparison result does not match, the virtual address upper bit 57 is different from the previous access, so it is necessary to obtain a new real page number corresponding to the new virtual page number. For this purpose, since access to the corresponding registration device is required, the control circuit 58 first requests an access right to the arbitration circuit 52 and waits until the access right is obtained. When the access right is given from the imperial court circuit 52, the control device 58 controls the selector 64 to output the virtual address upper bit 57 as the virtual page number 65 to the corresponding registration circuit 53, and at the same time, the corresponding reference request code is sent to the registration device 53. Output. The correspondence registration device 53 has a function of outputting a real page number 66 corresponding to the virtual page number 65 in accordance with the correspondence reference request code. If the real page number 66 is obtained from the corresponding registration device 53, it is stored in the register 60, and at the same time, the contents of the register 59 are saved in the register 63, and at the same time, the virtual address upper bit 57 is stored in the register 59. Then, since the virtual address upper bit 57 and the output of the register 59 match, the valid signal 62 of the real address is output at this point.

  If the processor 50 is the recording circuit 4 in FIG. 1, the accessed virtual page does not need to be accessed thereafter, so the real page is immediately released. For this purpose, the register 59 stores the immediately preceding virtual page number, and the control circuit 58 immediately switches the selector 64 to the output of the register 63 after saving the actual page number 66 and outputs the immediately preceding virtual page number to the corresponding registration device. At the same time, the control device 58 outputs a corresponding deletion request code to the registration device 53. The correspondence registration device 53 has a function of canceling the correspondence designated by the virtual page number 65 in accordance with the correspondence deletion request code.

  If the processor 50 is the imaging circuit 1 in FIG. 1, it is necessary to continue access without delay even when there is no real page corresponding to the accessed virtual page. Therefore, the control circuit 58 outputs a correspondence registration request code to the correspondence registration circuit 53 at the same time when the virtual page number 66 is outputted to the correspondence registration circuit 53. The correspondence registration circuit 53 has a function of associating a real page having no correspondence relationship with the requested virtual page according to the correspondence registration request code.

  FIG. 4 is a block diagram illustrating the configuration of the correspondence registration apparatus in the present embodiment. In FIG. 4, 53 is a corresponding registration device, 70 is a selector, 71 is a control device, 73 is a correspondence table, 74 is a valid bit table, 75 is an empty page table, 76 is a selected request code, and 77 is a selected virtual page. No. 79, actual page number, 80 valid bit, 81 response code, 82 loadable counter, 83 address, 85 bit data, 86 free page number. Hereinafter, the operation of the correspondence registration apparatus will be described with reference to FIG.

  The selector 70 selects and outputs an input with a valid request code among the inputs from the plurality of processor interfaces. The selected virtual page number 77 is input as an address to the correspondence table 73 and the effective bit table 74. The correspondence table 73 stores a real page number corresponding to the virtual page number, and the valid bit table 74 stores the presence / absence of a real page corresponding to the virtual page number. The real page number corresponding to the selected virtual page number 77 is stored. 79 and a valid bit 80 are output. Here, if the valid bit is 1, it is valid. The control device 71 monitors the valid bit 80. If it is 1, it outputs a success code as a response code 81, and if it is 0, it outputs a failure code. The response code 81 is output only to the processor interface outputting a valid request code by the selector 70. The real page number 79 is output to all the processor interfaces, and is received by the processor interface that has received the success code.

  If the request code 76 is a correspondence deletion request code, the control device 71 writes 0 in the valid bit table 74 and loads the real page number 79 output from the correspondence table 73 into the loadable counter 82. Here, the loadable counter 82 has a function of performing one of loading and incrementing according to the instruction of the control signal 84. In incrementing, since the upper bits of the sixth and higher bits are counted up from the LSB, the output increases by 32. Next, the control device 71 operates the effective bit table. The effective bit table 74 stores the presence / absence of corresponding virtual pages for all real page numbers in one bit, and is stored in a 32-bit wide RAM. If each bit is 1, it indicates correspondence and can be specified by an address and a bit position. The value of the loadable counter 82 is input to the control circuit 71, and the control circuit 71 outputs the higher-order bits of the 6th and higher bits as the address 83 to the effective bit table 74. In response to the deletion request code, the control device 71 reads the 32-bit data 83 from the valid bit table 74, sets the bit at the position indicated by the fifth and lower bits of the loadable counter output to 0, and writes it back to the same address. At this time, the real page corresponding to the designated virtual page becomes an empty page, and the registration deletion is completed. Therefore, the control circuit 71 outputs a success code.

  The control circuit 71 reads the 32-bit data 83 even when no valid request code is received, and repeats the operation of incrementing the loadable counter 82 by 32 if all bits are 0. As a result, as long as there is an empty page, the loadable counter 82 points to an address where the empty page can be referred to and stops. In this way, if an empty page is found in advance, registration is possible without delay when necessary. Further, in this configuration, 32 pages of free pages can be searched, so that the search can be completed in a much shorter time than the method of searching for free pages one by one.

  If the request code 76 is a corresponding registration request code, the control device 71 reads the 32-bit data 83, and if there is a bit of 1, obtains a free page number 86 from the bit position and address of the least significant bit. Are simultaneously written in the correspondence table 73, and 1 is written in the effective bit table 74, and the least significant bit of 1 in the 32-bit data 83 is set to 0 and written back to the same address. At this point, the number of empty pages is reduced by one, and the empty page number 86 is associated with the selected virtual page number 77 and is output as the real page number 79, so the control device 71 outputs a success code. If the 32-bit data 83 is all 0s, the loadable counter 82 is incremented by 32, the next 32-bit data 83 is read, the above operation is performed if there is a bit of 1, and if not, the number of times the counter makes a round The increment is repeated up to. If there is no bit which is 1 even if the counter makes a round, the control circuit outputs a failure code at that time.

  With the configuration and operation as described above, the corresponding registration device can always complete the operation within a certain time in response to a request for corresponding reference or deletion, and for a certain time as long as there is an empty page for the registration request. Within the operation can be completed. Therefore, the memory management device of the present invention can be applied to processing with extremely high real-time characteristics where delay is not allowed, such as taking in data from an imaging circuit, and used real pages are released without delay by each processor interface. Therefore, the memory can be used efficiently.

  The memory management device according to the present invention can be applied to processing with extremely high real-time characteristics in which delay is not permitted, such as data fetching from an imaging circuit, and each used real page is Since the memory interface can be used efficiently because it is released without delay by the processor interface, it can be applied to a digital camera, a mobile phone terminal, and the like.

The block diagram which shows the structure of the digital still camera using the memory management apparatus by this invention Block diagram explaining the configuration of the MMU and in particular the role of the arbitration circuit Block diagram showing a configuration example of the processor interface Block diagram for explaining the configuration of the correspondence registration apparatus in the present embodiment A block diagram showing a configuration of an image processing apparatus using a conventional memory management apparatus Explanatory diagram showing the correspondence between virtual addresses and real addresses Explanatory diagram showing the relationship between pages in the virtual address space and pages in the real address space

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Imaging circuit 2 YC processing circuit 3 Compression processing circuit 4 Recording circuit 5 CPU
6 MMU
7 Memory Circuit 11 Image Processing Device 12 Host Computer 13 CPU
14 Input buffer 15 Image compression circuit 16 Image expansion circuit 17 MMU
18 RAM
19 Output buffer 20 Virtual address 21 Real address 22 Lower bit 23 Virtual page number 24 Real page number 30 Virtual memory space 31 Real memory space 32 Page management table 33 Virtual page 34 Real pages 40, 41, 42, 43, 44 Processor interface 45 Arbitration Circuit 46 Corresponding Registration Circuit 50 Processor 51 Processor Interface 52 Arbitration Circuit 53 Corresponding Registration Device 54 Memory Device 55 Virtual Address Address Valid Signal 56 Address Lower Bit 57 Virtual Address Upper Bit 58 Control Circuit 59, 60, 63 Register 61 Real Address Upper bit 62 Address valid signal of real address 64 Selector 65 Real page number 70 Selector 71 Controller 73 Corresponding table 74 Valid bit table 75 Empty page Table 76 selected request code 77 selected virtual page number 79 real page number 80 valid bits 81 response code 82 loadable counter 83 address 85 32-bit data 86 empty page number

Claims (5)

A memory management device for performing virtual memory management by paging, comprising an arbitration circuit, a corresponding registration circuit, and a plurality of processor interfaces, the processor interface comprising an address translation buffer, and the address translation buffer comprising at least a pair of real pages and a virtual Has a function of storing the correspondence with pages, and converts a virtual address into a real address according to the correspondence, and the correspondence registration circuit has a function of storing the correspondence between all real pages and virtual pages. The processor interface has a function of requesting access to the corresponding registration circuit, and the arbitration circuit arbitrates the access requests from a plurality of processors, and gives the access right to the corresponding registration circuit to one processor interface at a time. And the process that gained the access right. Sa interface is intended to obtain the correspondence between the access to the corresponding register circuit and real page virtual page, a memory management device, characterized in that a plurality of processors can access the virtual memory space. 2. The memory management device according to claim 1, wherein at least one processor interface has a function of storing a virtual page number accessed by the processor in the past, and the stored virtual page number and the processor requesting access. A memory management device having a function of comparing the number of a virtual page, and a function of accessing the correspondence registration circuit according to the comparison result and registering a correspondence between a real page and a virtual page. 3. The memory management device according to claim 1, wherein at least one processor interface accesses the correspondence registration circuit according to the detection result, and in particular erases the correspondence between a virtual page and a real page accessed by the processor in the past. A memory management device having a function. 4. The memory management device according to claim 1, wherein the correspondence registration circuit includes at least a page management table and a page search device, and the page management table corresponds to all real pages and virtual pages. And the page search device has a function of accessing a page management table and searching for a real page having no corresponding virtual page. 4. The memory management device according to claim 1, wherein the correspondence registration circuit includes at least a page management table, an empty page table, and a page search device, and the page management table includes all real pages and virtual pages. The empty page table stores the presence / absence of the correspondence with the virtual page for each real page, and the page search device accesses the empty page table to correspond to the virtual page. A memory management device having a function of searching for a real page having no content.

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