JP2012088894A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor that enables safe access control using a virtual address space without largely changing processing content of an OS.SOLUTION: In a data processor (1, 2 and 3), when a circuit module (11, 31 and 41) accessed with a physical address and executing access control with a virtual address starts to operate according to a condition set by a central processing unit through a memory management part (16, 36 and 46) for performing processing for address conversion from a virtual address to a physical address, processing for changing association between a virtual address space and a physical address space at that time by the central processing unit is stopped.

Description

  The present invention relates to a data processing apparatus including a central processing unit and a peripheral circuit module, and more particularly to a technique effective when applied to a data processing apparatus compatible with access control using a virtual address space by a peripheral circuit module.

  In recent years, large-scale integrated circuits (LSIs), which are the core of these information device systems, have been identified as small information devices such as mobile phones, portable navigation devices, and portable terminals for business use. In order to execute the above processing at high speed, a dedicated processing circuit module has been built in separately from a central processing unit (CPU (Central Processing Unit)). Examples of the dedicated processing circuit module include a dedicated circuit for performing compression / decompression processing of image data and audio data, a DMA controller for DMA (Direct Memory Access) transfer, and the like. Some processor systems incorporating such dedicated processing circuit modules enable access control using virtual addresses by the dedicated processing circuit modules in order to protect the memory and improve the efficiency of memory utilization.

  Patent Document 1 discloses an example of access control using a virtual address space by the dedicated processing circuit module. The processor system of Patent Document 1 includes a CPU, a DMA controller for DMA transfer, and a DMA transfer address converter. When the DMA controller performs DMA transfer, it is stored in advance in the DMA transfer address converter. Address translation is performed using the address translation information indicating the correspondence between the virtual address and the physical address. As a result, in the processor system, the DMA controller eliminates the process of converting the virtual address into the physical address, and the processing speed of the software is improved.

Japanese Patent Laid-Open No. 5-120205

  In the above-mentioned information device, in order to increase the development efficiency of the increasing software, a general-purpose OS (Operating System) equipped with an inter-process protection function by operating a plurality of programs in multiple processes and allocating a virtual space for each process. Increasing use cases. However, such a general-purpose OS often does not support access control using the virtual address space of the dedicated processing circuit module. Therefore, when an information device including an LSI incorporating the dedicated processing circuit module in addition to the CPU adopts the general-purpose OS described above, software due to a decrease in processing performance, an increase in software development man-hours, and partial protection functions do not work. There is a possibility that problems such as a decrease in general safety may occur. For example, in the case where the processor system of Patent Document 1 employs a general-purpose OS that allocates a virtual space for each process, when the OS switches to processing related to another process during DMA transfer by the DMA controller, the MMU (Memory Management Unit) is used. The address conversion information stored in () is switched from information related to DMA transfer to information related to the other process. At this time, the DMA controller and the CPU can perform processing in parallel, but the processor system does not have means for dynamically updating the address conversion information of the DMA transfer address converter, and generally the CPU does not. Since the built-in memory management unit (MMU) and the DMA transfer address converter are not linked, the address conversion information of the MMU and the DMA transfer address converter does not match, and corresponds to the virtual address space used by the DMA controller. Inconsistency may occur in the physical address space. That is, in such a processor system, it is impossible to safely perform DMA transfer using a virtual address for a memory area dynamically allocated by the OS. The above problem is, for example, a system configuration in which the CPU and the DMA controller, which are dedicated processing circuit modules, share the MMU, and the OS distinguishes between the CPU and the DMA controller for exception handling for address translation errors or protection violations that occur in the MMU. It can be solved by making it executable. In order for the OS to execute such processing, it is necessary to greatly modify the OS program. However, the modification of the general-purpose OS is particularly difficult, and is accompanied by great difficulty in terms of the right to modify the general-purpose OS and the operation guarantee.

  An object of the present invention is to provide a data processing apparatus that enables safe access control using a virtual address space without greatly changing the processing contents by the OS.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  In other words, the data processing apparatus is accessed by a physical address, and a circuit module that performs access control using a virtual address uses a central processing unit via a memory management unit that performs processing for converting the virtual address into a physical address. When the operation is started in accordance with the set condition, the process of changing the correspondence between the virtual address space and the physical address space at that time by the central processing unit is suppressed.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the data processing apparatus can perform safe access control using the virtual address space without significant change in the processing contents by the OS.

FIG. 1 is a block diagram of the microprocessor according to the first embodiment. FIG. 2 is an explanatory diagram showing an example of the configuration of the TLB 161 used for address conversion by the memory management unit 16. FIG. 3 is a flowchart showing an example of TLB miss exception processing by the OS. FIG. 4 is a block diagram showing an example of the internal configuration of the dedicated processing circuit module 11. FIG. 5 is an example of a timing chart when the dedicated processing circuit module 11 executes processing. FIG. 6 is an explanatory diagram showing operation states of the CPU core unit 10 and the dedicated processing circuit module 11 when the dedicated processing circuit module 11 executes processing. FIG. 7 is a block diagram of a microprocessor according to the second embodiment. FIG. 8 is a block diagram of a microprocessor according to the third embodiment. FIG. 9 is a block diagram of a microprocessor according to the fourth embodiment.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] (When the circuit module operates using the virtual space, the CPU does not change the virtual space (FIGS. 1, 7, and 8))
A data processing device (1, 2, 3) according to a representative embodiment of the present invention is accessed by a physical address and a central processing device (10) that performs access control using a virtual address, and the virtual address is Circuit module (11, 31, 41) that performs access control using the memory management unit that performs processing for converting the virtual address output from the central processing unit and the virtual address output from the circuit module into a physical address (16, 36, 46), and when the circuit module starts operating according to the conditions set by the central processing unit via the memory management unit, the central processing unit The process of changing the correspondence between the virtual address space and the physical address space at that time is suppressed.

  According to this, since the correspondence between the virtual address space used by the circuit module and the physical address space is not changed while the circuit module is operating, the physical address space corresponding to the virtual address space used by the circuit module is not changed. There is no inconsistency.

[2] (CPU processing stopped by the stall signal asserted by the circuit module (FIGS. 1 and 5))
In the data processing device according to item 1, the circuit module (11) starts an operation in response to execution of a predetermined instruction for setting the condition by the central processing device, asserts a stall signal (stlp), and The central processing unit suspends execution of the instruction when the stall signal is asserted.

  While the stall signal is asserted, the central processing unit does not perform a new instruction fetch. As a result, it is possible to easily suppress processing for changing the correspondence between the virtual address space and the physical address space. In other words, it is possible to suppress processing for changing the correspondence between the virtual address space and the physical address space without the OS being actively involved.

[3] (Instruction to set start register (Fig. 1))
In the data processing device according to Item 2, the circuit module includes a control register (1151) in which a start bit for starting an operation is set, and the predetermined instruction is transmitted to the control register via the memory management unit. This command sets the start bit.

[4] (Conditions for stall signal negation (FIGS. 1, 4, and 6))
In the data processing device according to item 3, the circuit module negates the stall signal due to an error in the process for converting the address for the access control using the virtual address by the circuit module.

  According to this, the central processing unit can be released from a state in which execution of instructions is pending and can execute exception processing.

[5] (Exception handling (FIGS. 1 and 6))
In the data processing device according to Item 4, when the error occurs, the memory management unit issues an exception processing request (excp), the circuit module stops the operation according to the predetermined instruction, and the central processing unit The processing device executes exception processing for the error in response to the exception processing request, and executes processing for restarting the operation of the circuit module after the exception processing is completed.

  According to this, an error in the operation of the circuit module is eliminated as a result of the exception processing by the OS, and the operation can be resumed.

[6] (Process resumption by instruction re-execution by CPU (FIGS. 1, 4, and 6))
In the data processing device according to item 5, the process of restarting the operation of the circuit module is a process of re-executing the predetermined instruction.

  According to this, the operation can be easily restarted by the circuit module.

[7] (CPU processing stopped by asserting stall signal by MMU (FIGS. 7 and 8))
In the data processing device according to item 1, the circuit module starts an operation in response to execution of a predetermined instruction for setting the condition by the central processing unit, and the memory management unit (36, 46) A stall signal (stlc2) is asserted in response to the execution of the instruction, and the central processing unit suspends execution of the instruction when the stall signal is asserted.

  While the stall signal is asserted, the central processing unit does not perform a new instruction fetch. As a result, it is possible to easily suppress processing for changing the correspondence between the virtual address space and the physical address space.

[8] (Instruction to set start register (FIGS. 2, 7, and 8))
In the data processing device according to item 7, the circuit module includes a control register in which a start bit for starting an operation is set, and the predetermined instruction is transmitted to the start bit of the control register via the memory management unit. Is an instruction to set

  According to this, similarly to the item 3, during the operation by the circuit module, the OS can be recognized as a state in which the process of setting the start bit of the control register by the central processing unit is being executed.

[9] (Exception handling (FIGS. 7 and 8))
In the data processing device according to item 8, when an error occurs during the address conversion process for the access control using the virtual address by the circuit module, the memory management unit negates the stall signal (stlc2). An exception handling request is issued, the circuit module stops the operation according to the predetermined instruction in response to the exception handling request, and the central processing unit performs exception handling for the error in response to the exception handling request. Execute.

  According to this, when the memory management unit negates the stall signal, the central processing unit can be released from the instruction execution pending state and execute exception processing. Further, the exception processing by the OS eliminates an error in the operation of the circuit module as a result, and the operation can be resumed.

[10] (Restart circuit module processing (FIG. 7))
In the data processing device according to item 9, after the completion of the exception processing, the central processing unit executes processing for resuming the operation of the circuit module (31).

[11] (Process resumed by instruction re-execution by CPU (FIG. 7))
In the data processing device according to item 10, the process of restarting the operation of the circuit module is a process of re-executing the predetermined instruction.

[12] (Process restart by MMU (process restart signal rgm) (FIG. 8))
In the data processing device according to item 9, when the processing for eliminating the error is completed in the exception processing, the memory management unit (46) executes processing for restarting the operation of the circuit module (41).

  For example, in an exception process for an address translation error, the memory management unit causes the circuit module to resume operation when the update of the TLB address translation information is completed. According to this, it is possible to restart the processing of the circuit module earlier than in the case where the circuit module restarts the operation after a series of processing in the exception processing is completed.

[13] (Second TLB (FIG. 9))
A data processing device (4) according to a representative embodiment of the present invention has a central processing unit (10) that performs access control using a virtual address, and is accessed by a physical address and is controlled by using a virtual address. And a first address translation pair (161) for translating a virtual address into a physical address, and performing a process for address translation using the first address translation pair. 1 memory management unit (52) and a second address translation pair (501) having all or part of the first address translation pair as an entry, and the circuit module outputs using the second address translation pair A data processing device comprising: a second memory management unit (50) for executing a process for converting a virtual address to a physical address, When the circuit module starts operating according to the condition set by the central processing unit via the first memory management unit, the central processing unit changes the correspondence between the virtual address space and the physical address space at that time Is suppressed.

  According to this, similarly to the item 1, there is no inconsistency in the physical address space corresponding to the virtual address space used by the circuit module. For example, when the operating frequency of the circuit module is lower than the operating frequency of the central processing unit, one memory management unit performs access control for access from the central processing unit and access from the circuit module. In this case, the memory management unit needs to be designed so as to be compatible with the higher operating frequency. As a result, the memory management unit needs to operate a circuit with high power consumption designed for a high frequency even during operation of the circuit module with a low operating frequency, in terms of heat generation and power consumption. It is disadvantageous. In addition, the circuit scale of the memory management unit is increased compared with the case of designing only for access from the central processing unit, and the maximum operating frequency is reduced due to an increase in circuit delay. But it is disadvantageous. Therefore, as in the data processing device according to item 13, the second memory is provided by including two memory management units, the first memory management unit and the second memory management unit for controlling access from the circuit module. The operating frequency of the management unit can be optimized according to the circuit module, and the increase in the circuit size of the first memory management unit can be suppressed to prevent a reduction in the operating frequency. Contribute to

[14] (Processing by the first MMU at the time of TLB miss in the second MMU)
In the data processing device according to item 13, when the second memory management unit does not find an entry necessary for address conversion during the process for address conversion for access control using a virtual address by the circuit module, The first memory management unit is notified of the fact, and the first memory management unit searches the first address translation pair in response to the notification. Is registered in the second address translation pair and the second memory management unit is caused to execute the address translation process again. If a necessary entry is not found as a result of the search, an exception handling request is issued. .

  By causing the first memory management unit to perform the response process for the error in the access by the circuit module, not the second memory management unit, the function of the second memory management unit can be simplified and the scale can be reduced.

2. Details of Embodiments Embodiments will be further described in detail.

<< Embodiment 1 >>
FIG. 1 is a block diagram of a microprocessor according to an embodiment of the present invention.

  A microprocessor 1 shown in the figure is a microprocessor for a portable information terminal, for example. The microprocessor 1 realizes the function of a portable information terminal by being connected to a storage device such as a RAM (Random Access Memory) and a ROM (not shown) and an external I / O.

  The microprocessor 1 includes a CPU core unit 10 that is an execution subject of the OS and application programs, a dedicated processing circuit module 11 that executes predetermined processing on behalf of the CPU core unit 10, and an address conversion between a virtual address and a physical address. And a memory management unit (MMU) 16 that performs memory protection. The CPU core unit 10, the dedicated processing circuit module 11, and the memory management unit 16 are connected by a CPU bus 17 including a CPU address bus (ca) and a CPU data bus (cd). The microprocessor 1 also includes a cache memory 15, an external bus controller (BSC) 14, a timer unit (Timer) 13, and an interrupt controller (INTC) 12 as other functional units. These functional units are connected to the memory management unit 16 and the dedicated processing circuit module 11 by an internal bus 18 composed of an internal address bus (ia) and an internal data bus (id).

  The microprocessor 1 uses an operating system (OS) that is basic software. The OS program is stored in a storage device such as a ROM (Read Only Memory) and is executed by the CPU core unit 10. The CPU core unit 10 performs control of scheduling of a plurality of application software, memory management, management of external I / O, and the like by executing an OS program. The plurality of application softwares are assigned virtual address spaces independent from each other by the OS, and operate using the virtual address spaces. The plurality of application software is executed by the CPU core unit 10, and the CPU core unit 10 causes the dedicated processing circuit module 11 to execute a part of processing in the software.

  Access from the CPU core unit 10 and the dedicated processing circuit module 11 is performed by a virtual address, and the access is performed via the memory management unit 16. Specifically, the CPU core unit 10 and the dedicated processing circuit module 11 issue an access request by outputting a virtual address to the CPU bus 17. The memory management unit 16 that has received the access request converts the virtual address associated with the access request into a corresponding physical address. Then, the memory management unit 16 accesses the dedicated processing circuit module 11, the interrupt controller 12, the external bus controller 14, and the timer unit 13 by outputting the access request on the internal bus 18 with a physical address. Communicate the request.

  Hereinafter, each functional unit of the microprocessor 1 will be described in detail.

  The CPU core unit 10 controls each functional unit by accessing a control register for each functional unit via the memory management unit 16. For example, when the CPU core unit 10 executes an instruction that causes the dedicated processing circuit module 11 to execute a specific process, the CPU core unit 10 outputs a virtual address specified by the instruction on the CPU bus 17. Make an access request. The memory management unit 16 that has received the access request outputs the access request to the internal bus 18 with the physical address obtained by converting the address. The dedicated processing module 11 that has received the access request from the internal bus 18 sets a predetermined value in the control register 1151 described later. As described above, the dedicated processing circuit module 11 starts processing.

  Further, the CPU core unit 10 accesses a peripheral circuit such as a RAM or a ROM connected to an external bus 19 including an external address bus (ea) and an external data bus (ed) via the external bus controller 14. As a result, instructions necessary for software execution are read and various data are input / output. Further, the CPU core unit 10 executes interrupt processing in response to the interrupt signal int, and executes exception processing in response to an exception processing request signal (excp) from the memory management unit 16. Details of the exception processing will be described later. The interrupt processing and exception processing are executed in privileged mode.

  The external bus controller 14 is connected to the internal bus 18 and to the external bus 19, and is connected between the microprocessor 1 and an external storage device such as RAM and ROM and other external I / O via the external bus 19. Control for data transfer.

  The timer unit 13 outputs a signal (intt) for requesting a timer interrupt to the interrupt controller 12 at regular intervals.

  The interrupt controller 12 receives an interrupt request (intp) from the dedicated processing circuit module 11, an interrupt request (intt) from the timer unit 13, and an interrupt request (into) from an external device, etc., and performs arbitration, and the CPU core An interrupt signal (int) for requesting interrupt processing is output to the unit 10. Specifically, the interrupt controller 12 inputs the respective interrupt requests (intp signal, intt signal, into signal), a state indicating whether or not the CPU core unit 10 is capable of interrupting, the reception priority level, When the interrupt acceptance condition is satisfied, an interrupt signal (int) is output to the CPU core unit 10.

  As described above, the memory management unit 16 is connected to the CPU core unit 10 and the dedicated processing circuit module 11 via the CPU bus 17, and is connected to the dedicated processing circuit module 11, the interrupt controller 12, and the external bus controller via the internal bus 18. 14 and the timer unit 13. Further, the memory management unit 16 is connected to the cache memory 15 by a cache bus 20 including a cache address bus (ma) and a cache data bus (md). Access to the cache memory 15 is compatible with both virtual addresses and physical addresses.

  The memory management unit 16 includes a TLB (Translation Lookaside Buffer) 161 in which a part of information of an address conversion table stored in an external storage device (RAM or the like) is stored, and includes a virtual address space and a physical address space by paging. Perform management. Specifically, when the memory management unit 16 receives an access request by a virtual address from the CPU core unit 10 or the dedicated processing circuit module 11 via the CPU bus 17, the memory management unit 16 searches the TLB 161 to obtain the virtual address related to the access request. Convert to the corresponding physical address. Then, an access request with the converted physical address is generated for the internal bus 18. When an error such as no entry corresponding to the TLB 161 occurs, the CPU core unit 10 is requested to perform exception processing such as a TLB miss exception. Details of the address conversion will be described later.

  Further, when receiving an access request from the CPU core unit 10, the memory management unit 16 asserts a stall signal (stlc) to the CPU core unit 10. The stall signal stlc is asserted for a predetermined period necessary to obtain the result of address translation. As a result, the CPU core unit 10 suspends execution of subsequent instructions. Specifically, the memory management unit 16 asserts the stall signal stlc for the predetermined period after an access request is given from the CPU core unit 10 to the memory management unit 16. If a stall signal stlp described later is asserted from the dedicated processing circuit module 11 during that period, the memory management unit 16 continues to assert the stall signal stlc until the stall signal stlp is negated. On the other hand, when the stall signal stlp is not asserted by the dedicated processing circuit module 11, the memory management unit 16 negates the stall signal stlc after the predetermined period. Whether the stall signal stlc is to be asserted is determined based on a condition based on memory page attribute information, a virtual address, a physical address, or the like stored in an entry in the TLB 161 corresponding to the access request received by the memory management unit 16 This is done by judgment. If the memory management unit 16 does not immediately accept the read / write request on the CPU bus 17 for some reason, the processing of the CPU core unit 10 and the dedicated processing circuit module 11 may be temporarily stopped as a result. However, this is different from the control for completion of the instruction using the stlc signal and the synchronization of the processing related to the instruction.

  Here, address translation and exception processing in the memory management unit 16 will be described in detail.

  FIG. 2 shows an example of the configuration of the TLB 161 used for address conversion by the memory management unit 16.

  The TLB 161 shown in the figure is built in the memory management unit 16 and has 64 entries. Each entry includes an 8-bit address space identifier ASID [7: 0], a 22-bit virtual page number VPN [31:10], a valid bit V, a 19-bit physical page number PPN [28:10], and a 2-bit page size. Information such as bit SZ [1: 0], shared state bit SH, cache use bit C, 2-bit access right bit PR [1: 0], dirty bit D, and cache write through bit WT is stored. Details of each of the information are as follows. The address space identifier ASID indicates a process that can access a logical page. The virtual page number VPN represents the upper 22 bits of the logical address. The valid bit V indicates whether or not the entry is valid. For example, “1” indicates valid, and “0” indicates invalid. The physical page number PPN represents the upper 19 bits of the physical address. The page size bit SZ represents the size of the page. The sharing status bit SH indicates whether or not a page is shared between processes. For example, the sharing status bit SH indicates no sharing when “0”, and sharing when “1”. The cache use bit C indicates whether or not the page can be cached from the cache memory 15, for example, “0” indicates that caching is not possible, and “1” indicates that caching is possible. The access right bit PR indicates whether or not there is an access right in each operation mode of the CPU core unit 10. For example, “00” can be read only in privileged mode, “01” can be read / written in privileged mode, “10” can only be read in privileged / user mode, and “11” can be read / written in privileged / user mode. . The dirty bit D indicates whether or not writing has been performed on the page. For example, “0” indicates that writing has not been performed, and “1” indicates that writing has been performed. The cache write-through bit WT represents a write mode to the cache memory 15, for example, “0” indicates a copy-back mode, and “1” indicates a write-through mode.

  The address conversion using the TLB 161 by the memory management unit 16 is performed as follows.

  First, when the memory management unit 16 receives an access request from the CPU core unit 10 or the dedicated processing circuit module 11 via the CPU bus 17, the memory management unit 16 refers to the TLB 161. Then, a comparison is made between the virtual page number VPN in the bit range corresponding to the page size specified by the page size bit SZ and the upper address of the virtual address related to the access request for all entries whose valid bit V is “1”. I do. Here, for example, when SZ [1] = 0 and SZ [0] = 1, the page size is 4 kB, and the CPU address bus ca is a 32-bit bus, the comparison target is the virtual page number. VPN [31:12] and CPU address bus ca [31:12].

  Next, the memory management unit 16 adds, in addition to the comparison with the virtual page number VPN described above, the memory management unit 16 for the entry having the shared state bit SH “0” among the entries having the valid bit V “1”. The address space identifier CID [7: 0] set in the internal register of the management unit 16 is compared with the ASID [7: 0] of the corresponding entry. As a result of these comparisons, if they do not match, the memory management unit 16 stores the virtual address causing the error in an internal FVA (Failed Virtual Address) register 162, and also causes the CPU core unit 10 as a TLB miss. Is requested using the exception processing request signal (excp). On the other hand, if they match, the memory management unit 16 determines the access right specified by the access right bits PR [1: 0]. If the current access request is not permitted as a result of the determination, the memory management unit 16 saves the virtual address causing the error in the FVA register 162, and performs page protection violation exception processing using the exc signal. Request to 10. On the other hand, as a result of the determination of the access right, if the current access request is an permitted access, the memory management unit 16 determines the dirty bit D. As a result, when the access request is a write and the dirty bit D is “0”, an initial page write exception process is requested using the exc signal. On the other hand, when the dirty bit D is “1”, it is determined that the address can be converted regardless of whether the access request is read or write, and the memory management unit 16 sets the physical address obtained by converting the received access request. Accordingly, the data is output on the internal bus 18. The generation method for the physical address is as follows. For example, when SZ [1] = 0 and SZ [0] = 1, a 29-bit physical address [28: 0] obtained by concatenating the physical page number PPN [28:12] and the lower address [11: 0] of the CPU address bus ca. ] Is generated.

  When the use of the cache is specified in the range of the virtual address related to the access request (when the cache use bit C is “1”), the memory management unit 16 stores the cache memory 15 before performing the above processing. Perform a search. When a cache miss occurs as a result of the search, or when a write operation occurs when the cache operation mode is write-through, the memory management unit 16 generates a physical address by the above method and requests access to the internal bus 18. Is output.

  Next, exception processing for errors such as TLB misses in the CPU core unit 10 will be described.

  When an error such as a TLB miss, initial page write, or page protection violation occurs during the processing related to paging by the memory management unit 16 as described above, it becomes necessary to intervene in the processing by software. The memory management unit 16 stores the virtual address causing the error in the FVA register 162 and requests exception processing from the CPU core unit 10 by an exception processing request signal (excp). Upon receiving the exception processing request signal excp, the CPU core unit 10 shifts to control by the OS, and for example, saves the contents of the program counter (PC) and the status register (SR) to a saving register or the like, and manages the memory. The virtual address and process that caused the TLB miss are identified with reference to the FVA register 162 of the unit 16, and an exception handling routine is executed. Hereinafter, the flow of exception processing by the OS will be described by taking exception processing when a TLB miss exception occurs as an example.

  FIG. 3 is a flowchart showing an example of TLB miss exception processing by the OS.

  When the CPU core unit 10 receives the exception processing request signal exc from the memory management unit 16, TLB miss exception processing by the OS is started (S101). The CPU core unit 10 reads the information of the virtual address that caused the TLB miss from the register inside the memory management unit 16, and searches for the corresponding page entry from the page table information managed by the OS (S102). The CPU core unit 10 determines whether or not there is a page entry corresponding to the virtual address (S103). If no corresponding page entry is found, the CPU core unit 10 interrupts the TLB miss exception process (S111). . On the other hand, when the corresponding page entry is found, the CPU core unit 10 reads the virtual page attribute information from the page entry (S104). Then, the CPU core unit 10 determines whether the current process is permitted to access the virtual page based on the read virtual page attribute information (S105). If access is not permitted, the CPU core unit 10 interrupts the TLB miss exception process (S111). On the other hand, when access is permitted, the CPU core unit 10 determines whether or not physical memory is allocated to the page entry (S106). When physical memory is allocated to the page entry, the CPU core unit 10 registers the information of the page entry in the TLB 161, and resumes processing from the address of the instruction that caused the TLB miss (S109). On the other hand, if no physical memory is allocated, it is determined whether or not the physical memory to be allocated can be registered in the page entry (S107). If not possible, the TLB miss exception process is interrupted (S111). If possible, a physical address is assigned to the virtual address and the corresponding page entry is updated (S108). Thereafter, the CPU core unit 10 registers the information of the page entry in the TLB 161, and resumes the process from the address of the instruction that caused the TLB miss (S109). Specifically, after completion of the exception process, the CPU core unit 10 resets the contents saved in the save register and the like to the program counter and the status register and returns from the exception process to generate an error. The process is resumed by re-executing. With the above processing, the TLB miss exception processing ends (S110).

  Next, the dedicated processing circuit module 11 will be described.

  The dedicated processing circuit module 11 executes specific processing instead of the CPU core unit 10. The dedicated processing circuit module 11 is, for example, a DMA controller or an accelerator that executes processing such as compression / decompression of voice data and image data, encryption processing, and image recognition. As described above, the dedicated processing circuit module 11 is connected to the CPU bus 17 and the internal bus 18 respectively, and is accessed from the internal bus 18 by a physical address, and to other functional units via the CPU bus 17 by a virtual address. To access. For example, the operation of the dedicated processing circuit module 11 is controlled by the CPU core unit 10 via the internal bus 18 via the memory management unit 16. On the other hand, when the dedicated processing circuit module 11 accesses an external RAM, for example, the RAM is accessed from the CPU bus 17 via the memory management unit 16. The reason why the memory management unit 16 is used for the access from the dedicated processing circuit module 11 as described above is to apply the memory management function and the memory protection function to the access request of the dedicated processing circuit module 11 as well.

  FIG. 4 is a block diagram showing an example of the internal configuration of the dedicated processing circuit module 11.

  As shown in the figure, the dedicated processing circuit module 11 includes a CPU bus arbitration unit 111, a read request generation unit 112, a write request generation unit 113, a data processing unit 114, and a control unit 115. The data processing unit 114 performs various data processing on the input data. For example, when the dedicated processing circuit module 11 is a data processing apparatus for image processing, the data processing unit 114 executes data processing such as compression of image data.

  The read request generation unit 112 generates a read request (rreq) for reading data input to the data processing unit 114 from the external storage device (RAM or ROM) via the CPU bus 17. The write request generation unit 113 generates a write request (wreq) for writing data related to the data processing result by the data processing unit to the external storage device via the CPU bus 17. The CPU bus arbitration unit 111 arbitrates the read request rreq and the write request wreq output from the read request generation unit 112 and the write request generation unit 113, issues a read / write request to the CPU bus 17, and relates to the request Controls the transfer of data (rdata, wdata).

  The control unit 115 performs overall control of the CPU bus arbitration unit 111, the read request generation unit 112, the write request generation unit 113, and the data processing unit 114. The control unit 115 includes an access request determination unit 1150, a control register 1151, a control signal generation unit 1152, and a stall request generation unit 1153.

  The control register 1151 is a register in which commands, statuses, and other various parameters for controlling the dedicated processing circuit module 11 given from the CPU core unit 10 are set. Specifically, the control register 1151 has a start bit indicating whether or not the operation by the dedicated processing circuit module 11 is possible. For example, when the start bit is set to “1”, the operation of the dedicated processing circuit module 11 is enabled. , “0” is set, the operation is stopped. The control register 11151 can be set by the access request determination unit 1150 and the control signal generation unit 1152.

  The access request determination unit 1150 sets the value of the control register 1151 according to the access request given from the internal bus 18. For example, when an access request instructing the start of processing by the dedicated processing circuit module 11 is given from the CPU core unit 10 via the memory management unit 16, the access request determination unit 1150 displays the physical address specified by the access request. The control register 1151 is selected based on the above information and the start bit is set to “1”. Further, the access request determination unit 1150 asserts a signal (match) indicating that the start bit is set to “1”, and negates the match signal when the start bit is set to “0”. To do.

  The control signal generation unit 1152 controls the operation of each functional unit such as the data processing unit 114 based on the setting value of the control register 1151 and the exception processing request excp, and outputs an interrupt request (intp) as necessary. The specific operation content of the control signal generation unit 1152 is as follows. For example, when the access request determination unit 1150 sets “1” to the start bit of the control register 1151, the control signal generation unit 1152 performs processing according to the status and various parameter values set in the control register 1151. The data processing unit 114 is executed. Thereafter, when the processing of a predetermined processing unit by the data processing unit 114 is completed, the control signal generation unit 1152 sets “0” to the start bit of the control register 1151. Here, the processing of the predetermined processing unit is, for example, processing related to data transfer for one packet by the data processing unit 114 when the dedicated processing circuit module 11 is a DMA controller, and the dedicated processing circuit module 11 In the case of a data processing apparatus for image processing, data processing of image data for one block by the data processing unit 114 is performed. When an exception handling request excp is given from the memory management unit 16, the control signal generation unit 1152 controls the CPU bus arbitration unit 111 to output a signal (miss) for negating the stall signal stlp and perform data processing. The processing is interrupted by controlling the unit 114 and “0” is set to the start bit of the control register 1151. At this time, values such as the status and parameters of the control register 115 are held immediately before the processing of the data processing unit 114 is interrupted, for example. Furthermore, when the processing by the data processing unit 114 is completed or when an error occurs during the processing, the control signal generation unit 1152 outputs an interrupt request intp to notify the CPU core unit 10.

  The stall request generation unit 1153 receives the miss signal and the match signal, and outputs a stall signal stlp for interrupting instruction execution of the CPU core unit 10. The stall signal stlp is a signal for synchronizing the completion of the instruction in the CPU core unit 10 and the completion of the process of the dedicated processing circuit module 11 related to the instruction. Specifically, the stall request generation unit 1153 asserts the stall signal stlp when the access request determination unit 1150 sets “1” to the start bit of the control register 1151 and asserts the match signal. On the other hand, if the miss signal is asserted by the CPU bus arbitration unit 111 while the stall signal stlp is asserted, the stall signal stlp is negated. According to this, a new command execution of the CPU core unit 10 is suspended during the operation of the dedicated processing circuit module 11, and if an error such as a TLB miss occurs during the operation of the dedicated processing circuit module 11, The pending state of new instruction execution is released.

  Here, the operations of the CPU core unit 10, the memory management unit 16, and the dedicated processing circuit module 11 when the CPU core unit 10 controls the dedicated processing circuit module 11 to execute processing will be described with reference to FIGS. 5 and 6. Will be described in detail.

  FIG. 5 is an example of a timing chart when the CPU core unit 10 controls the dedicated processing circuit module 11 to execute processing. In the figure, the virtual address output from the CPU core unit 10 onto the CPU bus 17, the stall signal stlc, the physical address output from the memory management unit 16 onto the internal bus 18, and a predetermined stall signal stlp A state corresponding to the timing is shown. In the figure, the stall signals stlc and stlp are displayed as active low signals.

  First, when the CPU core unit 10 issues an access request for an external storage device (RAM), for example, at the timing indicated by reference numeral 501 in the figure, the virtual address A specified by the access request is output on the CPU bus 17. Is done. The memory management unit 16 that has received the access request asserts the stall signal stlp, converts the virtual address A to the physical address PA, for example, at the timing indicated by reference numeral 502, and outputs the physical address PA on the internal bus 18 As a result, an access request is transmitted to the external bus controller 14. In this case, since the access target is not the dedicated processing circuit module 11, the stall signal stlp remains negated. Thereafter, at a timing 503 when a predetermined time has elapsed since the stall signal stlc was asserted, the memory management unit 16 negates the stall signal stlc.

  Next, when the CPU core unit 10 issues a new access request to the dedicated processing circuit module 11 at timing 504, the virtual address B specified by the access request is output on the CPU bus 17. The memory management unit 16 that has received the access request asserts the stall signal stlc at timing 505, converts the virtual address B to the physical address PB, and outputs the physical address PB on the internal bus 18. To communicate. The dedicated processing circuit module 11 that has received the access request executes data processing related to the access request at timing 506 and asserts the stall signal stlp. The memory management unit 16 continues to assert the stall signal stlc in response to the assertion of the stall signal stlp. Thereafter, when the processing by the dedicated processing circuit module 11 is completed at the timing 507, the dedicated processing circuit module 11 outputs an interrupt request intp and negates the stall signal stlp. As a result, the instruction execution suspension state of the CPU core unit 10 is released, and a new instruction can be executed.

  FIG. 6 is an explanatory diagram showing operation states of the CPU core unit 10 and the dedicated processing circuit module 11 when the CPU core unit 10 controls the dedicated processing circuit module 11 to execute processing.

  In step 201, the CPU core unit 10 executes a command for setting the control register 1151 in the dedicated processing circuit module 11 in order to cause the dedicated processing circuit module 11 to execute processing. By executing this instruction, an access request is issued to the dedicated processing circuit module 11 via the memory management unit 16. Receiving this, the access request determination unit 1150 of the dedicated processing circuit module 11 selects the control register 1151 and sets “1” in the start bit. As a result, the dedicated processing circuit module 11 starts its operation and asserts the stall signal stlp, and the execution of a new instruction of the CPU core unit 10 is suspended. In step 202, if a TLB miss occurs during the operation of the dedicated processing circuit module 11, an exception handling request exc is output from the memory management unit 16. Upon receiving the exception processing request excp, the control signal generation unit 1152 of the dedicated processing circuit module 11 interrupts the process being executed in the data processing unit 114 and sets “0” in the start bit of the control register 1151. As a result, the stall signal stlp is negated, and the CPU core unit 10 is released from the pending state of instruction execution, shifts to control by the OS, and executes exception processing. When exception processing is completed in step 203, the CPU core unit 10 re-executes the instruction that caused the exception processing. By re-execution of the instruction, an access request is issued to the dedicated processing circuit module 11 via the memory management unit 16, and the access request determination unit 1150 of the dedicated processing circuit module 11 that has received this is sent to the start bit of the control register 1151. Set “1”. Then, the control signal generation unit 1152 of the dedicated processing circuit module 11 causes the data processing unit 114 to execute processing based on the status at the time of interruption. As a result, the dedicated processing circuit module 11 can resume the processing from where it was interrupted. Further, when “1” is set in the start bit, the access request determination unit 1150 asserts the match signal, and as a result, the stall signal stlp is asserted. As a result, the CPU core unit 10 suspends execution of a new instruction.

  If a TLB miss occurs again, the same processing as in steps 202 and 203 is executed (S204, S205). In step 206, when the processing by the dedicated processing circuit module 11 is completed, the dedicated processing circuit module 11 outputs an interrupt request intp and sets a start bit to “0”. Thereby, the interrupt signal int is given from the interrupt controller 12 to the CPU core unit 10, and the CPU core unit 10 performs an end process of an instruction for causing the dedicated processing circuit module 11 to execute the process.

  As described above, in the microprocessor 1 according to the first embodiment, when the dedicated processing circuit module 11 operates using a virtual address, the CPU core unit 10 operates by asserting the stall signals stlc and stlp. Interrupt and do not fetch a new instruction. As a result, the correspondence between the virtual address space used by the dedicated processing circuit module 11 and the physical address space is not changed during the operation of the dedicated processing circuit module 11, so that the physical address space corresponding to the virtual address space used by the dedicated processing circuit module 11 is changed. There is no inconsistency. Even when an error such as a TLB miss due to the operation occurs during the operation of the dedicated processing circuit module 11, the CPU core unit 10 determines the instruction that caused the error and the virtual address that caused the error. Therefore, the CPU core unit 10 executes the exception processing related to the error and re-executes the instruction that caused the error after the exception processing is completed. Can be resumed. As described above, according to the microprocessor 1 according to the first embodiment, the processing using the virtual address space of the dedicated processing circuit module 11 can be performed safely, so there is no need to modify the OS.

<< Embodiment 2 >>
In the microprocessor 1 according to the first embodiment, the dedicated processing circuit module 11 has a function for deferring execution of a new instruction of the CPU core unit 10 during the operation of the dedicated processing circuit module 11. In the microprocessor 2 according to 2, the memory management unit 36 has the function.

  FIG. 7 is a block diagram of the microprocessor 2 according to the second embodiment.

  A microprocessor 2 shown in the figure is a microprocessor for a portable information terminal, for example. The microprocessor 2 realizes the function of the portable information terminal by being connected to a storage device such as a RAM (Random Access Memory) and a ROM (not shown) and an external I / O. Of the constituent elements of the microprocessor 2 shown in the figure, the same constituent elements as those of the microprocessor 1 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  The dedicated processing circuit module 31 shown in FIG. 7 is an accelerator or the like that executes specific processing instead of the CPU core unit 10 in the same manner as the dedicated processing circuit module 11 according to the first embodiment. In this configuration, the stall request generator 1153 that generates the stall signal stlp is removed.

  Similarly to the memory management unit 16 according to the first embodiment, the memory management unit 36 includes a TLB 161 and an FVA register 162, and other functional units necessary for address conversion (not shown). Further, the memory management unit 36 includes a stall request generation unit 363. The stall request generation unit 363 outputs a stall signal stlc2 for suspending execution of a new instruction of the CPU core unit 10.

  Here, the operations of the CPU core unit 10, the memory management unit 36, and the dedicated processing circuit module 31 when the CPU core unit 10 controls the dedicated processing circuit module 31 to execute processing will be described in detail.

  First, in order to cause the dedicated processing circuit module 31 to execute processing, the CPU core unit 10 executes an instruction for setting the control register 1151 in the dedicated processing circuit module 31. By executing the instruction, an access request for the dedicated processing circuit module 31 is issued, and a virtual address specified by the access request is output on the CPU bus 17. The memory management unit 36 that has received the access request asserts the stall signal stlc2 by the stall request generation unit 363, converts the virtual address specified by the access request into a physical address, and generates an internal bus along with the access request. The access request is transmitted by outputting the data on 18. Upon receiving this, the access request determination unit 1150 of the dedicated processing circuit module 31 selects the control register 1151 and sets “1” in the start bit. As a result, the dedicated processing circuit module 31 starts its operation. The stall request generation unit 363 in the memory management unit 36 continues to assert the stall signal stlc2 even after the access request is transmitted to the dedicated processing circuit module 31. As a result, the CPU core unit 10 suspends execution of a new instruction.

  When a TLB miss occurs in the address conversion relating to the access request of the dedicated processing circuit module 31, the memory management unit 36 outputs an exception processing request excp and negates the stall signal stlc2 by the stall request generation unit 363. The control signal generation unit 1152 of the dedicated processing circuit module 31 that has received the exception processing request excp interrupts the processing being executed by the data processing unit 114 and sets “0” in the start bit of the control register 1151. Further, the CPU core unit 10 is released from the pending state of the new instruction execution by the negation of the stall signal stlc2, and shifts to the control by the OS to execute the exception process.

  When the exception processing is completed, the CPU core unit 10 re-executes the instruction that caused the exception processing. By re-execution of the instruction, an access request for the dedicated processing circuit module 11 is issued. Similarly to the above, the memory management unit 36 that has received the access request asserts the stall signal stlc2 by the stall request generation unit 363, The virtual address specified by the access request is converted into a physical address, and the access request is transmitted to the dedicated processing circuit module 31 by outputting it on the internal bus 18 in accordance with the access request. Receiving this, the access request determination unit 1150 of the dedicated processing circuit module 31 selects the control register 1151 and sets “1” in the start bit. When “1” is set in the start bit, the control signal generation unit 1152 causes the data processing unit 114 to execute processing based on the status at the time of the previous interruption. As a result, the dedicated processing circuit module 31 can resume the processing from the point of interruption.

  When the processing by the dedicated processing circuit module 31 is completed, the control signal generation unit 1152 of the dedicated processing circuit module 31 outputs an interrupt request intp and sets “0” in the start bit. Thereby, the interrupt signal int is given from the interrupt controller 12 to the CPU core unit 10, and the CPU core unit 10 shifts to the processing of the interrupt factor.

  As described above, according to the microprocessor 2 according to the second embodiment, the process using the virtual address space of the dedicated processing circuit module can be safely performed as in the case of the microprocessor 1, and therefore it is necessary to modify the OS. Absent.

<< Embodiment 3 >>
In the microprocessor 1 according to the first embodiment and the microprocessor 2 according to the second embodiment, the CPU core unit 10 re-executes the instruction when the exception processing for the TLB miss related to the access request from the dedicated processing circuit module is completed. As a result, the operation of the dedicated processing circuit module was resumed. In the microprocessor 3 according to the third embodiment, when the TLB information is updated by exception processing, the memory management unit restarts the operation of the dedicated processing circuit module.

  FIG. 8 is a block diagram of the microprocessor 3 according to the third embodiment.

  A microprocessor 3 shown in the figure is a microprocessor for a portable information terminal, for example. The microprocessor 3 realizes the function of the portable information terminal by being connected to a storage device such as a RAM (Random Access Memory) and a ROM (not shown) and an external I / O. Of the components of the microprocessor 3 shown in the figure, the same components as those of the microprocessors 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The memory management unit 46 shown in FIG. 8 has a TLB 161, an FVA register 162, a stall request generation unit 363, and other functional units necessary for address conversion not shown, like the memory management unit 36 according to the second embodiment. . Further, the memory management unit 46 includes a process resumption signal generation unit 464. The process resumption signal generation unit 464 outputs a process resumption signal (rgm) after the information of the TLB 161 is updated by the exception process corresponding to the TLB miss.

  In addition to the function of the dedicated processing circuit module 31 according to the second embodiment, the dedicated processing circuit module 41 has a function of setting the control register 1151 according to the processing restart signal rgm. Specifically, the access request determination unit 1150 in the dedicated processing circuit module 41 receives the process resumption signal rgm and sets “1” to the start bit of the control register 115 according to the signal.

  Here, operations of the CPU core unit 10, the memory management unit 46, and the dedicated processing circuit module 41 when the CPU core unit 10 controls the dedicated processing circuit module 41 to execute processing will be described in detail.

  First, the operation until the CPU core unit 10 executes an instruction to set the control register 1151 in the dedicated processing circuit module 41 and the dedicated processing circuit module 41 starts the operation is the same as that of the microprocessor 2. Thereafter, when a TLB miss occurs in the address conversion related to the access request of the dedicated processing circuit module 41, the memory management unit 46 outputs an exception processing request excp and negates the stall signal stlc2. The dedicated processing circuit module 41 that has received the exception processing request excp interrupts the process being executed, sets the start bit to “0”, and interrupts the process. Further, the CPU core unit 10 is released from the pending state of the new instruction execution when the stall signal stlc2 is negated, and shifts to control by the OS to execute exception processing. When the process of updating the entry information of the TLB 161 is completed in the exception process, the process restart signal generation unit 464 in the memory management unit 46 outputs the process restart signal rgm to the dedicated processing circuit module 41. The access request determination unit 1150 of the memory management unit 46 that has received the process restart signal rgm sets “1” to the start bit of the control register 1151. Thereby, even before all the processes in the exception process by the CPU core unit 10 are completed, the dedicated processing circuit module 31 can resume the process when the entry of the TLB 161 is updated.

  When the exception processing by the CPU core unit 10 is completed, the memory management unit 46 asserts the stall signal stlc2. Subsequent operations after completion of processing by the dedicated processing circuit module 31 are the same as those of the microprocessor 2.

  As described above, according to the microprocessor 3 according to the third embodiment, similarly to the microprocessors 1 and 2, the processing using the virtual address space of the dedicated processing circuit module can be performed safely, so it is necessary to modify the OS. There is no. Further, according to the microprocessor 3, in the exception process related to the TLB miss of the address conversion for the access request of the dedicated processing circuit module 41, the entry of the TLB 161 is updated even before all the processes in the exception process are completed. At this stage, the dedicated processing circuit module 41 is restarted. According to this, it is possible to restart the processing of the dedicated processing circuit module 41 earlier than in the case where the dedicated processing circuit module 41 restarts the operation after the series of processing in the exception processing is completed.

<< Embodiment 4 >>
FIG. 9 is a block diagram of the microprocessor 4 according to the fourth embodiment.

  A microprocessor 4 shown in the figure is a microprocessor for a portable information terminal, for example. The microprocessor 4 realizes the function of the portable information terminal by being connected to a storage device such as a RAM (Random Access Memory) and a ROM (not shown) and an external I / O. Of the constituent elements of the microprocessor 4 shown in the figure, the same constituent elements as those of the microprocessor 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The microprocessor 4 further includes a memory management unit 50 including a TLB 501 for address conversion for an access request of the dedicated processing circuit module 11. The memory management unit 50 is connected to the dedicated processing circuit module 11 via a dedicated bus 51 including a dedicated address bus pa and a dedicated data bus pd, and is connected to the interrupt controller 12, timer unit 13, external bus via the internal bus 18. The controller 14 and the dedicated processing circuit module 11 are connected. The TLB 501 stores a part of address conversion information stored in the TLB 161.

  An access request from the dedicated processing circuit module 11 is given to the memory management unit 50 via the dedicated bus 51. The memory management unit 50 that has received the access request converts the virtual address specified by the access request into a physical address using the TLB 501, and outputs the access request on the internal bus 18 with the physical address. An access request from the dedicated processing circuit module 11 is transmitted. Further, when an error occurs in the address conversion, the memory management unit 52 is notified.

  The memory management unit 52 operates in the same manner as the memory management unit 16 according to the first embodiment in response to an access request from the CPU core unit 10. When the memory management unit 52 receives a notification from the memory management unit 50 that an error has occurred in the address conversion related to the access request from the dedicated processing circuit module 11, the memory management unit 52 executes processing corresponding to the error. Specifically, when a TLB miss occurs in the memory management unit 50, the memory management unit 52 refers to the TLB 161 and searches for an entry corresponding to the virtual address that caused the TLB miss. When a necessary entry is found, the memory management unit 52 registers information on the entry in the TLB 161 in the TLB 501 and causes the memory management unit 52 to resume processing. On the other hand, when a necessary entry is not found, the memory management unit 52 issues an exception handling request excp. Subsequent operations of the CPU core unit 10 and the dedicated processing circuit module 11 are the same as those in the first embodiment. When the contents of the TLB 161 are updated after the exception processing is completed, the memory management unit 52 registers address translation information including necessary entries in the TLB 501 and the CPU core unit 10 re-executes the instruction. Other processes are the same as those in the first embodiment.

  As described above, according to the microprocessor 4 according to the fourth embodiment, the process using the virtual address space of the dedicated processing circuit module can be performed safely as in the case of the microprocessor 1, and therefore it is necessary to modify the OS. Absent. Further, by separating the memory management unit 50 having the TLB 501 for the dedicated processing circuit module 11 like the microprocessor 4 and the memory management unit 52 for controlling access from the CPU core unit 10, This is advantageous when the operating frequency is different from the operating frequency of the dedicated processing circuit module 11. For example, when the operating frequency of the dedicated processing circuit module 11 is lower than the operating frequency of the CPU core unit 10, a memory for accessing both the CPU core unit 10 and the dedicated processing circuit module 11 like the memory management unit 16 of the microprocessor 1. To perform management, the memory management unit must be designed for the higher operating frequency. This is because memory management with high power consumption designed for a high frequency in accordance with the CPU core unit 10 even when the CPU core unit 10 is stopped while the dedicated processing circuit module having a low operating frequency is operating. Use of the unit increases the power consumption. On the other hand, according to the microprocessor 4 according to the fourth embodiment, the operating frequency of the memory management unit 50 can be lowered according to the dedicated processing circuit module 11, so that the processing efficiency of the dedicated processing circuit module 11 is improved. To contribute.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in the microprocessor 4 according to the fourth embodiment, the TLB 501 stores a part of the address conversion information of the TLB 161 as an example. However, the present invention is not limited to this, and the TLB 501 stores all of the address conversion information of the TLB 161. Good. Further, in the microprocessor 4 according to the fourth embodiment, the example in which the configuration in which the memory management unit is divided for each of the CPU core unit 10 and the dedicated processing circuit module 11 is applied to the microprocessor 1 is shown. This can also be applied to 2 and 3.

  When the OS applied to the microprocessor 1 is permitted to be somewhat customized, such as an embedded OS, the dedicated processing circuit module is obtained by modifying the OS within the permitted range. It is possible to safely perform processing using the virtual address space. For example, when a TLB miss occurs in an address conversion process for an access request from a dedicated processing circuit module and a TLB entry is updated by subsequent exception processing, a TLB entry is added from the CPU core unit to the dedicated processing circuit module. In order to notify the update, it is necessary to modify the OS. Therefore, if the addition of the processing for notifying from the CPU core unit can be handled within the range where the modification of the OS is permitted, the processing using the virtual address space of the dedicated processing circuit module can be performed safely. It becomes possible.

1, 2, 3, 4 Microprocessor 10 CPU core unit 11, 31, 41 Dedicated processing circuit module 16, 36, 46, 50, 52 Memory management unit (MMU)
161, 501 TLB
162 FVA register ca CPU address bus cd CPU data bus 17 CPU bus ia internal address bus id internal data bus 18 internal bus ma cache address bus md cache data bus 20 cache bus ea external address bus ed external data bus 19 external bus 15 cache memory 14 External bus controller (BSC)
13 Timer unit (Timer)
12 Interrupt controller (INTC)
intp Interrupt request from dedicated processing circuit module 11 int Interrupt request from timer unit 13 into Interrupt request from external device etc. int Interrupt signal stlp, stlc, stlc2 Stall signal excp Exception processing request 111 CPU bus arbitration unit 112 Read request generation unit 113 write request generation unit 114 data processing unit 115 control unit 1150 access request determination unit 1151 control register 1152 control signal generation unit 1153 stall request generation unit rreq read request wreq write request rdata data related to read request wdata data related to write request 507 Predetermined timing 363 Stall request generator 464 Process restart signal generator rgm Process restart signal 51 Dedicated bus pa Dedicated address bus p Dedicated data bus

Claims (14)

A central processing unit that performs access control using virtual addresses;
A circuit module that is accessed by a physical address and performs access control using a virtual address;
A memory management unit that performs a process for converting a virtual address output from the central processing unit and a virtual address output from the circuit module into a physical address;
When the circuit module starts to operate according to the conditions set by the central processing unit via the memory management unit, the central processing unit performs processing for changing the correspondence between the virtual address space and the physical address space at that time. Data processing device to be suppressed. The circuit module starts an operation in response to execution of a predetermined instruction for setting the condition by the central processing unit, and asserts a stall signal.
The data processing apparatus according to claim 1, wherein the central processing unit suspends execution of an instruction when the stall signal is asserted. The circuit module has a control register in which a start bit for starting an operation is set,
The data processing apparatus according to claim 2, wherein the predetermined instruction is an instruction for setting a start bit of the control register via the memory management unit.   The data processing apparatus according to claim 3, wherein the circuit module negates the stall signal due to an error in processing for the address conversion for access control using a virtual address by the circuit module. When the error occurs, the memory management unit issues an exception handling request, the circuit module stops the operation according to the predetermined instruction,
5. The data processing device according to claim 4, wherein the central processing unit executes exception processing for the error in response to the exception processing request, and executes processing for resuming operation of the circuit module after completion of the exception processing. .   The data processing apparatus according to claim 5, wherein the process of resuming the operation of the circuit module is a process of re-executing the predetermined instruction. The circuit module starts operation in response to execution of a predetermined instruction for setting the condition by the central processing unit,
The memory management unit asserts a stall signal in response to execution of the predetermined instruction,
The data processing apparatus according to claim 1, wherein the central processing unit suspends execution of an instruction when the stall signal is asserted. The circuit module has a control register in which a start bit for starting an operation is set,
The data processing apparatus according to claim 7, wherein the predetermined instruction is an instruction to set a start bit of the control register via the memory management unit. When an error occurs during the process for converting the address for the access control using the virtual address by the circuit module, the memory management unit negates the stall signal and issues an exception processing request,
The circuit module stops the operation according to the predetermined instruction in response to the exception handling request;
The data processing apparatus according to claim 8, wherein the central processing unit executes exception processing for the error in response to the exception processing request.   The data processing device according to claim 9, wherein after the exception processing is completed, the central processing unit executes processing for resuming operation of the circuit module.   The data processing apparatus according to claim 10, wherein the process of resuming the operation of the circuit module is a process of re-executing the predetermined instruction.   The data processing apparatus according to claim 9, wherein when the process for eliminating the error is completed in the exception process, the memory management unit executes a process for restarting the operation of the circuit module. A central processing unit that performs access control using virtual addresses;
A circuit module that is accessed by a physical address and performs access control using a virtual address;
A first memory management unit having a first address translation pair for converting a virtual address into a physical address, and performing a process for address translation using the first address translation pair;
A second address translation pair having all or a part of the first address translation pair as an entry, and the virtual address output from the circuit module is converted into a physical address by using the second address translation pair A data processing device having a second memory management unit for executing processing,
When the circuit module starts operating according to the condition set by the central processing unit via the first memory management unit, the central processing unit changes the correspondence between the virtual address space and the physical address space at that time. A data processing device whose processing is suppressed. When the second memory management unit does not find an entry necessary for address conversion during the address conversion processing for the access control using the virtual address by the circuit module, the second memory management unit To that effect,
The first memory management unit searches the first address translation pair in response to the notification, and if a necessary entry is found as a result of the search, registers the entry in the second address translation pair and registers the first address translation pair. 14. The data processing apparatus according to claim 13, wherein the memory management unit is caused to execute the address conversion process again, and issues an exception processing request when a necessary entry is not found as a result of the search.

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