JP2008078809A - Image processor for vehicle - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor for a vehicle capable of reducing the capacity of an image data work memory for compression processing and drastically shortening the total processing time from image acquisition to completion of storing data as a compressed image data. <P>SOLUTION: The image processor executes transferring processing and compression processing in parallel. In the transferring processing, a frame of image data as an object of compression processing is transferred sequentially on an image data work memory in the form of fragmented image data divided in the line array direction. In the compression processing, the fragmented image data on the image data work memory are read sequentially and compressed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a vehicle image processing apparatus.

JP 2006-135435 A

  In recent years, crime prevention equipment for automobiles has become widespread, and in particular, a crime prevention system using a surveillance camera is penetrating into automobile applications. Many of these systems have a basic configuration for detecting a suspicious person's intrusion into a vehicle compartment, photographing it with a camera arranged at a predetermined position in the vehicle compartment, and storing and recording the photographed image. . Captured images are saved as digital image data, but color image data and grayscale image data are large in size, so they are saved as compressed image data in JPEG (Joint Photographic Experts Group) format, etc. to save memory space This is the mainstream (Patent Document 1).

  In Patent Document 1, when image data compression processing is performed, a large-capacity one-frame image acquired by a camera or the like is once transferred to the image data work memory on the processing device side, and the image data work memory is transferred. A method is employed in which image data is subjected to compression processing. Specifically, the inter-memory transfer process and the image compression process of the image data before compression are sequentially performed. However, this method has a drawback that a large-capacity image data work memory is required because image data to be compressed is collectively reserved on the image data work memory. In addition, since the data transfer process to the image data work memory and the data compression process are sequentially executed, there is a problem that the processing time is long, the response until the completion of image acquisition is deteriorated, and the current consumption is increased.

  An object of the present invention is to reduce the capacity of image data work memory for compression processing, and to greatly reduce the total processing time from acquisition of an image to completion of storage as compressed image data. Is to provide.

Means for Solving the Problems and Effects of the Invention

In order to solve the above problems, an image processing apparatus for a vehicle according to the present invention includes:
An image buffer memory that stores image data captured by the in-vehicle camera in units of frames;
Image data work memory for compressing image data transferred from the image buffer memory;
Fragmented image data transfer means for dividing a frame of image data in the image buffer memory in a line arrangement direction of image pixels into a plurality of fragmented image data, and sequentially transferring the fragmented image data to the image data work memory;
Compression processing means for performing the compression processing for sequentially reading and compressing the fragmented image data transferred to the image data work memory in parallel with the transfer processing of the fragmented image data to the image data work memory by the fragmented image data transfer means; ,
It is characterized by having.

  According to the above-described configuration of the present invention, the image data (frame) to be subjected to compression processing is sequentially transferred onto the image data work memory in the form of fragmented image data divided in the line arrangement direction, and the image The processing to sequentially read and compress the fragmented image data in the data work memory is executed in parallel, so the total processing time from the acquisition of the image to the completion of saving as compressed image data is greatly reduced. Can do. In addition, since transfer to the image data work memory and reading for compression processing are executed in units of fragmented image data, the capacity of the image data work memory is larger than the capacity that can store and hold all one frame of image data. It is possible to reduce the memory area and contribute to saving of the memory area.

  The compressed fragmented image data can be stored in a storage memory in the apparatus. In this case, it is possible to provide a compressed image data storage memory that includes a non-volatile memory and stores the compressed fragmented image data as compressed image data. If the compressed image data storage memory stores fragmented image data in the form of aggregated frames, it is possible to facilitate the convenience of reading the image data in units of frames.

  The compression processing means can compress one frame of image data in a compression processing unit in which a fixed number of image pixel lines are set, and the fragmented image data matches the compression processing unit. Data size can be determined. By doing so, the breaks in the fragmented image data match the breaks in the compression processing unit, so that there is no need for a processing step for temporarily storing the fragmented image data in the image data work memory and re-dividing it into compression processing units. In addition, since the fragmented image data transferred to the image data work memory by the fragmented image data transfer unit can be immediately used for the compression processing by the compression processing unit, the compression processing time can be further shortened. Can do.

  The compression processing means can be constituted by a microcomputer that executes compression processing of the fragmented image data read by the fragmented image data reading means by software processing by the CPU. In this case, it is possible to provide a direct memory access control unit that realizes the function of the fragmented image data transfer means by direct memory access (hereinafter also referred to as DMA) without going through the CPU. As a result, the process of transferring the fragmented image data to the image data work memory is separated from the CPU process by the DMA, and the CPU can be dedicated to the compression process of the fragmented image data. The efficiency can be increased, and as a result, the total processing time from the acquisition of an image to the completion of storage as compressed image data can be further shortened. In this case, the microcomputer is configured to immediately start the compression processing for the fragmented image data from the image data work memory after the transfer processing of the fragmented image data to the image data work memory by the direct memory access control unit is completed. It is good to keep.

  A plurality of fragmented image data storage areas can be secured in the image data work memory. In this case, the process of writing the fragmented image data newly transferred by the fragmented image data transfer means into one of the plurality of storage areas, and the fragmented image data already written in another storage area. Image data work memory control means for performing a reading process for reading out for the compression process in parallel can be provided. By separating the memory area where data is being written and the memory area where data is being read, the fragmented image data is transferred to the image data work memory and the fragmented image data is compressed on the image data work memory. Parallel processing can be executed more smoothly.

  In this case, the image data work memory control means can clear the storage area from which the fragmented image data has been read for the compression process, and the fragmented image data transfer means is stored in the image data work memory. If there is a cleared storage area, the transfer process of the fragmented image data is continued. If there is no cleared storage area, the transfer of the fragmented image data is performed until a new cleared storage area is generated. It may be waiting for processing. Since the compressed processing of the fragmented image data that has already been transferred generally takes a longer time than the transfer processing of the fragmented image data to the image data work memory, the routine on the transfer processing side is until the completion of the routine on the compression processing side. In many cases, it is necessary to wait for startup. In this case, since the transfer of the next fragmented image data to the image data work memory can be immediately resumed with the clearing of the storage area where the compression processing is completed as a trigger, the waiting time can be minimized.

  In this case, if three storage areas for fragmented image data are secured in the image data work memory, one of the storage areas is always waiting for reading processing in a state where writing of the fragmented image data is completed. It can be ensured as a read waiting area to be in a state. Thus, when the compression processing of one piece of fragmented image data is completed, the piece of fragmented image data to be subjected to the next compression processing is always waiting in the writing completed state, so that the compression processing can be executed seamlessly. Can increase efficiency. Particularly effective when the work time required for compression processing of one piece of fragmented image data by the compression processing means is more than twice the work time required for the transfer processing of fragmented image data by the fragmented image data transfer means. Is.

  As the image data to be subjected to the compression process, a part of the pixel line thinned out in the frame of the image data can be used. When image data is not required to have a very high resolution, it is possible to reduce the load of image processing by adopting a frame in which pixel lines are thinned out in this way. In this case, if one consisting of either the even field or the odd field constituting the frame of the image data is employed, the thinning process every two lines can be easily realized as a result. Further, if it is desired to further increase the line thinning rate, a part of the pixel line may be thinned in one of the even field and the odd field.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an electric board of the vehicle image processing apparatus 100 (a terminal bar with an overbar symbol added means that it operates with negative logic (active low). However, it is described without adding an over bar symbol in the text of this embodiment). The vehicular image processing apparatus 100 includes a main control power supply 1, an image power supply 2, a communication I / F (interface) 3, a microcomputer 4, a bus buffer 5, a field memory 6, a video decoder 7, an input I / F 8, and memory control. Each circuit block includes a unit 9, an image data work memory 10, and an image data nonvolatile storage memory 11. A communication I / F (interface) 3, a microcomputer 4, a bus buffer 5, a memory control unit 9, an image data work memory 10, and an image data nonvolatile storage memory 11 are included in the main control unit, a field memory 6, a video decoder 7. Is included in the image processing unit.

  The bus buffer 5, the image data work memory 10, and the image data nonvolatile storage memory 11 are connected to the microcomputer 4 via an external data bus (16 bits) and a chip select signal line. The video decoder 7 and the field memory 6 are cascade-connected to the bus buffer 5 via a dedicated data transfer line in this order. The communication I / F 3, the input I / F, and the memory control unit 9 are connected to corresponding signal terminals of the microcomputer 4 through various signal lines.

  The main control system power supply 1 converts the in-vehicle battery voltage (+ B) into a first power supply voltage (VDD1) for control, and constitutes a main control unit, here a communication I / F (interface) 3, a microcomputer 4. The data is supplied to the bus buffer 5, the input I / F 8, the memory control unit 9, the image data work memory 10, and the image data nonvolatile storage memory 11. The main control system power supply 1 has an operation monitoring function of the microcomputer 4. Specifically, a monitoring method using a well-known watchdog timer is employed, and a WD pulse signal output from a watchdog (WD) terminal of the microcomputer 4 is received by a CK terminal. When the WD pulse signal is interrupted for a certain time, it is determined that the operation of the microcomputer 4 is abnormal, and the microcomputer 4 is reset (RESET terminal).

  The image system power supply 2 converts the in-vehicle battery voltage (+ B) into a second power supply voltage (VDD2) for image processing different from the first power supply voltage, and forms a circuit block that constitutes the image processing unit. This is supplied to the field memory 6 and the video decoder 7. The image power supply 2 also has a function of taking in a control signal output from the DC_EN terminal of the microcomputer 4 from the EN terminal and supplying / stopping a voltage based on the content of the control signal.

  The vehicular image processing apparatus 100 is provided with a shielded GND terminal for connecting a shielded portion such as a camera power supply GND terminal, a signal GND terminal, and a coaxial cable that are commonly grounded. A camera power supply terminal (also used as a power supply terminal of an auxiliary light source used for camera photographing) is provided as an output terminal for the second power supply voltage from the image power supply 2, and the camera I / F unit together with the above terminals Is forming.

Hereinafter, the function of each circuit block will be described.
The video decoder 7 converts an analog video signal (for example, NTSC signal) sent from a camera (not shown) into digital image data. Specifically, the composite video signal or S video signal included in the input NTSC signal is Y / C separated and then converted into digital image data of various formats (for example, YCbCr or RGB). Specifically, a commercially available LSI such as MSM7664TB (trade name: Oki Electric Industry) can be employed.

  The field memory 6 corresponds to an image buffer memory, and receives two analog image field data sequentially sent from the camera side by interlaced scanning through digitization by the video decoder 7 and converts them into one frame. The synthesized digital image frame data is sequentially transferred to the image data work memory 10. In the present embodiment, the field memory 6 includes an odd field memory 6p and an even field memory 6s each composed of a FIFO (first-in first-out) memory. Two fields belonging to the same frame are stored in these memory areas. 6p and 6s are sequentially stored, and as shown in FIG. 2, the pixel lines P and S constituting each field are sequentially read and transferred from the memory areas 6p and 6s while being switched by a memory switch (not shown). As a result, the data is synthesized into one frame at the time of the transfer on the external data bus toward the image data work memory 10. As will be described later, this transfer of frame data is sequentially executed in units of fragmented image data consisting of 8 pixel lines, which are JPEG image data compression processing units. Note that the image buffer memory may be constituted by a RAM, and two fields may be synthesized on the RAM.

  The microcomputer 4 is a main controller of the vehicle image processing apparatus, and includes a well-known CPU, ROM, RAM (main memory 4M) and the like (not shown), and is based on execution of a control program stored in the ROM. Then, processing for transferring and saving the image frame data to the image data nonvolatile storage memory 11 is performed.

  The image data work memory 10 is a work area for temporarily storing digital image data fetched from the field memory 6 by the microcomputer 4. Transfer of digital image data from the microcomputer 4 is performed using DMA (Direct Memory Access) in order to reduce the load on the microcomputer 4. In the present embodiment, the DAM control unit is built in the microcomputer 4.

  The image data non-volatile storage memory 11 constitutes a compressed image data storage memory, and is constituted by a flash memory or the like that stores and holds data contents even when the vehicle image processing apparatus 100 is turned off. In this embodiment, the digital image data fetched from the image data work memory 10 is divided into fragmented image data consisting of 8 pixel lines in the image frame before compression, and the fragmented image data is used as a compression processing unit as JPEG. The compressed image data compressed in the (Joint Photographic Experts Group) format is stored in the image data nonvolatile storage memory 11.

  The memory control unit 9 controls reading / writing of image data to / from either the image data work memory 10 or the image data nonvolatile storage memory 11 according to a command from the microcomputer 4 (control signals from RD, WR0, WR1, CS3, and CS2). Is to do. Further, the bus buffer 5 is provided in order to prevent the microcomputer 4 and the field memory 6 from competing for the use of the data bus when the digital image data is DMA-transferred from the field memory 6 to the image data work memory 10. The microcomputer 4 operates in such a manner that the data transmission path (data bus) between the field memory 6 and the microcomputer 4 is connected / disconnected in accordance with a command (control signal from the CS 1) of the microcomputer 4.

  The communication I / F 3 is a circuit that performs communication between the microcomputer 4 and an external device, and has a circuit configuration corresponding to the communication standard of the connected external device. The device to be a communication partner is, for example, a control main body (ECU: mainly composed of a microcomputer) connected to an in-vehicle communication network (for example, CAN: Controller Area Network). These ECUs mainly control various electronic devices mounted on the vehicle, but may include an ECU that controls communication outside the vehicle (for example, wireless communication). The input I / F 8 takes in signals from the sensor signal terminals (A, B) and the theft detection signal terminal and adjusts the voltage level so that the microcomputer 4 can process them.

  The sensor signal A terminal captures, for example, a signal from an approach sensor (not shown) that detects the approach of an object to be detected (for example, a suspicious person) to the vehicle. The sensor signal B terminal receives a signal from an intrusion sensor (not shown) that detects the intrusion of a suspicious person into the vehicle. Furthermore, the theft detection signal terminal takes in a theft detection signal sent from a security ECU (not shown).

  For example, when a theft detection signal is detected, the vehicle image processing apparatus 100 captures an analog video signal from a camera (not shown) as digital image data (still image data) in the video decoder 7, and images the frame unit. Data is stored in the nonvolatile storage memory 11. Then, the stored image data is transmitted to the outside of the vehicle (management center, vehicle owner, etc.) via the communication I / F 3 and communication module terminals (Tx, Rx), for example, as evidence of theft, and promotes criminal clearance. Or monitoring the vehicle with a camera to prevent theft of the vehicle. Note that image data that has been transmitted is sequentially deleted. The specific operation is as follows.

  When power from a battery (not shown) is supplied, the main control system power supply 1 is turned on, a communication I / F (interface) 3, a microcomputer 4, a bus buffer 5, an input I / F 8, a memory control unit 9, and image data The voltage VDD1 is supplied to the work memory 10 and the image data nonvolatile storage memory 11 (in the image data nonvolatile storage memory 11, the voltage VDD1 is used for data reading drive: a booster circuit (not shown) for data erasing and writing Voltage VDDH (> VDD1) is used (reverse polarity at the time of erasure)).

  When a theft detection signal from the security ECU is detected via the theft detection signal terminal, or when the proximity sensor (sensor signal) detects the approach of the human body (OFF → ON state), the microcomputer 4 turns on the image power supply 2 In order to set the state, the DC_EN terminal is turned on. As a result, the image power supply 2 supplies the voltage VDD2 to the field memory 6, the video decoder 7, the camera (not shown), and the auxiliary light source for the camera, and puts the video decoder 7 into a wake-up state. On the other hand, when the theft detection signal is not detected (ON → OFF state), the microcomputer 4 turns off the DC_EN terminal. As a result, the supply of the voltage VDD2 from the image power supply 2 to the field memory 6, video decoder 7, camera (not shown), and camera auxiliary light source is stopped.

  When the video decoder 7 is in the wake-up state, the microcomputer 4 checks whether there is digital image data in the field memory 6, and if there is data, reads it and transfers it to the image data work memory 10. Details will be described with reference to FIG. The field memory 6 stores the captured digital image data for one frame, and is divided into 8 lines from the top pixel line (corresponding to the scanning lines constituting each field of the analog image data). Assume that the converted image data is 1, 2, 3, 4... N (A1 to A3).

  1 sequentially reads the fragmented image data 1, 2, 3, 4... N from the field memory 6 from the head side and transfers them to the image data work memory 10 (A4). . As described above, the field memory 6 is composed of an odd field memory 6p and an even field memory 6s each formed of a FIFO memory. When data of one pixel line is read from the odd field memory 6p, the memory switch is switched, Data of one pixel line is read from the field memory 6s. When this is repeated alternately and data for 8 lines is read, the process waits until the reading / transfer processing of one fragmented image data is completed and the transfer of the next fragmented image data is permitted. In FIG. 2, the odd-numbered field memory 6p and the even-numbered field memory 6s are drawn for one frame, but actually, these memories 6p and 6s are provided for a plurality of frames, While transferring the pixels from the memories 6p and 6s to the image data work memory 10, the pixels from the video decoder 7 are fetched in parallel to the last memories 6p and 6s.

  On the other hand, if the transferred fragmented image data exists in the image data work memory 10, the microcomputer 4 takes in the fragmented image data and performs data compression processing according to the JPEG system by software processing (A5, A5). A6) The obtained compressed image data is stored in the main memory in the microcomputer 4 (A8). In the image data work memory 10, there are a plurality of storage areas for fragmented image data. In this embodiment, as shown in FIG. 2, three storage areas of a first area to a third area are secured. While the DMA control unit 4D transfers the fragmented image data from the field memory 6 to one of the storage areas, the microcomputer 4 (or the CPU thereof) has already transferred to the other storage area. The compression processing of the fragmented image data to be executed is executed in parallel.

  FIG. 3 shows the flow of a program executed by the microcomputer 4 for the above processing. The left flow is a fragmented image data transfer command sequence to the DMA control unit 4D, and the left flow is fragmented image data. Each of the compression processing sequences is shown. These programs are executed in parallel by the CPU of the microcomputer 4. First, regarding the transfer sequence of fragmented image data, the CPU of the microcomputer 4 determines whether or not there is image data in the field memory 6 that is the data transfer source, and whether or not there is an empty area in the image data work memory 10 that is the data transfer destination. And determines whether or not data transfer is possible. If the data transfer is possible, the DMA control unit 4D is instructed to start the transfer of fragmented image data (of course, the CPU Is not involved in the fragmented image data transfer process itself).

  That is, in S1, if fragmented image data exists in the field memory 6, the process proceeds to S2, and it is confirmed whether or not there is an empty area in the image data work memory 10. If not, the process waits until an empty area is generated. On the other hand, if it exists, the process proceeds to S3, and a transfer start signal of the fragmented image data to the image data work memory 10 is transmitted to the DMA control unit 4D. The DMA control unit 4D starts the pixel transfer of the fragmented image data to the image data work memory 10, counts the transfer clock, and returns the transfer end status to the CPU of the microcomputer 4 when the last pixel is transferred. . Then, the process on the CPU side proceeds to S4, and the fragmented image data that has been transferred is deleted from the field memory 6 and the process returns to S1, and the following processes are repeated. If no fragmented image data remains in the field memory 6 in S1, the transfer process ends.

  On the other hand, in the flow of compression processing, whether or not there is fragmented image data in the image data work memory 10 is confirmed at T1, and if fragmented image data exists, the process proceeds to T2 and the fragmented image data is processed. The data is read and compressed, and the compressed image data is stored in the main memory 4M in FIG. If the compression process is completed, the process proceeds to T3 and the processed fragmented image data is deleted from the image data work memory.

  When the pixel transfer of the fragmented image data to the image data work memory 10 is started, the CPU of the microcomputer 4 waits until another transfer completion status is returned from the DMA control unit 4D. In other words, it is possible to concentrate on the compression processing of the fragmented image data, and the efficiency of the compression processing can be increased.

  In addition, since the size of the fragmented image data is adjusted to the 8-pixel line which is the compression processing unit in the JPEG format, the beginning and end (breaks) of the fragmented image data are unchanged at the beginning and end ( Matches the break). If these discontinuities do not match, if a compression processing unit that spans two fragmented image data occurs, the first half of the compression processing unit belonging to the preceding fragmented image data is the next one that compensates for the latter half. Until the transfer of the fragmented image data is completed, it is physically impossible to perform compression processing. However, if the fragmented image data and the compression processing unit match, as long as one fragmented image data is written alone on the image data work memory 10, the CPU waits for the start of the compression processing. When it reaches the state, it can be immediately subjected to compression processing.

  As shown in FIG. 4, in this embodiment, the CPU work time required for compression processing of one fragmented image data is the work time of the DMA control unit 4D required for transfer processing of one fragmented image data. It is 2 times or more and 3 times or less. Considering this, as shown in FIG. 2, the image data work memory 10 has three storage areas, ie, a first area A, a second area B, and a third area C. When the transfer of the first fragmented image data to the first area A is complete, as described above, the fragmented image data in the first area A is immediately started to be compressed. Since the work time of the compression process is longer than the work time required to transfer the two pieces of fragmented image data, the DMA control unit 4D is an empty area in the initial state using this interval. The transfer of the fragmented image data to the second area B and the third area C can be executed sequentially (that is, the DMA control unit 4D transfers the fragmented image data until there is no more free space in the image data work memory 10). Processing can continue).

  The fragmented image data in the second area B has been transferred before completion of the compression of the fragmented image data in the first area A, and the compression process can be started anytime. Therefore, when the compression processing of the fragmented image data in the first area A is completed, the process immediately shifts to the compression processing of the fragmented image data in the second area B. On the other hand, the fragmented image data in the first area A is cleared upon receiving a completion notification from the compression program side. Then, using the data clear as a trigger, the CPU instructs the DMA control unit 4D to transfer the next fragmented image data. That is, in the image data work memory 10, when an empty area is generated by data clear, the transfer processing of the next fragmented image data to the empty area is started immediately.

  With the above sequence, as shown in FIG. 4, except for the first fragmented image data, all the subsequent fragmented image data transfer processing periods are compressed for the fragmented image data that has been transferred first. It is obvious that the transfer / compression processing cycle of the image data of one frame is greatly shortened because it overlaps with the period.

  Returning to FIG. 2, when all the fragmented image data have been compressed, a set of compressed fragmented image data for one frame in the main memory is written to the image data nonvolatile storage memory 11 at once. The process is terminated (A9).

  In the above-described embodiment, as the image data to be subjected to compression processing, full data in which an odd field and an even field are combined into one frame and pixel lines are not thinned out is employed. However, when image data does not require a very high resolution, it is possible to use an image data frame obtained by thinning out a part of a pixel line. Specifically, as shown in FIG. 5, if only one of the even field and the odd field is employed, thinning processing for every other line can be realized as a result. In order to further increase the thinning rate of the odd field lines, a part of the pixel lines may be thinned out in either the even field or the odd field in the figure. In FIG. 6, the odd field is further thinned out every other line, but of course, it is possible to thin out every two lines or more. In the present embodiment, one line of data is fetched into the image data work memory 10 in the form of full data without thinning out pixel lines, and the pixel lines to be subjected to compression processing on the image data work memory 10 capable of random access. The thinning process is performed in the form of taking out only.

The block diagram which shows an example of the electrical constitution of the image processing apparatus for vehicles of this invention. The figure which shows typically the operation | movement sequence of the image processing apparatus for vehicles of FIG. FIG. 3 is a program flow diagram for realizing the operation sequence of FIG. 2. Explanatory drawing of the effect of the image processing apparatus for vehicles of this invention. The figure which shows typically the 1st example of the process which thins out a pixel line. The figure which shows a 2nd example typically similarly.

Explanation of symbols

4 Microcomputer (compression processing means, condition determination means, image processing end detection means)
4D DMA controller (fragmented image data transfer means)
6 Field memory (image buffer memory)
10 Image data work memory (main control unit)
11 Image data non-volatile storage memory (compressed image data storage memory)
100 image capturing device

Claims (12)

An image buffer memory for buffering image data captured by the in-vehicle camera in units of frames;
An image data work memory for compressing image data transferred from the image buffer memory;
Fragmented image data transfer means for dividing a frame of image data in the image buffer memory in a line arrangement direction of image pixels into a plurality of fragmented image data and sequentially transferring the fragmented image data to the image data work memory When,
Compression processing for sequentially reading and compressing the fragmented image data transferred to the image data work memory in parallel with the transfer processing of the fragmented image data to the image data work memory by the fragmented image data transfer means Processing means;
A vehicular image processing apparatus characterized by comprising:   The compression processing means performs the compression processing in a compression processing unit in which a certain number of image pixel lines are grouped into one frame of image data, and the fragmented image data matches the compression processing unit. The vehicle image processing apparatus according to claim 1, wherein a data size is determined. The compression processing means is constituted by a microcomputer that executes the compression processing of the fragmented image data read by the fragmented image data reading means by software processing by a CPU,
The vehicular image processing apparatus according to claim 1, wherein a direct memory access control unit that realizes the function of the fragmented image data transfer unit by direct memory access not via the CPU is provided.   The microcomputer immediately starts the compression processing on the fragmented image data from the image data work memory after the transfer processing of the fragmented image data to the image data work memory by the direct memory access control unit is completed. The vehicular image processing apparatus according to claim 3, wherein the vehicular image processing apparatus is used. The image data work memory has a plurality of storage areas for the fragmented image data,
The process of writing the fragmented image data newly transferred by the fragmented image data transfer means into one of the plurality of storage areas, and the fragmented image data already written in another storage area The vehicle image processing apparatus according to claim 1, further comprising an image data work memory control unit that performs reading processing for reading out the data for compression processing in parallel.   The image data work memory control means clears the storage area from which the fragmented image data has been read for the compression process, and the fragmented image data transfer means stores the image data work memory in the image data work memory. If the cleared storage area exists, the transfer processing of the fragmented image data is continued. If the cleared storage area does not exist, the fragmentation is performed until the newly cleared storage area is newly generated. The vehicular image processing apparatus according to claim 5, wherein the vehicular image processing apparatus waits for image data transfer processing.   The image data work memory has three storage areas for the fragmented image data, and one of the storage areas always waits for the reading process with the writing of the fragmented image data completed. The vehicular image processing apparatus according to claim 6, which is secured as a read standby area to be in a state.   The vehicular image processing apparatus according to any one of claims 1 to 7, further comprising a compressed image data storage memory that includes a nonvolatile memory and stores the compressed fragmented image data as compressed image data.   9. The vehicular image processing device according to claim 8, wherein the compressed image data storage memory stores the fragmented image data in a form of being aggregated in units of frames.   The vehicle according to any one of claims 1 to 9, wherein the image data to be subjected to compression processing is obtained by thinning out a part of the pixel line in a frame of the image data. Image processing device.   The vehicular image processing apparatus according to claim 10, wherein the image data to be subjected to compression processing is composed of only one of an even field and an odd field constituting a frame of the image data.   12. The vehicular image processing apparatus according to claim 11, wherein the image data to be subjected to compression processing is obtained by thinning out a part of the pixel line in one of the even field and the odd field.

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