JP2001237930A - Method and device for information processing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption by changing the frequency of a clock signal supplied to each processing block in accordance with the data volume in a memory in the processing block. SOLUTION: In a device which performs picture processing of a picture taken in by a picture taking-in controller 1 by a signal processing processor 2 and displays it by a display controller 3, the picture talking-in controller 1 takes in picture data with a resolution and a frame rate which are designated in accordance with an operation mode, and the display controller 3 displays picture data with the resolution and the frame rate which are designated in accordance with the operation mode. These controllers are operated synchronously with the supplied clock signal, and each controller has a FIFO where processed data or data to be processed is stored, and the data volume in the FIFO is reported to a clock generator, and the clock signal of which the frequency is changed in accordance with the data volume is inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and method applicable to, for example, a digital still camera, a portable videophone terminal, or a notebook PC with a built-in camera.

[0002]

2. Description of the Related Art In recent years, digital still cameras are typified by advances in technologies such as miniaturization and power saving of solid-state imaging devices such as CCDs, and high integration, high functionality, and low power consumption of LSIs. As described above, a portable photographing apparatus that can be driven by a battery has been generally used. Further, a portable videophone terminal with a built-in mobile phone function, a notebook PC with a built-in camera, and the like have been developed. In such an imaging device driven by a battery in particular, reduction of power is required to extend the operation time of the battery. AC
There is also a demand for a more effective power saving function in an imaging device driven by a power supply from the viewpoint of environmental protection and the like. For this reason, the remaining battery level is always displayed, and when the remaining battery level becomes low, the user is urged to turn off the power frequently or the clock supply to the non-operating part is cut off according to the operation mode selected by the user. Power saving function is realized.

[0003]

Generally, in a photographing apparatus, the higher the frame rate and the resolution of a photographed image, the larger the amount of image data to be processed per unit time, so that the number of electronic circuits handling image data is high. Requires operating clock frequency. In general, the power consumption of a circuit is
An increase in image frame rate and resolution results in an increase in power consumption because it increases in proportion to the clock frequency driving the circuit. Therefore, in order to reduce power consumption, it is desirable to reduce the frame rate and the resolution as much as possible.

However, in a photographing apparatus such as a digital camera, requirements for the frame rate and resolution of an image to be taken differ depending on the operation mode. For example, in the electronic viewfinder mode (referred to as EVF mode), it is desirable to display a smooth moving image as much as possible, but the display screen is often a small screen built in the device. Therefore, the higher the frame rate, the better, but the resolution is not so required. In the still image capturing mode (called a shooting mode), the frame rate may be the lowest (for a still image), but the resolution is required to be the maximum. Furthermore, in the reproduction mode for reproducing the recorded image, the image signal is not taken in by the image sensor, and the display on the display unit is performed at the maximum resolution. In the videophone mode, both the frame rate and resolution are determined by the data transfer capability of the telephone line.

As is apparent from the above example, each of the functional blocks constituting such a photographing apparatus, for example, a photographing function block, an image processing function block, a display function block, etc. The amount of data to be processed greatly differs, and it is not necessary to always operate at the maximum frequency. As long as normal operation is performed, it is possible to reduce the power consumption of the apparatus by operating at the lowest possible frequency. Nevertheless, in the conventional technology, the power consumption of the device is reduced only by stopping the supply of the clock signal to the functional block that is completely inactive, so that effective power reduction can be performed. could not.

The present invention has been made in view of the above conventional example, and the frequency of a clock signal supplied to each of a plurality of processing means is switched in accordance with the operation state of the processing means, so that the power consumption of the entire apparatus is reduced. It is an object of the present invention to provide an information processing apparatus and a method thereof that can suppress the occurrence of an error.

Another object of the present invention is to reduce the frequency of a clock signal supplied to each of a plurality of processing means in accordance with the load state of the processing means, thereby reducing the power consumption of the entire apparatus. An object of the present invention is to provide a processing apparatus and a method thereof.

[0008]

In order to achieve the above object, an information processing apparatus according to the present invention has the following arrangement.
That is, a clock generation source that generates a plurality of clock signals having different frequencies, and a selection unit that selects one of a plurality of frequency clock signals output from the clock generation source; And a plurality of processing units that are operated by a clock signal from a clock generation source selected by the control unit, and a selection unit that controls selection of a clock signal to the processing unit by the selection unit according to an operation state of each of the plurality of processing units. And control means.

In order to achieve the above object, an information processing method according to the present invention includes the following steps. That is, a selecting step of selecting any one of a plurality of clock signals output from a clock generating source that generates a plurality of clock signals having different frequencies, and a clock generating circuit selected in the selecting step. A selection control step of controlling selection of a clock signal for the processing means in accordance with an operation state of each of the plurality of processing means operated by a clock signal from a source.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a configuration of a portable videophone terminal according to an embodiment of the present invention.
In FIG. 1, of the lines connecting the functional blocks,
The connection of the data system is shown by a thick solid line, the connection of the control system is shown by a thin solid line, and the connection of the clock system is shown by a dotted line. However, not all connections are shown.
Only representative wiring connections required for the description are shown.

The main components of the videophone terminal device are an image capture controller 1 for executing processing relating to capture of a captured image signal, and a signal processor for executing image processing on image data generated from the image signal. 2, a display controller 3 for performing processing related to image display based on image data, a memory controller 4 for performing memory control for storing image data in a memory, and a CPU 5 for controlling the entire apparatus.

First, as a typical operation mode, EVF
The operation will be described for each of (viewfinder) mode, shooting mode, playback mode, and videophone mode.

[Explanation of Image Capture Controller 1] An image to be imaged is formed on the CCD 7 via the lens module 6, and an image signal corresponding to the image is output from the CCD 7. This lens module 6
Includes a lens, a drive system for an auto iris, a drive system for an auto focus, and the like. The control of these drive systems is performed by the CPU 5 by a control signal (not shown). The image signal output from the CCD 7 is input to a preprocessing module (CDS / AGC) 8. In the present embodiment, the number of effective pixels captured by the CCD 7 is 640 ×
There are 480 pixels (equivalent to VGA). Pre-processing module 8
Has CDS (correlated double sampling) and AGC (automatic gain control) functions. Clocks and timing signals for the CCD 7 and the preprocessing module 8 are supplied from a timing generation circuit (TG) 9. The image data pre-processed by the pre-processing module 8 is A /
The data is converted into 10-bit digital data by a D converter (ADC) 10 and input to the image capture controller 1 in synchronization with a pixel clock (Pixel Clock) generated by a timing generation circuit (SG) 11.

The image data input to the image capturing controller 1 is subjected to a thinning process by a thinning circuit 1a.
Data resulting from the thinning is written to the FIFO 1b. The thinning method in the thinning circuit 1a is set in advance by the CPU 5 based on a control signal (not shown).

FIG. 2A is a timing chart showing an example of the operation of the thinning circuit 1a. Thinning circuit 1a
Is the pixel clock (Pixel C) input from SG11.
lock), and a line counter (Line Num) for counting the number of image lines based on a horizontal / vertical synchronization signal (not shown).
The digital image data input from the ADC 10 is latched based on the thinning method set in advance by the PU 5 and the count values of these counters, and a clock (Latch Clock) for writing to the FIFO 1b is generated.

In the example of FIG. 2A, the data of 640 pixels in the horizontal direction and 480 lines in the vertical direction are both 1 in the horizontal and vertical directions.
/ 2 thinning out (320 × 240 pixels: CIF
(Equivalent). Therefore, the active line is an odd line, and a signal indicating this period is an active line.
Signal. The effective pixels are odd pixels, and a signal indicating this is an Active Pixel signal.

Based on these signals, a logical product of a Pixel Clock, an Active Line signal, and an Active Pixel signal is obtained as shown in FIG. 2B, and this is a Latch Clock signal for writing to the FIFO 1b. In FIG. 2A, the data written to the FIFO 1b is a Data to FIFO.
It is.

The thinning circuit 1a can be configured to have a frame thinning function. In this case, an additional frame counter is provided. For example, when capturing one frame every four frames, an active frame signal is generated when the frame counter is “multiple of 4 + 1”,
What is necessary is just to add to the input of the AND circuit shown in FIG.

Bus interface circuit (BUS IF) 1c
Detects a state in which the FIFO 1b is not empty (any data is written), generates a bus transaction for writing data on the main bus (MB), and transfers the data read from the FIFO 1b to the memory controller 4. . The bus interface circuit 1c normally operates with a bus clock that is asynchronous with the image capture clock (Latch Clock). Therefore, the read clock of the FIFO 1b is the write clock (Latch
Clock), the FIFO 1b is provided to buffer this asynchronous data transfer.

A plurality of other bus masters that generate bus transactions are connected to the main bus MB (signal processor 2, display controller 3,
CPU5), there is a possibility that a plurality of bus transactions may occur at the same time. Therefore bus arbiter 12
Arbitrates the bus so that only one bus master can generate a bus transaction at a time.

[Description of Memory Controller 4] The memory controller 4 is a bus interface circuit (BUS IF).
At 4a, a bus transaction is received, and image data to be stored and a memory address at which the image data is to be stored are written to the temporary buffer 4b. The SDRAM interface circuit (SDRAM IF) 4c outputs various control signals to the SDRAM 13, which is an image memory, and outputs the memory address and image data stored in the buffer 4b to the SDRAM 13. The bus interface circuit 4a, the buffer 4b, the SDRAM interface circuit 4c, and the SDRAM 13 all operate in synchronization with the bus clock.

[Explanation of the Signal Processor 2] The signal processor 2 generates a bus transaction for reading image data and captures the image data by a bus interface circuit (BUS IF) 2a operated by a bus clock by an image capture controller. The read image data is read from the image memory. The read image data is written to the bidirectional FIFO 2b in synchronization with the bus clock. DSP (Digital Signal Processor) 2c
Operates at a clock (DSP clock) different from the bus clock, accesses data in the bidirectional FIFO 2b in synchronization with the DSP clock, performs YC separation by color matrix processing, and subsequently performs color correction and edge correction. Performs processing such as emphasis, white balance adjustment, and gamma correction. The image data thus obtained is used not only for display on the monitor 15 but also for image compression. When used for display on the monitor 15, the bus interface circuit 2 a is activated so that the display controller 3 can read the data, generates a write bus transaction, and transfers data to the SDRAM 13.

[Explanation of EVF Mode] In the EVF mode, the above-described operation is repeated for each frame, so that a continuous frame is taken into the image memory 13.
As an area of the image memory where the signal processor 2 writes image data, an operation of overwriting the same area may be used. The display controller 3 obtains display data by reading image data from the area of the image memory. that time,
The display controller 3 generates a bus transaction for reading image data, and reads image data to be displayed from the image memory 13 by a bus interface circuit (BUS IF) 3a operated by a bus clock. The display controller 3 further inputs the read image data to the write port of the FIFO 3b in synchronization with the bus clock. Generally, a display device, such as an NTSC monitor or a liquid crystal display, needs to constantly refresh the screen. Therefore, during a valid screen period, the display device must continue to operate at a certain pixel clock. Therefore, the bus interface circuit 3a keeps reading image data from the image memory until the FIFO 3b becomes full.

Next, the interpolation circuit 3c reads out image data from the FIFO 3b in synchronization with the display pixel clock.
The interpolation circuit 3c has a line memory,
The image data read from b is first stored in this line memory. The image data stored in the line memory is sequentially read from the head when no interpolation is performed.
The data is input to the TSC encoder 3d, and is converted into video data in the NTSC format. In this case, the interpolation circuit 3c
Reads the image data for one pixel from the FIFO 3b immediately after the image data for one pixel is read. Here, in the case of performing the line interpolation, the line data of (number of lines to be interpolated-1) is transmitted to the NTSC encoder 3d, and then the next line of image data of one pixel is transmitted to the NTSC encoder 3d. FIFO3b
From the image data of one pixel. For example, when performing quadruple interpolation in the line direction, three lines are displayed by the image data from the line memory, and when displaying the fourth line, F is displayed while displaying the line.
The operation of reading the image data of the next line from the IFO 3b is performed.

The NTSC encoder 3d uses the NTSC
The video data converted to the format is converted to an analog signal by a D / A converter (DAC) 14 and then converted to an analog signal.
Displayed by the monitor 15 of the TSC.

By performing the above operation continuously for each frame, the operation becomes an EVF mode operation. In the EVF mode, it is necessary to read out image data of each frame even if the image capturing controller 1 performs frame thinning. In this case, the displayed image is dropped, but the monitor 15 needs to keep operating at a constant frame rate.

[Explanation of shooting mode] Next, the operation in the shooting mode will be described. In this shooting mode, after capturing one frame of image data, this image data is
The data is G-compressed and recorded in an external storage such as the memory card 17.

First, when the CPU 5 detects that the shutter button of the switch group 16 including the shutter button or the like is pressed, the CPU 5 fetches the next one frame of image data to the image fetch controller 1 by a control signal (not shown). , So as not to take in the image data of the subsequent frames. Similarly, it notifies the signal processor 2 to perform a compression process on the image data of the next one frame.

The image capture controller 1 is provided with the aforementioned E
Unlike the case of the VF mode, when the image of one frame is fetched and the image data is transferred to the image memory 13,
Pause the operation. The signal processor 2 reads out the image data for one frame stored in the memory 13, and performs the YC separation, the color correction, the edge enhancement, and the like in the same manner as when the image data for display is generated in the EVF mode.
Image processing such as white balance adjustment and gamma correction is performed. Thereafter, the coded data obtained by subjecting the image data to a DCT operation process, a quantization process, a variable length coding process, etc., is immediately stored in an area other than the display image data area in the image memory 13. Write to.

The CPU 5 reads out the image data stored in the image memory 13 and adds necessary markers and the like to the JP5.
After being converted into EG data, it is stored in the memory card 17.
When the storage of the image data for one frame is completed in this way, the CPU 5 instructs the image capturing controller 1 to
A notification is issued to restart the capture of the image signal in the EVF mode.

The encoded image data stored in the memory card 17 can be accessed from a PC or the like via a communication circuit 18 for realizing an interface with a host computer such as a PC. In the present embodiment, the communication circuit 1
8 is, for example, a serial interface, USB, Ir
DA, mobile phone module, etc.

[Explanation of Reproduction Mode] Next, the operation of the reproduction mode will be described. In this reproduction mode, the operation of the image capture controller 1 is stopped. The CPU 5 reads out the coded compressed data stored in the memory card 17 and writes it to the SDRAM 13. Signal processor 2
Reads out the code data written in the SDRAM 13 and performs image expansion processing such as decoding, inverse quantization, and inverse DCT conversion to obtain displayable image data, and then returns to SD
Write back to RAM13. The display controller 3 reads out the displayable data from the SDRAM 13 and performs a display operation.

[Explanation of Video Phone Mode] Next, the operation of the video phone mode will be described. In the above-described shooting mode, the image capturing controller 1 temporarily stops operation after capturing one frame of image data. However, in this videophone mode, the image data of successive frames is fetched without interrupting the image data fetching process. The capture frame rate at this time is
5 is determined on the basis of the thinning method set in step S5. The image data thus captured is subjected to image processing and image compression / encoding processing by the signal processor 2 by the same processing as in the shooting mode, and the SDRA
Written to M13. The code data thus written in the SDRAM 13 is read out by the CPU 5, and after a predetermined marker or the like is inserted, the code data is transmitted to the other party through the telephone line by the mobile phone module of the communication circuit 18.

On the other hand, the code data received from the other party through the telephone line
The data is written to the SDRAM 13 via the PU 5. The signal processor 2 reads out the code data written in the SDRAM 13 and decodes, dequantizes,
After performing image expansion processing such as conversion to obtain displayable image data, the image data is written back to the SDRAM 13 again. The display controller 3 performs a display operation such that image data to be displayed is read from the SDRAM 13 and displayed on the monitor 15.

As described above, the image picked up by the CCD 7 can be transmitted to the other party, and the image data sent from the other party can be received and displayed on the monitor 15.

[Description of Clock] Next, the clock supplied to each of the image capture controller 1, the signal processor 2, the display controller 3, and the memory controller 4 will be described.

Clock generators (CG) 19, 20, 21,
Reference numeral 22 denotes a variable clock generator whose clock output can be turned on / off by the CPU 5. The clock generator (CG (C)) 19 includes an SG 11 and an image capturing unit (the thinning circuit 1 a, the FIFO 1) of the image capturing controller 1.
The operation clock of b) is generated. Clock generator (CG
(D)) 20 generates an operation clock of the DSP 2c.
The clock generator (CG (B)) 21 generates an operation clock for the bus interface of each controller. The clock generator (CG (N)) 22 is connected to the F of the display controller 3.
An operation clock for the IFO 3b, the interpolation circuit 3c, the NTSC encoder 3d, and the D / A converter 14 is generated.

The bus clock output from the clock generator 21 is supplied to the bus interface circuit of each controller. The clock gate circuits (G) 23, 2 are provided so that the clock supply can be stopped for each controller.
4, 25, 26 are provided. Among them, the clock gate circuit 26 is controlled by the CPU 5, the clock gate circuit 23 is controlled by a control signal from the FIFO 1b, the clock gate circuit 24 is controlled by a control signal from the FIFO 2b, and the clock gate circuit 25 is controlled by a control signal from the FIFO 3b. .

Next, the thinning circuit 1 according to the operation mode
a, how to control the setting of the interpolation circuit 3c will be described.

The operation mode is changed by operating the switch group 16 by the user. Although various examples of the configuration of the switch can be considered, in this embodiment, the switch is configured by a dial and a push button. The operation mode candidates are sequentially updated and displayed by the rotation of the dial, and when the candidates are displayed, pressing the push button selects the displayed operation mode as the actual operation mode. The CPU 5 is interrupted by the operation mode selection event, and the operation mode change processing routine is executed by the interrupt processing routine stored in the ROM 27.

In this operation mode change processing routine, the operation mode newly selected is read, and the thinning circuit 1a and the interpolation circuit 3 are read in accordance with the read operation mode.
An initial value is set in c. The default values set in the thinning circuit 1a and the interpolation circuit 3c are stored in the ROM 27 at the time of shipment from the factory. When the user changes the set value, the RAM 28 stores the flag indicating the change and the correspondence of the changed portion.

FIG. 3 is a view for explaining an example of the correspondence between the operation mode and the set values of the thinning method and the interpolation method.

Here, four types of operation modes are defined: EVF, shooting, reproduction, and videophone. The thinning method is divided into a resolution (denoted as size in the figure) and a frame rate (denoted as frame in the figure), and the interpolation method indicates only the resolution.
This is because, in the present embodiment, the frame rate is constant because the display is an NTSC output. For the resolution thinning / interpolation method, the vertical / horizontal 1/2 thinning / interpolation method is referred to as “CI
F ”, and in the case of 1/4 vertical / horizontal thinning / interpolation,“ Q
CIF ". The frame rate is 1
If 30 frames per second, 30 frames / s (frame /
s). In addition, when indicating a stopped state, it is shown as "-".

According to the example shown in FIG. 3, when the new operation mode read by the operation mode change routine is the EVF mode, the resolution thinning / interpolation method is "CIF" and the frame rate is 30 frames / frame. Set to s.
In the photographing mode, the display is stopped, and the VGA is set so as to capture only one frame. Further, in the case of the reproduction mode, the image capturing is stopped, and "VGA" is displayed. In the case of the videophone mode, the resolution thinning / interpolation method is “QCIF” and the frame rate is 15 frames / frame.
Set to s. The CPU 5 reads the data corresponding to the contents of FIG. 3 from the ROM 27 or the RAM 28 and obtains the setting of the thinning method in the thinning circuit 1a and the setting of the interpolation method in the interpolation circuit 3c.

Next, how to control the settings of the clock generators 19 to 22 and the clock gate circuits 23 to 26 will be described.

The clock generator 19 outputs a 13.5 MHz clock signal as a pixel clock in response to the ON signal from the CPU 5. This pixel clock is normally turned on (output), but is turned off in the reproduction mode because there is no need to newly acquire an image signal.

The clock generator 20 receives the signal from the CPU 5
Clocks of four different frequencies can be generated by the bit clock selection signal. That is, when the selection signal is “0”
In the case of "0", it is 0 MHz, that is, the clock generation is stopped. In the case of "01", a clock of 50 MHz is output. In the case of "10", a clock of 100 MHz is output. In the case of "11", Outputs a clock of 150 MHz.The 2-bit selection signal is controlled by a control program stored in the ROM 27 and read out and executed by the CPU 5. That is, depending on the operation mode and the resolution of the image data to be processed. Since the amount of image data to be processed per unit time differs, for example, in the EVF mode, V
For GA, operate at 100MHz, CIF and QC
The IF operates at 50 MHz. In the videophone mode, the VGA operates at 150 MHz, the CIF operates at 100 MHz, and the QCIF operates at 50 MHz.
Control such as operating at MHz.

The clock generator 21 is started / stopped by an on / off signal from the CPU 5, and the frequency of the generated clock is changed by a control signal from the FIFOs 1b, 2b, 3b even in the activated state. .

FIG. 4 is a block diagram showing an example of the clock generator 21.

Reference numeral 21a denotes a clock source oscillator, 80 MHz
Clock is always generated. 21b is the clock 1
/ 2 frequency divider, which receives a clock signal of 80 MHz and outputs a clock signal of 40 MHz. Reference numeral 21c denotes a clock frequency divider which receives a 40 MHz clock signal and outputs a 20 MHz clock signal. 2
Reference numeral 1d denotes a clock frequency divider which receives a 20 MHz clock signal and outputs a 10 MHz clock signal. 21e is a clock selector which selects one of the four clock inputs A, B, C, D from the selection signal Se.
Output to the output terminal Out according to lA, SelB, SelC, SelD.

FIG. 5 is a diagram for explaining the process of selecting a clock signal in the clock selector 21e.

The priority becomes higher in the order of the selection signals SelA, SelB, SelC, and SelD. For example, when SelD is "1", the clock signal input to the D terminal is output to the Out terminal regardless of the state of other selection signals. Is output. Here, each of the inputs A, B, C, and D has a frequency of 10 M
Hz, 20 MHz, 40 MHz, and 80 MHz clock signals are input, respectively. The output of the AND circuit 21f is connected to the terminal SelA, and the OR 21g is connected to the terminal SelB.
The output of OR21h is connected to the terminal SelC, and the output of OR21I is connected to the terminal SelD. AND21f, OR21g, 21h, 21i
Are connected to pointer status signals of FIFOs 1b, 2b and 3b, respectively. The meaning of each pointer status signal will be described with reference to FIG. 6, which is a configuration diagram of an example of the FIFO 1b, FIG. 7, which is a configuration diagram of an example of the FIFO 2b, and FIG. 8, which is a configuration diagram of an example of the FIFO 3b.

FIG. 6 is a block diagram showing a configuration example of the FIFO 1b of the present embodiment.

The FIFO 1b includes a synchronous dual-port SRAM 1b0, a write control circuit 1b1, a write address generation (pointer generation) circuit 1b2, a read control circuit 1b3, and a read address generation (pointer generation).
An image path 1b4 and a pointer status generation circuit 1b5 are provided.

The dual port SRAM 1b0 is, for example, a 128 (word) × 8 (bit) dual port SR.
In AM, the write enable signal (writ) from the thinning circuit 1a
e en) is input, the CCD pixel clock (ccd
In synchronization with clk), WRITE DATA, which is CCD data, is written to a memory address output from the write address generation (pointer generation) circuit 1b2. After one image data is written in the dual-port SRAM 1b0, the write address output from the write address generation circuit 1b2 is incremented by one. The read operation starts from an address indicated by a pointer generated by a read address generation (pointer generation) circuit 1b4 in synchronization with a bus clock (bus clk) when a read enable signal (read en) is input from the bus interface circuit 1c. READ DATA is output.

After one image data is thus read, the read address output from the read address generation circuit 1b4 is incremented by one. The pointer status circuit 1b5 outputs the status of the FIFO 1b by calculating the absolute value of the difference between the write pointer (address) and the read pointer (address). For example, if the absolute value of the difference is “0”, FIFO1
Since “b” is empty, “1b: Empty” signal is output. If the absolute value of this difference is 80% or more of the capacity (128 words) of the FIFO 1b, the FIFO 1
Since the effective data of b is less than 20% of the capacity of the FIFO 1b, a "1b <20%" signal is output. Similarly, when the valid data of the FIFO 1b is between 20% and 40%, a “1b> 20%” signal is output, and when the valid data is between 40% and 60%, a “1b> 40%” signal is output. 6
If it is 0% or more, a "1b>60%" signal is output.

FIG. 7 is a block diagram showing the structure of the FIFO 2b.

The FIFO 2b is connected to the bus interface circuit 2a from the DSP 2c in the direction opposite to the FIFO.
Implemented as a combination of IFOs. The FIFO from the bus interface circuit 2a to the DSP 2c includes a synchronous dual-port SRAM 2b0, a write control circuit 2
b1, write address generation (pointer generation) circuit 2b
2, a read control circuit 2b3, a read address generation (pointer generation) circuit 2b4, and a pointer status generation circuit 2b5.

On the other hand, a FIFO from the DSP 2c to the bus interface circuit 2a is a synchronous dual port S
RAM 2b6, write address generation (pointer generation)
The circuit includes a circuit 2b7, a read address generation (pointer generation) circuit 2b8, a write control circuit 2b9, a read control circuit 2b10, and a pointer status generation circuit 2b11.

The dual port SRAM 2b0 is, for example, a 128 (word) × 8 (bit) dual port SR.
AM, and when a write enable signal (write en) is input from the bus interface circuit 2a, WRITE DAT which is bus transfer data is synchronized with a bus clock (bus clk).
A is a write address generation (pointer generation) circuit 2b2
Is written to the memory address generated by. After writing the data, the write pointer (address) output from the write address generation circuit 2b2 is incremented. In the read operation, when a read valid signal (read en) from the DSP 2c is input, READDATA is output from the address indicated by the pointer generated by the read address generation (pointer generation) circuit 2b4 in synchronization with the DSP clock (dsp clk). This is read out. After reading this data, the read address generation circuit 2b
The read pointer output from 4 is incremented. The pointer status circuit 2b5 outputs the status data of the FIFO 2b by calculating the absolute value of the difference between the write pointer and the read pointer.

The dual port SRAM 2b6 is, for example, a 128 (word) × 8 (bit) dual port SRAM, and is a write enable signal (writ) from the DSP 2c.
When “en” is input, WRITE DATA, which is bus transfer data, is written to the memory address generated by the write address generation (pointer generation) circuit 2b7 in synchronization with the DSP clock (dsp clk). After writing the child data, the write pointer output from the write address generation circuit 2b7 is incremented. The read operation is
When a read enable signal (read en) is input from the bus interface circuit 2a, the read address generation (pointer generation) circuit 2 is synchronized with the bus clock (bus clk).
READ from the memory address indicated by the pointer generated by b8
It reads DATA because it outputs DATA. After reading the child data, the read pointer output from the read address generation circuit 2b8 is incremented. The pointer status circuit 2b11 outputs the status of the FIFO 2b by calculating the absolute value of the difference between the write pointer and the read pointer.

The pointer status signal of the FIFO 2b is generated by calculating the outputs of the pointer status circuits 2b5 and 2b11. For example, if the absolute value of the difference between the two FIFO pointers is both "0", FIFO2
b indicates that it is empty.
b: Empty "signal is output. If the absolute value of the difference between the two FIFO pointers is 80% or more of the capacity (128 words) of the FIFO 2b, it indicates that the valid data of the FIFO 2b is 20% or less of the capacity of the FIFO 2b. % "Signal. Similarly, when the valid data of at least one FIFO is between 20% and 40%, a “2b> 20%” signal is output by OR2b14, and at least one of the signals is 40%.
% To 60%, OR2b15 indicates "2b>
A signal of "2b>60%" is output by the OR2b16 when at least one of the signals is 60% or more.

FIG. 8 is a block diagram showing the structure of the FIFO 3b.

As shown in FIG. 8, the FIFO 3b is a synchronous dual-port SRAM 3b0, a write control circuit 3b.
1. Write address generation (pointer generation) circuit 3b
2, a read control circuit 3b3, a read address generation (pointer generation) circuit 3b4, and a pointer status generation circuit 3b5.

Here, 3b0 is, for example, 128 (words)
X8 (bit) dual port SRAM, and a write enable signal (wr) from the bus interface circuit 3a.
When iteen is input, WRITE DATA, which is bus transfer data, is written to the memory address generated by the write address generation (pointer generation) circuit 3b2 in synchronization with the bus clock (bus clk). After this data writing, the write pointer output from the write address generation circuit 3b2 is incremented. In addition, the read operation starts from the memory address indicated by the pointer generated by the read address generation (pointer generation) circuit 3b4 in synchronization with the display clock (disp clk) when the read valid signal (read en) from the interpolation circuit 3c is input. Read this because it outputs READ DATA. After the reading of the child data, the read pointer output from the read address generation circuit 3b4 is incremented. The pointer status circuit 3b5 outputs the status of the FIFO 3b by calculating the absolute value of the difference between the write pointer and the read pointer. For example, the absolute value of the difference is “128”
Indicates that the FIFO 3b is full.
b: full "signal, and if the absolute value of the difference is 20% or less of the capacity (128 words) of the FIFO 3b, the FIFO
Since the valid data of 3b is equal to or more than 80% of the FIFO capacity, the signal "3b>80%" is output. Similarly, when the valid data of the FIFO 3b is between 80% and 60%, a “3b <80%” signal is output, and the signal is output from 60% to 4%.
If it is between 0%, a "3b <60%" signal is output and 40%
%, The signal "3b <40%" is output.

The operation of the clock generator 21 will be described again with reference to FIG.

The pointer status signals input from each FIFO are AND 21f, OR 21g, 21h, 21
Input to i. Here, FIFOs 1b and 2b are FIFO
This indicates that the smaller the valid data in the data, the more the transfer capacity of the bus is.

On the other hand, since the FIFO 3b prefetches data as long as there is a free space, the closer the FIFO 3b is to FULL, the more the transfer capacity of the bus is. AND
21f has a "1b <20%" signal and a "2b <20%" signal.
The signal and the “3b> 80%” signal are input, and the state where all inputs are “1” indicates that all bus masters have sufficient bus transfer capability. Therefore, the frequency of the clock can be set to the lowest, so that AN
The output of D2f is set as SelA input so that a clock signal having a frequency of 10 MHz is selected.

The amount of data to be transferred next increases and the
If at least one of O1b and FIFO2b is greater than 20% or FIFO3b is less than 80%,
The output of the OR 21g becomes "1", and a clock signal having a frequency of 20 MHz is selected. When the amount of data to be transferred further increases and at least one of the FIFO1b and the FIFO2b exceeds 40% or the FIFO3b falls below 60%, the output of the OR 21b becomes "1" and a clock signal with a frequency of 40 MHz is selected. Is done. Further, the amount of data to be transferred increases and at least one of FIFO1b and FIFO2b exceeds 60%, or FIFO3b
Is less than 40%, the output of OR21i becomes "1", and a clock signal with a frequency of 80 MHz is selected.
That is, it is possible to dynamically detect that the data transfer capability of at least one bus master has become insufficient and automatically increase the frequency of the bus clock. In order to stop the bus clock of the clock generator 21, the CPU 5
To set the clock-on signal to "0". By doing so, the selector 21 is selected by the AND gate 21j.
The bus clock selected in e is gated, and the output of the clock signal is stopped.

On the other hand, the clock generator 22 receives the ON signal from the CPU 5 to generate
A 3.5 MHz clock signal is output.

Next, the clock gate circuits 23, 24, 2
The operation of No. 5 will be described with reference to a configuration diagram of an example of a clock gate circuit.

FIG. 9 is a circuit diagram illustrating the clock gate circuit 23.

As shown in FIG. 9, the clock gate circuit 2
3 gates the bus clock (bus clk) with an inverted signal of the "1b: Empty" signal (FIG. 6) which is an empty signal of the FIFO 1b. That is, the image capture controller 1
When there is no more captured data, the operation clock of the bus interface circuit 1a of the image capture controller 1 and the read clock of the FIFO 1b automatically stop.

FIG. 10 is a circuit diagram illustrating the clock gate circuit 24.

As shown in FIG. 10, the clock gate circuit 24 gates the bus clock (bus clk) with an inverted signal of the "2b: Empty" signal (FIG. 7) which is an empty signal of the FIFO 2b. That is, when the processing data of the signal processor 2 runs out, the operation clock of the bus interface circuit 2a of the signal processor 2 and the FI
The bus-side clock of FO2b stops.

FIG. 11 is a circuit diagram illustrating the clock gate circuit 25.

As shown in FIG. 11, the clock gate circuit 25 gates the bus clock (bus clk) with an inverted signal of the "3b: full" signal (FIG. 8) which is a full signal of the FIFO 3b. That is, when the display data of the display controller 3 cannot be read any more, the operation clock of the bus interface circuit 3a of the display controller 2 and the write clock of the FIFO 3b are automatically stopped.

The setting of the clock generators 19 to 22 and the clock gate circuits 23 to 26 corresponding to the frame rate is performed by controlling the clock generator and the clock gate circuit for each frame by the CPU 5. For example, if the frame rate is set to 10 frames / s in the EVF mode, the image capture controller 1 and the signal processor 2 need only perform one frame per three frames. The clock gate circuits 23 and 24 and the clock generator 20 stop the supply of the clock signal to the image capture controller 1 and the signal processor 2 during the middle two frames.

The thinning method as shown in this embodiment,
By setting the interpolation method and controlling the clock frequency, the resolution and frame rate desired by the user can be set flexibly in any operation mode, and the clock frequency for normal operation at the resolution and frame rate set by the user is automatically set. , The maximum power saving effect can be obtained in any operating condition.

Even if the present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), a device composed of one device (for example, a copying machine, a facsimile machine, etc.) ) May be applied.

Further, an object of the present invention is to supply a storage medium (or a recording medium) in which a program code of software for realizing the functions of the above-described embodiments is recorded to a system or an apparatus, and a computer of the system or the apparatus. (Or CP
U or MPU) reads out and executes the program code stored in the storage medium. in this case,
The program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. By executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an operating system (OS) running on the computer based on the instruction of the program code. This also includes a case where some or all of the actual processing is performed and the functions of the above-described embodiments are realized by the processing.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer, based on the instruction of the program code, This also includes the case where the CPU provided in the function expansion card or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

As described above, according to the portable videophone terminal of the present embodiment, it is possible to extremely easily realize flexible image quality control in accordance with the usage pattern of the user.
Further, there is an effect that the maximum power consumption can be reduced in any operation mode.

[0085]

As described above, according to the present invention, the frequency of the clock signal supplied to each of the plurality of processing means is switched in accordance with the operation state of the processing means, thereby reducing the power consumption of the entire apparatus. Can be suppressed.

According to the present invention, the frequency of the clock signal supplied to each of the plurality of processing means is reduced in accordance with the load state of the processing means, so that the power consumption of the entire apparatus can be reduced. effective.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a portable videophone terminal device according to an embodiment of the present invention.

FIGS. 2A and 2B are a timing chart showing an example of the operation of a thinning circuit of the present embodiment and a latch clock (Latch).
(B) of FIG.

FIG. 3 is a diagram illustrating correspondence between an operation mode, a thinning method, and an interpolation method.

FIG. 4 is a block diagram showing a configuration of a clock generator according to the present embodiment.

FIG. 5 is a diagram illustrating clock selection in the clock selector of FIG. 4;

FIG. 6 is a block diagram illustrating a configuration example of a FIFO 1b according to the present embodiment.

FIG. 7 is a block diagram illustrating a configuration example of a FIFO 2b according to the present embodiment.

FIG. 8 is a block diagram illustrating a configuration example of a FIFO 3b according to the present embodiment.

FIG. 9 is a diagram showing a configuration example of a clock gate circuit 23 according to the present embodiment.

FIG. 10 shows a clock gate circuit 24 according to the present embodiment.
FIG. 3 is a diagram showing an example of the configuration.

FIG. 11 shows a clock gate circuit 25 according to the present embodiment.
FIG. 3 is a diagram showing an example of the configuration.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) // H04N 7/14 H04B 7/26 X F term (Reference) 5C064 AA01 AB04 AC02 AC12 AD01 AD08 AD14 5C076 AA21 AA22 BA03 BA04 BA06 BB01 BB06 5K027 AA11 BB17 FF22 HH29 5K067 AA43 BB04 BB21 DD52 EE02 HH21 HH23 KK00 5K101 LL12 NN06 NN18 NN45

Claims (11)

[Claims] 1. A clock generation source that generates a plurality of clock signals having different frequencies, and a selection unit that selects one of a plurality of frequency clock signals output from the clock generation source. A plurality of processing units that are operated by a clock signal from a clock generation source selected by the selection unit; and a selection of a clock signal for the processing unit by the selection unit in accordance with an operation state of each of the plurality of processing units. An information processing apparatus, comprising: selection control means for controlling. 2. One of the plurality of processing means includes: an input means for inputting a captured image signal; a thinning means for thinning out the image signal input by the input means; and an image thinned by the thinning means. The information processing apparatus according to claim 1, further comprising a memory for storing a signal. 3. One of the plurality of processing units includes: a memory that stores the image signal thinned by the thinning unit; an interpolation unit that interpolates the image signal stored in the memory; 3. The information processing apparatus according to claim 2, further comprising: display means for displaying an image based on the interpolated image signal. 4. Each of the plurality of processing units has a storage unit for storing processed or processed data,
2. The information processing apparatus according to claim 1, wherein the selection control unit controls to select a clock signal for the processing unit according to a data amount stored in the storage unit. 5. The selection control unit performs control so as to select a clock signal for the processing unit according to an amount of image data stored in a memory of each of the plurality of processing units. The information processing device according to claim 3. 6. The selection control means, when each of the plurality of processing means does not require high-speed processing, controls to lower the frequency of a clock signal to the processing means. The information processing apparatus according to any one of claims 1 to 5, wherein 7. A selecting step of selecting one of a plurality of frequency clock signals output from a clock generation source for generating a plurality of frequency clock signals having different frequencies, each of which is selected in the selecting step. A selection control step of controlling selection of a clock signal for each of a plurality of processing means operating in response to a clock signal from a clock generation source. . 8. Each of the plurality of processing means has a memory for storing processed or processed data, and in the selection control step, the processing is performed in accordance with an amount of data stored in the memory. 8. The information processing method according to claim 7, wherein control is performed to select a clock signal for the means. 9. The selection control step is characterized in that control is performed such that a clock signal for the processing means is selected in accordance with an amount of image data stored in a memory of each of the plurality of processing means. The information processing method according to claim 7. 10. In the selection control step, when the operation state of each of the plurality of processing units does not require high-speed processing, control is performed such that the frequency of a clock signal for the processing units is reduced. Claim 7
10. The information processing method according to claim 1. 11. A computer-readable storage medium storing a program for executing the information processing method according to claim 7. Description: