JP2007293053A - Transfer circuit, image projecting device, and image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transfer circuit of an image projecting device capable of suppressing power consumption and cost. <P>SOLUTION: In order to carry out 1st bit plane transfer from a storage device to buffer memory 35 having a temporary storage area equivalent to m (2≤m<n) sheets in bit plane units while sequentially switching the inside of the above temporary storage area in bit plane units, between the 1st bit plane transfer having a projection display time by the micro mirror array 2 longer than a predetermined projection display time and a 2nd bit plane transfer different from the 1st bit plane transfer, 3rd bit plane transfer having a projection display time by a micro mirror array 2 shorter than the above predetermined projection display time is carried out, and also the 2nd transfer of the above bit plane is carried out from the above temporary storage area to the micro mirror array 2 in the sequence stored the above bit plane in the above temporary storage area. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a transfer circuit, an image projection apparatus using the transfer circuit, and an image display apparatus using the image projection apparatus.

  In recent years, mainly in the United States, there has been an increase in demand for image display devices using a liquid crystal and a semiconductor display device of a fixed pixel type such as a device having a minute mirror capable of controlling the reflection angle (hereinafter referred to as a micromirror device). is doing. In particular, a binary spatial light modulator using a micromirror device has attracted attention as a display device for realizing the above-mentioned image display device with a smaller size, lower cost, lower power consumption and higher contrast performance.

  FIG. 6 shows a system configuration diagram of an image display apparatus using a conventional micromirror device. This image display apparatus includes an image projection apparatus including a light source 1, a micromirror array 2, a controller 3, an image memory 4, and a projection lens 5, and a screen 6.

  Here, the micromirror array 2 is formed by arranging a plurality of micromirror devices corresponding to image information of one pixel in an array for the display area. The image memory 4 is a storage device that holds image data to be displayed. The controller 3 controls the amount of light reflected by each micromirror of the micromirror array 2 based on the image information in the image memory 4. The projection lens 5 is a condensing lens for collecting the reflected light from the micromirror array 2. The screen 6 is a screen for projecting an image.

  FIG. 7 is a diagram showing the mechanism of the image display device. In the figure, of the micromirror array 2, two micromirror devices 21A and 21B are shown as representatives.

  Each of the micromirror devices 21A and 21B has a mechanical mechanism in which the mirrors 211A and 211B are independently fixed to the lower support bases 212A and 212B by hinges or the like, and move at a predetermined swing angle around a fulcrum. Yes. For example, in the micromirror devices 21A and 21B, the mirrors 211A and 211B can be driven at an angle of ± θ. Corresponding to the image information of 1 pixel (R / G / B value or brightness component density), the amount of emitted light to be projected onto the screen 6 is predetermined for each mirror 211A, 211B at the predetermined deflection angle. It is determined by holding for the time. Thus, the reflected light with respect to the incident light irradiated on each of the mirrors 211A and 211B is uniquely determined by the predetermined touch angle and time, and a grayscale image or a color image corresponding to the amount of reflected light is formed at a desired location. It becomes possible to display. In the example of FIG. 7, the mirror 211A of the micromirror device 21A is tilted by + θ, and the reflected light is projected onto the screen 6 as luminance information corresponding to 1 pixel of image data (ON state). The mirror 211B of the micromirror device 21B is tilted by −θ, and the reflected light is not projected onto the screen 6 and becomes a black level (off state). Furthermore, a means for replacing the luminance (or color information) gradation of the display image with the mirror angle holding time (on / off period) is required. For example, the holding time is obtained by decomposing a digital value of a luminance signal of one pixel into MSB to LSB and setting a weighting value corresponding to each bit. The MSB has the longest retention period (+ θ retention in FIG. 7), and the LSB has the shortest retention period (−θ retention in FIG. 7).

  FIG. 8A shows an example of control of the micromirror array 2 and supplements FIGS. 6 and 7. In the example of FIG. 8A, an example in which one image is displayed will be described. It is assumed that the above image is a monochrome image having an 8-bit gradation of 1 pixel, and the angle of view is 4 rows (Row) × 4 columns (Column) = 16 pixels. Note that the image to be displayed is a monochrome shading chart shown in FIG.

  The example of FIG. 8A shows a micromirror array 2 in which 16 micromirror devices corresponding to an angle of view of 4 rows (Row) × 4 columns (Column) are arranged. Here, one square is one micromirror device and corresponds to an image of one pixel. The hatched micromirror device is in a state where it does not reflect light toward the projection lens 5 (off state). The micromirror device that is not hatched is in a state of reflecting light (on state) toward the projection lens 5.

  In FIG. 8A, the on / off state of the micromirror array 2 with respect to a predetermined time is shown in time series in order from the top. FIG. 8C shows an example (timing chart) of the control of the micromirror array 2 in the time axis direction.

  That is, in this example, the predetermined time is T0, T0 / 2, T0 / 4, T0 / 8 (period: T0> T0 / 2> T0 / 4> T0 / 8), and a display period of one cycle at 2T0 And Now, since the first column (1 Column) micromirror device groups are all on, T0, T0 / 2, T0 / 4, and T0 / 8 are projected on the screen 6 in FIG. 8B corresponding to this position. The portion CL1 in the image is the brightest. Since the second column (2 Column) micromirror device group is ON at T0 / 2, T0 / 4, and T0 / 8, the CL2 portion of the screen 6 in FIG. Second brightest. Since the third column (3 Column) micromirror device group is ON at T0 / 4 and T0 / 8, the CL3 portion of the screen 6 in FIG. 8B corresponding to this position is the third brightest. . Since the fourth column (4 Column) micromirror device group is ON only for T0 / 8, the CL4 portion of the screen 6 in FIG. 8B corresponding to this position is the darkest. Thus, a desired monochrome shade chart is projected on the screen 6.

  In recent years, in such an image display device, higher resolution and higher image quality are desired as a still image / moving image playback function. For example, display specifications of a high-definition (1,920 × 1,080 pixels / 30 fps) class are required. ing.

For example, Patent Document 1 discloses a display system that realizes high image quality performance at a frame rate compliant with a standard television system. In such a system, a plurality of frames of image data are converted into the aforementioned weighted data group for each bit. The data is held in a storage device (memory circuit such as RAM), and the micromirror device array is driven based on this data. The weighted data group for each bit will be described in more detail. For example, if one pixel image is 8-bit monochrome data and one image is VGA size (640 × 480 pixels), one image data of 8 bits × 640 × 480 is converted to 640 × MSB bit plane. 480, 6-bit plane 640 × 480,..., LSB bit-plane 640 × 480 8 binary data are expanded into bit planes. In other words, there is no difference in the data capacity between the original image and the bit plane as the image information, and the format is converted for the micromirror device array. In such a system, in order to provide a more comfortable device such as a high image quality and a high frame rate, the configuration of the electrical system must inevitably become complicated and large-scale.
JP-A-5-224644

  An image display device such as the display system disclosed in Patent Document 1 is desired to have a higher frame rate and higher image quality by a multi-pixel. In order to realize such an apparatus, it is indispensable to support a digital processing unit such as high-speed image data transfer to a semiconductor display device such as a micromirror array or an increase in image memory.

  However, there is a concern about the increase in the power consumption of the processing apparatus due to the high-speed data transfer as described above and the increase in the cost of the apparatus due to the addition of the image memory.

  The present invention has been made in view of the above points, and provides a transfer circuit, an image projection device, and an image display device that reduce power consumption and cost in response to high-speed image data transfer accompanying high image quality. The purpose is to do.

  According to one aspect of the transfer circuit of the present invention, digital image data in which the density or color information of each pixel is expressed by n bits is stored so as to be readable in bit plane units composed of bit data of the same bit order of each pixel. A transfer circuit that transfers the bit plane in units of the bit plane from a device to a projection display device that projects and displays a pixel specified by the bit data for a time according to the bit order of the bit plane; A bit plane storage buffer having temporary storage areas corresponding to m (2 ≦ m <n) sheets in units of planes, and the bit planes from the storage device while sequentially switching the temporary storage areas in units of the bit planes. In performing the first transfer of the bitplane to the storage buffer, Between the transfer of a first bit plane having a projection display time by the projection display device that is longer than a fixed projection display time and a transfer of a second bit plane different from the first bit plane. Performing a transfer of a third bit plane having a projection display time by the projection display device that is shorter than the projection display time, and from the temporary storage area in the order in which the bit planes are stored in the temporary storage area Control means for performing a second transfer of the bit plane to the projection display device.

  In addition, according to an aspect of the image projection apparatus of the present invention, digital image data in which the density or color information of each pixel is expressed by n bits can be read in units of bit planes including bit data of the same bit order of each pixel. According to the stored storage device, the transfer circuit of the above aspect, the light source, and the bit plane data transferred from the storage device by the transfer circuit, there is a minute mirror that reflects light from the light source in a predetermined direction. A projection display device arranged in an array; and a lens for condensing and projecting the reflected light from the projection display device.

  According to another aspect of the image display device of the present invention, the image projection device according to the one aspect described above and a screen that displays an image projected from the lens are provided.

  According to the present invention, it is possible to provide a transfer circuit, an image projection device, and an image display device capable of suppressing both power consumption and cost.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a diagram showing a configuration of a transfer circuit according to the first embodiment of the present invention. With regard to the “predetermined projection display time” according to claim 1, in the present embodiment, on the premise that an image of 60 frames / second is displayed with an 8-bit gradation, 1 / 60th of 1/4. / 240 seconds. This transfer circuit functions as the controller 3 constituting the image projection apparatus of the above-described image display apparatus, and includes an interface (I / F) circuit 31, a memory controller 32, a CPU 33, a serial-parallel converter 34, a buffer memory 35, and a sequencer. 36, and selectors 37 and 38.

  Here, the I / F circuit 31 has a function of converting image data quantized to n bits per pixel (arbitrary value of n> 1) into N weighted data for each bit. Have For example, if an image of one pixel is monochrome data of 8 bits (n = 8) and one image is VGA size (640 × 480), one image data of 8 bits × 640 × 480 is converted into MSB bits. Bit plane development is performed on 8 (N = 8) binary data of 640 × 480 plane, 640 × 480 6 bit plane,... 640 × 480 LSB bit plane.

  This will be described with reference to FIGS. 2A to 2C. FIG. 2A shows one piece of input image data. The column direction is 640 pixels, and the row direction is 480 pixels. One square in the figure corresponds to one pixel and one micromirror device. The numbers in the squares in the figure indicate examples of luminance data. The data of FIG. 2A input to the I / F circuit 31 is broken down into eight bit planes shown in FIG. For example, the bit plane of the MSB bit is 1 only for a pixel having a numerical value of 128 in the data of FIG.

  The bit plane data decomposed by the I / F circuit 31 as shown in FIG. 2B is written to the frame memory 41 constituting the image memory 4 by the memory controller 32 with a predetermined bit width w. It is. That is, the bit plane data is stored in the frame memory 41 for each bit plane with the number of words matching the bus width of the memory and digital processing device. FIG. 2C shows an example of data arrangement in the frame memory 41. In the example of FIG. 2C, a frame memory having a word width of w = 32 bits and an address of depth of 76,800 or more is prepared.

  The memory controller 32 is controlled by a CPU 33 that controls the entire image projection apparatus including the transfer circuit.

  Recent image display devices including this embodiment are required to have a moving image performance of, for example, VGA / 30 fps or higher. In order to secure such a display band, the frame memory 41 can store a plurality of pieces of image data. In general, the functions corresponding to the I / F circuit 31, the memory controller 32, and the CPU 33 are integrated into one chip as a controller chip together with various functional blocks not shown in FIG. In such a case, the bus width w cannot secure a width corresponding to one row (640 bits) or one column (480 bits) of the VGA size in order to suppress an increase in chip cost due to the number of terminals. Therefore, a desired bandwidth cannot be secured unless a large amount of moving image data is transferred to the micromirror array 2 at a higher speed.

  The serial-parallel converter 34 performs serial / parallel conversion for converting bit plane data sent with w = 32 bit width into a p-bit width corresponding to one row (640 bits) or one column (480 bits) of VGA size. In the present embodiment, p = 640 bits corresponding to the column direction of the micromirror array 2.

  The buffer memory 35 is a memory that holds m arbitrary bit planes, two in this embodiment. That is, the buffer memory 35 includes bit plane data storage buffers DRAM_A and DRAM_B for each bit plane. Each of these bit plane data storage buffers DRAM_A and DRAM_B is composed of a dual port DRAM of 1 port each of read / write of 640 words × 480 bits.

  Each of the selectors 37 and 38 selectively connects one common terminal D to one of the two switching terminals A and B in accordance with the switching signal S supplied from the sequencer 36. Here, the common terminal D of the selector 37 is connected to the serial-parallel converter 34, one switching terminal A is the bit plane data storage buffer DRAM_A of the buffer memory 35, and the other switching terminal B is the bit plane data storage buffer of the buffer memory 35. Each is connected to DRAM_B. The common terminal D of the selector 38 is connected to the micromirror array 2, one switching terminal A is the bit plane data storage buffer DRAM_A of the buffer memory 35, and the other switching terminal B is the bit plane data storage buffer DRAM_B of the buffer memory 35. Are connected to each other.

  Thus, when bit plane data is transferred to the bit plane data storage buffer DRAM_A of the buffer memory 35 with the p-bit width from the serial-parallel converter 34, the common terminal D of the selector 37 is connected to the switching terminal A side. Is done. During this period, the common terminal D of the selector 38 is connected to the switching terminal B side in order to transfer the contents of the bit plane data storage buffer DRAM_B of the buffer memory 35 to the micromirror array 2. Conversely, when bit plane data is transferred to the bit plane data storage buffer DRAM_B of the buffer memory 35 with the p-bit width from the serial-parallel converter 34, the common terminal D of the selector 37 is connected to the switching terminal B side. The During this period, the common terminal D of the selector 38 is connected to the switching terminal A side in order to transfer the contents of the bit plane data storage buffer DRAM_A of the buffer memory 35 to the micromirror array 2. Image data is sent to the micromirror array 2 by such a butterfly operation.

  For such a butterfly operation, the sequencer 36 sends the switching signal S from the switching signal output terminals SEL_X and SEL_Y to the selectors 37 and 38 and selects the bit plane data stored in the buffer memory 35. Then, a signal q for designating the bit plane head address is sent from the MEM_SEL terminal to the memory controller 32. In the present embodiment, since the image gradation is 8 bits, there are 8 bit planes, so q = 3 bits. The memory controller 32 reads the data in the frame memory 41 indicated by the memory address r = 9-bit address with the 3 bits from the sequencer 36 as the upper 3 bits of the address, and supplies the data to the serial-parallel converter 34. To do.

  The memory controller 32, CPU 33, serial-parallel converter 34, sequencer 36, and selectors 37, 38 load the bit plane data from the frame memory 41 to the buffer memory 35, and transfer the buffer memory 35 to the micromirror array 2. Functions as control means for controlling the transfer of the bit plane data.

  Next, the transfer operation of the image data to the micromirror array 2 in the transfer circuit according to the present embodiment will be described with reference to the timing chart of FIG.

  In one frame period 2T0, shades are expressed by time division with 8-bit gradation. The relationship between the bit plane and the display period is as follows: MSB bit = T0, 6 bit = T0 / 2, 5 bit = T0 / 4, 4 bit = T0 / 8, 3 bit = T0 / 16, 2 bit = T0 / 32, 1 Bit = T0 / 64 and LSB bit = T0 / 128. Further, the period during which the bit plane data is transferred from the frame memory 41 to the DRAM of the buffer memory 35 (DRAM transfer) is equivalent to T0 / 16, and the bit plane data in the DRAM of the buffer memory 35 is transferred to the micromirror array 2. The transfer (device transfer) period is T0 / 320. In general, the period of DRAM transfer is much longer than the period of device transfer due to the aforementioned data transfer width (w bits << p bits). For example, when bit plane data is sequentially transferred from the MSB to the LSB, after the bit plane of bit 3 (= T0 / 16), the DRAM transfer period exceeds the display period, and a correct video cannot be displayed. The same applies when bit plane data is sequentially transferred from the LSB to the MSB. That is, as in the configuration shown in FIG. 1, in a system in which DRAM is not mounted for all bit planes in consideration of the reduction in circuit scale, there is a possibility that DRAM transfer is not completed by the display start timing.

  Therefore, in this embodiment, the bit planes can be transferred to the DRAM in a predetermined order to eliminate such a concern. That is, as shown in FIG. 3, the bit plane data of the long display period is displayed from the frame memory 41 to the buffer memory 35 so that the bit plane data of the LSB bit plane is displayed next to the bit brain data of the MSB bit plane. Bit plane data is transferred alternately.

  That is, first, the bit plane data of the MSB bit plane is transferred from the frame memory 41 to the bit plane data storage buffer DRAM_A of the buffer memory 35, and then transferred from the bit plane data storage buffer DRAM_A to the micromirror array 2. During this period, the bit plane data of the MSB bit plane is displayed. During this period T0, the bit plane data of the LSB bit plane is transferred from the frame memory 41 to the bit plane data storage buffer DRAM_B of the buffer memory 35. After the transfer is completed, the bit plane data of the MSB bit plane is transferred. Is transferred to the bit plane data storage buffer DRAM_A of the buffer memory 35 that has been transferred to the micromirror array 2.

  Next, the bit plane data of the LSB bit plane is transferred from the bit plane data storage buffer DRAM_B of the buffer memory 35 to the micromirror array 2, and the bit plane data of the LSB bit plane is displayed for the period of T0 / 128. To do. Here, with respect to the bit plane data storage buffer DRAM_B, already stored data is transferred, so that the bit plane data of 1 bit plane can be transferred from the frame memory 41. This transfer takes longer than the period of T0 / 128. After the bit plane data of the LSB bit plane is displayed, the bit plane data of the 6 bit plane is stored in the bit plane data storage buffer of the buffer memory 35. The data is transferred from the DRAM_A to the micromirror array 2 and the bit plane data of the 6-bit plane is displayed for the period of T0 / 2. Therefore, the transfer of the bit plane data of the 1-bit plane from the frame memory 41 is displayed. There is no effect.

  Hereinafter, in the same manner, the data with long display period / short data so as to display the bit plane data of 5 bit plane, the bit plane data of 2 bit plane, the bit plane data of 4 bit plane, and the bit plane data of 3 bit plane. Data is transferred alternately.

  Even if such alternate data transfer is performed, the on / off time of each micromirror device is the same as when bit plane data is sequentially transferred from the MSB to the LSB when viewed as a total of one frame period. Therefore, an image without any sense of incongruity is observed for the observer of the image projected on the screen 6.

  According to the transfer circuit according to the present embodiment as described above, data can be transferred to the micromirror array 2 with a small amount of memory, so that a transfer circuit with low power consumption and low cost can be obtained.

  Therefore, an image projection apparatus using such a transfer circuit, and even an image display apparatus using the same can be an inexpensive apparatus with low power consumption.

  In addition, the outputs of the bit plane data storage buffers DRAM_A and DRAM_B of the buffer memory 35 are not sent to the micromirror array 2, but are selectively transferred by the selector 38 so that only one transfer path is prepared. . In general, in an image projection apparatus, the arrangement position of the micromirror array 2 is limited so as to satisfy optical requirements, and is often arranged at a position away from a circuit board on which an electric circuit is configured. As in this embodiment, if there is one transfer path, wiring within the image projection apparatus is facilitated.

[Second Embodiment]
Next, a second embodiment of the present invention will be described.

  In the first embodiment, the mirror itself is held at a desired angle by the on (+ θ) / off (−θ) drive of each micromirror device in accordance with the shade or color image information of the corresponding pixel, and necessary reflection. I get the light.

  The present embodiment further provides a higher-quality image that enables fine adjustment of the amount of reflected light by realizing a mirror-free state other than on / off with a simpler structure for the micromirror device. A projection device and an image display device are provided.

  FIG. 4 shows that the micromirror device 21 is in a first state / second state / third state multi-value state, for example, on / off / free ternary state, thereby finely adjusting the amount of light. It is a figure which shows the structure of the transfer circuit based on this embodiment which enables. Note that the I / F circuit 31, the memory controller 32, the frame memory 41, the CPU 33, the serial-parallel conversion unit 34, and the selector 37 are not shown, but the portions have the same configuration as in the first embodiment. It has become. The buffer memory 35 and the selector 38 are the same as those in the first embodiment.

  The sequencer 36 is the same as that of the first embodiment except that a MODE signal terminal for outputting a 1-bit MODE signal is added.

  In the present embodiment, a row register (Row Resistor) 71 and combinational circuits 72 and 73 are further provided. The row register 71 is a 640-bit flip-flop that holds binary data (mirror on / off) in the column direction (640 columns). In FIG. 4, the configuration of the micromirror device 21 corresponding to the hatched portion of the row register 71 is schematically shown.

  The combinational circuits 72 and 73 mask the value of the row register 71 with the value of the mode signal (MODE) from the sequencer 36. When the mode signal = L, the normal mode is set, and when the mode signal = H, the adjustment mode is set. FIG. 5 shows combinations of mirror operations.

  Here, the FETs 213 and 214 of the micromirror device 21 have their respective gates when the row in which the micromirror device 21 is arranged is selected by a row selection signal (output from the ROW SEL terminal) from the sequencer 36. Becomes H level and becomes conductive.

  Therefore, in the normal mode with the mode signal = L, if the output of the row register 71 is L, the output of the combinational circuit 72 is H, and charges are accumulated in the electrode 216 through the FET 214. On the other hand, since the output of the combinational circuit 73 is L, no charge is accumulated in the electrode 215. Therefore, the mirror 211 is attracted to the electrode 216 by the electrostatic force due to the electric charge accumulated in the electrode 216, and rotates -θ (mirror off).

  In the normal mode, when the output of the row register 71 is H, the output of the combinational circuit 73 is H, and charges are accumulated in the electrode 215 through the FET 213. On the other hand, since the output of the combinational circuit 72 is L, no charge is accumulated in the electrode 216. Therefore, the mirror 211 is attracted to the electrode 215 by the electrostatic force due to the electric charge accumulated in the electrode 215, and rotates + θ (mirror on).

  On the other hand, in the adjustment mode with the mode signal = H, if the output of the row register 71 is L, the output of the combinational circuit 72 is H, and charges are accumulated in the electrode 216 through the FET 214. On the other hand, since the output of the combinational circuit 73 is L, no charge is accumulated in the electrode 215. Therefore, the mirror 211 is attracted to the electrode 216 by the electrostatic force due to the electric charge accumulated in the electrode 216, and rotates -θ (mirror off).

  In the adjustment mode, when the output of the row register 71 is H, both outputs of the combinational circuits 72 and 73 are L, and no charge is accumulated in any of the electrodes 215 and 216. That is, in the adjustment mode, the state of output = H of the row register 71 is masked to 0 by the logic of the combinational circuits 72 and 73 to create an equilibrium state (mirror free) of θ = 0 °. As a result, the display of the image during this period is close to the black level and can be adjusted to a state where the amount of light is reduced. Note that the logic of the combinational circuits 72 and 73 is changed so that the output of the combinational circuits 72 and 73 when the adjustment mode = H and the output of the row register 71 = H are L and H, respectively, and the mirror 211 is forcibly turned off ( (Black level).

  The sequencer 36 controls the timing for setting the mode signal = H. The mode signal may be output at an arbitrary timing in the display period (2T0) shown in FIG.

  The amount of reflected light can be finely adjusted according to the timing at which this mode signal is set to the H state.

  The present invention has been described above based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications and applications are possible within the scope of the gist of the present invention. .

  For example, in the above-described embodiment, an example in which the memory (bit plane data storage buffer) that holds the bit plane is configured by two sheets, but other numbers may be used.

  In addition, the bit plane data storage buffer for holding the bit plane is configured by a dual port DRAM having 1 port for each read / write. For example, the same effect can be obtained if the bit plane data storage buffer is configured by one 2 port memory for each read / write. I can expect. Further, the memory is not limited to DRAM.

  Further, although it has been described that an image of one pixel is 8 bits (n = 8) and decomposed into 8 (N = 8) bit plane data, the present invention is not limited to n = N.

  Furthermore, the micromirror is not limited to the micromirror device of the present embodiment.

FIG. 1 is a diagram showing a configuration of a transfer circuit according to the first embodiment of the present invention. 2A shows an example of luminance data of each pixel in one piece of input image data, and FIG. 2B shows bit plane data obtained by disassembling the image data in FIG. FIG. 2C is a diagram illustrating an example of arrangement of bit plane data in the frame memory. FIG. 3 is a timing chart for explaining the transfer operation of the image data to the micromirror array in the transfer circuit according to the first embodiment. FIG. 4 is a diagram showing a configuration of a transfer circuit according to the second embodiment of the present invention. FIG. 5 is a diagram for explaining a combination of mirror operations. FIG. 6 is a system configuration diagram of an image display apparatus using a conventional micromirror device. FIG. 7 is a diagram showing a mechanism of an image display apparatus using a conventional micromirror device. FIG. 8A is a diagram showing an example of control of a micromirror array in an image display device using a conventional micromirror device, and FIG. 8B is a screen by control of the micromirror array of FIG. FIG. 8C is a diagram showing a timing chart of control of the micromirror array of FIG. 8A.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 1 ... Light source, 2 ... Micro mirror array, 21, 21A, 21B ... Micro mirror device, 211, 211A, 211B ... Mirror, 212A, 212B ... Lower support base, 213, 214 ... FET, 215, 216 ... Electrode, 3 ... Controller, 31 ... Interface (I / F) circuit, 32 ... Memory controller, 33 ... CPU, 34 ... Serial-parallel converter, 35 ... Buffer memory, 36 ... Sequencer, 37, 38 ... Selector, 4 ... Image memory, 41 ... Frame Memory 5 ... Projection lens 6 ... Screen 71 71 Row register 72, 73 Combination circuit DRAM_A, DRAM_B Bit plane data storage buffer

Claims (8)

The digital image data in which the density or color information of each pixel is expressed by n bits is stored in a readable manner in bit plane units composed of bit data of the same bit order of each pixel. A transfer circuit for transferring the bit plane in units of the bit plane to a projection display device for projecting and displaying the pixel specified by the bit data for a corresponding time,
A bit plane storage buffer having temporary storage areas corresponding to m (2 ≦ m <n) number of sheets in the bit plane unit;
The projection display that is longer than a predetermined projection display time in executing the first transfer of the bit plane from the storage device to the bit plane storage buffer while sequentially switching the temporary storage area in units of the bit plane. The projection display device shorter than the predetermined projection display time between the transfer of a first bit plane having a projection display time by the device and the transfer of a second bit plane different from the first bit plane. Transfer of the third bit plane having the projection display time according to the first and second bit planes from the temporary storage area to the projection display device in the order in which the bit planes are stored in the temporary storage area. A control means for performing the transfer of 2;
A transfer circuit comprising:   The control means is configured to project the bit plane being projected and displayed by the projection display device to the temporary storage area corresponding to the bit plane for which the second transfer has been completed during a projection display period by the projection display device. The transfer circuit according to claim 1, wherein the first transfer relating to the bit plane different from the first is executed.   2. The transfer circuit according to claim 1, wherein the control unit executes the second transfer for each bit plane with respect to the bit plane stored in the temporary storage area. 3.   The transfer circuit according to claim 2, wherein the control circuit is set to double the transfer period related to the first transfer as the predetermined projection display time.   4. The transfer circuit according to claim 3, wherein the bit plane storage buffer is a two-port memory.   2. The transfer circuit according to claim 1, wherein the projection display device is a micromirror device in which minute mirrors whose reflection angles can be controlled according to the data of the bit plane are arranged in an array. . A storage device that stores digital image data in which shading or color information of each pixel is expressed by n bits so as to be readable in bit plane units composed of bit data of the same bit order of each pixel;
A transfer circuit according to any one of claims 1 to 5;
A light source;
A projection display device in which minute mirrors that reflect light from the light source in a predetermined direction are arranged in an array according to the data of the bit plane transferred from the storage device by the transfer circuit;
A lens that collects and projects the reflected light from the projection display device;
An image projection apparatus comprising: An image projection device according to claim 7,
A screen for displaying an image projected from the lens;
An image display device comprising:

Images