JP2007288356A - Power supply control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply control device which is capable of suppressing the variance of abnormal current judgement due to the variance among semiconductor switch elements while reducing the number of components, when connecting a plurality of semiconductor switch elements in parallel to control the power supply to a load. <P>SOLUTION: Two semiconductor switch devices 11a and 11b connected in parallel to a power line 63 between a power source 61 (a power source for a vehicle) and a load 50 cause a resultant sense current Is of sense currents Is1 and Is2 output from respective semiconductor switch devices to flow to a common RC parallel circuit 12 and compare a terminal voltage Vo of the RC parallel circuit 12 with a divided voltage Vr as a threshold voltage to detect current abnormality. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power supply control device.

  Conventionally, a power switch connecting a power source and a load is provided with a high-power semiconductor switch element such as a power MOSFET, and the power supply to the load is controlled by turning on and off the semiconductor switch element. A supply control circuit is provided. In such a power supply control circuit, when an overcurrent flows through the energization path, the semiconductor switch element is turned off by controlling the potential of the control terminal of the semiconductor switch element to turn off the semiconductor switch element. A device having a self-protecting function for protecting the device is known.

In the following Patent Document 1, a sense FET that flows a sense current corresponding to the amount of current of a power MOSFET is provided, and the sense current flowing through the sense FET is passed through a current detection resistor via a potential control circuit. A voltage drop is detected, and when this voltage drop exceeds a predetermined threshold value, an overcurrent (current abnormality) is determined. Specifically, the drains of the power MOSFET and the sense FET are commonly connected to the power supply side, while the source potential of both is held at the same potential by, for example, a potential control circuit having an operational amplifier having a voltage follower connection. Yes. As a result, a sense current having a stable constant ratio (the sense ratio between the power MOSFET and the sense FET) can flow to the sense FET with respect to the load current flowing through the power MOSFET.
JP 2004-236405 A

By the way, when performing power supply control to a load through which a very large load current flows in the energization path, a plurality of semiconductor switch elements are connected in parallel to the energization path, and power supply control is performed by the plurality of semiconductor switch elements. It may be. However, in the conventional device, overcurrent determination of the same current path is performed, but overcurrent determination is performed based on each voltage drop of a plurality of current detection resistors provided corresponding to each of the plurality of semiconductor switch elements. It was supposed to be configured to do.
Specifically, when it is desired to detect a current abnormality in the current path to the load with the same on-resistance (for example, 10 [mΩ]) and the same threshold value (for example, 100 [A]) in the two semiconductor switch elements, it is equally as designed. If the current can be shunted, a current of up to 200 [A] should be able to flow through the current path. However, since there is actually a variation in on-resistance between the semiconductor switch elements, before the current flowing through the energization path reaches 200 [A], the current flowing through one semiconductor switch element is equal to the threshold value (100 [A]). There was a problem that the current of 200 [A] could not flow through the load.

  The present invention has been completed based on the above circumstances, and its purpose is to reduce the number of parts when controlling power supply to a load by connecting a plurality of semiconductor switch elements in parallel. An object of the present invention is to provide a power supply control device capable of suppressing variations in abnormal current determination due to variations between semiconductor switch elements.

  As means for achieving the above object, a power supply control device according to the invention of claim 1 is provided between a power supply and a load, and controls the power supply from the power supply to the load. A plurality of semiconductor switch elements connected in parallel to each other from the power source to the load, and corresponding to each of the plurality of semiconductor switch elements, and a current flowing through the corresponding semiconductor switch element A plurality of current detection elements that respectively output corresponding detection currents, and are commonly connected to the output side of the plurality of current detection elements, and convert the combined detection current from the plurality of current detection elements into a voltage. A circuit, and an abnormality detection circuit that outputs an abnormality signal when the output voltage of the common conversion circuit exceeds a threshold voltage.

  According to a second aspect of the present invention, in the power supply control device according to the first aspect, each of the semiconductor switch elements is a power FET, and each of the current detection elements has a predetermined relationship with respect to a current flowing through the corresponding power FET. The sense current flows and the sense current is output as the detection current.

  According to a third aspect of the present invention, in the power supply control device according to the first or second aspect, the common conversion circuit is connected in series to a merging path of detected currents from the plurality of semiconductor switch elements. The first resistance element and the capacitor, and the second resistance element connected in parallel to the first resistance element and the capacitor are configured.

  According to a fourth aspect of the present invention, in the power supply control device according to the third aspect, the second resistance element has a resistance value larger than that of the first resistance element.

  According to a fifth aspect of the present invention, in the power supply control device according to the first or second aspect, the common conversion circuit is a resistance element.

A sixth aspect of the present invention is the power supply control device according to any one of the first to fifth aspects, wherein a plurality of the abnormality detection circuits are provided corresponding to the plurality of semiconductor switch elements, respectively, Based on each abnormal signal output from the detection circuit, a protection circuit is provided that causes each of the semiconductor switch elements corresponding thereto to perform a blocking operation.
The “protection circuit” of the present invention includes, for example, a reset circuit for canceling the cutoff state of the semiconductor switch element based on an external signal and returning the semiconductor switch element to the energized state, and causes the semiconductor switch element to perform a cutoff operation. After that, a configuration in which the shut-off state is maintained until it is released by the reset circuit, or a configuration in which the semiconductor switch element is forcibly returned to the energized state after a certain time after the shut-off operation is performed may be employed.

  According to a seventh aspect of the present invention, in the power supply control device according to any one of the first to fifth aspects, the abnormality detection circuit is a common abnormality detection circuit for the plurality of semiconductor switch elements. And a protection circuit that collectively shuts off the plurality of semiconductor switch elements based on the abnormality signal output from the common abnormality detection circuit.

<Invention of Claim 1>
According to this configuration, a plurality of semiconductor switch elements are connected in parallel to control power supply to the load, and a detection current corresponding to the amount of current of each semiconductor switch element is merged to flow to the common conversion circuit. An abnormal signal is output when the terminal voltage of the conversion circuit exceeds the threshold voltage. Therefore, unlike the conventional configuration in which individual current detection resistors are provided for a plurality of semiconductor switch elements to perform abnormality determination, it is possible to control variation in abnormal current determination due to variation between semiconductor switch elements, and The number of parts can be reduced.

<Invention of Claim 2>
This configuration employs a so-called sensing method in which a detection current is output using a sense FET in which a sense current having a predetermined relationship with respect to a current flowing in the power FET is used. Even in this configuration, of course, the effect of the present invention is achieved. Obtainable.

<Invention of Claims 3 and 4>
According to this configuration, the common conversion circuit exhibits a characteristic of increasing the conversion rate from the combined detection current to the voltage as the combined detection current (sense current) is energized. In other words, for example, there is a short circuit abnormality in an external circuit (such as a load or wiring member of a control target device) or an overcurrent abnormality in which a current larger than the rated current of the load flows through the semiconductor switch element (power FET) even if the short circuit is not short When this occurs, the output voltage rises due to an increase in the conversion rate in the common conversion circuit as the energization time elapses, and an abnormal signal is output when the threshold voltage is exceeded. And the energization time of the abnormal current from the occurrence of the current abnormality to the output of the abnormal signal is shorter as the abnormal current level is larger and longer as it is smaller.
In short, the power supply control device immediately outputs an abnormal signal when a high level abnormal current flows in an external circuit (for example, a wiring member (wire)) connected to the semiconductor switch element, and a relatively low level abnormal current. Operates to output an abnormal signal after a certain energization time has passed. As a result, it is possible to suppress a large current from flowing through the external circuit to cause burning.
In this configuration, the common conversion circuit includes a first resistance element and a capacitor that are connected in series to the detection current merging path, and a second resistance element that is connected in parallel to the first resistance element and the capacitor. Having a resistance value larger than that of the resistance element). In such a configuration, by changing the circuit constants of the common conversion circuit (resistance value of each resistance element, capacitance of the capacitor), the relationship between the combined detection current and the energization time until the output voltage exceeds the threshold voltage The curve can be adjusted appropriately. Further, since the maximum amount of the combined detection current flowing in the common conversion circuit is finite, the maximum amount of current is adjusted by adjusting the resistance value of at least one of the first resistance element and the second resistance element. It can be set to a value corresponding to the maximum allowable current value of the switch element. Further, by adjusting the resistance value of the second resistance element, the convergence value of the combined detection current when the overcurrent state continues for a long time can be adjusted. Further, by adjusting the values of the first and second resistance elements and the capacitor, it is possible to adjust the degree of convergence over time of the combined detection current-energization time relationship curve.

<Invention of Claim 5>
According to this configuration, it is possible to detect a current abnormality in each semiconductor switch element based on the magnitude relationship between the terminal voltage of the resistance element as the common conversion circuit and the threshold voltage.

<Invention of Claim 6>
According to this configuration, fluctuation of abnormal current determination may occur for each abnormality detection circuit, but the influence due to variation (variation of on-resistance) for each semiconductor switch element can be suppressed.

<Invention of Claim 7>
According to this configuration, a plurality of semiconductor switches can be collectively cut off with respect to the occurrence of current abnormality.

<Embodiment 1>
Embodiment 1 of the present invention will be described with reference to FIGS.
[Entire configuration of power supply control device]
FIG. 1 is a block diagram illustrating an overall configuration of a power supply control device 10 according to the present embodiment. The power supply control device 10 includes a plurality (two in this embodiment) of semiconductor switch devices (semiconductor devices) 11. Each semiconductor switch device 11 includes a power MOSFET 15 (corresponding to “semiconductor switch element, power FET” of the present invention) connected in parallel to a current path 63 between a power source 61 (vehicle power source) and a load 50. The power supply from the power supply 61 to the load 50 is controlled by turning on and off these two power MOSFETs 15. The power supply control device 10 is mounted on a vehicle (not shown) and is used as a load 50 to control driving of, for example, a vehicle lamp, a cooling fan motor, a defogger heater, and the like. In the following description, “load” is a control target device of the power supply control device 10 and does not include the electric wire (wiring member) 51 connected between the power supply control device 10 and the control target device. The “external circuit” will be described as meaning including the load 50 and the electric wire 51. In the following description, reference is made to 11 when two semiconductor switch devices are not distinguished from each other, and reference numerals 11a and 11b are assigned to distinguish between the two semiconductor switch devices.

  Each semiconductor switch device 11 is provided with an input terminal P1, a power supply (Vcc) terminal P2, an output terminal P3, an external connection terminal P4, and a diagnosis output terminal P5, as shown in FIG. In the two semiconductor switch devices 11, both input terminals P1 are commonly connected to the operation switch 52, both power supply terminals P2 are commonly connected to the power supply 61, the output terminal P3 is commonly connected to the load 50, and the external connection terminal P4 is described later. The RC parallel circuit 12 is connected in common.

  The load current Ip from the power supply 61 is shunted to the shunt currents Ip1 and Ip2 at the common connection point of both power supply terminals P2, the shunt current Ip1 flows to the power MOSFET 15 of the semiconductor switch device 11a, and the shunt current Ip2 of the semiconductor switch device 11b. It flows to the power MOSFET 15. Each semiconductor switch device 11 includes a sense MOSFET 16 (corresponding to “current detection element, sense FET” of the present invention) and a control circuit 14. Each control circuit 14 is commonly connected to the operation switch 52 via the input terminal P1. The input terminal P1 is pulled up to the power supply voltage Vcc side when the operation switch 52 is turned off. When the operation switch 52 is turned on, a low-level control signal S1 (load drive command signal) is supplied to the control circuit. 14, the control circuit 14 operates, and a constant voltage signal or a PWM (Pulse Width Modulation) signal is applied to the control input terminal (gate terminal G) of the power MOSFET 15 to perform an energization operation.

  As will be described later, each sense MOSFET 16 receives sense currents Is1 and Is2 (corresponding to the “detection current” of the present invention) corresponding to the current amounts of the shunt currents Ip1 and Ip2 of each power MOSFET 15, and these sense currents Is1, Is2 merges through each control circuit 14 and each external connection terminal P4, and this combined sense current Is (= Is1 + Is2 corresponds to the “combined detection current” of the present invention) flows through the RC parallel circuit 12.

1. Overall Configuration of Each Semiconductor Switch Device FIG. 2 is a block diagram showing the internal configuration of each semiconductor switch device 11. The internal configuration of both semiconductor switch devices 11 is the same, and the configuration of the semiconductor switch device 11a is shown in FIG.

  As shown in FIG. 2, the control signal S1 is input to the input interface 45 connected to the input terminal P1, and the FET 47 is turned on when the low-level control signal S1 is input to the input interface 45. Thus, the protection logic circuit 40 is energized. A charge pump circuit 41 and a turn-off circuit 42 are connected to the protection logic circuit 40, respectively, and an overcurrent detection circuit 13 and an overtemperature detection circuit 48 are also connected. A dynamic clamp 44 is connected between the drain terminal D and the gate terminal G of the power MOSFET 15. The overtemperature detection circuit 48 detects the temperature in the vicinity of the power MOSFET 15 and outputs a high level output signal S3 as a temperature abnormality when the temperature exceeds a predetermined threshold temperature.

  The output of the charge pump circuit 41 is given to the gate terminal G of the power MOSFET 15 and also to the gate terminal G of the sense MOSFET 16 in the overcurrent detection circuit 13 (see FIG. 3). The turn-off circuit 42 is provided between the drain terminal D and the source terminal S of the power MOSFET 15 and is connected to the gate terminal G of the power MOSFET 15 and the sense MOSFET 16, respectively. As will be described later, the charge pump circuit 41 and the turn-off circuit 42 are driven based on the control signal S4 from the protection logic circuit 40 to cause the power MOSFET 15 and the sense MOSFET 16 to conduct or cut off.

2. Overcurrent Detection Circuit Next, the overcurrent detection circuit 13 will be described. FIG. 3 is a circuit diagram mainly showing the overcurrent detection circuit 13 (corresponding to the “abnormality detection circuit” of the present invention) of the power supply control device 10. The figure also shows the configuration of the semiconductor switch device 11a.

  As shown in the figure, the power supply control device 10 includes a power MOSFET 15, a sense MOSFET 16 in which a sense current Is 1 corresponding to the current amount of the power MOSFET 15 flows, and an overcurrent detection to be described later that detects an abnormality in the current flowing in the power MOSFET 15. The semiconductor switch device 11 is configured in a form in which the circuit 13 and the protection logic circuit 40 are formed in one chip, or in a form in which the circuit 13 and the protection logic circuit 40 are formed in a single package.

  As for the power MOSFET 15 and the sense MOSFET 16, a plurality of MOSFETs connected to the power supply terminal P2 with the drain terminal D connected in common are arranged, and most of the MOSFET groups are powered by connecting the source terminal S to the output terminal P3 in common. A MOSFET 15 is configured, and a sense MOSFET 16 is configured by a common connection of the source terminals S of some MOSFET groups. The ratio of the number of MOSFET groups constituting the power MOSFET 15 and the number of MOSFET groups constituting the sense MOSFET 16 is approximately the sense ratio. The source terminal S of the power MOSFET 15 and the source terminal S of the sense MOSFET 16 are connected to respective input terminals of the operational amplifier 18, and the gate terminal of the FET 20 is connected to the output side of the operational amplifier 18.

  In this way, by making the drain terminals D and the source terminals S of the power MOSFET 15 and the sense MOSFET 16 have the same potential, the sense current Is1 having a stable and constant ratio with respect to the shunt current Ip1 flowing in the power MOSFET 15 is caused to flow in the sense MOSFET 16. be able to. The power MOSFET 15 and the sense MOSFET 16 are configured to be energized on the precondition that the operation switch 52 is turned on and a low-level control signal S1 is input from the input terminal P1.

  As for the sense current Is1 from the sense MOSFET 16, a mirror current Is1 'having the same level as the sense current Is1 flows through the connection line of the FET 26 and FET 28 by the current mirror circuit including the FET 24 and FET 26. Further, a mirror current Is1 ″ having the same level as the sense current Is1 flows from the FET 30 to the external connection terminal P4 by the current mirror circuit including the FET 28 and the FET 30.

  Now, between the source terminal S of the power MOSFET 15 and the ground, a voltage dividing circuit 55 formed by connecting a plurality of (for example, two) voltage dividing resistors R1 and R2 in series is arranged. As a result, the divided voltage Vr (corresponding to the “threshold voltage” of the present invention) at the connection point A between the voltage dividing resistor R1 and the voltage dividing resistor R2 is the source potential Vs (the output side voltage of the power FET) of the power MOSFET 15. The voltage is divided according to the resistance ratio of the two voltage dividing resistors R1 and R2. Here, as the voltage dividing resistors R1 and R2, those having a certain resistance ratio (for example, the resistance value of the voltage dividing resistor R1: the resistance value of the voltage dividing resistor R2 = 1: 1) are selected in advance.

  The divided voltage Vr at the connection point A is applied to one input terminal (negative input terminal) of the comparator 32, and the other input terminal (positive input terminal) of the comparator 32 is connected to the connection line between the FET 30 and the external connection terminal P4. ) Is connected.

  Further, an FET 66 that is diode-connected (the gate terminal G and the drain terminal D are commonly connected) is disposed between the voltage dividing circuit 55 and the ground. The gate terminal G of the FET 66 is connected to the power supply terminal P2 via the bias resistor 68 and the FET 70 (dark current cutoff circuit). The FET 70 is turned on when a low-level control signal S1 is input to the input terminal P1, and allows energization between the power supply terminal P2 and the bias resistor 68 (the input signal to the semiconductor switch element is active). When). The FET 66 applies a constant voltage Vt (bias) between the voltage dividing circuit 55 and the ground. With such a configuration, when the high-level control signal S1 is input to the input terminal P1, that is, when the load drive command signal is not input, the FET 70 is in a cutoff state, whereby the bias is applied from the power supply 61. The dark current flowing into the load 50 through the resistance 68 and the voltage dividing circuit 55 can be prevented. In the present embodiment, the FETs 66 and 70 and the bias resistor 68 are accommodated in the semiconductor switch device 11.

  The RC parallel circuit 12 flows a combined sense current Is (= Is1 ″ + Is2 ″) that is a combination of the sense current Is1 ″ from the semiconductor switch device 11a and the sense current Is2 ″ from the semiconductor switch device 11b. The combined sense current Is has a constant ratio with respect to the load current Ip flowing from the power supply 61 to the load 50. The terminal voltage Vo (corresponding to the “output voltage” of the present invention) of the RC parallel circuit 12 varies in accordance with the combined sense current Is. The comparator 32 compares the terminal voltage Vo (potential of the external connection terminal P4) of the RC parallel circuit 12 with the divided voltage Vr at the connection point A, and a large level of the sense current Is1 flows through the RC parallel circuit 12 to cause the terminal voltage. When Vo exceeds the divided voltage Vr, a high-level output signal S2 (corresponding to the “abnormal signal” of the present invention) is output. This divided voltage Vr is (1/2) · (Vs−Vt) + Vt (Vs: the source potential of the power MOSFET 15), and is applied to the load resistance of an external circuit (for example, the load 50) connected to the power supply control device 10. Accordingly, the abnormality detection value can be freely set by changing the circuit constant of the RC parallel circuit 12.

3. RC Parallel Circuit (1) Circuit Configuration As shown in FIGS. 1 and 3, the RC parallel circuit 12 (corresponding to the “common conversion circuit” of the present invention) includes a first resistor 60 (resistance value r of the present invention) connected in series. “Corresponding to“ first resistance element ”) and a capacitor 62 and a second resistor 64 (resistance value R corresponding to“ second resistance element ”of the present invention) are connected in parallel. One end side of the RC parallel circuit 12 is connected to the external connection terminal P4, and the other end side is connected to the ground. Therefore, the terminal voltage Vo of the RC parallel circuit 12 is applied to the input terminal of the comparator 32 in each semiconductor switch device 11 via the external connection terminal P4.

ｒ：第１抵抗６０の抵抗値
Ｃ：コンデンサ６２の容量
Ｒ：第２抵抗６４の抵抗値
ｔ：通電時間
従って、数式１から、異常検出される電流（端子電圧Ｖｏが閾値電圧としての分圧電圧Ｖｒに達したときの合成センス電流Ｉｓ、以下、「異常電流Ｉｏ」という）は、次の数式２で表すことができる。

そして、通電開始当初は、合成センス電流Ｉｓが第１抵抗６０、第２抵抗６４及びコンデンサ６２に流れる。このときの異常電流Ｉｏは、上記数式２より、次の数式３に示す電流Ｉｏ１となる。

（通電時間ｔ＝０）
そして、その通電状態が継続し通電時間ｔが経過するに従って、異常電流Ｉｏは、数式４に示す電流Ｉｏ２に収束していく。

（通電時間ｔ＝∞）
以上から、異常電流Ｉｏと通電時間ｔとの関係は、図４の点線で示す収束曲線Ｌ９となる。このことは、通電開始当初、ＲＣ並列回路１２の電流／電圧の変換率が小さく異常電流Ｉｏは大きなレベルとなり（つまり、大電流を流すことができ）、そのまま通電状態が継続した場合、ＲＣ並列回路１２における電流／電圧の変換率が徐々に増大し、異常電流Ｉｏのレベルが低減していく（流すことができる電流量が低減していく）ことを意味する。要するに、ＲＣ並列回路１２は、それに流れた合成センス電流Ｉｓの通電時間に応じて増大する変換率によって当該合成センス電流Ｉｓを端子電圧Ｖｏに変換するのである。なお、後述するように、閾値電圧としての分圧電圧ＶｒはパワーＭＯＳＦＥＴ１５のソース電圧Ｖｓに依存して変化するため、上記収束曲線Ｌ９も、同ソース電圧Ｖｓに応じた電流レベルの曲線となる（ソース電圧Ｖｓに依存して変化する分圧電圧Ｖｒの各値を上記数式１〜４に代入して求められる各曲線）。 (2) Setting of Circuit Constants Here, the terminal voltage Vo when the combined sense current Is (= Is1 ″ + Is2 ″) is passed through the RC parallel circuit 12 can be obtained by the following formula 1.

r: resistance value of the first resistor 60 C: capacitance of the capacitor 62 R: resistance value of the second resistor 64 t: energization time Therefore, from Equation 1, the current that is detected abnormally (the terminal voltage Vo is divided as the threshold voltage) The combined sense current Is when the voltage Vr is reached (hereinafter referred to as “abnormal current Io”) can be expressed by the following Equation 2.

Then, at the beginning of energization, the combined sense current Is flows through the first resistor 60, the second resistor 64, and the capacitor 62. The abnormal current Io at this time becomes a current Io1 shown in the following equation 3 from the above equation 2.

(Energization time t = 0)
Then, as the energization state continues and the energization time t elapses, the abnormal current Io converges to the current Io2 shown in Equation 4.

(Energization time t = ∞)
From the above, the relationship between the abnormal current Io and the energization time t is the convergence curve L9 indicated by the dotted line in FIG. This means that at the beginning of energization, the current / voltage conversion rate of the RC parallel circuit 12 is small and the abnormal current Io is at a large level (that is, a large current can flow). This means that the current / voltage conversion rate in the circuit 12 gradually increases and the level of the abnormal current Io decreases (the amount of current that can be passed decreases). In short, the RC parallel circuit 12 converts the combined sense current Is into the terminal voltage Vo at a conversion rate that increases in accordance with the energization time of the combined sense current Is that has flowed through the RC parallel circuit 12. As will be described later, since the divided voltage Vr as the threshold voltage changes depending on the source voltage Vs of the power MOSFET 15, the convergence curve L9 is also a current level curve corresponding to the source voltage Vs ( Each curve obtained by substituting each value of the divided voltage Vr, which varies depending on the source voltage Vs, into the above formulas 1-4).

  In addition, the curve shown by the solid line in FIG. 5 indicates the combined sense current and the energization time corresponding to the load current Ip for the smoke generation characteristics of the electric wire 51 (for example, the electric wire covering material) connected between the power supply control device 10 and the load 50, for example. It is the smoke generation characteristic curve L10 which showed the relationship with (smoke generation time). That is, it shows the time until burning of the covering material of the electric wire 51 occurs when an arbitrary constant current (one-shot current) is continuously supplied to the electric wire 51.

  In the figure, Istd is a combined sense current corresponding to the rated current of the load 50 (hereinafter simply referred to as “rated current Istd”), and Imax is allowed to flow in a thermal equilibrium state in which the heat generation and heat dissipation in the electric wire 51 are balanced. A combined sense current corresponding to a possible equilibrium limit current (hereinafter simply referred to as “equilibrium limit current Imax”). In the case where a current having a level higher than the equilibrium limit current Imax is applied, the region becomes an excessive thermal resistance region, and the current level and the energization time t until burning are in a substantially inversely proportional relationship. The smoke generation characteristic curve L10 can be obtained experimentally, for example.

  In the present embodiment, as shown in FIG. 4, the RC parallel circuit 12 is configured so that the convergence curve L9 becomes a curve substantially parallel to the smoke generation characteristic curve L10 in the region of the current level lower than the smoke generation characteristic curve L10. Each circuit constant (the resistance values r and R of the first resistor 60 and the second resistor 64 and the capacitance C of the capacitor 62) is adjusted. Further, the current Io2 is made substantially coincident with the rated current Istd of the electric wire 51. Here, the first resistor 60 and the second resistor 64 function to set the current Io1 at the beginning of energization so as not to exceed the smoke generation characteristic curve L10.

  The smoke generation characteristic curve L10 varies depending on the type of electric wire as an external circuit connected to the power supply control device 10, but the circuit constants (r, C, R) of the external RC parallel circuit 12 are adjusted. By doing, the convergence curve according to the smoke generation characteristic curve of each electric wire used as protection object can be formed.

  The high-level output signal S2 from the comparator 32 described above is configured to be input to the protection logic circuit 40, and a protection operation described later is performed. As shown in FIG. 2, the output signal S2 is also input to the OR circuit 49. The output signal S2 and a high-level output signal indicating a temperature abnormality from the over-temperature detection circuit 48 are provided. When any signal of S3 is input, the FET 46 is turned on, and a signal indicating an abnormality is output to an external circuit (for example, a warning lamp) using the pull-up resistor 54 connected to the diagnosis output terminal P5. . As will be described later, when the temperature abnormality occurs, the power MOSFET 15 is temporarily or continuously cut off.

4). Protection Logic Circuit FIG. 5 shows the configuration of a protection logic circuit 40 (corresponding to the “protection circuit” of the present invention) that is activated by receiving the low-level control signal S1. The protection logic circuit 40 has an RS-FF 90 (corresponding to an RS flip-flop “reset circuit”) as a latch circuit that applies a control signal S4 to the charge pump circuit 41 and the turn-off circuit 42 to perform an on / off operation. . In the RS-FF 90, the set signal SET from the OR circuit 91 is input to the set terminal S, and the output signal from the AND circuit 92 is input to the reset terminal R. The OR circuit 91 is supplied with a high-level output signal S2 indicating a current abnormality and a high-level output signal S3 indicating a temperature abnormality, and is set when any of these signals is input. The signal SET is output to set the RS-FF 90 in a set state, whereby the RS-FF 90 outputs a high level control signal S4.

  The AND circuit 92 receives a signal obtained by inverting the level of the output signal S3 from the overtemperature detection circuit 48 and a reset signal RST. Thus, the AND circuit 92 enables the reset signal RST to reset the RS-FF 90 when the temperature abnormality does not occur or is eliminated and the protection logic circuit 40 receives the low level output signal S3. To. On the other hand, when the protection logic circuit 40 receives the output signal S3 due to the occurrence of temperature abnormality, the reset signal RST is invalidated. This reset signal RST is generated when the low-level control signal S1 is input to the input terminal P1 (when a load drive command signal is input) or when the temperature is lowered due to a temperature abnormality (overheating state) (normally When the threshold temperature is reached, it is given to the protection logic circuit 40 as a pulse signal.

  With this configuration, the protection logic circuit 40 is activated by receiving the low-level control signal S1, and when normal, the charge pump circuit 41 is driven. The charge pump circuit 41 generates a boosted voltage from the power MOSFET 15 The sense MOSFET 16 is operated between the gate and the source to be turned on and to be energized. On the other hand, the protection logic circuit 40 turns off the charge pump circuit 41 and outputs a high-level control signal S4 for driving the turn-off circuit 42 when detecting an abnormality when receiving the high-level output signal S2 indicating the current abnormality. As a result, the electric charges between the gates and the sources of the power MOSFET 15 and the sense MOSFET 16 are discharged, and the operation is performed to cut off. And this interruption | blocking operation | movement is an interruption | blocking operation | movement which cannot return to an energized state unless self-reset is possible unless control signal S1 is input again (for example, load drive command signal is input).

  The protection logic circuit 40 also outputs a control signal S4 to cause the power MOSFET 15 and the sense MOSFET 16 to perform a shut-off operation when receiving a high-level output signal S3 indicating a temperature abnormality. This shut-off operation is a self-recoverable shut-off operation in which, when the power MOSFET 15 reaches the return temperature, the protection logic circuit 40 does not receive the abnormal temperature output signal S3 and returns to the energized state again.

[Effect of this embodiment]
(1) Rapid detection of current abnormality until the power MOSFET 15 is turned on and energized to reach a stable point FIG. 6 shows the drain-source voltage Vds and the divided voltage Vr of both sense MOSFETs 16 of the semiconductor switch devices 11a and 11b. FIG. 6 is a diagram showing a relationship with a synthesized sense current Is. The horizontal axis shows the drain-source voltage Vds of both sense MOSFETs 16, and the vertical axis shows the divided voltage Vr and the combined sense current Is according to the drain-source voltage Vds. The line L1 is a load line indicating a change in the combined sense current Is determined by the load resistance, and the line L2 is an on-resistance line indicating a change in the combined sense current Is determined by the on-resistance of the sense MOSFET 16.

  When the load 50 is in a normal state and the power MOSFET 15 is turned on, the stable point of the drain-source voltage Vds and the combined sense current Is of the sense MOSFET 16 becomes the intersection A between the load line L1 and the on-resistance line L2. That is, the values of the drain-source voltage Vds and the combined sense current Is of the sense MOSFET 16 correspond to the point B (Vs (source voltage of the power MOSFET 15) = 0, Id ( It changes along the load line L1 from the state (the drain current of the power MOSFET 15) = 0) and becomes stable when it reaches the stable point (intersection A). In FIG. 6, three load lines L <b> 1 are shown. A region surrounded by the load lines L <b> 1 indicates a variation range in the manufacturing stage of the semiconductor switch device 11.

  However, when an abnormal situation such as a short circuit of the load occurs, the source voltage Vs of the power MOSFET 15 hardly increases because the voltage drop at the load 50 is very small even when starting from the point B at the time of startup. That is, in a state where the drain-source voltage of the power MOSFET 15 does not change so much, the load current Ip flowing through the power MOSFET 15 rapidly increases, and the combined sense current Is rapidly increases starting from the point B. (Line L8 in FIG. 6).

  If the threshold voltage set as a constant value exceeds the terminal voltage Vo of the RC parallel circuit 12 and this is detected as a current abnormality, the threshold voltage is stable as shown in FIG. Since it must be set to a value higher than A, it takes time to detect a current abnormality when the source voltage Vs is low and the drain-source voltage Vds is high. Therefore, in order to quickly detect a current abnormality, it is desirable that the threshold voltage is low in a region where the drain-source voltage Vds is high and the threshold voltage is high in a region where the voltage Vds is low.

  Therefore, in the present embodiment, as shown by the line L3 in FIG. 6, the divided voltage Vr as the threshold voltage changes basically with substantially the same gradient as the load line L1 according to the drain-source voltage Vds. Is set. In order to make the change mode of the divided voltage Vr as the threshold voltage have such a gradient, in this embodiment, as described above, the divided voltage Vr obtained by dividing the source voltage Vs of the power MOSFET 15 is used as the threshold voltage. Yes. As a result, the divided voltage Vr changes linearly according to the drain-source voltage Vds of the power MOSFET 15, and is low in a region where the voltage Vds is high and high in a region where the voltage Vds is low.

  Further, in the region where the source voltage Vs is low and the drain-source voltage Vds is high, the load current Ip increases rapidly in the abnormal state, but the constant voltage Vt is applied by the FET 66 and the bias resistor 68. Therefore, a stable rising operation can be performed. As a result, an appropriate threshold voltage can be set even in a region where the drain-source voltage Vds of the power MOSFET 15 is very high, and the power MOSFET 15 can be quickly and appropriately set as an appropriate threshold voltage as compared with a configuration in which the threshold voltage is a constant value. It is possible to cut off in a state where the power loss at is small.

  In FIG. 6, a dotted line L <b> 3 indicates a transition of the divided voltage Vr as a threshold value when a short circuit is abnormal, and indicates a variation range in the manufacturing stage of the semiconductor switch device 11. As described above, in the present embodiment, even when the semiconductor switch device 11 is manufactured, the resistance values of the voltage dividing resistors R1 and R2 vary, which is manufactured in the same chip or the same package. The resistance values of the voltage dividing resistors R1 and R2 (L3 in FIG. 6) also vary in the same direction (direction in which the resistance value decreases or increases), and the voltage dividing ratio does not change. Therefore, by setting the RC parallel circuit 12 to an appropriate circuit constant according to the abnormal current level to be detected (current level at the time of short circuit abnormality, current level at the time of overcurrent abnormality), the voltage dividing resistors R1 and R2 Anomalous detection with high accuracy can be performed without affecting the variation of the resistance value.

(2) Fuse function When the operation switch 52 is turned on and the low-level control signal S1 is supplied to the power supply control device 10, the RS-FF 66 of the protection logic circuit 40 is reset. As a result, the charge pump circuit 41 is driven, the power MOSFET 15 and the sense MOSFET 16 are turned on, and the power supply state to the load 50 is started.

  Here, for example, when an external circuit such as the electric wire 51 or the load 50 is short-circuited and a large current flows through the power MOSFET 15, a high level composite sense current Is proportional to this flows through the RC parallel circuit 12 (hereinafter, this time) The synthesized sense current Is is referred to as “short-circuit current Is1”). The short-circuit current Is1 flows into the first resistor 60, the second resistor 64, and the capacitor 62 at the beginning of occurrence of the short-circuit abnormality. At this time, since the RC parallel circuit 12 is in the low conversion rate state, the terminal voltage Vo does not yet reach the divided voltage Vr, and the output signal S2 is not output from the comparator 32.

  When the short-circuit current Is1 continues to flow as it is, the RC parallel circuit 12 gradually becomes in a high conversion rate state, and when the energization time reaches t1 as shown in FIG. 4 (the relationship between the short-circuit current Is1 and the energization time is the above convergence). When the voltage reaches the curve L9), the terminal voltage Vo exceeds the threshold voltage Vr, and the output signal S2 is output from the comparator 32. In response to this output signal S2, the RS-FF 66 of the protection logic circuit 40 enters a set state and outputs a high level control signal S4 to cause the power MOSFET 15 and the sense MOSFET 16 to perform the shut-off operation incapable of self-recovery. Here, since the convergence curve L9 is set in a level region lower than the smoke generation characteristic curve L10 of the electric wire 51, if the short-circuit abnormality continues after the occurrence of the short-circuit abnormality, the power MOSFET 15 is turned on after the energization time t1 has elapsed. It is possible to prevent the electric wire 51 from being burned out by performing a blocking operation. That is, the power supply control device 10 has a so-called fuse function for protecting the electric wire 51.

  Even if the short circuit state does not occur, an overcurrent abnormality in which a current larger than the rated current Istd flows may occur in the power MOSFET 15 for some reason (hereinafter, the combined sense current Is at this time is referred to as “overcurrent Is2”. (<Short-circuit current Is1) "). In this case, when the overcurrent abnormality continues and the energization time reaches t2 (> t1) as shown in FIG. 4 (when the relationship between the overcurrent Is2 and the energization time reaches the convergence curve L9). In addition, the output voltage S2 is output from the comparator 32 when the terminal voltage Vo exceeds the threshold voltage Vr. As a result, when the overcurrent abnormality continues after the occurrence of the overcurrent abnormality, the power MOSFET 15 can be prevented from performing self-recovery after the energization time t2, and the electric wire 51 can be prevented from being burned out. .

  As described above, the power supply control device 10 according to the present embodiment self-activates itself at an appropriate energization time (t1, t2) corresponding to each abnormal current level when a current abnormality such as a short circuit abnormality or an overcurrent abnormality occurs, for example. An unrecoverable shut-off operation can be performed.

  Further, since the RC parallel circuit 12 is provided outside the semiconductor switch device 11, the RC parallel circuit 12 is suppressed by suppressing variations in resistance values (so-called large halves, which are also referred to as double halves) due to the manufacturing process. The 12 characteristics can be set with high accuracy and the circuit constants can be set freely. As a result, a highly accurate fuse function corresponding to the electric wire can be realized.

  Moreover, the RC parallel circuit 12 has a configuration in which a first resistor 60 and a capacitor 62 connected in series and a second resistor 64 are connected in parallel. With this configuration, the maximum amount of abnormal current Io at the beginning of energization or at the beginning of abnormal current generation can be set to a finite value as shown in Equation 3 above. Therefore, by adjusting the resistance values R and r of the first and second resistors 60 and 64, the power MOSFET 15 and the sense MOSFET 16 can be protected by setting them to a value that does not exceed the maximum allowable current value of the power MOSFET 15 and the sense MOSFET 16. can do.

  Furthermore, in the present embodiment, two power MOSFETs 15 are connected in parallel to the current path 63 between the power supply 61 and the load 50, and the power is supplied to the load 50 by turning these two power MOSFETs 15 on and off. In FIG. 3, a current abnormality is detected using a common RC parallel circuit 12. Therefore, current abnormality can be detected efficiently while reducing the number of parts compared to the configuration in which the RC parallel circuit 12 is provided for each of the two power MOSFETs 15.

<Embodiment 2>
FIG. 8 shows a second embodiment. The difference from the above embodiment is the set value of the circuit constant of the RC parallel circuit 12, and the other points are the same as in the first embodiment. Therefore, the same reference numerals as those in the first embodiment are given and the redundant description is omitted, and only different points will be described next.

  A convergence curve L11 indicated by a dotted line in FIG. 8 indicates the relationship between the abnormal current Io and the energization time t, and can be expressed by mathematical expressions 1 to 4 similar to the convergence curve of the first embodiment. The curve shown by the solid line in FIG. 5 is the relationship between the combined sense current corresponding to the current level flowing through the power MOSFET 15 and the allowable energization time until the power FET 15 can self-destruct at that current level, with respect to the self-destructive characteristic of the power MOSFET 15. It is the self-destructive characteristic curve L12 which showed the curve which showed. That is, the time until the power MOSFET 15 self-destructs when an arbitrary constant current (one-shot current) is continuously supplied to the power MOSFET 15 is shown.

  In the figure, Istd is a combined sense current corresponding to the rated current (hereinafter simply referred to as “rated current Istd”), and Imax is an equilibrium that can flow in a thermal equilibrium state in which the power MOSFET 15 is balanced between heat generation and heat dissipation. This is a combined sense current corresponding to the time limit current (hereinafter simply referred to as “equilibrium limit current Imax”). When a current having a level higher than the equilibrium limit current Imax is applied, the region becomes an excessive thermal resistance region, and the current level and the energization time t until self-destruction are in an approximately inversely proportional relationship. The self-destructive characteristic curve L12 can be obtained experimentally, for example.

  In the present embodiment, as shown in FIG. 8, the RC parallel circuit 12 is configured so that the convergence curve L11 becomes a curve substantially parallel to the self-destructive characteristic curve L12 in a level region lower than the self-destructive characteristic curve L12. Each circuit constant (the resistance values r and R of the first resistor 60 and the second resistor 64 and the capacitance C of the capacitor 62) is adjusted. Further, the current Io2 is made substantially equal to the rated current Istd of the power MOSFET 15. Here, the first resistor 60 and the second resistor 64 function to set the current Io1 at the beginning of energization so as not to exceed the self-destruct characteristic curve L12.

  Although the self-destructive characteristic curve L12 varies depending on the configuration of the power MOSFET 15 and manufacturing variations, it can be protected by adjusting the circuit constants (r, C, R) of the external RC parallel circuit 12. A convergence curve corresponding to the self-destructive characteristic curve of each power MOSFET can be formed.

  Further, the curve indicated by the alternate long and short dash line in FIG. 8 shows the relationship between the combined sense current corresponding to the load current flowing through the load 50 and the energization time for the inrush current characteristics of the load 50 such as a lamp or a motor. Inrush current characteristic curve L13. That is, it shows a change with time in the load current level (synthetic sense current level) from the start of energization of the load 50 to the steady state in a state where no current abnormality occurs. The inrush current characteristic curve L13 can also be obtained experimentally, for example. The circuit constants of the RC parallel circuit 12 (resistance values r and R of the first resistor 60 and the second resistor 64 are set so that the convergence curve L11 is positioned in a level region higher than the inrush current characteristic curve L13. The capacitance C) of the capacitor 62 is adjusted.

  With such a configuration, for example, when a current abnormality such as a short circuit abnormality or an overcurrent abnormality occurs, a shut-off operation that is not self-recoverable is executed in an appropriate energization time (t1, t2) corresponding to each abnormal current level. Thus, the power MOSFET 15 can be reliably protected from self-destruction. Moreover, it is possible to prevent the power MOSFET 15 from being cut off by detecting an abnormality with respect to the inrush current flowing at the beginning of energization of the load 50.

<Other embodiments>
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention.
(1) In each of the above embodiments, the plurality of voltage dividing resistors (voltage dividing resistors R1, R2) have the same resistance value, but the present invention is not limited to this, and may have different resistance values.

  (2) In each of the above embodiments, the positive logic circuit that outputs the high-level output signal S2 when the terminal voltage Vo exceeds the divided voltage Vr in the comparator 32 is output, but the low-level output signal S2 is output. Of course, it may be configured by a negative logic circuit.

  (3) In each of the embodiments described above, the protection logic circuit 40 that receives the output signal S2 and causes the power MOSFET 15 to perform the shut-off operation is provided in the power supply control device 10, but the configuration is not limited thereto. The output signal S2 may be output from the device 10 to the outside, and the power MOSFET 15 may be cut off by a protection circuit provided outside.

  (4) In the first embodiment, similarly to the second embodiment, the convergence curve L9 is positioned in a higher level region than the inrush current characteristic curve L13 of the load 50, thereby avoiding abnormality detection for the inrush current. It is good.

  (5) Compared to the second embodiment, the convergence curve L11 is a curve along the inrush current characteristic curve L13 in a level region higher than the inrush current characteristic curve L13, and other characteristic curves (the smoke generation characteristic curve described above) The circuit constant of the RC parallel circuit 12 may be set so as to be a curve located in a level region lower than L10 or a characteristic curve other than the self-destructive characteristic curve L12.

  (6) In the above embodiment, the second resistor 64 is substantially the same as the resistance value of the first resistor 60. However, the present invention is not limited to this, and the second resistor 64 may be larger or smaller than the resistance value of the first resistor 60. May be. Specifically, for example, the ratio of the resistance values of the first resistor 60 and the second resistor 64 may be 1: 4.

  (7) Although the RC parallel circuit is used as the common conversion circuit in each of the above embodiments, the present invention is not limited to this, and an RC parallel circuit excluding the first resistor 60 as the first resistance element may be used. Further, it may be a simple resistor or a capacitor.

  (8) In each of the above embodiments, the power supply to the load 50 is performed using the two semiconductor switch devices 11. However, the power supply to the load 50 is performed using three or more semiconductor switch devices 11. The structure to perform may be sufficient. Also in this case, the combined sense current of the sense currents from the sense MOSFETs 16 of the three or more semiconductor switch devices 11 is allowed to flow to the RC parallel circuit 12, so that the number of parts can be reduced.

  (9) In each of the above embodiments, the power MOSFET 15 is used as the semiconductor switch element. However, the present invention is not limited to this, and other unipolar transistors or bipolar transistors may be used.

  (10) In each of the above embodiments, a so-called sensing method is used in which the sense MOSFET 16 is used as a current detection element. However, the present invention is not limited to this. For example, a shunt resistor is provided in the current path and a load current is detected based on the voltage drop. The so-called shunt method may be used.

  (11) In each of the above-described embodiments, the overcurrent detection circuits 13 and 13 are individually provided for each power MOSFET 15. However, the present invention is not limited to this, and a common overcurrent detection circuit 13 is provided for all the power MOSFETs 15. The structure which provides one may be sufficient. In this case, on the condition that the output signal S2 is output from the common overcurrent detection circuit 13, all power is supplied by the protection logic circuit 40 provided for each power MOSFET 15 or one common protection logic circuit 40. A configuration in which the MOSFETs 15 are collectively cut off is desirable.

1 is an overall schematic diagram of a power supply control device according to a first embodiment of the present invention. Block diagram showing the configuration of each semiconductor switch device Circuit diagram mainly illustrating the configuration of the overcurrent detection circuit Graph showing convergence curve and smoke characteristics curve Block diagram conceptually illustrating a protection circuit The figure which shows the relationship between the drain-source voltage of a sense MOSFET, the divided voltage, and the synthetic | combination sense current Is. Explanatory drawing explaining the problem when setting the threshold value constant The graph which showed the convergence curve, self-destructive characteristic curve, and inrush current characteristic curve of Embodiment 2

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Power supply control apparatus 12 ... RC parallel circuit (common conversion circuit)
13. Overcurrent detection circuit (abnormality detection circuit)
15 ... Power MOSFET (semiconductor switch element, power FET)
16 ... sense MOSFET (current detection element, sense FET)
40 ... logic circuit for protection (protection circuit)
50 ... Load (external circuit)
61 ... Power source 63 ... Energizing path 60 ... First resistance (first resistance element)
62 ... Capacitor 64 ... Second resistance (second resistance element)
Is1 (Is1 ′, Is1 ″), Is2 (Is2 ″)... Sense current (detection current)
S2 ... Output signal (abnormal signal)
Vr: Divided voltage (threshold voltage)
Vo: Terminal voltage (output voltage)
Vs: Source potential (power FET output side voltage)

Claims (7)

A power supply control device that is provided between a power source and a load and controls power supply from the power source to the load,
A plurality of semiconductor switch elements connected in parallel to each other in a current path from the power source to the load;
A plurality of current detection elements provided corresponding to each of the plurality of semiconductor switch elements, each of which outputs a detection current corresponding to a current flowing through the corresponding semiconductor switch element,
A common conversion circuit that is commonly connected to the output side of the plurality of current detection elements and converts a combined detection current from the plurality of current detection elements into a voltage;
A power supply control device comprising: an abnormality detection circuit that outputs an abnormality signal when an output voltage of the common conversion circuit exceeds a threshold voltage. Each of the semiconductor switch elements is a power FET, and each of the current detection elements is a sense FET in which a sense current having a predetermined relationship with respect to a current flowing in the corresponding power FET is output, and the sense current is output as the detection current. The power supply control device according to claim 1, which has a configuration. The common conversion circuit includes a first resistance element and a capacitor connected in series to a joining path of detection currents from the plurality of semiconductor switch elements, and a first resistance element and a capacitor connected in parallel to the first resistance element and the capacitor. The power supply control device according to claim 1, comprising a two-resistance element. The power supply control device according to claim 3, wherein the second resistance element has a resistance value larger than that of the first resistance element. The power supply control device according to claim 1, wherein the common conversion circuit is a resistance element. A plurality of the abnormality detection circuits are provided corresponding to the plurality of semiconductor switch elements,
6. The power supply control device according to claim 1, further comprising a protection circuit that causes each of the semiconductor switch elements corresponding to the abnormality signal to be cut off based on each abnormality signal output from each abnormality detection circuit. 7. The abnormality detection circuit is one common abnormality detection circuit for the plurality of semiconductor switch elements,
The power supply control device according to any one of claims 1 to 5, further comprising a protection circuit that causes the plurality of semiconductor switch elements to collectively perform a shut-off operation based on an abnormality signal output from the common abnormality detection circuit.

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