JP2001160746A - Semiconductor switching device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely carrying out the protection of a switching element against an overcurrent and high heat, to prevent internal destruction and to improve reliability as a switching device. SOLUTION: When an overcurrent state to a load 102 is detected and the repetitive ON/OFF control of an FET QA with a built-in temperature sensor is performed, an overcurrent state control circuit 200 times 1 msec in a 1 msec timer circuit 202, then stops overcurrent detection by tuning ON a switching transistor Tr1 by the output of a latch circuit 203 and holds the ON state of the FET QA with the built-in temperature sensor. After timing 9 msec in a 9 msec timer circuit 204 from the overcurrent detection stoppage, that is before 10 msec without the danger of generating the internal destruction of the FET QA with the built-in temperature sensor, the switching transistor Tr3 is turned ON by the output of the latch circuit 207, the switch input of a driving circuit 111 is turned to an L level and the FET QA with the built-in temperature sensor is controlled to an OFF state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor switching device which uses a power semiconductor as a switching element to turn on and off a relatively large current to a vehicle light or the like. The present invention relates to a semiconductor switching device that performs overheat cutoff control and overcurrent protection control so as not to perform the control.

[0002]

2. Description of the Related Art Conventionally, power M
OS / FET and IGBT (Insulatedgate bipolar tran
2. Description of the Related Art A semiconductor switching device which turns on and off a relatively large current by using a switching device as a switching element is well known. As such a semiconductor switching device, an insulated gate type semiconductor switching device including an overheat protection control circuit and an overcurrent protection control circuit integrated is known (for example, Japanese Patent Application Laid-Open No. 5-95633, "Power Control Device").
JP-A-9-331625, "Intelligent power switch and switching device", JP-A-11-11331, "Electric power steering control device".

[0003] In such a semiconductor switching device, the overcurrent protection control circuit compares the voltage at which the current to the load is detected with a threshold value of the reference voltage, and determines the overcurrent when a short circuit occurs on the load side. Judgment is performed, and switching control is performed to forcibly turn off the switching element based on the judgment.

FIG. 5 is an operation waveform diagram for explaining overcurrent protection control in a semiconductor switching device constructed using a conventional shunt resistance element. In FIG. 5, in this example, when a load short circuit occurs, an overcurrent is applied to a load short circuit current exceeding a threshold value under software control during a monitoring time (for example, sampling every 5 msec is performed for a period of 30 msec). Depending on the hardware configuration of the protection control circuit, power switching elements (so-called,
Switching control is performed such that a temperature sensor built-in FET is repeatedly turned on and off around a threshold value of the circuit. In this repetitive on / off control, the power switching element is forcibly turned off by software control. In the case of a short-circuit current due to a load short-circuit just below the threshold of software (for example, a wire harness in a car), if the time is long, the power switching element heats up and finally self-protection by the temperature sensor built-in FET Is performed. In other words, in this example, double protection is performed by software control and hardware configuration.

FIG. 6 is an operation waveform diagram for explaining another overcurrent protection control in a semiconductor switching device constituted by using a conventional shunt resistance element. The example of FIG. 6 is a configuration in Japanese Patent Application Laid-Open No. 9-331625. In this intelligent power switch (IPS), when an overcurrent occurs in the power switching element, the power switching element is turned off every time the overcurrent threshold is exceeded. It is designed to be turned off.

FIG. 5 shows such an overcurrent protection control.
In the example shown in FIG. 6, thermal stress occurs inside the power switching element. FIG. 7 is a configuration diagram for explaining the problem of internal thermal stress in the power MOS-FET.

FIG. 7A shows a top configuration of the power MOS-FET, and FIG. 7B shows a side configuration thereof.
In this power MOS-FET, when a long-time low-current supply to a chip (appropriately described as an internal semiconductor circuit element portion) 14 is performed, the temperature of the entire stem (appropriately described as a base) 10 increases. When the power supply is stopped at this point, especially in a low-temperature atmosphere (low-temperature environment),
4 and the temperature of the stem 10 decrease. Such overheating,
Due to the stress caused by repeated cooling, the Al
In some cases, sliding (deformation movement) occurs in the (aluminum) wiring 13, and cracking or peeling (referred to as internal destruction as appropriate) occurs in the solder joint 15 between the stem 10 and the chip 14.

For example, in FIG. 5, when the current value at which on / off control is performed by the hardware configuration is set to 20 amps [A], overheat cutoff control (for example, with a temperature sensor built-in FET) is performed for several tens of msec. Cutoff temperature 175
C). If this overheat cutoff control is repeated in an atmosphere at -40 ° C, the internal stress is likely to occur as described above due to the accumulation of the thermal stress. The number of times of endurance (the number of times of temperature rise and fall) to this thermal stress is about several thousand times at present.

[0009]

As described above, in the conventional semiconductor switching device, when the overcurrent state continues or is repeated several times, the FET with a built-in temperature sensor is used.
The internal stress in the chip or the stem is likely to occur due to the thermal stress caused by the repetition of overheating and cooling in the semiconductor device, and the reliability as a semiconductor switching device may be reduced.

The present invention has been made in view of the above circumstances, and performs overheat cutoff control and overcurrent protection control before internal destruction due to heat occurs inside a switching element.
An object of the present invention is to provide a semiconductor switching device capable of reliably protecting a switching element against overcurrent and high heat and improving reliability as a switching device.

[0011]

According to the present invention, there is provided a semiconductor switching device having an overheat cutoff function, for turning on / off a power supply to a load, detecting an overcurrent to the load, and detecting an overcurrent. Overcurrent detection control means for repeatedly performing on / off control of the semiconductor switching element when a state is detected; and after the lapse of a first predetermined time from the start of repetitive on / off control by the overcurrent detection control means, The detection of current is stopped to keep the ON state of the semiconductor switching element, and after a lapse of a second predetermined time from the stop of the overcurrent detection, the overcurrent state continues without operating the overheat cutoff function of the semiconductor switching element. And an overcurrent state control means for controlling the semiconductor switching element to be in an off state.

[0012] Preferably, the overcurrent state control means includes a first timekeeping means for measuring the first predetermined time, and an overcurrent detection by the overcurrent detection control means when the first timekeeping means finishes the timekeeping. Overcurrent detection stop means for stopping and maintaining the ON state of the semiconductor switching element, second time counting means for counting the second predetermined time, and driving of the semiconductor switching element at the end of the time counting by the second time counting means Switching element cutoff means for cutting off the control signal.

Preferably, the semiconductor switching element, the overcurrent detection control means, and the overcurrent state control means,
It shall be mounted as a one-chip device.

In the above configuration, when an overcurrent state due to a short circuit on the load side is detected, the overcurrent state control means includes:
After a first predetermined time has elapsed from the start of the repeated on / off control by the overcurrent detection control means, the overcurrent detection of the overcurrent detection control means is stopped and the on state of the semiconductor switching element is maintained. Here, when a large current flows due to the continuation of the supply of the overcurrent, the overheat cutoff function of the semiconductor switching element operates and the semiconductor switching element is turned off.
Further, if the overcurrent cut-off function of the semiconductor switching element is not operating and the overcurrent state continues after the lapse of the second predetermined time from the stop of the overcurrent detection, the overcurrent state control means forcibly switches the semiconductor switching element. Control to the off state.

Thus, the overheat cutoff control and the overcurrent protection control are performed so that the internal destruction due to the internal overheating in the semiconductor switching element does not occur. For example, the overheating cutoff control for the semiconductor switching element is executed before the overheating of the chip that causes internal destruction is transmitted to the stem. Therefore, thermal stress due to repetition of overheating and cooling in the semiconductor switching element does not accumulate much, and internal breakdown due to heat is less likely to occur. As a result, protection of the switching element against overcurrent and high heat is reliably performed, and the reliability of the switching device is improved.

By configuring the semiconductor switching device as a one-chip device, the device configuration can be reduced in size, the mounting space can be reduced, and the device cost can be reduced.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram and a circuit diagram showing a basic configuration according to an embodiment of the semiconductor switching device of the present invention. FIG. 2 shows a configuration of an overcurrent state control circuit which is a main part of the semiconductor switching device according to the present embodiment. It is a block and circuit diagram shown. In FIG. 2, only the essential parts of the components corresponding to FIG. 1 are shown.

First, a semiconductor switching device having a basic configuration will be described with reference to FIG. The semiconductor switching device of the present embodiment is configured as a one-chip switching device 110, and the present applicant has proposed this basic configuration in Japanese Patent Application No. 11-140421.

The switching device 110 includes a power supply 1
01 is connected to the supply voltage VB line,
A load 102 such as a lamp or a motor is connected as an external element. Also, the on-
Switch SW1 and resistance element R1 for giving an OFF instruction
0 is provided and connected to the supply voltage VB line and the switching device 110.

The switching device 110 includes a temperature sensor FET / QA having a switching function as a semiconductor switching element and its own temperature protection function, and is provided on a path for supplying the supply voltage VB from the power supply 101 to the load 102. , The drain D-source S of the FET QA with a built-in temperature sensor is connected in series. The switching device 110 controls power supply by switching control of the temperature sensor built-in FET / QA, and includes a drive control unit, an overheat protection unit, a load current detection unit, etc. This is an integrated circuit that is integrated and mounted on a PC.

The switching device 110 includes a charge pump circuit 305 and a drive circuit 111 as drive control means for controlling ON / OFF of the FET QA with a built-in temperature sensor. The drive circuit 111 includes a source transistor having a collector connected to the output of the charge pump circuit 305 and a sink transistor having an emitter connected to the ground potential connected in series.
Based on the switching signal by switching off, the source transistor and the sink transistor are turned on / off to output a signal for driving and controlling the temperature sensor built-in FET QA. When the supply voltage VB is, for example, 12 [V], the output voltage of the charge pump is, for example, VB + 10
[V] is set.

Further, a cutoff latch circuit 306 is provided as an overheat protection means for the FET QA with a built-in temperature sensor.
The cutoff latch circuit 306 realizes an overheat cutoff function which is also added to the thermal FET, and uses a built-in temperature sensor (not shown) to notify that the temperature of the temperature sensor built-in FET QA has risen to a temperature higher than a specified value. If detected, the detection information to that effect is held in the latch circuit, and the overheating cutoff FET (not shown) connected between the gate and the source of the temperature sensor built-in FET QA is turned on. Thus, the temperature sensor built-in FET QA is forcibly turned off. The information held by the latch circuit is output via the terminal T14 and can be used as a diagnosis (diagnosis) information signal by, for example, a microcomputer (not shown).

Further, as load current detecting means of the FET QA with a built-in temperature sensor, there are provided an overcurrent detection control section 301 corresponding to the overcurrent detection control means and an undercurrent detection section. More specifically, the overcurrent detection control unit 301 includes an FET / QB as a second semiconductor switching element and a resistance element R
1, R2, R5, Rr1, a diode D1, and a comparator CMP1. That is, the temperature sensor built-in FET QA, the FET QB connected in parallel to the load 102, and the resistance element Rr1 are means for generating a first reference voltage in overcurrent detection.
The source SB potential of QB is supplied to the inverting input terminal (-) of the comparator CMP1. Further, the comparator C
The non-inverting input terminal (+) of MP1 has a built-in temperature sensor F
A voltage obtained by dividing the voltage VDSA between the drain D and the source S of ET / QA by the resistance elements R1 and R2 is supplied via the resistance element R5.

That is, as a reference voltage generating means, a first reference voltage having a voltage characteristic substantially equivalent to the voltage of a load connected to the source S of the FET QA with a built-in temperature sensor is connected to the FET QB on the same chip and the external circuit. Generated by the resistance element Rr1. The comparator CMP1 compares the first reference voltage with the voltage between the source S of the FET QA with built-in temperature sensor and the ground to detect a difference therebetween, thereby detecting an overcurrent.

When a complete short circuit (dead short circuit) occurs on the load 102 side by the overcurrent detection control section 301, the output of the comparator CMP1 becomes valid (high level: hereinafter, referred to as H level) and the drive is started. Circuit 1
11 turns off the FET QA with a built-in temperature sensor. When an incomplete short circuit (rare short) having a certain short-circuit resistance occurs, the temperature sensor built-in F
On / off control (so-called current limit control) for repeating on / off operations of the ET / QA is performed.
In general, when a short circuit occurs on the load side, even if it is a dead short circuit, the temperature sensor FET QA often repeats the ON / OFF operation because of the resistance of the wiring and the like. The period from when the FET QA with a built-in temperature sensor changes from the OFF state to the ON state until the voltage VDSA between the drain D and the source S is saturated is a so-called pinch-off operation of the FET. That is, when an excessive current as described above flows, the FET QA with a built-in temperature sensor operates in the pinch-off region, and the on / off control is repeated. With such ON / OFF control, the supply voltage VB
In the power supply path from the line to the load, it is possible to protect the circuit including the temperature sensor built-in FET / QA against excessive current.

Here, the setting of the first reference voltage, that is, the setting of the resistance value of the resistance element Rr1 is performed as follows. That is, normally, the FET QA with a built-in temperature sensor has n F
Since ET (having the same characteristics as FET and QB) is connected in parallel, the resistance element Rr
1 may be set to [resistance value of load 102 × n], that is, the load resistance components are substantially equivalent when viewed from each of the temperature sensor built-in FET QA and the FET QB. In this case, it is appropriate to use a value of the short-circuit resistance at the time of incomplete short-circuit (rare short) (that is, a value in which the resistance element Rr1 is slightly larger than the resistance value of the load 102) as the resistance value of the load as a setting reference. is there. In FIG. 1, the output of the comparator CMP1 is supplied only to the drive circuit 111. However, the output can be output to the outside via a terminal and used for other control or the like.

Next, the undercurrent detection unit, specifically,
ET / QC, resistance element Rr2 and comparator CMP2
Has been realized. That is, the FET QC and the resistance element Rr2 are means for generating a second reference voltage in detecting an undercurrent, and the source SC potential of the FET QC is supplied to the inverting input terminal (-) of the comparator CMP2. The non-inverting input terminal (+) of the comparator CMP2 is connected to the source S of the temperature sensor built-in FET QA.
A potential is supplied.

That is, the second reference voltage having a voltage characteristic substantially equivalent to the source voltage of the temperature sensor built-in FET QA is connected to the FET QC on the same chip and the resistance element Rr of the external circuit.
2 is generated. And the comparator CMP2
, The second reference voltage and the temperature sensor built-in FET QA
Undercurrent detection is performed by comparing these source voltages with each other and detecting these differences.

The undercurrent detector detects the load 102
When a disconnection failure or the like occurs on the
The output of P2 becomes valid (low level: hereinafter, referred to as L level), and an undercurrent detection signal is sent to the terminal T1 as a signal indicating that the load is open (for example, lamp disconnection information).
5 to the outside. Here, the setting of the second reference voltage, that is, the setting of the resistance value of the resistance element Rr2 is performed as follows. Similarly to the first reference voltage (the resistance element Rr1), the resistance value of the resistance element Rr2 may be set to [the resistance value of the load 102 × n]. It is appropriate to use a value on the order of resistance.

In addition to the drive control means, overheat protection means and load current detection means described above, the switching device 1
10 includes a power supply Enable 302 and masking (rush current mask circuit) 30 for avoiding overcurrent determination of the rush current.
3. ON / OFF to perform cutoff control by integrating the number of ON / OFF times
An OFF counting integration circuit 304 is also provided. Since these components are not directly related to the overheat cutoff control and the overcurrent protection control of the present invention, the description is omitted.

Finally, the characteristics of the switching device 110 can be summarized as follows.
This is advantageous for large current circuits because it eliminates the need for a shunt resistor for detecting the current flowing in the power supply path, and is advantageous for large current circuits. Second, it has high current sensitivity and high current detection accuracy. Third, it is simple. Drive control with built-in temperature sensor F
The ET / QA can be controlled on / off, and the overheating cutoff function and the ON / OFF counting and integrating circuit 304 enable high-speed processing as compared with the program processing of a microcomputer or the like. The circuit configuration can be reduced in size, the mounting space can be reduced, and the device cost can be reduced. Fifth, the current detection is based on the drain-source voltage VDSA of the FET / QA with a built-in temperature sensor.
Since the detection is performed by detecting a difference between the reference voltage and the second reference voltage, forming the FETs QB and QC and the FET QA with a built-in temperature sensor on the same chip allows a common-mode error factor in current detection, that is, a power supply Voltage fluctuations,
It is possible to eliminate the effects of temperature drift, lot-to-lot variation, and the like.

Here, the on / off operation of the temperature sensor built-in FET QA will be described in more detail. Built-in temperature sensor F
When the ET / QA transitions to the ON state, the drain current ID
QA rises toward the final load current value determined by the circuit resistance. Further, the gate-source voltage VTGSA of the FET QA with a built-in temperature sensor takes a value determined by the drain current IDQA, and the brake is applied by the Miller effect of the capacitor CGD due to the decrease in the drain-source voltage VDSA. Stand up. In addition, FET
The gate-source voltage VTGSB of QB is determined by the fact that the FET QB operates as a source follower with Rr1 as a load.

Further, since the gate-source voltage VTGSA of the temperature sensor built-in FET QA increases as the drain current IDQA increases, the gate-source voltage becomes VTGSB <VTGSA. VDSA = VTGSA + VTG
D, VDSB = VTGSB + VTGD, so that VDSA
-VDSB = VTGSA-VTGSB. Here, the gate-source voltage difference VTGSA-VTGSB is equal to the drain current IDQA.
-IDQB, the current ID flowing through the temperature sensor built-in FET QA by detecting VTGSA-VTGSB.
The difference between QA and the current IDQB flowing through the FET QB can be obtained. IDQB approaches a current (IDQA / n) corresponding to IDQA as VDSB decreases (in this case, VDSA also decreases).

The drain-source voltage V of the FET QB
DSB is directly input to the comparator CMP1, and the voltage VDSA between the drain and source of the FET QA with a built-in temperature sensor is obtained by dividing the voltage VIN divided by the resistance elements R1 and R2 into the comparator C1.
Input to MP1. That is, VIN = VDSA × R1 / (R1 + R2) (1) is input to the comparator CMP1.

Immediately after the temperature sensor built-in FET QA transitions to the ON state, the input voltage VIN of the comparator CMP1 is changed.
Is VDSB> VIN with respect to the drain-source voltage VDSB of the FET QB, but the temperature sensor built-in FET QA
As the drain current IDQA increases, VIN increases and finally exceeds VDSB. At this time, the output of the comparator CMP1 changes from H level to L level, and the temperature sensor built-in FET QA is turned off.

Assuming that the drain-source voltage VDSA when the FET QA with the built-in temperature sensor is turned off is the threshold value VDSAth, the following equation is established. VDSAth−VDSB = R2 / R1 × VDSB (2) Therefore, the overcurrent determination value is determined based on the equation (2).

In other words, the drain current IDQA increases as time elapses after the temperature sensor built-in FET QA transitions to the on state, and when the overcurrent determination value is exceeded and the drain-source voltage VDSA becomes larger than VDSAth. , The temperature sensor built-in FET QA transitions to the off state.

After the FET QA with a built-in temperature sensor transits to the OFF state, the drain current IDQA decreases, and the input voltage VIN of the comparator CMP1 again changes to the FET QB.
VDSB> VIN for the drain-source voltage VDSB of
Becomes At this time, the output of the comparator CMP1 changes from the L level to the H level, and the temperature sensor FET
The QA is turned on. As described above, the FET QA with a built-in temperature sensor repeats the transition to the ON state and the OFF state in the pinch-off region.

Next, the overcurrent state control circuit 20 shown in FIG.
0 will be described. The semiconductor switching device of the present embodiment has an overcurrent state control circuit 200 corresponding to the overcurrent state control means of FIG. 2 integrated and mounted in the same package in addition to the basic configuration of FIG. ing.

The overcurrent state control circuit 200 controls the FET / QA with built-in temperature sensor to the above-mentioned overheat protection means before the overheating of the chip of the FET / QA with built-in temperature sensor is transmitted to the stem (within 10 msec in this embodiment). This is a configuration for preventing the occurrence of internal destruction by performing off control by the overcurrent detection control means. The overcurrent detection signal output from the comparator CMP1 in the overcurrent detection control unit 301 to the overcurrent control input of the drive circuit 111 is provided. An integration circuit 201 for integration, a 1 msec timer circuit 202 corresponding to a first time counting means for counting 1 msec for counting a period until the overcurrent detection control section 301 is stopped, a latch circuit 203 for latching and outputting an input signal, 205, 207,
Switching transistors Tr1, Tr2 and Tr3,
9ms to time the period until forcible off control
9 msec corresponding to the second clock means for counting ec
A timer circuit 204 and an AND gate circuit 206 for processing a logical product are provided. The latch circuit 203 and the switching transistor Tr1 allow the overcurrent detection stop means to operate as the latch circuits 205 and 207 and the AND gate circuit 20.
6 and the switching transistor Tr3 constitute switching element cutoff means.

Next, the operation of the embodiment corresponding to the present invention will be described. As shown in FIG. 1 and FIG.
01 is connected to an energizing path for supplying the supply voltage VB to the load 102 with a temperature sensor built-in F as a semiconductor switching element.
The drain D-source S of the ET / QA is connected in series, and the switching control of the FET / QA with a built-in temperature sensor is performed based on the on / off of the switch SW1, thereby supplying the supply voltage VB to the load 102. The basic operation of the semiconductor switching device that is turned off (on / off) is executed.

The operation when a short circuit occurs on the load side and an excessive current flows will be described in detail. First, the general operation will be described. FIG. 3 is an operation waveform diagram for explaining a schematic operation of the present embodiment.

When a short circuit occurs on the load 102 side, the overcurrent detection control section 301 of the semiconductor switching device performs the on / off control of the FET QA with a built-in temperature sensor repeatedly as shown in FIG. As described above, the ON / OFF control of the FET QA with a built-in temperature sensor is an operation in a pinch-off region in which the current supplied from the rated load current (switching operation current) of the FET with a built-in temperature sensor (switching operation current) is increased and saturated.

In the configuration shown in FIG. 2, the overcurrent state control circuit 200 stops the overcurrent detection control section 301 after 1 msec of the repetitive on / off control, and switches the overcurrent supply state to the temperature sensor built-in FET / QA. Hold. If a current sufficiently larger than the overcurrent threshold value flows through the FET / QA with a built-in temperature sensor during a period of 9 msec from this point (elapse of 10 msec from the start of the repeated on / off control) as shown by a solid line in FIG. The overheat protection means performs the overheat cutoff function at the time of a large current, and the temperature sensor built-in FET / QA is controlled to the off state, and this state is maintained.

As shown by the broken line in FIG. 3, the overheat cutoff function does not operate even after 10 msec has elapsed from the start of the repeated on / off control, and the overcurrent conduction state of the temperature sensor built-in FET QA continues. In this case, the switch input of the drive circuit 111 is turned off to turn off the FET QA with a built-in temperature sensor, and this state is maintained.

In the time of 10 msec, when overheating (junction temperature) of the chip of the FET QA with a built-in temperature sensor is transmitted to the stem, transmission of this overheating and internal destruction due to accumulation of thermal stress become a problem. In consideration of the time required for heat to reach from the chip to the stem, which is well known among traders, this is set as the time for performing overheat interruption within a range in which internal destruction does not occur.

Therefore, the temperature sensor built-in FET QA
If an overcurrent flows and the overheat cut-off function does not work until 10 msec elapses after the repeated on / off control is started, the off-control is forcibly performed after 10 msec elapses, and the temperature sensor built-in FET QA The FET QA with a built-in temperature sensor can be turned off before the overheating of the chip that causes internal destruction is transmitted to the stem. As a result, when the thermal stress is accumulated by repeating the overheating when the overcurrent is applied and the cooling when the energization is stopped,
1 The wiring is less likely to slide, and cracking and peeling at the solder joint between the chip and the stem are less likely to occur, and the reliability of the semiconductor switching device is improved.

Next, the operation when an overcurrent occurs will be described with reference to FIGS.
This will be described in detail with reference to FIG. FIG. 4 shows the overcurrent state control circuit 2
6 is a timing chart showing the operation of the control unit 00.

As shown in FIG. 4 (a), when a short circuit occurs on the load 102 side and the power supply path becomes in an overcurrent state, the on / off control of the temperature sensor built-in FET QA is started as described above. . From this point on, the integration circuit 201 integrates a control signal for on / off control (repetition of H level / L level change) to the drive circuit 111, and performs on / off control several times to integrate a predetermined value. After the completion of the integration period (A in FIG. 4A), FIG.
As shown in (b), the integration circuit 201 sets the H level to 1 level.
msec timer circuit 202 and AND gate circuit 206
Output to It should be noted that the integration performed during the period in which the on / off control is performed several times by the integration circuit 201 is 1 m
This is to prevent a malfunction in the sec timer circuit 202.

Next, when an H level is output from the integration circuit 201, the 1 msec timer circuit 202 is activated and counts 1 msec as shown in FIG. 4C. This one
When the msec timer circuit 202 times out, FIG.
As shown in (d), the latch circuit 203 outputs the H level to the switching transistor Tr1. This allows
When the switching transistor Tr1 turns on (conducts),
The inverting input terminal (-) of the comparator CMP1 is grounded. As a result, the output of the comparator CMP1 is held at the H level, and the overcurrent detection of the load 102 based on the FET QB and the resistance element Rr1 is not detected while the temperature sensor built-in FET QA remains on.

At the time when the 1 msec timer circuit 202 times out, as shown in FIG.
The c timer circuit 204 starts and counts 9 msec. During this 9 msec, the operation of the overcurrent detection control unit 301 is stopped, and a large current exceeding the overcurrent threshold continuously flows through the FET QA with a built-in temperature sensor as shown in FIG. During this 9 msec, as shown by the solid line in FIG. 3, a large current flows through the FET / QA with a built-in temperature sensor, and if the temperature of the FET / QA with a built-in temperature sensor exceeds a predetermined value, the overheating protection means The shutoff function is immediately executed, and the temperature sensor built-in FET / QA is controlled to the off state.

When the 9 msec timer circuit 204 times out, a reset signal is output to the latch circuit 203 as shown in FIG.
H level output to 1 is stopped. Furthermore, 9msec
When the timer circuit 204 times out, FIG.
As shown in (g), the latch circuit 205 outputs the H level to the switching transistor Tr2. This allows
When the switching transistor Tr2 is turned on (conducting),
The base of the switching transistor Tr1 is grounded and turned off. As a result, the inverting input terminal (-) of the comparator CMP1 returns to the non-ground state, and the overcurrent detection control unit 3
01 restarts, and the overcurrent of the load 102 is detected. Then, the output of the integrating circuit 201 shown in FIG. 4B and the output of the latch circuit 205 shown in FIG. 4G are ANDed by the AND gate circuit 206 and output to the latch circuit 207. At this point, since both inputs of the AND gate circuit 206 are at the H level, the latch circuit 207 outputs the H level.

When an H level is output from the latch circuit 207 to the switching transistor Tr3 as shown in FIG. 4H, the switching transistor Tr3 is turned on (conducting), and the switch input of the drive circuit 111 is grounded. It becomes zero potential. As a result, the drive current from the drive circuit 111 to the gate of the temperature sensor built-in FET QA is turned off, and the temperature sensor built-in FET QA is turned off. When the temperature sensor built-in FET QA is held in the off state, as shown in FIG. 4 (i), an L level switch switching signal due to the turning off of the switch SW1 shown in FIG. When the signal is input to 207 and reset, the switching transistors Tr2 and Tr3 are turned off, the switch input of the drive circuit 111 is turned off, and the drive circuit 111 is reset to the initial state.

As described above, in this embodiment, when the load side is short-circuited and an overcurrent state is detected, the on / off control of the FET / QA with a built-in temperature sensor for limiting the current is started to start the first predetermined operation. After a lapse of time (1 msec), the overcurrent detection control unit 301 is stopped, the overcurrent is continuously supplied, and the overheat protection function by the overheat protection means is executed, and the FET / QA with a built-in temperature sensor is turned off. Control and hold. Further, the overheat cutoff function does not operate until the second predetermined time (9 msec) elapses after the overcurrent detection control unit 301 is stopped (until 10 msec elapses from the start of the repeated on / off control), and the overcurrent state is changed. If it has continued, after the second predetermined time has elapsed, the temperature sensor FET QA is forcibly controlled to the OFF state and held.

Thus, the temperature sensor built-in F
Before the transmission of overheating that causes internal destruction of ET / QA,
The temperature sensor built-in FET QA can be turned off. As a result, thermal stress due to repetition of overheating and cooling in the switching element does not accumulate much, and overheating cutoff control and overcurrent protection control are performed so that internal destruction due to heat does not occur. , The switching element can be reliably protected, and the reliability of the switching device can be improved.

By configuring the semiconductor switching device as a one-chip switching device 110, the device configuration can be reduced in size, the mounting space can be reduced, and the device cost can be reduced. further,
FET • QB, on the same switching device 110
Since the QC and the FET / QA with a built-in temperature sensor are mounted, power supply voltage fluctuations and temperature drifts occur at the same time,
Since there is no characteristic difference between the semiconductor elements and no variation between production lots occurs, an operation error hardly occurs and a highly accurate and stable operation can be obtained.

In the above-described embodiment, the overcurrent state control circuit 200 shown in FIG. 2 has been described as being mounted in the same package as the semiconductor switching device body. However, the present invention is not limited to this. Instead, the present invention includes a case where the overcurrent state control circuit is configured as an external circuit in the semiconductor switching device shown in FIG.

In the operation of the embodiment, 1 msec
The time such as c, 9 msec, and 10 msec is not particularly limited, and is changed as a design matter. The setting of the L level and the H level is also a matter of design, and is inverted depending on the polarity of the element used.

[0059]

As described above, according to the present invention, the overheat cutoff control and the overcurrent protection control are executed before the internal destruction due to heat inside the switching element, thereby protecting the switching element against overcurrent and high heat. The effect can be obtained reliably, and the reliability as a switching device can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram and a circuit diagram showing a basic configuration according to an embodiment of a semiconductor switching device of the present invention.

FIG. 2 is a block diagram and a circuit diagram showing a configuration of an overcurrent state control circuit which is a main part of the semiconductor switching device according to the embodiment.

FIG. 3 is an operation waveform diagram for explaining a schematic operation of the present embodiment.

FIG. 4 is a timing chart showing an operation of the overcurrent state control circuit of FIG. 2;

FIG. 5 is an operation waveform diagram for explaining overcurrent protection control in a conventional semiconductor switching device.

FIG. 6 is an operation waveform diagram for explaining another overcurrent protection control in the conventional semiconductor switching device.

FIG. 7 is a configuration diagram for describing a problem of internal thermal stress in a power MOS • FET.

[Explanation of symbols]

 Reference Signs List 101 power supply 102 load 110 switching device 111 drive circuit 200 overcurrent state control circuit 201 integration circuit 202 1 msec timer circuit 203, 205, 207 latch circuit 204 9 msec timer circuit 206 AND gate circuit 301 overcurrent detection control section 305 charge pump circuit 306 cutoff Latch circuit CMP1, CMP2 Comparator QA Temperature sensor built-in FET QB, QC FET R1-R5, R10, Rr1, Rr2 Resistance element SW1 Switch Tr1-Tr3 Switching transistor

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 5G004 AA04 BA03 BA04 CA05 DA04 DC01 DC04 DC07 DC12 EA01 5G053 AA01 AA02 BA01 BA04 CA02 EA03 EA09 EB02 EC03 FA05 5J055 AX15 AX32 AX37 AX39 AX44 AX55 CX22 CX22 CX DX54 DX73 EX01 EX02 EX04 EX06 EX11 EX24 EY01 EY03 EY10 EY12 EY13 EY17 EZ01 EZ07 EZ10 EZ25 EZ31 EZ43 EZ55 FX04 FX32 FX33 FX38 GX01 GX02 GX04 GX05

Claims (3)

[Claims] 1. A semiconductor switching element having an overheat cutoff function for turning on / off power supply to a load, and detecting an overcurrent to the load and repeating the semiconductor switching element when an overcurrent state is detected. Overcurrent detection control means for performing on / off control, and after elapse of a first predetermined time from the start of repetitive on / off control by the overcurrent detection control means, the detection of the overcurrent is stopped and the semiconductor switching element When the overcurrent state is maintained without operating the overheat cutoff function of the semiconductor switching element after a second predetermined time has elapsed from the stop of the overcurrent detection, the semiconductor switching element is turned off. A semiconductor switching device, comprising: overcurrent state control means for controlling. 2. The overcurrent state control means, comprising: first timekeeping means for counting the first predetermined time; and stopping overcurrent detection by the overcurrent detection control means when the first timekeeping means finishes timekeeping. An overcurrent detection stop means for holding the on state of the semiconductor switching element, a second time means for measuring the second predetermined time, and a drive control signal to the semiconductor switching element at the end of the time measurement by the second time means. 2. The semiconductor switching device according to claim 1, further comprising a switching element cutoff means for cutting off. 3. The semiconductor switching device according to claim 1, wherein the semiconductor switching element, the overcurrent detection control unit, and the overcurrent state control unit are mounted as a one-chip device.