JP7238710B2 - Gate drives and compound gate drives - Google Patents

Description

The present invention relates to gate drives and composite gate drives.

In recent years, due to the spread of PHVs (Plug-in Hybrid Vehicles) and EVs (Electric Vehicles), there is an increasing need for higher current in electrical systems for driving vehicles. In this case, multiple insulated gate semiconductor devices are used in parallel as semiconductor power devices in order to handle large currents in the power path to the load such as a motor, but the number of parallel connections varies. It is a challenge to realize a configuration of a gate driver that satisfies the desired characteristics while being compatible.

2. Description of the Related Art Conventionally, drive ICs as gate drive devices for driving and controlling a plurality of insulated gate semiconductor devices connected in parallel generally drive two or three semiconductor devices in parallel. This is because the use of four or more semiconductor elements in parallel is a rare case, and it is not cost-effective to manufacture a dedicated driver IC.

For this reason, when more semiconductor elements than can be handled by one driving IC are to be driven in parallel, a configuration using a plurality of driving ICs is adopted. However, although it is possible to turn off the semiconductor elements handled by a single drive IC when an abnormality occurs, the remaining semiconductor elements are left unattended. In addition, there was a problem that the protection operation delay increased.

JP 2014-230307 A

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a gate drive device capable of reliably protecting an insulated gate type semiconductor element when a plurality of gate drive devices are used. and to provide a composite gate drive.

A gate drive device according to claim 1 is a gate drive device for driving a plurality of insulated gate semiconductor elements connected in parallel, wherein the plurality of insulated gate semiconductor elements are driven according to a control signal externally applied. a gate drive circuit (20) for driving gates; and a plurality of abnormality detection terminals respectively connected to current detection terminals provided corresponding to the plurality of insulated gate semiconductor elements, wherein the abnormality detection terminals an anomaly detection circuit (30) for detecting an anomaly state of the plurality of insulated gate semiconductor devices and outputting an anomaly detection signal based on an output signal from the current detection terminal provided via the plurality of anomaly detection terminals; an output circuit ( 40).

By adopting the above configuration, the gate drive circuit drives the gates of some or all of the plurality of insulated gate semiconductor devices in accordance with an externally applied control signal. At this time, when detecting an abnormal state of the insulated gate semiconductor device or an abnormal state occurring in the internal circuit, the abnormality detection circuit outputs an abnormality detection signal. The output circuit outputs an abnormality detection output signal to the outside via an abnormality detection terminal for abnormality detection when the abnormality detection signal is output by the abnormality detection circuit.

By using a plurality of gate driving devices constructed as described above, it is possible to drive a larger number of insulated gate semiconductor devices connected in parallel. Each gate driver is configured to drive as many insulated gate semiconductor elements as can be driven, thereby driving all the insulated gate semiconductor elements.

In this configuration, when an overcurrent flows through any of the insulated gate semiconductor elements or an abnormal state occurs inside any of the gate drive devices, the insulated gate driven and controlled by itself The semiconductor element can be turned off according to an abnormality detection signal output from the abnormality detection circuit and an abnormality detection output signal transmitted from another gate driving device. As a result, even when a plurality of gate drive devices are used for control, all of the insulated gate semiconductor devices can be turned off when an abnormality occurs in one of them.

1 is a configuration diagram of a gate drive device showing a first embodiment; FIG. Configuration diagram of composite gate drive Action diagram A diagram showing an example of a first connection mode A diagram showing an example of a second connection mode A diagram showing a third connection mode example Configuration diagram of a composite gate drive device showing a second embodiment Configuration diagram of a composite gate drive device showing a third embodiment

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS. 1 to 6. FIG.
As shown in FIG. 1, in this embodiment, as a gate drive device 10, a plurality of insulated gate semiconductor devices to be driven in single use are, for example, two IGBTs (Insulated Gate Bipolar Transistors) 1, 2 are connected in parallel with the collector-emitter common. A sense emitter is formed in each of the IGBTs 1 and 2, and gate terminals G1 and G2 and current detection terminals A1 and A2 are provided.

The gate drive device 10 is composed of, for example, an IC (integrated circuit). The gate drive device 10 is configured to drive two IGBTs 1, 2, for example. Note that the number of IGBTs to be driven may be three or more if they have driving capability, and they may be driven by a common output instead of being driven individually.

The gate drive device 10 includes a gate drive circuit 20, an abnormality detection circuit 30 and an output circuit 40 inside. The gate drive circuit 20 comprises a gate-on circuit 21 and a gate-off circuit 22 for driving the two IGBTs 1,2. The gate drive circuit 20 receives a control signal Sc from the outside via an input terminal S1.

The gate drive circuit 20 outputs gate drive signals from the output terminals C1 and C2 to the gate terminals G1 and G2 via the resistors 1b and 2b, respectively, corresponding to the IGBTs 1 and 2 to perform on/off drive control. Further, when the abnormality detection signal is input from the abnormality detection circuit 30, the gate drive circuit 20 drives the IGBTs 1 and 2 off if they are on-driven, and thereafter maintains the off state. Further, if the gate drive circuit 20 does not drive the IGBTs 1 and 2 when the abnormality detection signal is input, the gate drive circuit 20 does not drive the IGBTs 1 and 2 thereafter and maintains the OFF state.

The abnormality detection circuit 30 detects an overcurrent abnormality such as a short circuit or an overcurrent based on the signals output from the current detection terminals A1 and A2 of the IGBTs 1 and 2, and also detects an abnormal state in the internal circuit of the gate drive device 10. outputs an anomaly detection signal. Abnormality detection terminals D1 and D2 of the abnormality detection circuit 30 are connected to current detection terminals A1 and A2 of the IGBTs 1 and 2, respectively. When the abnormality detection circuit 30 detects an abnormality in the IGBT 1 or 2 or detects an abnormality in the internal circuit of the device, the abnormality detection circuit 30 outputs an abnormality detection signal to the gate drive circuit 20 and externally detects the abnormality through the output terminal P1. It outputs the signal Sx.

When the abnormality detection signal is output from the abnormality detection circuit 30, all or a combination of the following three functions (1) to (3) can be performed.

(1) Stop the gate drive function of the gate drive circuit 20 . This is the function of not driving the gates after the gate driving circuit 20 has not driven the gates.
(2) Stop the gate drive by the gate drive circuit 20 to turn off. This is the function of stopping the gate driving and turning off the gate when the gate driving circuit 20 is driving the gate.
(3) A function for outputting an abnormal state.

The output circuit 40 includes an N-channel MOS transistor 41 and a buffer circuit 42 for output. The output circuit 40 has an output terminal commonly connected to the abnormality detection terminal D2. The abnormality detection terminal D2 is configured to be connected to an abnormality detection terminal of another gate drive device to transmit output information.

The MOS transistor 41 has a drain connected to the power supply terminal and a source as an output terminal connected to the abnormality detection terminal D2. The abnormality detection circuit 30 is configured to output an abnormality detection signal also to the output circuit 40 when an abnormality is detected. The buffer circuit 42 outputs a high-level gate signal to the gate of the MOS transistor 41 when receiving the abnormality detection signal from the abnormality detection circuit 30 .

The MOS transistor 41 is in an off state in a normal state, and is in a high impedance state with respect to the abnormality detection terminal D2. Therefore, the abnormality detection terminal D2 is in a state for detecting an overcurrent state or a short circuit state of the IGBT 2, and the abnormality detection circuit 30 detects the abnormality. When the MOS transistor 41 turns on in response to the abnormality detection signal, the level of the abnormality detection terminal D2 is set to the power supply voltage level, that is, the high level state.

Note that the output circuit 40 is not used in the form of using the gate driving device 10 alone as shown in FIG. The gate drive device 10 turns on or off the IGBTs 1 and 2 by the gate drive circuit 20 in response to the input of the control signal Sc from the outside. Further, when the abnormality detection signal is output from the abnormality detection circuit 30, the gate drive circuit 20 turns off the IGBTs 1 and 2 or maintains the off state upon receiving the abnormality detection signal.

On the other hand, when using three or more IGBTs connected in parallel as a plurality of semiconductor elements, drive control can be performed by using a plurality of gate driving devices 10 .

Next, FIG. 2 shows a configuration for driving a semiconductor element section 100 in which three IGBTs 1 to 3 are connected in parallel as a plurality of insulated gate semiconductor elements connected in parallel. In this case, a composite gate drive device 200 is configured using two gate drive devices 10 described above. The two gate drive devices 10A and 10B use ICs of the same configuration connected in parallel.

In FIG. 2, the gate drive of the three IGBTs 1 to 3 of the semiconductor element section 100 is shown without wiring showing the connection configuration, and the sense emitters of the IGBTs 1 to 3 are connected to the abnormality detection circuits 30a and 30b. It shows the form to be used. There are various methods for connecting the gates of the three IGBTs 1 to 3, as will be described later, and any one of them can be selectively used.

The configurations of the gate driving devices 10A and 10B are indicated with suffixes a and b, respectively, with respect to the configurations described with reference to FIG. Further, each terminal of each of the gate driving devices 10A and 10B includes, in order of the gate driving devices 10A and 10B, abnormality detection terminals S1 and S2, abnormality detection output terminals P1 and P2, output terminals C1 to C4, and abnormality detection terminals D1 to D4. and Further, these gate driving devices 10A and 10B are arranged in a high voltage region while being insulated from the outside, and arranged in the same insulating region.

The IGBTs 1 to 3 of the semiconductor element section 100 have their collectors connected in common, and their gates connected to gate terminals G1 to G3, respectively. The emitters of the IGBTs 1-3 are connected in common, and the sense emitters are connected in common to the emitters via current detection resistors 1a-3a, respectively. Common connection points between the sense emitters of the IGBTs 1-3 and the current detection resistors 1a-3a are connected to current detection terminals A1-A3.

Input terminals S1 and S2 of the two gate driving devices 10A and 10B are commonly connected to receive a control signal Sc. The output terminals P1 and P2 output the abnormality detection signals Sx1 and Sx2 of the respective gate driving devices 10A and 10B to the outside. Abnormality detection terminals D1 to D3 are connected to current detection terminals A1 to A3 of the semiconductor element section 100, respectively.

The abnormality detection terminal D4 of the gate drive device 10B is not used for current detection, but here it is connected to the abnormality detection terminal D2 of the gate drive device 10A. As a result, the output terminal of the output circuit 40b of the gate drive device 10B is connected from the fault detection terminal D4 to the fault detection circuit 30a via the fault detection terminal D2 of the gate drive device 10A.

Next, the operation of the above configuration will be described. The composite gate driving device 200 operates as follows when a gate driving control signal Sc is input from the outside. When the control signal Sc is input to the input terminals S1 and S2 of the gate drive devices 10A and 10B, the gate drive circuits 20a and 20b drive the IGBTs 1-3 by one or both of the gate-on circuits 21a and 21b. As a result, the three IGBTs 1-3 are turned on.

Emitter currents of the IGBTs 1 to 3 are detected by abnormality detection circuits 30a and 30b of the gate driving devices 10A and 10B, respectively. When an overcurrent flows through IGBT1 or 2 while IGBT1-3 are on-driven, when the abnormality detection circuit 30a of the gate drive device 10A detects a current exceeding the threshold by the voltage of the resistors 1a and 2a connected to the sense emitter, It determines that an overcurrent has flowed and outputs an abnormality detection signal.

In the gate drive device 10A, in response to the output of the abnormality detection signal from the abnormality detection circuit 30a, the gate OFF circuit 22a of the gate drive circuit 20a is turned off, and the output circuit 40a is output from the abnormality detection circuit 30a. An output signal is output as a high-level voltage signal from the abnormality detection terminal D2 according to the abnormality detection signal.

In the gate drive device 10B, an abnormality detection signal is input from the abnormality detection terminal D4 connected to the abnormality detection terminal D2, and the abnormality detection circuit 30b detects that an overcurrent has flowed in the gate drive device 10A side and an abnormality has occurred. It is recognized and responsively causes the gate off circuit 22b of the gate drive circuit 20b to perform an off operation.

As a result, when an overcurrent flows through one of the IGBTs 1 and 2, which is the target of abnormality detection by the gate drive device 10A, the gate-off circuit 22a of the gate drive circuit 20a is caused to perform an off operation, and the gate is turned off. An abnormality detection signal can be transmitted to the drive device 10B from the output circuit 40a. As a result, the gate-off circuit 22b of the gate drive circuit 20b is also turned off by the gate drive device 10B, and all the IGBTs 1 to 3 can be turned off.

Further, with regard to the cooperative operation by the gate driving devices 10A and 10B as described above, even when an overcurrent flows through the IGBT 3, the gate driving device 10B similarly detects this and outputs the output circuit 40b to the abnormality detection terminal D4. An output signal is transmitted to the gate driving device 10A side via. As a result, all IGBTs 1-3 can be turned off.

Furthermore, not only when an overcurrent flows through one of the IGBTs 1 to 3, but also when an abnormality occurs in the internal circuit of the gate drive device 10A or 10B, when the abnormality detection circuit 30a or 30b detects this, the above-described Similarly, by transmitting an abnormality detection signal to the other gate drive circuit 10B or 10A side, all the IGBTs 1 to 3 can be turned off. In this case, when the IGBTs 1 to 3 are not turned on, the subsequent turn-on operation is stopped instead of the turn-off operation.

Next, with reference to FIG. 3, the relationship between the number of IGBTs, which are insulated gate semiconductor elements connected in parallel as described above, and the number M of gate driving devices 10 required for this will be described. In this case, it is assumed that the gate drive device 10 is provided with the number L of abnormality detection terminals D corresponding to the number of elements that can be detected by the abnormality detection circuit 30 . As described above, when a plurality of gate driving devices 10 are provided, one abnormality detection terminal D connecting the output terminal of the output circuit 40 is commonly connected between the gate driving devices 10, and the IGBT , the current of one IGBT is basically detected so that the detection can be made without mutual interference.

Considering this relationship, the relationship between the number L of the abnormality detection terminals of the gate drive device 10, the number M of the installed gate drive devices 10, and the maximum number N of IGBTs, which are insulated gate semiconductor elements, that can be connected in parallel is as follows. It becomes like Formula (A).
N≦(L−1)×M+1 …(A)

The relationship of the above formula (A) is such that one of the M gate drive devices 10 uses all L fault detection terminals, and the remaining (M-1) gate drive devices 10 use one fault detection terminal. It shows that the maximum number N of the insulated gate semiconductor devices is obtained when (L-1) abnormal detection terminals other than the terminals are used.

The numerical values shown in FIG. 3 are the results of summarizing the above relationship with specific numerical values. Here, cases where the installed number M of the gate drive devices 10 is 2 and 3, and the cases where the number L of the abnormality detection terminals provided in each gate drive device 10 are 2 and 3 are shown. The maximum number N of insulated gate semiconductor devices that can be connected in parallel is not a continuous number. For example, when six devices are provided, the maximum number is seven, and the number of abnormality detection terminals is three. can be dealt with by providing three gate driving devices 10 of .

Next, with reference to FIGS. 4 to 6, the mode of driving the gates of the three parallel-connected IGBTs 1 to 3 forming the semiconductor element section 100 will be described. As shown in FIG. 1, the gate drive device 10 is basically provided with a function of detecting an abnormality corresponding to the two IGBTs 1 and 2 like the abnormality detection terminals D1 and D2. It is assumed to gate drive two IGBTs 1,2.

However, the gate drive capability of the gate drive device 10 is not limited to the two IGBTs 1 and 2, but is dependent on the characteristics, standards, and conditions of use of the insulated gate semiconductor device. It may also be possible to drive

In this case, only one gate drive device 10 can detect an abnormal state for only two of the three IGBTs 1 to 3 because of the two abnormality detection terminals D1 and D2. For example, if the third IGBT 3 does not need to be subjected to abnormality detection, such a usage pattern may be used. A compound gate driver 200 with drivers 10A and 10B is used. 4 to 6, illustration of the current detection resistors 1a to 3a is omitted.

In FIG. 4, the three parallel-connected IGBTs 1 to 3 constituting the semiconductor element section 100 have their respective gates G1 to G3 commonly connected via gate resistors 1b, 2b, and 3b, respectively, and a resistor 1c. are connected in common to the output terminals C1 and C2 of the gate drive circuit 20a of the gate drive device 10A. In this case, as described above, the output terminals C3 and C4 of the gate drive device 10B are not used.

On the other hand, the sense emitters of the three IGBTs 1-3 are connected to current detection terminals A1-A3, and the current detection terminals A1-A3 are connected to abnormality detection terminals D1-D3, respectively. The abnormality detection terminal D2 of the gate drive device 10A is commonly connected to the abnormality detection terminal D4 of the gate drive device 10B.

In this configuration, the three IGBTs 1 to 3 forming the semiconductor element section 100 are collectively gate-driven by the gate drive device 10A, so that the three IGBTs 1 to 3 are driven at the same timing. can be

Next, in the gate drive mode shown in FIG. 5, the gate drive device 10B is also configured to drive the IGBTs 1 to 3 in contrast to the configuration of FIG. That is, the three IGBTs 1 to 3 connected in parallel have the same state in which the respective gates G1 to G3 are commonly connected via gate resistors 1b, 2b, and 3b, respectively. This commonly connected portion is further connected to the output terminals C1 and C2 of the gate driving circuit 20a of the gate driving device 10A via a resistor 1c and to the output terminals C1 and C2 of the gate driving circuit 20b of the gate driving device 10B via a resistor 1d. It is configured to be commonly connected to the output terminals C3 and C4.

On the other hand, the sense emitters of the three IGBTs 1-3 are connected to current detection terminals A1-A3, and the current detection terminals A1-A3 are connected to abnormality detection terminals D1-D3, respectively. The abnormality detection terminal D2 is commonly connected to the abnormality detection terminal D4.

This configuration compensates for the lack of gate drive capability for the three IGBTs 1-3 in the configuration of FIG. In this case, the connection mode is such that priority is given to increasing the driving capability rather than the difference in driving timing that can occur between the two gate driving devices 10A and 10B.

Next, in the mode of gate driving shown in FIG. 6, unlike the connection modes in FIGS. 4 and 5, the IGBTs 1 to 3 are individually driven. That is, the gates G1 and G2 of the IGBTs 1 and 2 are connected to the output terminals C1 and C2 of the gate driving device 10A through gate resistors 1b and 2b, respectively. Also, the gate G3 of the IGBT 3 is connected to the output terminal C3 of the gate driving device 10B through the gate resistor 3b. Here, the output terminal C4 of the gate drive device 10B is not used.

In this connection mode, in driving the three IGBTs 1 to 3, the gates are individually driven. Therefore, there is a possibility that variations in driving timing may occur. is suitable. For example, when changing the level of the current supplied by the semiconductor element section 100, it is possible to drive the number of IGBTs 1 to 3 corresponding to the current capability.

In such a first embodiment, the gate drive device 10 is provided with the output circuit 40, and when the abnormality detection circuit 30 detects an abnormality, an abnormality detection output signal is output to the outside from the abnormality detection terminal through the output circuit 40. and The two gate drive devices 10A and 10B are used to drive and control the three IGBTs 1 to 3 connected in parallel. shared with

As a result, even if an overcurrent flows through one of the IGBTs 1 to 4 or an abnormality occurs, the gate drive devices 10A and 10B transmit an abnormal A detection state can be signaled, which can turn off all IGBTs 1-3.

In addition, while making the configuration simple by adding the output circuit 40 using one of the abnormality detection terminals of the abnormality detection circuit 30, the cooperative operation when an abnormality occurs between the gate drive devices 10A and 10B is made possible. The abnormal state can be notified between the gate drive devices 10A and 10B corresponding to the abnormal state occurring in any one of the IGBTs 1-3.

(Second embodiment)
FIG. 7 shows a second embodiment, and portions different from the first embodiment will be described below. In this embodiment, as shown in FIG. 7, a configuration for driving a semiconductor element section 300 in which five IGBTs 1 to 5 are connected in parallel as a plurality of insulated gate semiconductor elements connected in parallel is shown. ing. In this case, the composite gate drive device 400 uses two gate drive devices 10Aa and 10Bb each having three abnormality detection terminals in contrast to the configuration of FIG.

The configuration of the gate drive devices 10Aa and 10Bb is basically the same as the configuration of the gate drive devices 10A and 10B described in FIG. are shown with the same reference numerals. The gate drive device 10Aa has an input terminal S1, an abnormality detection output terminal P1, output terminals C1 to C3, and abnormality detection terminals D1 to D3. The gate driving device 10Bb has an input terminal S2, an abnormality detection output terminal P2, output terminals C4 to C6, and abnormality detection terminals D4 to D6.

The IGBTs 1 to 5 of the semiconductor element section 300 are connected in parallel in the same manner as in the semiconductor element section 100 shown in FIG. Gates of the IBGTs 1-5 are connected to gate terminals G1-G5, respectively. Sense emitters of the IGBTs 1-5 are connected to current detection terminals A1-A5, respectively. Illustration of the current detection resistor is omitted.

The input terminals S1 and S2 of the two gate driving devices 10Aa and 10Bb are connected in common to receive the control signal Sc. The output terminals P1 and P2 output the abnormality detection signals Sx1 and Sx2 of the respective gate driving devices 10Aa and 10Bb to the outside. Abnormality detection terminals D1 to D5 are connected to current detection terminals A1 to A5 of the semiconductor element section 300, respectively. Although the manner of connection between the output terminals C1 to C6 and the gate terminals G1 to G5 of the semiconductor element portion 300 is omitted here, various manners can be selectively configured similarly to the first embodiment. can.

The abnormality detection terminal D6 of the gate drive device 10Bb is not used for current detection, but here it is connected to the abnormality detection terminal D3 of the gate drive device 10Aa. As a result, the output terminal of the output circuit 40b of the gate driving device 10Bb is connected from the abnormality detecting terminal D6 to the abnormality detecting circuit 30a through the abnormality detecting terminal D3 of the gate driving device 10Aa.

The above configuration corresponds to the case where the number L of the abnormality detection terminals of the gate drive device in FIG. 3 is 3 and the number M of the gate drive devices is 2. corresponds to 5.

Next, the operation of the above configuration will be described. The composite gate driving device 400 operates as follows when a gate driving control signal Sc is input from the outside. When the control signal Sc is input to the input terminals S1 and S2 of the gate drive devices 10Aa and 10Bb, the gate drive circuits 20a and 20b drive the IGBTs 1 to 5 by one or both of the gate-on circuits 21a and 21b.

Emitter currents of the IGBTs 1 to 5 are detected by abnormality detection circuits 30a and 30b of the gate driving devices 10Aa and 10Bb, respectively. When an overcurrent flows through one of the IGBTs 1 to 3 while the IGBTs 1 to 5 are on-driven, the abnormality detection circuit 30a of the gate drive device 10Aa detects a current exceeding the threshold and determines that an overcurrent has flowed. Outputs an anomaly detection signal.

In the gate drive device 10Aa, in response to the output of the abnormality detection signal from the abnormality detection circuit 30a, the gate OFF circuit 22a of the gate drive circuit 20a is turned off, and the output circuit 40a is output from the abnormality detection circuit 30a. An output signal is output from the abnormality detection terminal D3 according to the abnormality detection signal.

In the gate drive device 10Bb, when the abnormality detection signal notified from the abnormality detection terminal D3 is input from the abnormality detection terminal D6, the abnormality detection circuit 30b detects that an overcurrent has flowed in the gate drive device 10A side and an abnormality has occurred. It is recognized and responsively causes the gate off circuit 22b of the gate drive circuit 20b to perform an off operation.

As a result, when an overcurrent flows in any one of the IGBTs 1 to 3, which is the target of abnormality detection by the gate drive device 10Aa, the gate off circuit 22a of the gate drive circuit 20a is caused to perform an off operation, and the gate An abnormality detection signal can be transmitted to the drive device 10B from the output circuit 40a. As a result, the gate-off circuit 22b of the gate drive circuit 20b is also turned off by the gate drive device 10B, and all the IGBTs 1 to 5 can be turned off.

Further, regarding the cooperative operation by the gate driving devices 10Aa and 10Bb as described above, even if an overcurrent flows in either of the IGBTs 4 and 5, the gate driving device 10Bb similarly detects this and outputs the output circuit 40b. , an output signal is transmitted to the gate driving device 10A through the abnormality detection terminal D6. As a result, all IGBTs 1-5 can be turned off.

Furthermore, not only when an overcurrent flows through one of the IGBTs 1 to 5, but also when an abnormality occurs in the internal circuit of the gate drive device 10Aa or 10Bb, if the abnormality detection circuit 30a or 30b detects this, the above-described Similarly, by transmitting an abnormality detection signal to the other gate drive circuit 10Bb or 10Aa side, all the IGBTs 1 to 5 can be turned off. In this case, if the IGBTs 1 to 5 are not turned on, the subsequent turn-on operation is stopped instead of the turn-off operation.
Therefore, according to the second embodiment, it is possible to obtain the same effects as in the case of the composite gate device 200 of the first embodiment.

(Third embodiment)
FIG. 8 shows a third embodiment, and the parts different from the configuration of FIG. 2 of the first embodiment will be described below. In this embodiment, as shown in FIG. 8, a composite gate drive device 500 that drives the semiconductor element section 100 uses gate drive devices 10Ax and 10Bx configured by adding a communication function to the gate drive devices 10A and 10B, respectively. It is configured as follows.

The gate driving devices 10Ax and 10Bx are configured by adding communication circuits 50a and 50b to the gate driving devices 10A and 10B described above, respectively. The gate drive devices 10Ax and 10Bx are provided with corresponding communication terminals T1 and T2. Since the communication circuits 50a and 50b have the same configuration, the configuration of the communication circuit 50a will be described here. The configuration of the communication circuit 50b is obtained by replacing the suffix of the reference numerals in the configuration of the communication circuit 50a with b.

The communication circuit 50a includes a determination circuit 51a, a reception circuit 52a, and an output circuit 53a. The communication circuit 50a is connected to an external communication path CP via a communication terminal T1, and communicates with communication circuits of other gate drive circuits connected to this communication path CP. In this case, the communication circuit 50a outputs the abnormality detection signal output from the abnormality detection circuit 30a to the communication path CP from the output circuit 53a, and receives the abnormality detection signal input from the outside via the communication path CP to the reception circuit 52a. received by

The determination circuit 51a receives the abnormality detection signal from the abnormality detection circuit 30a and also receives the abnormality detection signal from the reception circuit 52a via the communication path CP. The determination circuit 51a outputs an OFF drive signal to the gate drive circuit 20a and the output circuit 53a when the above-described abnormality detection signal is input. The receiving circuit 52a is composed of a comparator, and detects when the level of the signal input from the communication terminal T1 through the communication path CP is equal to or higher than a predetermined level.

The output circuit 53a is composed of an output MOS transistor 54a and a buffer circuit 55a for driving the MOS transistor 54a. The drain of the MOS transistor 54a is connected to the communication terminal T1, and the source is connected to the ground equivalent level. When the output circuit 53a receives the drive signal from the determination circuit 51a, the buffer circuit 55a turns on the MOS transistor 54a. As a result, the communication terminal T1 is switched from the high impedance state to the low level, and is output as a communication signal to the communication path CP.

In the above configuration, the gate drive devices 10Ax and 10Bx are commonly connected to the communication terminals T1 and T2 via the communication path CP, and an abnormality detection signal is exchanged between them. The gates G1 to G3 of the three IGBTs 1 to 3 of the semiconductor element section 100 are connected to the communication terminal T1 through the gate resistors 1b to 3b, respectively, and the OFF circuit 6 and the resistor 7 connected in series. .

The OFF circuit 6 is a circuit in which a series circuit of a diode D and a resistor R, which are connected in the forward direction from the gates G1 to G3, is commonly connected on the resistor R side. The off circuit 6 has a diode function to prevent conduction from the communication path CP side to the gates G1 to G3. Further, when the output circuit 53a of the communication circuit 50a is driven by the determination circuit 51a, the communication terminals T1 and T2 are switched to the ground level, so that the gates of the IGBTs 1 to 3 are lowered to the ground level through the off circuit 6 to perform the off operation. Let

Next, the operation of the above configuration will be described. When the IGBTs 1 to 3 are operating normally, the operation is the same as in the first embodiment, and the operation when an abnormality is detected by the abnormality detection circuit 30a or 30b will be described below.

First, when there is no abnormality such as an overcurrent state or a short circuit state in the IGBTs 1 to 3 and no abnormality in the gate drive devices 10Ax and 10Bx, the communication circuits 50a and 50b are connected to the MOSFETs 54a and 54a of the output circuits 53a and 53b. 54b is kept off, so the communication path CP is kept at a high level.

Emitter currents of the IGBTs 1 to 3 are detected by abnormality detection circuits 30a and 30b of the gate driving devices 10Ax and 10Bx, respectively. If an overcurrent flows through one of the IGBTs 1 and 2 while the IGBTs 1 to 3 are on-driven, the abnormality detection circuit 30a of the gate drive device 10Ax detects a current exceeding the threshold and determines that an overcurrent has flowed. Outputs an anomaly detection signal.

In the gate drive device 10Ax, in response to the output of the abnormality detection signal from the abnormality detection circuit 30a, the gate OFF circuit 22a of the gate drive circuit 20a is turned off, and the output circuit 40a is output from the abnormality detection circuit 30a. An output signal is output from the abnormality detection terminal D3 according to the abnormality detection signal.

In the gate drive device 10Bx, an abnormality detection signal is input from the abnormality detection terminal D4, and the abnormality detection circuit 30b recognizes that an overcurrent has flowed on the side of the gate drive device 10Ax and an abnormality has occurred. The gate-off circuit 22b of the gate drive circuit 20b is caused to perform an off operation.

As a result, all the IGBTs 1-3 are turned off by causing the gate-off circuits 22a and 22b of the gate drive circuits 20a and 20b to turn off.

The abnormality detection signal output from the abnormality detection circuit 30a is also output to the determination circuit 51a of the communication circuit 50. FIG. The determination circuit 51a outputs a drive signal to the output circuit 53a to turn on the MOS transistor 54a. As a result, the drain of the MOS transistor 54a changes to the ground level, that is, to the low level, so that the gates G1 to G3 of the IGBTs 1 to 3 are all set to the low level potential through the off circuit 6, and the IGBTs 1 to 3 are turned off.

Therefore, when an overcurrent flows in any of the IGBTs 1 to 3 and an abnormal state occurs, the abnormal state is detected by the abnormality detection circuits 30a and 30b of the gate drive devices 10Ax and 10Bx, and the abnormality detection state is entered. Correspondingly, the communication circuits 50a and 50b are also operated to cooperate with each other through the communication path CP, so that all the IGBTs 1 to 3 can be turned off.

In such a third embodiment, in addition to the configuration of the first embodiment shown in FIG. It is configured to be connected to the communication path CP via the OFF circuit 6 . As a result, in addition to the effects of the first embodiment, the communication circuits 50a and 50b can also perform the OFF operation corresponding to the abnormality detection.

As a result, even if one of the output circuits 40a and 40b or the communication circuits 50a and 50b has a failure or malfunction, the IGBTs 1 to 3 can be reliably turned off when an abnormality occurs.

(Other embodiments)
The present invention is not limited to the above-described embodiments, and can be applied to various embodiments without departing from the scope of the invention. For example, the following modifications or extensions can be made.

In the above-described embodiments, the case of using IGBTs as insulated gate semiconductor devices has been shown, but MOSFETs can also be used as insulated gate semiconductor devices, and can also be applied to the case of using a mixture of MOSFETs. . Also, the insulated gate semiconductor element can be applied to those using various materials such as silicon, silicon carbide, and gallium nitride.

In the above-described embodiments, the semiconductor element portions 100 and 300 provided with three or five IGBTs as insulated gate semiconductor elements are shown, but the present invention is not limited to this, and by satisfying the relationship shown in FIG. It is also possible to drive a semiconductor element section in which four or more than six insulated gate semiconductor elements are provided.

Further, the mode of driving the IGBTs 1 to 5 constituting the semiconductor element portions 100 and 300 is not limited to the connection modes shown in FIGS. 4 to 6, and other connection modes can be used.
Although the present disclosure has been described with reference to examples, it is understood that the present disclosure is not limited to such examples or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.

In the drawings, 1 to 5 are IGBTs (insulated gate semiconductor devices), 10, 10A, 10B, 10Aa, 10Bb, 10Ax, and 10Bx are gate drive devices, 20, 20a, and 20b are gate drive circuits, and 21, 21a, and 21b are 22, 22a, 22b are gate-off circuits; 30, 30a, 30b are abnormality detection circuits; 40, 40a, 40b are output circuits; 42a, 42b are buffer circuits; 50a, 50b are communication circuits; 100 and 300 are semiconductor element portions, 200, 400 and 500 are composite gate driving devices, and CP is a communication path.

Claims (4)

A gate drive device for driving a plurality of insulated gate semiconductor devices connected in parallel,
a gate drive circuit (20, 20a, 20b) for driving the gates of the plurality of insulated gate semiconductor elements according to a control signal supplied from the outside;
a plurality of abnormality detection terminals respectively connected to current detection terminals provided corresponding to the plurality of insulated gate semiconductor devices, and an output signal from the current detection terminals provided via the abnormality detection terminals; an abnormality detection circuit (30, 30a, 30b) for detecting an abnormal state of the plurality of insulated gate semiconductor elements based on and outputting an abnormality detection signal;
When the abnormality detection signal output from the abnormality detection circuit is input to any one of the plurality of abnormality detection terminals, the abnormality detection signal is externally transmitted via the connected abnormality detection terminal. and an output circuit (40, 40a, 40b) for outputting to. When the abnormality detection signal is output by the abnormality detection circuit, the abnormality detection signal is transmitted to the outside via a communication path (CP), and the abnormality detection signal transmitted from the outside via the communication path is received. 2. The gate drive device according to claim 1, further comprising a communication circuit (50a, 50b) for turning off said plurality of insulated gate semiconductor elements according to said abnormality detection signal. A composite gate drive device for driving a plurality of insulated gate semiconductor devices connected in parallel,
A plurality of gate drive devices (10A, 10B, 10Aa, 10Ax, 10Bx) according to claim 1 or 2, wherein the number of the plurality of abnormality detection terminals is less than the number of the plurality of insulated gate semiconductor devices,
The gate drive circuits (20a, 20b) of the plurality of gate drive devices are provided to drive a part or all of the plurality of insulated gate semiconductor devices,
In the plurality of gate drive devices, among the plurality of abnormality detection terminals provided in the abnormality detection circuits (30a, 30b), at least those to which the output circuit is not connected are the plurality of insulated gate semiconductor elements. a composite gate drive device connected to detect an abnormality of the output circuits (40a, 40b) connected in common. Let the number of the abnormality detection terminals of the gate drive device be L, the number of the gate drive devices be M, and the number of the insulated gate semiconductor elements connected in parallel be N,
The plurality of gate drive devices are configured to connect at most L pieces of the insulated gate semiconductor elements to one, and at most (L−1) pieces to the abnormality detection terminals to which the output circuits of the remaining ones are not connected. When the condition is
4. The composite gate drive device according to claim 3, wherein said L, M, and N satisfy the relationship of formula (A).
N≦(L−1)×M+1 …(A)

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