JP6927239B2 - Gate drive and compound gate drive - Google Patents

Description

The present invention relates to a gate drive device and a composite gate drive device.

In recent years, with the spread of PHVs (Plug-in Hybrid Vehicles) and EVs (Electric Vehicles), there is an increasing need for larger currents in electric systems for driving vehicles. In this case, a form in which a plurality of insulated gate type semiconductor elements are used in parallel as semiconductor power elements is adopted for the energization path to a load such as a motor so as to correspond to a large current.

By the way, as a drive IC as a gate drive device for driving and controlling a plurality of insulated gate type semiconductor elements connected in parallel, conventionally, it is common to drive two to three semiconductor elements in parallel. This is because it is a rare case that four or more semiconductor elements are used in parallel, and it is not worth the cost to manufacture a dedicated drive IC.

Therefore, when the number of semiconductor elements that can be supported by one drive IC is driven in parallel, a configuration using a plurality of drive ICs is adopted. However, the semiconductor element that one drive IC is in charge of can be turned off when an abnormality occurs, but the remaining semiconductor elements are left unattended, so the protection operation for abnormality detection cannot be performed or the accuracy is reduced. There was a problem that the protection operation delay became large.

Japanese Unexamined Patent Publication No. 2014-230307

The present invention has been made in consideration of the above circumstances, and an object of the present invention is a gate drive device capable of reliably protecting an insulated gate type semiconductor element when a plurality of gate drive devices are used. And to provide a composite gate drive device.

The gate driving device according to claim 1 is a gate driving device that drives a part or all of a plurality of insulated gate type semiconductor elements (1 to 6) connected in parallel, and responds to a control signal given from the outside. An abnormal state of at least one of the gate drive circuit (20, 20A, 20B, 20C, 20x) for driving a part or all of the gates of the plurality of insulated gate type semiconductor elements and the insulated gate type semiconductor element and the internal circuit. An abnormality detection circuit (30, 30A, 30B, 30C, 30a) that detects and outputs an abnormality detection signal, and a communication path (CP, CP1, CP2) when the abnormality detection signal is output by the abnormality detection circuit. , CP3) to another gate drive device, receive an abnormality detection signal transmitted from the other gate drive device via the communication path, and the plurality of abnormality detection signals according to any one of the abnormality detection signals. A communication circuit (40, 40A, 40B, 40C) that turns off a part or all of the insulated gate type semiconductor element is provided , and the communication path is in a state of passing a diode (51, 51A, 51B) in the opposite direction. It is connected to the gate of the plurality of insulated gate type semiconductor elements .

By adopting the above configuration, the gate drive circuit drives a part or all of the gates of the plurality of insulated gate type semiconductor elements according to the control signal given from the outside. At this time, the abnormality detection circuit outputs an abnormality detection signal when it detects an abnormal state of the insulated gate type semiconductor element or an abnormal state generated in the internal circuit. When the abnormality detection signal is output by the abnormality detection circuit or the abnormality detection signal is received from the outside via the communication path, the communication circuit turns off a part or all of the plurality of insulated gate type semiconductor elements.

Then, it is possible to drive an insulated gate type semiconductor element in which a larger number of gate driving devices are connected in parallel by using a plurality of gate driving devices configured as described above. Each gate driving device is configured to drive a driveable number of insulated gate semiconductor elements, whereby all insulated gate semiconductor elements can be driven.

In this configuration, if an abnormal state occurs in which an overcurrent flows through one of the insulated gate type semiconductor elements, or if an abnormal state occurs inside one of the gate drive devices, the insulated gate that is self-driven and controlled. The type semiconductor element can be off-driven in response to an abnormality detection signal output from the abnormality detection circuit or an abnormality detection signal transmitted from another gate drive device via a communication path. As a result, even when controlled by a plurality of gate driving devices, all the insulated gate type semiconductor elements can be off-driven when an abnormality occurs in any of them.

Configuration diagram of the gate drive device showing the first embodiment Configuration diagram of compound gate drive device Operation explanatory diagram Explanatory drawing of usage form of insulated gate type semiconductor element Configuration diagram of the composite gate drive device showing the second embodiment Operation explanatory diagram Configuration diagram of the composite gate drive device showing the third embodiment Configuration diagram of the composite gate drive device showing the fourth embodiment Configuration diagram of the composite gate drive device showing the fifth embodiment Configuration diagram of the composite gate drive device showing the sixth embodiment Configuration diagram of the gate drive device showing the seventh embodiment Configuration diagram of compound gate drive device Configuration diagram of the composite gate drive device showing the eighth embodiment Configuration diagram of the composite gate drive device showing the ninth embodiment Configuration diagram of the composite gate drive device showing the tenth embodiment Electrical configuration diagram of a gate drive circuit showing an eleventh embodiment Time chart Explanatory drawing of off drive control pattern and contents Electrical configuration diagram of an abnormality detection circuit showing a twelfth embodiment Operation explanatory diagram Configuration diagram of the composite gate drive device showing the thirteenth embodiment

(First Embodiment)
Hereinafter, the first embodiment of the present invention will be described with reference to FIGS. 1 to 4.
As shown in FIG. 1, in this embodiment, as the gate driving device 10, a plurality of insulated gate type semiconductor elements to be driven in single use include, for example, two IGBTs (Insulated Gate Bipolar Transistors) 1. 2 is configured to be usable in a state where the collector and the emitter are shared and connected in parallel. Further, a sense emitter is formed in each of the IGBTs 1 and 2, and gate terminals G1 and G2 and current detection terminals A1 and A2 are provided.

The gate drive device 10 is arranged in a high pressure region insulated from the outside. The gate drive device 10 is configured to drive two IGBTs 1 and 2, and includes a gate drive circuit 20, an abnormality detection circuit 30, and a communication circuit 40 inside. The gate drive circuit 20 includes a gate-on circuit 21 and a gate-off circuit 22 for driving the two IGBTs 1 and 2. The gate drive circuit 20 receives a control signal Sc from the outside via the input terminal S1.

The gate drive circuit 20 outputs a gate drive signal to the gate terminals G1 and G2 via the output terminals C1 and C2 corresponding to the IGBTs 1 and 2, respectively, and performs on / off drive control. Further, when the abnormality detection signal is input, the gate drive circuit 20 drives the IGBTs 1 and 2 off when the IGBTs 1 and 2 are driven on, and then maintains the off state. Further, when the abnormality detection signal is input, the gate drive circuit 20 keeps the OFF state without driving the IGBTs 1 and 2 thereafter.

The abnormality detection circuit 30 detects an overcurrent abnormality based on the signals output from the current detection terminals A1 and A2 of the IGBTs 1 and 2, and also detects an abnormality state in the internal circuit of the gate drive device 10 and outputs an abnormality detection signal. do. The input terminals D1 and D2 of the abnormality detection circuit 30 are connected to the current detection terminals A1 and A2 of the IGBTs 1 and 2, respectively. When the abnormality detection circuit 30 detects an abnormal state of the IGBT 1 or 2 or detects an abnormality in the internal circuit of the apparatus, the abnormality detection circuit 30 outputs an abnormality detection signal to the gate drive circuit 20 and detects the abnormality to the outside via the output terminal P1. Output the signal Sx.

The communication circuit 40 includes an output circuit 41 and a receiving circuit 42. The communication circuit 40 is connected to an external communication path CP via the communication terminal T1 and communicates with a communication circuit of another gate drive circuit connected to the communication path CP. In this case, the communication circuit 40 outputs the abnormality detection signal output by the abnormality detection circuit 30 from the output circuit 41 to the communication path CP, and receives the abnormality detection signal transmitted from the communication path CP by the reception circuit 42.

The gate driving device 10 described above can be used independently when driving the two IGBTs 1 and 2, and in this case, the communication circuit 40 is not used. When the gate drive device 10 is used alone, the gate drive circuit 20 drives the IGBTs 1 and 2 on or off in response to the input of the control signal Sc from the outside. Further, when the abnormality detection signal is output by the abnormality detection circuit 30, the IGBTs 1 and 2 are driven off or kept in the off state.

On the other hand, when three or more IGBTs are connected in parallel as a plurality of semiconductor elements, drive control can be performed by using a plurality of gate drive devices 10.

FIG. 2 shows a configuration in which a semiconductor element unit 100 in a state where four IGBTs 1 to 4 are connected in parallel is driven as a plurality of insulated gate type semiconductor elements connected in parallel. In this case, a composite gate drive device 200 using two of the above-mentioned gate drive devices 10 is configured. The two gate drive devices 10A and 10B are used by connecting those having the same configuration in parallel.

Each configuration described with reference to FIG. 1 is shown with subscripts A and B in the configurations of the gate drive devices 10A and 10B, respectively. Further, the terminals of the gate drive devices 10A and 10B are the input terminals S1, S2, the abnormality detection output terminals P1, P2, the output terminals C1 to C4, the input terminals D1 to D4, and the communication in the order of the gate drive devices 10A and 10B. The terminals are T1 and T2. Further, these gate driving devices 10A and 10B are arranged in a high pressure region in a state of being insulated from the outside, and are arranged in the same insulating region.

Collectors are commonly connected to each of the IGBTs 1 to 4 of the semiconductor element unit 100, and the gates are connected to the gate terminals G1 to G4, respectively. Further, the emitters of the IGBTs 1 to 4 are commonly connected, and the sense emitters are commonly connected to the emitters via the current detection resistors 1a to 4a, respectively. The common connection points between the sense emitters of the IGBTs 1 to 4 and the current detection resistors 1a to 4a are connected to the current detection terminals A1 to A4.

The input terminals S1 and S2 of the two gate drive devices 10A and 10B are commonly connected, and the control signal Sc is input. The output terminals P1 and P2 output the abnormality detection signals Sx of the respective gate drive devices 10A and 10B to the outside. The output terminals C1 to C4 are connected to the gate terminals G1 to G4 of the semiconductor element unit 100, respectively. The input terminals D1 to D4 are connected to the current detection terminals A1 to A4 of the semiconductor element unit 100, respectively. The communication terminals T1 and T2 of the two gate drive devices 10A and 10B are connected via a communication path CP.

According to the above configuration, the composite gate drive device 200 operates as follows when the control signal Sc for gate drive is input from the outside. When the control signal Sc is input to the input terminals S1 and S2 of the gate drive devices 10A and 10B, the gate drive circuits 20A and 20B drive the IGBTs 1 and 2 by the gate-on circuit 21A, and the IGBTs 3 and 4 are driven by the gate-on circuit 21B. Drive. As a result, the four IGBTs 1 to 4 are turned on.

In each of the IGBTs 1 to 4, the emitter current is detected by the abnormality detection circuits 30A and 30B of the gate drive devices 10A and 10B, respectively. When an overcurrent flows through the IGBTs 1 or 2 while the IGBTs 1 to 4 are being driven on, the abnormality detection circuit 30A of the gate drive device 10A detects a current equal to or higher than the threshold value by the voltage of the resistors 1a and 1b connected to the sense emitter. It determines that an overcurrent has flowed and outputs an abnormality detection signal.

In the gate drive device 10A, the gate-off circuit 22A of the gate drive circuit 20A turns off both IGBTs 1 and 2 in response to the abnormality detection signal output from the abnormality detection circuit 30A, and the output circuit 41A of the communication circuit 40A The abnormality detection signal is output from the communication terminal T1 to the communication path CP.

As a result, in the gate drive device 10B, when the reception circuit 42B of the communication circuit 40B receives the abnormality detection signal from the communication path CP via the communication terminal T2, the abnormality detection circuit 30B responds to the gate drive circuit 20B. The gate-off circuit 22B drives both IGBTs 3 and 4 off.

As a result, when an overcurrent flows through any of the IGBTs 1 and 2 that are the targets of the drive control by the gate drive device 10A, the IGBTs 1 and 2 are turned off and the communication path CP is provided in the gate drive device 10B. An abnormality detection signal can be transmitted via. As a result, the gate drive device 10B can also turn the IGBTs 3 and 4 off.

Further, regarding the cooperative operation by the gate drive devices 10A and 10B as described above, even when an overcurrent flows through the IGBT 3 or 4, the gate drive device 10B detects this and turns off the IGBTs 3 and 4 in the same manner. At the same time, an abnormality detection signal is transmitted to the gate drive device 10A side via the communication path CP. As a result, the IGBTs 1 and 2 can be turned off by the gate drive device 10A.

Further, when an abnormality occurs in the internal circuit of the gate drive device 10A or 10B as well as when an overcurrent flows through any of the IGBTs 1 to 4, the abnormality detection circuit 30A or 30B detects this, as described above. By transmitting the abnormality detection signal to the other gate drive circuit 10B or 10A side in the same manner as in the above, all the IGBTs 1 to 4 can be turned off.

Next, the gate drive device 10 (10A, 10B) configured as described above can be used as a gate-on drive function (first function) by the gate-on circuit 21 of the gate drive circuit 20, as shown in FIG. 3, for example. The gate-off drive function (second function) by the gate-off circuit 22 and the abnormality detection function (third function) by the abnormality detection circuit 30 can be selectively used under various conditions.

In the above-described embodiment, the first condition of using the three functions (first to third functions) of the gate drive device 10 is supported. The second to fourth conditions use the anomaly detection function, which is the third function, but do not use the second function, do not use the first function, or do not use both the first and second functions. There is. The fifth to seventh conditions do not use the third function, and are conditions in which the first and second functions are used together, the second function is not used, or the first function is not used.

Of the above conditions, the first and fifth conditions have a large on-off drive capability, the second and sixth conditions have a large on-drive capability, and the third and seventh conditions have a large off-drive capability. Further, the fourth condition can eliminate the drive variation between the gate drive devices that are driven in parallel. Further, since the first condition to the fourth condition can perform abnormality detection for all semiconductor elements, accurate control can be performed, and the fifth to seventh conditions simplify the abnormality detection circuit. Can be done.

Further, in the above-described embodiment, the IGBTs 1 to 4 are used as the insulated gate type semiconductor element, but in this case, the MOSFET can be used as the insulated gate type semiconductor element, and the material for forming the element can be used. A SiC element (silicon carbide element) can be used in addition to the Si element (silicon element).

For example, although the SiC element is currently expensive, it has a merit that the loss becomes small when it is used in a small current region, so that it is also an effective usage mode to use it in combination with the Si element. FIG. 4 shows a combination of a Si element and a SiC element in a form in which two or more insulated gate type semiconductor elements are connected in parallel and used.

In FIG. 4, conditions 1 and 2 show a case where only the Si element or only the SiC element is used in two or more. Conditions 3 to 6 use one SiC element and use one, two, three, four or more Si elements to obtain a total of two, three, four, five or more elements. The conditions for parallel drive are shown. Conditions 7 to 10 use two SiC elements and use one, two, three, four or more Si elements to obtain a total of three, four, five, six or more elements. The conditions for parallel drive are shown.

In the above configuration, combination conditions such as when MOSFET is used, IGBT is used, and mixed is used as the insulated gate type semiconductor element are possible, and two or more insulated gate type semiconductor elements are connected in parallel. It can be applied to various usage patterns.

In such a first embodiment, the gate drive device 10 is provided with a communication circuit 40, and when the abnormality detection circuit 30 detects an abnormality, the output circuit 41 outputs an abnormality detection signal to the communication path CP to generate the communication path CP. An abnormality detection signal is received by the receiving circuit 42 via the receiving circuit 42. Then, using the two gate drive devices 10A and 10B, two of the four IGBTs 1 to 4 connected in parallel are shared for drive control.

As a result, even if an overcurrent flows through any of the IGBTs 1 to 4, or even if an abnormality occurs, the gate drive devices 10A and 10B can receive the state by the communication circuits 40A and 40B, so that all the IGBTs 1 to 4 can receive the state. 4 can be turned off.

Further, even if the two gate drive devices 10A and 10B are arranged in a high-voltage region insulated from the outside, the communication path CP is connected between them for communication, so that the two gate drive devices 10A and 10B communicate through the same insulation region. It is possible to communicate with each other. As a result, communication can be performed between the gate drive devices 10A and 10B without adding an isolated communication means or the like, and high-speed communication can be performed with a configuration that suppresses cost increase.

In the above embodiment, the gate drive device 10 is configured to drive and control two IGBTs 1, 2 (3, 4), but is configured to drive and control three insulated gate gate type semiconductor elements. It can also be. In this case, in the case of a configuration in which four or more insulated gate gate type semiconductor elements are connected in parallel, the same effect as described above can be obtained by using two or more gate driving devices.

(Second Embodiment)
5 and 6 show the second embodiment, and the parts different from the first embodiment will be described below. In this embodiment, the composite gate drive device 201 is used as a state in which the communication path CP connecting the communication terminals T1 and T2 of the two gate drive devices 10A and 10B is pulled up to the DC power supply DC. be.

As shown in FIG. 5, the communication path CP is connected to the DC power supply DC as a fixed potential via a pull-up resistor 50 as a resistance element. Further, in the communication circuits 40A and 40B of the gate drive devices 10A and 10B, the output circuits 41A and 41B and the reception circuits 42A and 42B are configured as follows. Hereinafter, since the communication circuits 40A and 40B have the same circuit configuration, the communication circuit 40A will be described as a representative.

The output circuit 41A of the communication circuit 40A is mainly composed of an N-channel type MOSFET 43 and a drive circuit 44 as switching elements. The drain of the MOSFET 43 is connected to the communication terminal T1, and the source is connected to the ground side. A drive signal is given to the gate of the MOSFET 43 from the drive circuit 44.

In the OFF state of the MSOFET 43, the drain is in the open state, and in this state, the communication terminal T1 is in a high level state pulled up to the DC power supply DC. In the output circuit 41A, the MOSFET 43 is in the off state when no abnormality has occurred. Then, when the abnormality detection signal is output from the abnormality detection circuit 30A, the drive circuit 44 outputs the drive signal to the gate of the MOSFET 43 to turn it on. As a result, the drain of the MOSFET 43 becomes low level, and the communication path CP becomes low level via the communication terminal T1.

The receiving circuit 42A of the communication circuit 40A is mainly composed of the comparator 45. The inverting input terminal of the comparator 45 is connected to the communication terminal T1, and the non-inverting input terminal is given a determination threshold voltage. The comparator 45 outputs a high-level abnormality detection signal when the communication terminal T1 becomes low-level.

The operation of the above configuration will be described with reference to FIG. In this description, the operations of the communication circuits 40A and 40B will be mainly described. Similar to the first embodiment, in the state where the four IGBTs 1 to 4 are driven by the gate driving devices 10A and 10B, and no abnormality is detected, the MOSFET 43 of the output circuit 41A is in the off state. , The drain of the MOSFET 43 is in the open state.

As a result, as shown in the first stage of FIG. 6, the communication path CP is in a high level state pulled up by the DC power supply DC, which corresponds to a normal state in which no abnormality has occurred. Further, in this normal state, since the communication terminal T1 of the receiving circuit 42A is at a high level, the comparator 45 is in a low level output state, that is, a state in which an abnormality is not detected.

In this state, for example, when an overcurrent flows through the IGBTs 1 or 2, or when an abnormality occurs in the internal circuit of the gate drive device 10A, the abnormality detection circuit 30A detects this and outputs an abnormality detection signal. In response to this, the gate-off circuit 22A turns both IGBTs 1 and 2 off.

Further, since the abnormality detection signal is output, as shown in the second stage of FIG. 6, in the output circuit 41A of the communication circuit 40A, the MOSFET 43 is turned on and the communication terminal T1 is inverted to a low level. In this state, the communication path CP becomes low level, and the abnormality detection signal is transmitted.

On the other hand, in the gate drive device 10B, since the communication terminal T2 becomes a low level via the communication path CP, the input level of the receiving circuit 42B becomes Low as shown in the third stage of FIG. 6, and the comparator 45 Will output a high level anomaly detection signal. As a result, similarly to the above, the gate-off circuit 22B turns the IGBTs 3 and 4 off.

The above operation is abnormal through the communication path CP, except that the gate drive circuits 10A and 10B are exchanged even when an overcurrent flows through the IGBT 3 or 4 or an abnormality occurs in the internal circuit of the gate drive device 10B. Since the detection signal is sent and received, the same operation is executed and all the IGBTs 1 to 4 are turned off.

Therefore, even with such a second embodiment, the same effect as that of the first embodiment can be obtained. Further, since the communication path CP is pulled up and the output circuits 41A and 41B use the N-channel type MSOFET 43, the MOSFET 43 is turned on at the time of abnormality detection to lower the communication path CP as an abnormality detection signal. Can be set.

(Third Embodiment)
FIG. 7 shows a third embodiment, and in this embodiment, the configuration in the case of driving the semiconductor element unit 101 in a state where three IGBTs 1 to 3 are connected in parallel is shown. A composite gate drive device 202 using the two gate drive devices 10A and 10B described above is configured.

The two gate drive devices 10A and 10B are wired so as to be on-drive and off-drive in common to the three IGBTs 1 to 3 by the gate drive circuits 20A and 20B. Here, the output terminals of the two gate-on circuits 21A and 21B are both connected from the terminals Ca and Cc to the gates G1 to G3 of the three IGBTs 1 to 3 via the connection circuit 60. Similarly, the output terminals of the two gate-off circuits 22A and 22B are both connected from the terminals Cb and Cd to the gates G1 to G3 of the three IGBTs 1 to 3 via the connection circuit 60.

In this embodiment, in the gate drive device 10A, the output terminals C1 and C2 provided corresponding to the two insulated gate type semiconductor elements are the output terminals Ca in which the on-output of the gate-on circuit 21A is integrated. The output terminal Cb is integrated with the off output of the gate-off circuit 22A. Similarly, in the gate drive device 10B, the output terminals C3 and C4 provided corresponding to the two insulated gate type semiconductor elements are output terminals Cc in which the on-output of the gate-on circuit 21B is integrated, and the gate is off. The output terminal Cd that integrates the off output of the circuit 22B is used.

The connection circuit 60 is connected from the output terminal Ca to the gates G1 to G3 of the IGBTs 1 to 3 via the gate resistors 6a to 6c, respectively, and from the output terminal Cb to the gates of the IGBTs 1 to 3 via the gate resistors 7a to 7c, respectively. It is connected to G1 to G3. Further, the connection circuit 60 is connected from the output terminal Cc to the gates G1 to G3 of the IGBTs 1 to 3 via the gate resistors 8a to 8c, respectively, and from the output terminal Cd via the gate resistors 9a to 9c to the IGBTs 1 to 3 respectively. It is connected to the gates G1 to G3 of.

The gate resistors 6a to 6c and 8a to 8c used in the connection circuit 60 are provided in a state where the resistance values are adjusted so as to become a predetermined gate resistance when all three IGBTs 1 to 3 are turned on. ing.

Further, the current detection terminals A1 and A2 of the semiconductor element unit 101 are connected to the input terminals D1 and D2 of the gate drive device 10A, respectively, and the current detection terminal A3 is connected to the input terminal D3 of the gate drive device 10B. The input terminal D4 of the gate drive device 10B is unused.

According to the above configuration, when two gate drive devices 10A and 10B are used in parallel, all the IGBTs 1 are used even if their characteristics vary as compared with the case where the IGBTs 1 to 3 are individually driven. Since the gate resistance is set to be a predetermined value when ~ 3 is turned on, current imbalance is unlikely to occur, and it is possible to eliminate the deviation of the ON timing of the IGBTs 1 to 3. As a result, the balance of the currents flowing through the three IGBTs 1 to 3 is improved.

In the above configuration, the off operation is also performed by connecting the gate off circuits 22A and 22B of the two gate drive devices 10A and 10B in common so that the off operation can be performed at the same time. Can also be configured to individually turn off the IGBTs 1-3.

According to the third embodiment, the plurality of gate drive devices 10A and 10B are connected via the connection circuit 60 so as to drive all the IGBTs 1 to 3 at the same time, so that stable parallel drive can be achieved. can do. Further, when an abnormality occurs, an abnormality detection signal can be sent and received through the communication path CP in the same manner as described above, so that all the IGBTs 1 to 3 can be turned off.

(Fourth Embodiment)
FIG. 8 shows the fourth embodiment, and the parts different from the first embodiment will be described below. In this embodiment, the function of driving the gate off in the event of an abnormality is configured to also serve as the output circuit 41 of the communication circuit 40.

That is, in FIG. 8, the composite gate drive device 203 drives and controls the four IGBTs 1 to 4 constituting the semiconductor element unit 100 by the two gate drive devices 10A and 10B. In this case, the gate drive devices 10A and 10B are connected to the gates G1 to G4 of the IGBTs 1 to 4 from the output terminals C1 to C4 via the gate resistors 71 to 74, respectively.

Each connection point between the output terminals C1 to C4 and the gate resistors 71 to 74 is commonly connected to the communication path CP via the off circuit 51 and the resistor 52 in series. The off circuit 51 is a circuit in which a series circuit of the diode D and the resistor R connected in the forward direction from each output terminal C1 to C4 side is connected in common on the resistor R side, and is from the communication path CP side to the gates G1 to G4. It has a diode function to prevent the continuity of the circuit.

The gate drive devices 10A and 10B are newly provided with gate voltage detection circuits 80A and 80B, respectively, and the communication circuits 40A and 40B are provided with a determination unit 46. The gate voltage detection circuit 80A monitors the gate voltages of the two IGBTs 1 and 2 by the output terminals C1 and C2, and outputs the detected voltage to the determination unit 46 of the communication circuit 40A. Similarly, the gate voltage detection circuit 80B monitors the gate voltages of the two IGBTs 3 and 4 by the output terminals C3 and C4, and outputs the detected voltage to the determination unit 46 of the communication circuit 40B.

Each determination unit 46 of the communication circuits 40A and 40B receives an abnormality detection signal from the abnormality detection circuits 30A and 30B, respectively, and also inputs an abnormality detection signal input from the reception circuits 42A and 42B via the communication path CP. NS. Further, in this embodiment, the determination unit 46 receives a gate voltage detection signal from the gate voltage detection circuits 80A and 80B. When the above-mentioned abnormality detection signal or gate voltage abnormality occurs, the determination unit 46 outputs an off drive signal to the output circuits 41A and 41B to turn on the MOSFET 43.

Next, the operation of the above configuration will be described. In the same manner as described above, when the control signal Sc is input from the input terminals S1 and S2, in the gate drive circuits 20A and 20B, a high-level drive signal is transmitted from the output terminals C1 to C4 to the gates G1 to G4 of the IGBTs 1 to 4. Output. As a result, the IGBTs 1 to 4 are turned on, and the communication path CP is held in a high level state via the off circuit 51.

Further, in this state, when the operations of the IGBTs 1 to 4 and the gate driving devices 10A and 10B are not abnormal, the communication circuits 40A and 40B hold the MOSFET43 of the output circuits 41A and 41B in the off state. Therefore, the communication path CP is maintained at a high level.

Then, in this state, when the abnormality detection signal is output by the abnormality detection circuit 30A or 30B, the determination unit 46 of the communication circuit 40A or 40B outputs the signal to output the abnormality detection signal to the output circuit 41A or 41B. do. In the output circuit 41A or 41B, the MOSFET 43 is turned on based on the signal given to the drive circuit 44.

As a result, the drain of the MOSFET 43 changes to the ground level, that is, the low level, so that the gates G1 to G4 of the IGBTs 1 to 4 all have low level potentials through the off circuit 51, and the IGBTs 1 to 4 are turned off. As a result, the on-drive signals output from the gate drive circuits 20A and 20B via the output terminals C1 to C4 are invalidated.

When the abnormality detection signal is output in the abnormality detection circuit 30A or 30B, the determination unit 46 also outputs a signal indicating that an abnormality has occurred in the gate drive circuit 20A or 20B, and the gate-on circuit 21A And 21B stop the high-level drive signal output from the output terminals C1 to C4, and output the off drive signal by the gate-off circuits 22A and 22B.

According to the fourth embodiment, since the gates G1 to G4 of the IGBTs 1 to 4 are connected to the communication path CP via the off circuit 51, the abnormality detection signal is output in the abnormality detection circuit 30A or 30B. When this is done, the output circuits 41A and 41B invert the communication path CP to a low level, so that all the IGBTs 1 to 4 can be quickly turned off via the off circuit 51.

(Fifth Embodiment)
FIG. 9 shows the fifth embodiment, and the parts different from the fourth embodiment will be described below. In the two gate drive devices 10A and 10B constituting the composite gate drive device 204, gate-on circuits 21A and 21B are provided as the configurations of the gate drive circuits 20A and 20B, and the gate-off circuits 22A and 22B are omitted. be.

The gate drive circuits 20A and 20B also have a gate-off function by the output circuits 41A and 41B of the communication circuits 40A and 40B. In the fourth embodiment, the gate-off operation of the IGBTs 1 to 4 in the normal operation is carried out by the gate-off circuit 22A or 22B, but in this embodiment, the off-drive is always carried out by the output circuits 41A and 41B in the communication path CP and the off circuit. A low-level signal is given to the gates G1 to G4 of the IGBTs 1 to 4 via the 51 to operate the gates G1 to 4 off.
Therefore, even with such a fifth embodiment, the same effect as that of the fourth embodiment can be obtained.

(Sixth Embodiment)
FIG. 10 shows a sixth embodiment, and the parts of the composite gate drive device 205 different from those of the second embodiment will be described below. In the second embodiment, the communication path CP is pulled up by the DC power supply DC, whereas in this embodiment, it is not necessary to use an external pull-up power supply, and the inside of the gate drive devices 10A and 10B is used. It is configured to have a power supply for pull-up.

Each of the gate drive devices 10A and 10B is configured to include a voltage source circuit 47 as a power source for pull-up in the communication circuits 40A and 40B. The voltage source circuit 47 is connected to the drain of the MOSFET 43 of the output circuits 41A and 41B. Further, the voltage source circuit 47 has a configuration in which a current limiting circuit 47a is provided in the power feeding path so as to secure a low level when the MOSFET 43 is on.

Further, the voltage source circuit 47 is stabilized by interposing a resistor 53 in series in the communication path CP. Further, in order to stabilize the voltage source circuit 47, the communication terminals T1 and T2 are connected to the ground in series with a resistor 54 and a capacitor 55, respectively. The capacitor 55 functions as a stabilizing capacitance. The resistor 54 connected in series with the capacitor 55 may be omitted.

By adopting the above configuration, when the abnormal state is not detected by the gate drive devices 10A and 10B, that is, when the MOSFET 43 of the output circuits 41A and 41B is off, the communication path CP is set to a high level by the voltage source circuit 47. It is pulled up to the state of. Here, the capacitor 55 connected to the communication path CP is in a state of being charged to the voltage of the voltage source circuit 47. Further, even if there is a slight deviation in the output voltage of each voltage source circuit 47 of the gate drive devices 10A and 10B, the resistor 53 keeps the current in a state where no current flows.

Then, when an overcurrent flows through any of the IGBTs 1 to 4 or an abnormality occurs in any of the gate drive devices 10A and 10B, the abnormality detection circuit 30A or 30B detects this and outputs an abnormality detection signal. As a result, in the determination unit 46 of the communication circuit 40A or 40B, the output circuit 41A or 41B drives the MOSFET 43 on via the drive circuit 44. As a result, the drain of the MOSFET 43 is inverted to the low level, so that the charge of the capacitor 55 is discharged and the communication path CP becomes the low level.
Therefore, the same effect as that of the second embodiment can be obtained by such a sixth embodiment.

(7th Embodiment)
11 and 12 show the seventh embodiment, and the parts different from the third embodiment will be described below. In this embodiment, instead of the switching element unit 101 used in the third embodiment, the semiconductor element unit 100 having a configuration in which four IGBTs 1 to 4 are connected in parallel is used. Further, in this embodiment, the gate drive devices 10A and 10B provided with the voltage source circuit 47 used in the sixth embodiment are applied.

That is, in FIG. 11 showing the gate drive device 10A, the gate drive device 10A) is provided with the voltage source circuit 47 in the communication circuit 40A, respectively, as in the configuration shown in FIG. Further, the voltage source circuit 47 is provided with a current limiting circuit 47a. The gate drive device 10B is similarly configured.

As shown in FIG. 12, the two gate drive devices 10A and 10B are wired so that the gate drive circuits 20A and 20B commonly drive the four IGBTs 1 to 4 on and off. Here, the output terminals of the two gate-on circuits 21A and 21B are both connected to the gates G1 to G4 of the four IGBTs 1 to 4 from the terminals Ca and Cc via the connection circuit 61. Similarly, the output terminals of the two gate-off circuits 22A and 22B are both connected to the gates G1 to G4 of the four IGBTs 1 to 4 from the terminals Cb and Cd via the connection circuit 61.

In this embodiment, in the gate drive device 10A, the output terminals C1 and C2 provided corresponding to the two insulated gate type semiconductor elements are the output terminals Ca in which the on-output of the gate-on circuit 21A is integrated. The output terminal Cb is integrated with the off output of the gate-off circuit 22A. Similarly, in the gate drive device 10B, the output terminals C3 and C4 provided corresponding to the two insulated gate type semiconductor elements are output terminals Cc in which the on-output of the gate-on circuit 21B is integrated, and the gate is off. The output terminal Cd that integrates the off output of the circuit 22B is used.

The connection circuit 61 is connected to the gates G1 to G4 of the IGBTs 1 to 4 from the output terminals Ca via the gate resistors 6a to 6d, respectively, and the gates of the IGBTs 1 to 4 via the gate resistors 7a to 7d from the output terminals Cb, respectively. It is connected to G1 to G4. Further, the connection circuit 61 is connected from the output terminal Cc to the gates G1 to G4 of the IGBTs 1 to 4 via the gate resistors 8a to 8d, respectively, and from the output terminal Cd via the gate resistors 9a to 9d to the IGBTs 1 to 4 respectively. It is connected to the gates G1 to G4 of.

The gate resistors 6a to 6d, 7a to 7d, 8a to 8d, and 9a to 9d used in the connection circuit 61 are set to become predetermined gate resistors when all four IGBTs 1 to 4 are turned on. ing. Further, the current detection terminals A1 and A2 of the semiconductor element unit 100 are connected to the input terminals D1 and D2 of the gate drive device 10A, respectively, and the current detection terminals A3 and A4 are connected to the input terminals D3 and D4 of the gate drive device 10B, respectively. Be connected.

As in the sixth embodiment, resistors 53, 54, capacitors 55, and the like are connected to the communication path CP connected between the communication terminals T1-T2 of the gate drive devices 10A and 10B. Further, in this embodiment, the function of driving the gate off at the time of abnormality is configured to also use the output circuits 41A and 41B of the communication circuits 40A and 40B.

The gate terminals G1 to G4 of the four IGBTs 1 to 4 are connected to the communication terminal T1 via the off circuit 51A and connected to the communication terminal T2 via the off circuit 51B. In the off-circuits 51A and 51B described above, similarly to the off-circuit 51, a series circuit of the diode D and the resistor R connected in the forward direction from the gate terminals G1 to G4 side is commonly connected on the resistor R side. It is a circuit.

According to the above configuration, four IGBTs 1 to 4 are collectively driven by each of the two gate drive devices 10A and 10B, so that all the IGBTs 1 to 4 are turned on even if there are variations in their characteristics. By setting the gate resistance to be a predetermined value at that time, current imbalance is less likely to occur, and it is possible to eliminate the deviation of the on-timing of the IGBTs 1 to 4. As a result, the balance of the currents flowing through the four IGBTs 1 to 4 is improved.

Further, the communication path CP can be pulled up by the voltage source circuits 47 of the gate drive devices 10A and 10B, and it is not necessary to use a power source for pulling up by an external power source.

Further, when an overcurrent flows through any of the IGBTs 1 to 4 or an abnormality occurs in any of the gate drive devices 10A and 10B, the abnormality detection circuit 30A or 30B detects this and outputs an abnormality detection signal. As a result, in the determination unit 46 of the communication circuit 40A or 40B, the output circuit 41A or 41B drives the MOSFET 43 on via the drive circuit 44. As a result, the drain of the MOSFET 43 is inverted to the low level, so that the charge of the capacitor 55 is discharged and the communication path CP becomes the low level. As a result, all the IGBTs 1 to 4 can be quickly turned off by either the off circuit 51A or 51B.

(8th Embodiment)
FIG. 13 shows the eighth embodiment, and the parts different from the first embodiment will be described below. In this embodiment, an effective usage mode is provided in a case where, for example, two gate drive devices 10A and 10B are used as the composite gate drive device 207 to drive and control a semiconductor element unit 101 in which three IGBTs 1 to 3 are connected in parallel. Is what you do.

As described above, each of the gate driving devices 10A and 10B has a configuration capable of independently driving two insulated gate type semiconductor elements and detecting an abnormality. In this case, when the three IGBTs 1 to 3 are driven by using the two gate driving devices 10A and 10B, a surplus terminal is generated as a driving capacity.

In this embodiment, as the configuration of the gate drive devices 10A and 10B, among the surplus terminals generated as described above, the abnormality detection circuits 30A and 30B are provided with configurations that can be used for other purposes. The abnormality detection circuit 30A (30B) is provided with comparators 31 and 32 for determining an abnormality such as an overcurrent corresponding to the input terminals D1 and D2 (D3, D4).

Of the two comparators 31 and 32, the unused terminal detection circuit 33 is connected in parallel to the comparator 32 in which a signal is input from the input terminal D2 (D4) which may be a surplus terminal. The unused terminal detection circuit 33 detects, for example, when the input terminal D2 (D4) is pulled up to the DC power supply DC, and outputs a detection signal to the gate drive circuit 20A (20B). It is a configuration to be performed. The gate drive circuit 20A (20B) is configured to stop supplying power to the comparator 32 when a detection signal is input from the unused terminal detection circuit 33.

By adopting the above configuration, when the input terminal D4 of the gate drive device 10B is not used and is not connected, if it is pulled up to the DC power supply DC, the unused terminal detection circuit 33 of the abnormality detection circuit 30B will be used. This is detected. As a result, the unused comparator 32 is stopped from being fed by the gate drive circuit 20B, so that wasteful standby power can be avoided.

According to the eighth embodiment as described above, the unused terminal detection circuits 33 are provided in the abnormality detection circuits 30A and 30B. As a result, when the semiconductor element section 101 is driven and controlled, when the input terminals D2 and D4 are in an unused state in the gate drive devices 10A and 10B, the power supply to the comparator 32 is stopped by pulling them up. This can save power.

In the above embodiment, the surplus terminals in the abnormality detection circuits 30A and 30B have been described in the case where the power supply of the corresponding circuit is stopped to save power, but the present invention is not limited to this and can be used for other purposes.

For example, unused terminals can be positively used for the following purposes.
(1) The surplus terminals such as the input terminals D2 and D4 to the abnormality detection circuit are used as reception-only terminals.
(2) The surplus terminals such as the output terminals C2 and C4 for driving the gate are used as drivers for other functions.
(3) The control signal input terminal Sc is used for speed transmission signal transmission and the like.
(4) Although not shown in the embodiment, the surplus terminals of the terminals provided for temperature detection are used for measuring the substrate temperature of the semiconductor element portion, measuring the sense current, measuring the gate voltage, and the like.

(9th Embodiment)
FIG. 14 shows a ninth embodiment, and the parts different from the first embodiment will be described below. In this embodiment, in a configuration in which two gate drive devices 10A and 10B are used as the composite gate drive device 208, the power supply is stopped when the IGBTs 1 to 4 are turned off when an abnormality is detected. There is.

Each of the gate drive devices 10A and 10B is provided with relay switches 90A and 90B as energization control switches in the power supply path. The relay switches 90A and 90B are normally closed contacts, are always in the on state, and change to the off state when an off command signal is given to the control terminal. The control terminal of the relay switch 90A is connected to the communication terminal T2 of the gate drive device 10B via the communication path CP2. Further, the control terminal of the relay switch 90B is connected to the communication terminal T1 of the gate drive device 10A via the communication path CP1. In this embodiment, the communication circuits 40A and 40B use only the output circuits 41A and 41B, and do not use the reception circuits 42A and 42B.

According to the above configuration, the IGBTs 1 to 4 are driven and controlled by the gate drive devices 10A and 10B, and when an overcurrent flows in any of the IGBTs 1 to 4, or an abnormality occurs in any of the gate drive devices 10A and 10B, The abnormality detection circuit 30A or 30B detects this and outputs an abnormality detection signal.

For example, when the abnormality detection circuit 30A of the gate drive device 10A detects an abnormality, the IGBTs 1 and 2 that the gate drive device 10A controls are turned off, and the output circuit 41A of the communication circuit 40A via the communication path CP1. The relay switch 90B is turned off. As a result, when the drive power supply of the gate drive device 10B is turned off, the IGBTs 3 and 4 that have been driven on are automatically turned off.

On the other hand, when the abnormality detection circuit 30B of the gate drive device 10B detects an abnormality, the IGBTs 3 and 4 that the gate drive device 10B controls are turned off, and the output circuit 41B of the communication circuit 40B via the communication path CP2. The relay switch 90A is turned off. As a result, the gate drive device 10A automatically turns off the IGBTs 1 and 2 that have been driven on when the drive power supply is turned off.
Therefore, the same effect as that of the first embodiment can be obtained by such a ninth embodiment.

In the above embodiment, since the receiving circuits 42A and 42B of the communication circuits 40A and 40B are not substantially functioning, the power supply can be stopped to save power.

(10th Embodiment)
FIG. 15 shows the tenth embodiment, and the parts different from the first embodiment will be described below. In this embodiment, the composite gate drive device 209 adopts a configuration in which one of the two gate drive devices 10A and 10B is used as the master gate drive device 10A and the other is used as the slave gate drive device 10B. ..

That is, for example, the master gate drive device 10A drives and controls the IGBTs 1 and 2 and the slave gate drive device 10B drives and controls the IGBTs 3 and 4 with respect to the semiconductor element unit 100 in which four IGBTs 1 to 4 are connected in parallel. .. On the other hand, the master gate drive device 10A detects the overcurrents of the IGBTs 1 and 2, but the slave gate drive device 10B does not detect the overcurrents of the IGBTs 3 and 4. Therefore, the master gate drive device 10A does not use the reception circuit 42A of the communication circuit 40A.

Since the reception circuit 42A of the master gate drive device 10A and the abnormality detection circuit 30B and the output circuit 41B of the slave gate drive device 10B are unused, power can be saved by stopping their functions.

According to the above configuration, the overcurrents of IGBTs 1 and 2 are detected on the master gate drive device 10A side, and when an overcurrent flows through any of these, the slave gate drive device via the communication path CP. By transmitting the abnormality detection signal to 10B, all the IGBTs 1 to 4 can be turned off.

In this usage mode, it is suitable when IGBTs 1 and 2 are mainly used among the four IGBTs 1 to 4, and IGBTs 3 and 4 are used as auxiliary. For example, IGBTs 1 and 2 are selectively used normally, and IGBTs 3 or 4 are additionally used when the current level to be energized is large.

(11th Embodiment)
16 to 18 show the eleventh embodiment, and the parts different from the first embodiment will be described below. In this embodiment, the gate-off circuit 22x is provided as the gate drive circuit 20x. In this embodiment, the gate-on circuit 21 and the gate-off circuit 22x are provided corresponding to the connected IGBTs 1 and 2, respectively.

FIG. 16 shows the configuration of the gate-off circuit 22x corresponding to the output terminal C1 for driving the gate of the IGBT 1 in the configuration of the gate drive circuit 20x. The gate-off circuit 22x corresponding to the output terminal C2 has the same configuration. The gate-off circuit 22x is configured to include two systems of off-circuits 22a and 22b. The first off circuit 22a includes a driving MOS transistor 25a driver 26a and an off resistor 27a, and the second off circuit 22b includes a driving MOS transistor 25b, a driver 26b, and an off resistor 27b.

The control unit 28 is configured to select and drive one of the first and second off circuits 22a and 22b by a signal given from another circuit. Here, the off resistors 27a and 27b used for the first off circuit 22a and the second off circuit 22b are set to different resistance values Ra and Rb, respectively, and the gate voltage fall speed at the time of off operation is different. Is set.

Since the gate current differs due to the difference in the resistance values of the off resistors 27a and 27b, different gate voltage time change rates dv / dt1 and dv / dt2 are set. When the gate voltage time change rate dv / dt is large, the gate voltage fall speed becomes high, and when the gate voltage time change rate dv / dt is small, the gate voltage fall speed becomes slow. The smaller the resistance values of the off resistors 27a and 27b, the faster the gate voltage of the IGBT 1 can be turned off at the faster gate voltage fall rate.

As a result, for example, when the IGBT 1 is operated in the normal off operation, the first off circuit 22a is operated by the control unit 28, and when the IGBT 1 is turned off at a gate voltage fall speed faster than the normal off operation, the operation is performed. The second off circuit 22b can be operated.

This is effective when an abnormal state is detected and an off operation is attempted at a gate voltage fall speed faster than the normal off operation. For example, the IGBT can be turned off by quickly operating the off operation. This is a case where the current flow is controlled so as to be as short as possible.

FIG. 17 is a time chart showing the time change of the signal of each part when the above-mentioned gate voltage fall speed is set to be different. In the time chart of FIG. 17, four IGBTs 1 to 4 are shown in the case of a configuration corresponding to a composite gate drive device 200 driven by two gate drive devices 10A and 10B. Further, the gate drive devices 10A and 10B are connected so as to individually drive two IGBTs on and off.

In the above configuration, first, as shown in FIG. 17 (a), when the on control signal Sc is given at time t0, as shown in FIGS. 17 (b) and 17 (c), the gate-on circuit of the gate drive circuit 20 The gate voltage Vg1 to Vg4 is applied from the output terminals C1 to C4 to the gates of the IGBTs 1 to 4 by the 21.

As a result, as shown in FIGS. 17 (d) to 17 (f), the currents I1 to I4 flowing through the IGBTs 1 to 4 gradually increase. Then, when the control signal Sc is turned off at the time t1 when the predetermined time elapses, the control unit 28 of the gate-off circuit 22x gives an instruction signal to the first off circuit 22a to turn off the IGBT 1 at a normal gate voltage fall speed. Make it work. Similarly, the other IGBTs 2 to 3 are also turned off at the normal gate voltage drop speed.

Next, the operation when an abnormality occurs in the IGBT 1 will be described. When the on control signal Sc is given at time t2 in the same manner as above, the gate voltage Vg1 to Vg4 is similarly applied to the gates of the output terminals C1 to C4 to the IGBTs 1 to 4 by the gate-on circuit 21 of the gate drive circuit 20. It is applied.

As a result, as shown in FIGS. 17 (d) to 17 (f), the currents I1 to I4 flowing through the IGBTs 1 to 4 gradually increase. At this time, when a current I1 of the IGBT 1 is larger than that of the other IGBTs 2 to 3 flows with the passage of time, the abnormality detection circuit 30 detects that the threshold current Is has been exceeded, as shown in FIG. 17 (h). , The abnormality detection signal Sx1 is output.

In the gate-off circuit 22x, as shown in FIG. 17B, the control unit 28 causes the second off-circuit 22b to turn off the two IGBTs 1 and 2 at a slow gate voltage fall speed in response to the abnormality detection signal Sx1. .. On the other hand, in response to the abnormality detection signal Sx1, the communication circuit 40 outputs an abnormal state from the communication terminal T1 to another gate drive device 10 via the communication path CP, as shown in FIG. 17 (g).

When the other gate drive device 10 receives this, similarly, in the gate-off circuit 22x, as shown in FIG. 17 (c), the control unit 28 receives the abnormality detection signal Sx1 detected by the communication circuit 40. The two IGBTs 3 and 4 are operated off from the 2 off circuit 22b at a slow gate voltage fall speed.

Contrary to the above setting, when the off resistors 27a and 27b used for the first off circuit 22a and the second off circuit 22b are set to different resistance values Ra and Rb, the off operation is different from the above. It is also possible to set the gate voltage fall speed to be the opposite condition. For example, when the IGBT 1 is normally turned off, the control unit 28 operates the first off circuit 22a, and when the IGBT 1 is turned off at a gate voltage fall speed slower than the normal off operation, the second off is performed. The circuit 22b can be operated.

This is effective when an abnormal state is detected and an attempt is made to perform an off operation at a gate voltage fall speed slower than the normal off operation. For example, the off operation is performed at a normal gate voltage fall speed. When operating, a surge voltage is generated to damage the IGBT, and this can be prevented by a slow gate voltage falling speed.

FIG. 18 shows as an off-drive control pattern when various settings are made for how to set the gate voltage fall speed when an abnormal state is detected as described above. The content of the control operation shows the operation when the abnormal state is not detected and the operation when the abnormal state is detected. In the case of the abnormal state detection, the self controls when the compound gate drive device is configured. The operation of the gate drive device that detects the abnormal state of the IGBT and the operation of the gate drive device that has not detected the abnormal state are divided.

First, as the basic pattern, in any of the above cases, the one performed at the normal gate voltage falling speed is shown. Then, the first to third patterns can be set so that the gate voltage falls at different speeds. In either case, when the abnormal state is not detected, it is assumed that the vehicle is driven off at the "normal" gate voltage fall speed.

The first pattern shows a pattern in which both gate drive devices are off-driven at a slow or fast gate voltage fall speed when an abnormal state is detected. In the second pattern, when an abnormal state is detected, the gate drive device on the side where the abnormal state is detected is driven off at a slow or fast gate voltage fall speed, and the gate drive device in which the abnormal state is not detected is normally turned off. The driving pattern is shown.

Further, in the third pattern, contrary to the second pattern, when an abnormal state is detected, the gate drive device on the side where the abnormal state is detected performs a normal off drive, and the gate drive device in which the abnormal state is not detected is performed. Shows a pattern of off-driving at a slow or fast gate voltage fall rate.

According to the eleventh embodiment, when any of the currents of the IGBTs 1 to 4 becomes an overcurrent state, the abnormality detection circuit 30 detects the current, and the abnormality detection signal Sx is output. NS. When an abnormality of the IGBT that it is driving is detected, when the gate-off circuit 22x receives the abnormality detection signal Sx, the control unit 28 drives the second off circuit 22b to drive the IGBT at a slow gate voltage fall speed. Can be turned off.

Further, when the signal of the abnormal state is received via the communication circuit 40, when the gate-off circuit 22x receives the abnormality detection signal Sx, the control unit 28 drives the second off circuit 22b to drive the IGBT at a slow gate voltage fall speed. It can be operated off.
As a result, even when an abnormal state occurs, all the IGBTs 1 to 4 can be quickly turned off, which can contribute to suppressing damage or destruction.

In the above embodiment, the gate-off circuit 22x is provided with two systems of the first off circuit 22a and the second off circuit 22b, but an off circuit of three or more systems may be provided.

In this case, in addition to the normal off drive, one or more gate-off circuits that drive off at a slow gate voltage fall speed and one or more gate-off circuits that drive off at a fast gate voltage fall speed are provided. , A control pattern that selectively drives off according to an abnormal state can be provided.

(12th Embodiment)
19 and 20 show the twelfth embodiment, and the parts different from the first embodiment will be described below. In this embodiment, the abnormality detection circuit 30a shows a specific configuration capable of detecting various abnormal states. Here, the case where the IGBT 1 is targeted as the element to be connected will be described.

The abnormality detection circuit 30a in this embodiment includes (A) element overcurrent detection, (B) element short circuit detection, (C) element overheat detection, (D) half-on detection when on, and (E) half-on detection when off. It is possible to detect abnormal states of (F) power supply undervoltage detection, (G) power supply overvoltage detection, and (H) device overheat detection.

As shown in FIG. 19, in (A) element overcurrent detection and (B) element short circuit detection, the current flowing from the sense emitter of the IGBT 1 to the sense resistor 1a is detected from the terminal voltage. The terminal voltage of the sense resistor 1a input to the terminal D1a is compared with the threshold voltage Vth1 by the comparator 34a to detect the element overcurrent state, and the comparator 34b is compared with the threshold voltage Vth2 to detect the element short-circuit state.

As shown in FIG. 20 (a), the current after the IGBT 1 is driven on is normally in a state of flowing without exceeding the threshold current Is1 level of the overcurrent, but when the overcurrent flows, the threshold current flows. It will exceed the Is1 level. The comparator 34a detects the element overcurrent state by the threshold voltage Vth1 corresponding to the threshold current Is1.

Further, the current after the IGBT 1 is driven on will exceed the threshold current Is2 level for short-circuit detection when the current rapidly increases and flows due to the short-circuit state. The comparator 34b detects the element short-circuit state by the threshold voltage Vth2 corresponding to the threshold current Is2.

(C) As shown in FIG. 19, the element overheat detection is detected by providing a diode 1b for temperature detection in the vicinity of the IGBT 1 of the semiconductor element unit 102. A constant current is passed from the DC power supply VD to the diode 1b via the constant current circuit 35a, the diode 35b, and the terminal D1b, and the terminal voltage is detected by the comparator 34c in comparison with the threshold voltage Vth3. Since the forward voltage Vf of the diode 1b has a temperature dependence, the forward voltage Vf for determining the superheat state is compared with the terminal voltage detected as the threshold voltage Vth3 for determination.

As shown in FIG. 20B, the forward voltage Vf of the diode 1b becomes smaller than the diode characteristic as the temperature of the element increases. Further, since this forward voltage Vf is a function of temperature, a threshold voltage Vth3 corresponding to a temperature indicating a superheated state is set, and if it is lower than this, it can be determined that the superheated state is present.

(D) The half-on detection at the time of on is configured to take in the gate voltage Vg of the IGBT 1 into the comparator 34d and compare it with the threshold voltage Vth4, as shown in FIG. As shown in FIG. 20 (c), a state in which the gate voltage Vg of the IGBT 1 exceeds the threshold voltage Vth4 and does not reach a predetermined gate voltage Vg after being driven on is detected as half-on at the time of on.

(E) As shown in FIG. 19, the half-on detection at the time of off is configured to take in the gate voltage Vg of the IGBT 1 into the comparator 34e and compare it with the threshold voltage Vth5. As shown in FIG. 20D, a state in which the gate voltage Vg of the IGBT 1 drops below the threshold voltage Vth5 after the off drive and does not reach the ground level is detected as half-on at the time of off.

The (F) power supply undervoltage detection and (G) power supply overvoltage detection detect a state in which the gate drive circuit 10 deviates from the lower limit or the upper limit of the range of the power supply voltage in which the gate drive circuit 10 can operate normally. In the power supply voltage reduction detection, the DC power supply VD is taken into the comparator 34f and compared with the threshold voltage Vth6 for determination. In the power supply overvoltage detection, the DC power supply VD is taken into the comparator 34g and compared with the threshold voltage Vth7 for determination.

As shown in FIG. 20 (e), if the voltage of the DC power supply VD is in the range of the threshold voltage Vth6 to Vth7, it is in the normal state, and if it is lower than the threshold voltage Vth6, the reduced voltage state is determined and the threshold den pressure Vth7 is exceeded. And judge the overvoltage state.

(H) The device overheat detection detects the overheated state in the gate drive device 10, and the overheat detection unit 36 installed in the device determines the overheated state of the gate drive device 10 and outputs an abnormality detection signal. ..

According to such a twelfth embodiment, as the abnormality detection circuit 30a, (A) element overcurrent detection, (B) element short circuit detection, (C) element overheating detection, (D) half-on detection when on, (E) ) Half-on detection when off, (F) power supply undervoltage detection, (G) power supply overvoltage detection, and (H) device overheat detection are configured to detect abnormal states. , It is possible to correspond to the protection operation in response to various abnormal states of the DC power supply VD to be supplied with power.

In the above embodiment, the configurations for detecting various abnormal states of (A) to (H) are shown, but in addition to the configurations for detecting all the abnormal states described, the abnormalities of (A) to (H) are detected. It is also possible to have a configuration in which a part of the state detection is detected. Further, it is possible to add a configuration for detecting an abnormal state or other abnormal state of the semiconductor element to be driven, the DC power supply VD to be fed, or the like, which is not described in the above embodiment.

(13th Embodiment)
FIG. 21 shows a thirteenth embodiment, and a part different from the composite gate driving device shown in the first embodiment will be described below.

FIG. 21 shows a configuration in which the semiconductor element unit 103 in a state where six IGBTs 1 to 6 are connected in parallel is driven as a plurality of insulated gate type semiconductor elements connected in parallel. In this case, a composite gate drive device 210 using three of the above-mentioned gate drive devices 10 is configured. The three gate drive devices 10A to 10C are used by connecting those having the same configuration in parallel.

Each configuration described with reference to FIG. 1 of the first embodiment is indicated by subscripts A to C in the configurations of the gate drive devices 10A to 10C, respectively. Further, the terminals of the gate drive devices 10A to 10C are the input terminals S1 to S3, the abnormality detection output terminals P1 to P3, the output terminals C1 to C6, the input terminals D1 to D6, and the communication in the order of the gate drive devices 10A to 10C. The terminals are T1 to T3. Further, these gate driving devices 10A to 10C are arranged in a high pressure region in a state of being insulated from the outside, and are arranged in the same insulating region.

Collectors are commonly connected to each of the IGBTs 1 to 6 of the semiconductor element unit 103, and the gates are connected to the gate terminals G1 to G6, respectively. Further, the emitters of the IGBTs 1 to 6 are commonly connected, and the sense emitters are commonly connected to the emitters via the current detection resistors 1a to 6a, respectively. The common connection point between the sense emitters of the IGBTs 1 to 6 and the current detection resistors 1a to 6a is connected to the current detection terminals A1 to A6.

The input terminals S1 to S3 of the three gate drive devices 10A to 10C are commonly connected, and the control signal Sc is input. The output terminals P1 to P3 output the abnormality detection signal Sx of the respective gate drive devices 10A to 10C to the outside. The output terminals C1 to C6 are connected to the gate terminals G1 to G6 of the semiconductor element unit 103, respectively. The input terminals D1 to D6 are connected to the current detection terminals A1 to A6 of the semiconductor element unit 103, respectively. The communication terminals T1 to T3 of the three gate drive devices 10A to 10C are connected via a communication path CP.

Even with the above configuration, the same operation as that of the first embodiment can be performed except that the three gate drive devices 10A to 10C are provided. As a result, the six IGBTs 1 to 6 are turned on and off. Further, if an overcurrent flows through, for example, the IGBTs 1 or 2 while the IGBTs 1 to 6 are being driven on, it is determined that the abnormality detection circuit 30A overcurrent of the gate drive device 10A has flowed, and an abnormality detection signal is output.

The gate drive device 10A turns off both the IGBTs 1 and 2 and outputs an abnormality detection signal from the communication circuit 40A to the communication path CP. When the other gate drive devices 10B and 10C receive the abnormality detection signal from the communication path CP via the communication terminals T2 and T3, the IGBTs 3 to 6 are driven off.

Regarding the cooperative operation by the gate drive devices 10A to 10C as described above, even when an overcurrent flows through any of the IGBTs 3 to 6, the gate drive device 10B or 10C detects this and operates off. At the same time, an abnormality detection signal is transmitted to other of the gate drive devices 10A to 10C via the communication path CP. As a result, all the IGBTs 1 to 6 can be turned off.

Therefore, even with such a thirteenth embodiment, the same effect as that of the first embodiment can be obtained.
In the above embodiment, the configuration in which three gate drive devices 10A to 10C are provided as the composite gate drive device is shown, but the configuration is applied to a configuration in which four or more gate drive devices are provided to drive more IGBTs. You can also do it.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and can be applied to various embodiments without departing from the gist thereof. For example, the present invention can be modified or extended as follows.

In each of the above embodiments, a configuration in which two IGBTs are driven by one gate driving device is shown, but the present invention is not limited to this, and a configuration in which three or more IGBTs are driven may be used. Similarly, although the case where two gate drive devices are used as the composite gate drive device is shown, the case where three or more gate drive devices are used can also be applied.

In each of the above embodiments, an example of a configuration in which three or four IGBTs are driven as the semiconductor element unit is shown, but it can also be applied when a MOSFET is used in addition to the IGBT, or when a mixed one is used. Can also be applied. Further, the insulated gate type semiconductor element can be applied to those using various materials such as those made of silicon, silicon carbide, and gallium nitride.

Although the present disclosure has been described in accordance with the examples, it is understood that the present disclosure is not limited to the examples and structures. The present disclosure also includes various modifications and modifications within a uniform range. In addition, various combinations and forms, as well as other combinations and forms that include only one element, more, or less, are also within the scope of the present disclosure.

In the drawings, 1 to 6 are IGBTs (insulated gate type semiconductor elements), 10, 10A, 10B, and 10C are gate drive devices (master gate drive device, slave gate drive device), 20, 20A, 20B, 20C, 20x. Is a gate drive circuit, 21, 21A, 21B, 12C are gate-on circuits, 22, 22A, 22B, 22C, 22x are gate-off circuits, 22a is a first gate-off circuit, 22b is a second gate-off circuit, 30, 30A, 30B. , 30C, 30a are abnormality detection circuits, 31 are unused terminal detection circuits, 40, 40A, 40B, 40C are communication circuits, 41, 41A, 41B, 41C are output circuits, 42, 42A, 42B, 42C are reception circuits. 43 is an N-channel MOSFET (switching element), 45 is a comparator, 46 is a judgment unit, 47 is a voltage source circuit, 47a is a current limiting circuit, 50 is a pull-up resistor (resistance element), 51 is an off circuit, 80A, 80B is a gate voltage detection circuit, 90A and 90B are relay switches (energization control switches), 100, 101, 102 and 103 are semiconductor element units, 200 to 210 are composite gate drive devices, and CP, CP1, CP2 and CP3 are communication paths. Is.

Claims (15)

A gate drive device that drives a part or all of a plurality of insulated gate type semiconductor elements (1 to 6) connected in parallel.
A gate drive circuit (20, 20A, 20B, 20C, 20x) that drives a part or all of the gates of the plurality of insulated gate type semiconductor elements according to a control signal given from the outside, and
Anomaly detection circuits (30, 30A, 30B, 30C, 30a) that detect an abnormal state of at least one of the insulated gate type semiconductor element and the internal circuit and output an abnormality detection signal.
When the abnormality detection signal is output by the abnormality detection circuit, it is transmitted to another gate drive device via a communication path (CP, CP1, CP2, CP3), and the other gate drive device passes through the communication path. With a communication circuit (40, 40A, 40B, 40C) that receives the abnormality detection signal transmitted and operates a part or all of the plurality of insulated gate type semiconductor elements in response to any of the abnormality detection signals. equipped with a,
The communication path is a gate drive device connected to the gates of the plurality of insulated gate type semiconductor elements with diodes (51, 51A, 51B) interposed in the opposite direction. The gate drive device according to claim 1, wherein the gate drive circuit is configured so that all of the plurality of insulated gate type semiconductor elements can be driven in a gate-on operation or a gate-off operation in common with other gate drive devices. The gate drive device according to claim 1 or 2 , wherein the communication circuit operates a part or all of the plurality of insulated gate type semiconductor elements off in response to the abnormality detection signal via the communication path. The communication circuit includes a voltage source circuit (46) that pulls up the communication path to a high potential.
The gate drive device according to claim 1, wherein the voltage source circuit includes a current limiting circuit (46a) inside. When the number of the plurality of insulated gate type semiconductor elements that detect an abnormality is small compared to the number of input terminals provided corresponding to the abnormality detection circuit, the surplus of the input terminals can be used for other purposes. The gate drive device according to any one of claims 1 to 4 , which is provided so as to be able to be used in the above. The invention according to any one of claims 1 to 5 , wherein the plurality of insulated gate type semiconductor elements use one or both of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an IGBT (Isolated Gate Bipolar Transistor). Gate drive device. Claim that the plurality of insulated gate type semiconductor elements are formed of any one of Si (silicon), SiC (silicon carbide) and GaN (gallium nitride), and one or more of them are used. The gate drive device according to 6. When the abnormality detection circuit detects an abnormal state of at least one of the insulated gate type semiconductor element or the internal circuit, the gate-off operation is performed when the abnormal state is not detected in the gate drive circuit (20x). The gate drive device according to claim 1, wherein a part or all of the plurality of insulated gate type semiconductor elements is operated off at a gate voltage drop-off speed different from the gate voltage fall-off speed. The abnormality detection circuit (30a) includes abnormal states of the insulated gate type semiconductor element such as short circuit, overcurrent, and overheating of the insulated gate type semiconductor element, and half-on state abnormalities at the time of gate-on and gate-off of the insulated gate type semiconductor element. Detects all or part of the abnormal state of the insulated gate type semiconductor element or the inside of the device, the abnormal state of the overvoltage or devoltage of the power supply that supplies power to the inside of the device, and the abnormal state caused by the overheating inside the device. The gate drive device according to any one of claims 1 to 8 , wherein the gate drive device is configured to be the same. It is a composite gate driving device that drives a plurality of insulated gate type semiconductor elements (1 to 6) connected in parallel.
A plurality of gate drive devices (10A, 10B, 10C) according to any one of claims 1 to 9 are provided.
The plurality of gate drive devices are composite gate drive devices provided so as to drive a part or all of the plurality of insulated gate type semiconductor elements, respectively. The communication circuits (40A, 40B, 40C) of the plurality of gate drive devices are connected so as to turn off all of the plurality of insulated gate type semiconductor elements based on the abnormality detection signal output from any of them. The composite gate driving device according to claim 10. The plurality of gate drive devices include energization control switches (90A, 90B) interposed in series with the power supply path, respectively.
When the abnormality detection circuit outputs the abnormality detection signal in one of the plurality of gate drive devices, the communication circuit is provided in the other gate drive devices via the communication path. The composite gate drive device according to claim 10 , wherein the energization control switch is turned off to cut off the power. One of the plurality of gate drive devices is set as the master gate drive device (10A), and the other gate drive device is set as the slave gate drive device (10B).
The composite gate drive device according to claim 10 , wherein the slave gate drive device is used in a state where the operation of the abnormality detection circuit is stopped. Of the plurality of gate drive devices,
The gate drive device in which the abnormality detection circuit detects the abnormal state of the insulated gate type semiconductor element turns off the insulated gate type semiconductor element at a gate voltage fall rate different from the gate off operation when the abnormal state is not detected. To work,
The gate drive device in which the abnormality detection circuit does not detect the abnormal state of the insulated gate type semiconductor element turns off the insulated gate type semiconductor element at the same gate voltage fall rate as the gate off operation when the abnormal state is not detected. The composite gate driving device according to any one of claims 10 to 13 to be operated. Of the plurality of gate drive devices,
The gate drive device in which the abnormality detection circuit detects the abnormal state of the insulated gate type semiconductor element turns off the insulated gate type semiconductor element at the same gate voltage drop-off speed as the gate off operation when the abnormal state is not detected. To work,
The gate drive device in which the abnormality detection circuit does not detect the abnormal state of the insulated gate type semiconductor element turns off the insulated gate type semiconductor element at a gate voltage fall rate different from the gate off operation when the abnormal state is not detected. The composite gate driving device according to any one of claims 10 to 13 to be operated.

Images