JP2007287820A5 - - Google Patents
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- JP2007287820A5 JP2007287820A5 JP2006111661A JP2006111661A JP2007287820A5 JP 2007287820 A5 JP2007287820 A5 JP 2007287820A5 JP 2006111661 A JP2006111661 A JP 2006111661A JP 2006111661 A JP2006111661 A JP 2006111661A JP 2007287820 A5 JP2007287820 A5 JP 2007287820A5
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- 239000004065 semiconductor Substances 0.000 claims 23
- 239000000463 material Substances 0.000 claims 18
- 239000000758 substrate Substances 0.000 claims 18
- 239000004020 conductor Substances 0.000 claims 9
- 238000007789 sealing Methods 0.000 claims 9
- 229910000679 solder Inorganic materials 0.000 claims 8
- 239000011347 resin Substances 0.000 claims 5
- 229920005989 resin Polymers 0.000 claims 5
- 238000004519 manufacturing process Methods 0.000 claims 4
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 230000000875 corresponding Effects 0.000 claims 2
- 238000005755 formation reaction Methods 0.000 claims 2
- 238000004806 packaging method and process Methods 0.000 claims 1
- 230000000149 penetrating Effects 0.000 claims 1
Claims (24)
第１面、及び前記第１面とは反対側の第２面を有し、前記第１面が前記第１基材の前記第１主面と向かい合う状態で、前記第１基材に固定された枠体と、
第２主面、及び前記第２主面とは反対側の第２裏面を有し、前記第２主面が前記枠体の前記第２面と向かい合う状態で、前記枠体に固定された第２基材と、
第３主面、前記第３主面に形成された電極パッド、及び前記第３主面とは反対側の第３裏面を有し、前記第１基材の前記第１主面上に搭載された第１半導体チップと、
前記第１基材の前記第１主面、前記枠体、及び前記第２基材を封止する樹脂封止体と、
を含み、
前記第１半導体チップは、前記第１基材、前記枠体、及び前記第２基材で囲まれる領域内に位置するように、前記第１基材の前記第１主面上に搭載されていることを特徴とする電子装置。 A first base material having a first main surface and a first back surface opposite to the first main surface;
First surface, and have a second surface opposite to the first surface, in a state where the first surface faces the first major surface of the first substrate is fixed to the first substrate a frame body was,
Second main surface, and a second back surface opposite the second major surface, a second major surface in a state facing the second surface of the frame, fixed to the frame Two substrates ,
A third main surface, an electrode pad formed on the third main surface, and a third back surface opposite to the third main surface, are mounted on the first main surface of the first base material. A first semiconductor chip;
A resin sealing body for sealing the first main surface of the first base material, the frame body , and the second base material ;
Including
The first semiconductor chip is mounted on the first main surface of the first base so as to be located in a region surrounded by the first base, the frame, and the second base. electronic device characterized by there.
前記第１半導体チップは、パッケージングされており、かつ前記第１基材に半田材によって実装されていることを特徴とする電子装置。 The electronic device according to claim 1,
The electronic device, wherein the first semiconductor chip is packaged and mounted on the first base material with a solder material.
前記第２基材には、第２半導体チップがパッケージングされた第２半導体装置が搭載されており、
前記第２半導体装置は、前記第１半導体チップと平面的に重なって配置されていることを特徴とする電子装置。 The electronic device according to claim 2 .
A second semiconductor device in which a second semiconductor chip is packaged is mounted on the second base material,
Before Stories second semiconductor device, the electronic apparatus characterized by being arranged to overlap the first semiconductor chip in plan view.
前記第１基材には、前記第１基材の前記第１主面から前記第１裏面に亘って貫通し、前記第１基材、前記枠体、及び前記第２基材で囲まれる領域と連結する通気孔が設けられていることを特徴とする電子装置。 The electronic device according to claim 1,
The first base material penetrates from the first main surface of the first base material to the first back surface , and is surrounded by the first base material, the frame body, and the second base material. An electronic device characterized in that a vent hole is provided for connection with the electronic device.
前記第１基材は、前記枠体で囲まれた領域を覆うように、前記枠体の前記第１面に固定され、
前記第２基材は、前記枠体で囲まれた領域を覆うように、前記枠体の前記第２面に固定されていることを特徴とする電子装置。 The electronic device according to claim 1,
Said first substrate so as to cover the region surrounded by the frame, is secured to the first surface of the frame body,
The second substrate so as to cover the region surrounded by the frame member, an electronic device characterized by being fixed to the second surface of the frame body.
前記第１基材は、前記第２基材の平面サイズよりも大きい平面サイズで形成され、
前記樹脂封止体は、前記枠体の外壁面及び前記第２基材の裏面を覆うように、前記第１基材の前記第１主面上に形成されていることを特徴とする電子装置。 The electronic device according to claim 1,
The first substrate is formed with a plane size larger than the plane size of the second substrate ,
The resin sealing body so as to cover the outer wall surface and the back surface of the second base material of the frame body, the electronic apparatus characterized by being formed on the first substrate of the first main surface .
前記第１半導体チップをパッケージングする第１半導体装置は、複数の第１外部接続用端子を有し、
前記第２半導体チップをパッケージングする前記第２半導体装置は、複数の第２外部接続用端子を有し、
前記第１基材は、前記第１基材の前記第１主面に前記複数の第１の外部接続用端子に対応して配置された複数の第１電極パッドを有し、
前記第２基材は、前記第２基材の前記第２主面に前記複数の第２の外部接続用端子に対応して配置された複数の第２電極パッドを有し、
前記複数の第１外部接続用端子は、半田材によって前記複数の第１電極パッドと夫々電気的にかつ機械的に接続され、
前記複数の第２外部接続用端子は、半田材によって前記複数の第２電極パッドと夫々電気的にかつ機械的に接続されていることを特徴とする電子装置。 The electronic device according to claim 3 .
The first semiconductor chip first semiconductor device packaging includes a terminal plurality of first external connection,
Wherein the second semiconductor chip is packaged second semiconductor device has a terminal a plurality of second external connection,
The first substrate has a plurality of first electrode pads arranged on the first main surface of the first substrate corresponding to the plurality of first external connection terminals,
The second base material has a plurality of second electrode pads arranged on the second main surface of the second base material so as to correspond to the plurality of second external connection terminals,
The terminal for a plurality of first external connection, first electrodes pads respectively electrically and the plurality by solder material are mechanically connected,
Wherein the plurality of second external connection terminal is an electronic device characterized by being connected the plurality of second electrode pads and the respective electrically and mechanically by the solder material.
前記枠体は、前記第１面に配置された複数の第３電極パッドと、前記第２面に配置され、かつ前記第３電極パッドと夫々電気的に接続された複数の第４電極パッドとを有し、
前記第１基材は、前記第１基材の前記第１主面に前記複数の第３電極パッドに対応して配置され、かつ前記複数の第１電極パッドと夫々電気的に接続された複数の第５電極パッドを有し、
前記第２基材は、前記第２基材の前記第２主面に前記複数の第４電極パッドに対応して配置され、かつ前記複数の第２電極パッドと夫々電気的に接続された複数の第６電極パッドを有し、
前記複数の第３電極パッドは、半田材によって前記複数の第５電極パッドと夫々電気的にかつ機械的に接続され、
前記複数の第４電極パッドは、半田材によって前記複数の第６電極パッドと夫々電気的にかつ機械的に接続されていることを特徴とする電子装置。 The electronic device according to claim 7.
The frame body includes a plurality of third electrode pad disposed on the first surface, disposed on the second surface, and said third electrode pad and electrically connected respectively to the plurality of fourth electrode pad was Have
Said first substrate, said said first substrate are arranged corresponding to the plurality of third electrode pads on the first main surface, and connected the plurality of first electrodes pads respectively electrically A plurality of fifth electrode pads;
The plurality of second substrates are arranged on the second main surface of the second substrate so as to correspond to the plurality of fourth electrode pads, and are electrically connected to the plurality of second electrode pads, respectively. A sixth electrode pad,
The plurality of third electrode pads are electrically and mechanically connected to the plurality of fifth electrode pads by a solder material,
The plurality of fourth electrode pads are electrically and mechanically connected to the plurality of sixth electrode pads by a solder material, respectively.
前記枠体は、平面が方形状で形成され、
前記複数の第３電極パッド及び前記複数の第４電極パッドは、前記枠体の各辺に沿って千鳥状に配置されていることを特徴とする電子装置。 The electronic device according to claim 8.
The frame is formed in a rectangular plane.
The plurality of third electrode pads and the plurality of fourth electrode pads are arranged in a staggered manner along each side of the frame.
前記第３、第４、第５及び第６の電極パッドは、平面が長方形で形成され、
前記第３、第４、第５及び第６の電極パッドは、各々の長辺が各々の配列方向に沿うように、配置されていることを特徴とする電子装置。 The electronic device according to claim 9.
The third , fourth, fifth and sixth electrode pads are formed in a rectangular plane.
It said third, fourth, electrode pads of the fifth and sixth electronic device, wherein each of the long sides along the arrangement direction of each are disposed.
前記複数の第１電極パッドは、前記第１基材の前記第１主面に設けられた複数の配線を介して前記複数の第５電極パッドと夫々電気的に接続されていることを特徴とする電子装置。 The electronic device according to claim 8.
Wherein the plurality of first electrodes pads, characterized in that it is the plurality of fifth electrode pad and electrically connected respectively via a plurality of wires provided on the first major surface of said first substrate An electronic device.
前記第１基材は、前記第１基材の前記第１裏面に複数の外部接続用端子を有することを特徴とする電子装置。 The electronic device according to claim 1,
Wherein the first substrate is an electronic device characterized by having a plurality of external connection terminal to the first back surface of the first substrate.
前記複数の外部接続用端子の夫々は、半田バンプであることを特徴とする電子装置。 The electronic device according to claim 12.
Wherein the plurality of respective external connection terminals, the electronic device which is a solder bump.
前記複数の外部接続用端子の夫々は、導電膜からなる電極パッドであることを特徴とする電子装置。 The electronic device according to claim 12.
Wherein the plurality of respective external connection terminals, electronic devices, characterized in that the electrode pad made of a conductive film.
前記第１半導体チップには、制御回路が搭載され、
前記第２半導体チップには、前記制御回路の制御信号によって書き込み動作及び読み出し動作が制御される記憶回路が搭載されていることを特徴とする電子装置。 The electronic device according to claim 3 .
A control circuit is mounted on the first semiconductor chip,
The electronic device, wherein the second semiconductor chip includes a memory circuit in which a write operation and a read operation are controlled by a control signal of the control circuit.
前記記憶回路は、電子情報の電気的な書き換えが可能なＡＮＤ型若しくはＮＡＮＤ型ＥＥＰＲＯＭであることを特徴とする電子装置。 The semiconductor device according to claim 15,
The electronic device according to claim 1, wherein the memory circuit is an AND type or NAND type EEPROM capable of electrically rewriting electronic information.
前記第１半導体装置は、主面に前記第１半導体チップが実装され、前記主面と反対側の裏面に前記複数の第１外部接続用端子が配置された第１配線基板と、前記第１半導体チップを封止する第１樹脂封止体とを有し、
前記第２半導体装置は、主面に前記第２半導体チップが実装され、前記主面と反対側の裏面に前記複数の第２外部接続用端子が配置された第２配線基板と、前記第２半導体チップを封止する第２樹脂封止体とを有することを特徴とする電子装置。 The electronic device according to claim 7.
The first half conductor device is the first semiconductors chips mounted on a main surface, a first wiring board having the plurality of first external connection terminal on the back of the main surface and opposite side is disposed, and a first tree Aburafutome body for sealing the first half conductor chip,
The second half conductor arrangement is the second semiconductors chips mounted on a main surface, a second wiring board on which the plurality of second external connection terminals are disposed on the rear surface of the main surface opposite, electronic apparatus characterized by a second tree Aburafutome member for sealing the second semiconductors chips.
前記第１外部接続用端子は、導電膜からなる電極パッド、若しくは半田バンプからなることを特徴とする電子装置。 The electronic device according to claim 7.
It said first external connection terminal is an electronic device characterized by comprising an electrode pad or solder bumps, made of a conductive film.
前記第２外部接続用端子は、導電膜からなる電極パッド、若しくは半田バンプであることを特徴とする電子装置。 The electronic device according to claim 7.
It said second external connection terminal, an electronic device, characterized in that an electrode pad or solder bumps, made of a conductive film.
前記第１半導体装置は、前記第１半導体チップを封止する第１樹脂封止体と、前記第１半導体チップと電気的に接続され、かつ前記第１樹脂封止体から突出する複数の第１リードとを有し、
前記第１外部接続用端子は、前記第１リードの一部で形成されていることを特徴とする電子装置。 The electronic device according to claim 7.
The first half conductor device comprises a first tree Aburafutometai for sealing the first half conductor chip, said first half conductor chips and are electrically connected, and from the first tree Aburafutome body and a plurality of first rie de projecting,
It said first external connection terminal is an electronic device characterized by being formed by a portion of the first rie de.
前記第２半導体装置は、前記第２半導体チップを封止する第２樹脂封止体と、前記第２半導体チップと電気的に接続され、かつ前記第２樹脂封止体から突出する複数の第２リードとを有し、
前記第２外部接続用端子は、前記第２リードの一部で形成されていることを特徴とする電子装置。 The electronic device according to claim 7.
The second half conductor arrangement includes a second tree Aburafutometai which seals the second half conductor chip, said second half-conductor chips and are electrically connected, and from the second tree Aburafutome body and a plurality of second rie de projecting,
It said second external connection terminal, the electronic apparatus characterized by being formed by a portion of the second rie de.
（ｂ）互いに反対側に位置する主面及び裏面と、前記主面に配置された第１の製品搭載領域と、前記主面に前記第１の製品搭載領域を囲むようにして配置された第１の枠体搭載領域とを有する第１の配線基板を準備する工程と、
（ｃ）互いに反対側に位置する主面及び裏面と、前記主面に配置された第２の製品搭載領域と、前記主面に前記第２の製品搭載領域を囲むようにして配置された第２の枠体搭載領域とを有する第２の配線基板を準備する工程と、
（ｄ）半導体チップをパッケージングした第１及び第２の半導体装置を準備する工程と、
（ｅ）前記第１の配線基板の主面において、前記第１の製品搭載領域に前記第１の半導体装置を実装すると共に、前記第１の枠体搭載領域に前記第１の半導体装置を囲むようにして前記枠体を接着固定する工程と、
（ｆ）前記第２の配線基板の主面において、前記第２の製品搭載領域に前記第２の半導体装置を実装すると共に、前記第２の枠体搭載領域に前記第２の半導体装置を囲むようにして前記枠体を接着固定する工程と、
（ｇ）前記枠体及び第１の配線基板を樹脂封止する樹脂封止体を形成する工程と、
を有することを特徴とする電子装置の製造方法。 (A) preparing a frame;
(B) a main surface and a back surface located on opposite sides, a first product mounting region disposed on the main surface, and a first product disposed on the main surface so as to surround the first product mounting region. Preparing a first wiring board having a frame mounting area;
(C) a main surface and a back surface located on opposite sides of each other; a second product mounting region disposed on the main surface; and a second product disposed on the main surface so as to surround the second product mounting region Preparing a second wiring board having a frame mounting area;
(D) preparing a first and second semiconductor device packaged with a semiconductor chip;
(E) On the main surface of the first wiring board, the first semiconductor device is mounted in the first product mounting region, and the first semiconductor device is enclosed in the first frame mounting region. A step of bonding and fixing the frame body,
(F) On the main surface of the second wiring board, the second semiconductor device is mounted in the second product mounting region, and the second semiconductor device is enclosed in the second frame mounting region. A step of bonding and fixing the frame body,
(G) forming a resin sealing body for resin sealing the frame body and the first wiring board;
A method for manufacturing an electronic device, comprising:
前記第２の配線基板は、前記第２の製品形成領域に前記第２の配線基板の主面から裏面に亘って貫通する通気孔を有することを特徴とする電子装置の製造方法。 The method of manufacturing an electronic device according to claim 22,
The method of manufacturing an electronic device, wherein the second wiring board has a vent hole penetrating from a main surface to a back surface of the second wiring board in the second product formation region.
前記第２の配線基板は、各々がスクライブ領域によって区画され、かつ各々に前記第２の製品搭載領域及び前記第２の枠体搭載領域が配置された複数の製品形成領域を有し、
前記（ｇ）工程の後、前記スクライブ領域に沿って前記第２の配線基板及び前記樹脂封止体を分割する工程を有することを特徴とする電子装置の製造方法。 The method of manufacturing an electronic device according to claim 22,
The second wiring board has a plurality of product formation regions each defined by a scribe region, and each having the second product mounting region and the second frame mounting region disposed therein,
After the step (g), there is a step of dividing the second wiring substrate and the resin sealing body along the scribe region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006111661A JP4889359B2 (en) | 2006-04-14 | 2006-04-14 | Electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006111661A JP4889359B2 (en) | 2006-04-14 | 2006-04-14 | Electronic equipment |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2007287820A JP2007287820A (en) | 2007-11-01 |
| JP2007287820A5 true JP2007287820A5 (en) | 2009-04-23 |
| JP4889359B2 JP4889359B2 (en) | 2012-03-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2006111661A Expired - Fee Related JP4889359B2 (en) | 2006-04-14 | 2006-04-14 | Electronic equipment |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8987872B2 (en) * | 2013-03-11 | 2015-03-24 | Qualcomm Incorporated | Electromagnetic interference enclosure for radio frequency multi-chip integrated circuit packages |
| JP6375517B2 (en) * | 2013-06-25 | 2018-08-22 | パナソニックＩｐマネジメント株式会社 | Microwave circuit |
| CN106783805A (en) * | 2017-03-13 | 2017-05-31 | 中国科学院微电子研究所 | Radio frequency multi-chip package and shielding circuit |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63128736A (en) * | 1986-11-19 | 1988-06-01 | Olympus Optical Co Ltd | Semiconductor element |
| KR20010090354A (en) * | 1999-03-26 | 2001-10-18 | 가나이 쓰토무 | Semiconductor module and mounting method for same |
| JP2001111232A (en) * | 1999-10-06 | 2001-04-20 | Sony Corp | Electronic component mounting multilayer board and manufacturing method thereof |
| JP2002043507A (en) * | 2000-07-31 | 2002-02-08 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
| JP4045083B2 (en) * | 2000-12-25 | 2008-02-13 | 株式会社ルネサステクノロジ | Semiconductor module and mounting structure |
| JP2005005092A (en) * | 2003-06-11 | 2005-01-06 | Sony Corp | Electronic circuit device and connection member |
| KR100521279B1 (en) * | 2003-06-11 | 2005-10-14 | 삼성전자주식회사 | Stack Chip Package |
| JP3842272B2 (en) * | 2004-06-02 | 2006-11-08 | 株式会社Ｇｅｎｕｓｉｏｎ | Interposer, semiconductor chip mount sub-board and semiconductor package |
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2006
- 2006-04-14 JP JP2006111661A patent/JP4889359B2/en not_active Expired - Fee Related
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