JP2007281029A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the conventional problem that it is difficult both to reduce collector resistance and to improve breakdown voltage between a collector and an emitter. <P>SOLUTION: A semiconductor device 1 includes an SOI substrate 10 (semiconductor substrate), a collector region 22 and a collector pull-up region 26 formed on a surface layer of the SOI substrate 10, a collector extraction region 28 provided between the collector region 22 and the collector pull-up region 26, and an emitter region 34 provided on the collector region 22 via a base region 32 and constituting a bipolar transistor together with the collector region 22 and the base region 32. The collector extraction region 28 has a higher impurity concentration than that of the collector region 22. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  FIG. 9 is a cross-sectional view showing an example of a conventional semiconductor device (for example, Patent Document 1). This semiconductor device includes an NPN self-aligned SiGe bipolar transistor in which a collector region 101 is formed by ion implantation. In addition, an SOI substrate 110 including a silicon substrate 111, an insulating film 112, and an SOI layer 113 is used as a semiconductor substrate.

  A method for manufacturing this semiconductor device will be described. First, the collector pull-up region 102 is formed on the SOI substrate 110 having a thickness of about 1 μm to 5 μm by a photoresist (PR) process and ion implantation. Subsequently, the collector region 101 is formed by a PR process and ion implantation.

  Thereafter, a trench 103 having a depth of about 0.5 μm to 3 μm is formed in the SOI layer 113 by PR process and silicon etching. Next, the trench 103 is embedded with an insulating film by CVD oxide film embedding and planarization (for example, CMP). Thereafter, an insulating film 121 and a base lead region 122 made of polysilicon are sequentially formed on the SOI substrate 110. Subsequently, after implanting boron into the base extraction region 122, the insulating film 123 is grown. Further, an emitter region opening (emitter opening) 124 is formed by the PR process and the etching process.

  Thereafter, an insulating film is grown to a thickness of about 50 nm and etched back to form an insulating film 125 on the sidewall of the emitter opening 124. Next, after opening the base formation region by a wet etching process, the base region 126 is formed by selectively growing boron-doped SiGe. Subsequently, an insulating film is grown to a thickness of about 100 nm and etched back to form an insulating film 127 on the insulating film 125.

  Furthermore, after growing As-doped polysilicon with a thickness of about 200 nm, patterning is performed by a PR process and a poly-silicon etching process to form an emitter extraction region 128. Thereafter, an emitter region 129 is formed by heat treatment. Subsequently, the electrode forming part is opened by the PR process and the dry etching process. The above-described collector extraction region 102, base extraction region 122, and emitter extraction region 128 are connected to the collector electrode 131, the base electrode 132, and the emitter electrode 133, respectively. Thus, the semiconductor device of FIG. 9 is obtained.

In Patent Document 1, the collector region is formed by ion implantation and epitaxial growth.
JP 2005-26483 A

  However, when the collector region is formed by ion implantation, if the dose amount of ion implantation is increased, the collector resistance (R3 + R4 in FIG. 9) is reduced while the collector-emitter breakdown voltage is lowered. Further, when the dose is decreased, the collector-emitter breakdown voltage is improved, while the collector resistance is increased. That is, there is a trade-off between reducing the collector resistance and improving the collector-emitter breakdown voltage. Therefore, conventionally, it has been difficult to achieve both reduction of collector resistance and improvement of collector-emitter breakdown voltage.

  A method of manufacturing a semiconductor device according to the present invention includes a collector region and a collector pull-up region provided on a surface layer of a semiconductor substrate, a collector lead region provided between the collector region and the collector pull-up region, A method of manufacturing a semiconductor device including a collector region and an emitter region that constitutes a bipolar transistor together with the base region, the collector region being provided on the collector region via a base region, wherein the collector region is subjected to first ion implantation. And the step of forming the collector extraction region by second ion implantation, wherein the implantation amount of the second ion implantation is larger than the implantation amount of the first ion implantation. To do.

  In this manufacturing method, the formation of the collector region and the formation of the collector extraction region are performed in separate steps. Thereby, the adjustment of the collector-emitter breakdown voltage by the first ion implantation (collector implantation) when forming the collector region and the adjustment of the collector resistance by the second ion implantation when forming the collector extraction region are mutually performed. Can be done independently. Here, the implantation amount of the second ion implantation is larger than the implantation amount of the first ion implantation. For this reason, it is possible to reduce the collector resistance without lowering the collector-emitter breakdown voltage.

  The semiconductor device according to the present invention includes a semiconductor substrate, a collector region and a collector pull-up region provided on the surface layer of the semiconductor substrate, and a collector lead region provided between the collector region and the collector pull-up region. And an emitter region that is provided on the collector region via a base region and forms a bipolar transistor together with the collector region and the base region, and the collector extraction region has an impurity concentration higher than that of the collector region. Is characterized by high.

  In this semiconductor device, a collector extraction region is provided between the collector region and the collector pull-up region. Here, the impurity concentration of the collector extraction region is higher than that of the collector region. With such a structure, it is possible to reduce the collector resistance without lowering the collector-emitter breakdown voltage.

  According to the present invention, a semiconductor device capable of achieving both reduction of collector resistance and improvement of collector-emitter breakdown voltage and a manufacturing method thereof are realized.

  Hereinafter, preferred embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted.

  FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. The semiconductor device 1 is provided between an SOI substrate 10 (semiconductor substrate), a collector region 22 and a collector pull-up region 26 provided on the surface layer of the SOI substrate 10, and a collector region 22 and a collector pull-up region 26. A collector extraction region 28 and an emitter region 34 provided on the collector region 22 via a base region 32 and constituting a bipolar transistor together with the collector region 22 and the base region 32 are provided. Here, the collector extraction region 28 has a higher impurity concentration than the collector region 22. In addition, the semiconductor device 1 includes a trench 24 that is provided on the surface layer of the SOI substrate 10 adjacent to the collector region 22 and is embedded with an insulating film 23. The collector region 22 and the collector pull-up region 26 described above are separated from each other by the trench 24. Further, the collector extraction region 28 is provided in the lower portion of the trench 24.

The SOI substrate 10 includes a silicon substrate 12, an insulating film 14, and an SOI layer 16. The insulating film 14 is, for example, a SiO ₂ film. In the present embodiment, the SOI layer 16 corresponds to the surface layer of the SOI substrate 10.

  An insulating film 42 is formed around the base region 32 on the SOI substrate 10. On the insulating film 42, a base lead region 44 and an insulating film 46 are sequentially stacked. An emitter opening 50 is formed in the base lead region 44 and the insulating film 46. An insulating film 52 and an insulating film 54 are sequentially formed on the side wall of the emitter opening 50. An emitter extraction region 56 is formed in the emitter opening 50. The emitter lead region 56 is connected to the emitter electrode 66.

  Further, a collector opening 63 is formed in the insulating film 42, the base lead region 44, and the insulating film 46, and the collector pull-up region 26 is connected to the collector electrode 62 through the collector opening 63. A base opening 65 is formed in the insulating film 46, and the base extraction region 44 is connected to the base electrode 64 through the base opening 65.

With reference to FIGS. 2 to 7, an example of a method for manufacturing the semiconductor device 1 will be described as an embodiment of the method for manufacturing a semiconductor device according to the present invention. In general, this manufacturing method includes the following steps (a) and (b). However, in the step (b), ion implantation is performed so that the impurity concentration in the collector extraction region 28 is higher than that in the collector region 22. That is, the implantation amount of the second ion implantation is larger than the implantation amount of the first ion implantation.
(A) Step of forming collector region 22 by first ion implantation (b) Step of forming collector extraction region 28 by second ion implantation

  More specifically, first, the collector pull-up region 26 is formed on the SOI substrate 10 having a thickness of about 1 μm to 5 μm by the PR process and ion implantation (FIG. 2A). Subsequently, the collector region 22 is formed by a PR process and ion implantation (FIG. 2B).

  Thereafter, a trench 24 having a depth of about 0.5 μm to 3 μm is formed by a PR process and silicon etching (FIG. 3A). Next, the collector extraction region 28 is formed by the PR process and the ion implantation process (FIG. 3B). Specifically, ion implantation is performed in a state where the SOI substrate 10 is covered with a photoresist R1 having an opening at a portion where the collector extraction region 28 is formed. In this example, phosphorus ions are implanted.

  Subsequently, the trench 24 is embedded with the insulating film 23 by CVD oxide film embedding and planarization processing (for example, CMP) (FIG. 4A). Thereafter, an insulating film 42 and a base lead region 44 made of polysilicon are sequentially formed on the SOI substrate 10. Subsequently, after implanting boron into the base extraction region 44, the insulating film 46 is grown (FIG. 4B).

  Further, the emitter opening 50 is formed by the PR process and the etching process (FIG. 5A). The thicknesses of the insulating film 42, the base lead region 44, and the insulating film 46 are, for example, about 50 nm, 200 nm, and 150 nm, respectively. Thereafter, an insulating film is grown to a thickness of about 50 nm and etched back to form an insulating film 52 on the sidewall of the emitter opening 50 (FIG. 5B).

  Next, a base formation region is opened in the insulating film 42 by a wet etching process. Thereafter, the base region 32 is formed by selectively growing boron-doped SiGe (FIG. 6A). Subsequently, an insulating film is grown to a thickness of about 100 nm and etched back to form an insulating film 54 on the insulating film 52 (FIG. 6B).

  Further, an As-doped polysilicon 56a is grown with a thickness of about 200 nm (FIG. 7A). Thereafter, patterning is performed by a PR process and a polysilicon etching process to form an emitter extraction region 56. Next, the emitter region 34 is formed by heat treatment. The heat treatment at this time can be performed by, for example, an RTA (Rapid Thermal Annealing) method under conditions of 1000 ° C. and about 10 seconds. Subsequently, a collector opening 63 and a base opening 65 are formed by a PR process and a dry etching process (FIG. 7B). Thereafter, the collector pull-up region 26, the base lead region 44, and the emitter lead region 56 are connected to the collector electrode 62, the base electrode 64, and the emitter electrode 66, respectively, so that the semiconductor device 1 of FIG. 1 is obtained. The semiconductor device 1 manufactured in this example includes an NPN self-aligned SiGe bipolar transistor in which a collector region 22 is formed by ion implantation.

  The effect of this embodiment will be described. In the present embodiment, the formation of the collector region 22 and the formation of the collector lead region 28 are performed in separate steps. Thereby, the collector-emitter breakdown voltage is adjusted by the first ion implantation (collector implantation) when the collector region 22 is formed, and the collector resistance (FIG. 1) is formed by the second ion implantation when the collector extraction region 28 is formed. And R1 + R2) can be adjusted independently of each other. Here, the implantation amount of the second ion implantation is larger than the implantation amount of the first ion implantation. For this reason, it is possible to reduce the collector resistance without lowering the collector-emitter breakdown voltage. Actually, in the semiconductor device 1, the impurity concentration of the collector extraction region 28 is higher than that of the collector region 22 as described above. Therefore, the semiconductor device 1 and its manufacturing method that can achieve both reduction of the collector resistance and improvement of the collector-emitter breakdown voltage are realized.

  In contrast, in the semiconductor device of FIG. 9, when the collector injection concentration is increased to reduce the collector resistance, the distance between the emitter and the collector is shortened, and the collector-emitter breakdown voltage is lowered. On the other hand, if the collector-base junction is formed at a deep position while increasing the impurity concentration of the collector region, the distance between the emitter and the collector becomes long, and the collector resistance increases. The increase in collector resistance leads to deterioration of high frequency characteristics such as the current gain cutoff frequency fT and the maximum oscillation frequency fmax.

  In Patent Document 1, the collector region is formed by ion implantation and epitaxial growth. Therefore, the collector resistance is reduced by increasing the concentration of the collector implantation, but diffusion of impurities (diffusion from the high concentration epitaxial layer to the base side) occurs in the heat treatment in the subsequent process, thereby causing a distance between the emitter and the collector. Becomes shorter and the breakdown voltage between the emitter and the collector decreases. Further, as a method for achieving both improvement of the emitter-collector breakdown voltage and reduction of the collector resistance, it is conceivable to increase the thickness of the epitaxial layer while increasing the dose during collector implantation. However, this method reduces the current gain cutoff frequency.

  With respect to such a problem, according to the present embodiment, as described above, it is possible to reduce the collector resistance without causing a decrease in the emitter-collector breakdown voltage and a deterioration in the high frequency characteristics. Moreover, the manufacturing method according to the present embodiment is obtained by adding 1PR to the conventional manufacturing method described with reference to FIG. As described above, in the present embodiment, the semiconductor device 1 having the above-described effects is realized while minimizing an increase in manufacturing steps.

  The semiconductor device and the manufacturing method thereof according to the present invention are not limited to the above-described embodiment, and various modifications can be made. For example, in the above-described embodiment, an example in which an SOI substrate is used as a semiconductor substrate has been described. However, as shown in FIG. The semiconductor device 2 shown in the figure is different from the semiconductor device 1 shown in FIG. 1 in that a silicon substrate 70 is used instead of the SOI substrate 10. Other configurations of the semiconductor device 2 are the same as those of the semiconductor device 1.

  In the above embodiment, the NPN type is exemplified as the bipolar transistor, but the bipolar transistor may be a PNP type.

It is sectional drawing which shows one Embodiment of the semiconductor device by this invention. (A) And (b) is process drawing which shows one Embodiment of the manufacturing method of the semiconductor device by this invention. (A) And (b) is process drawing which shows one Embodiment of the manufacturing method of the semiconductor device by this invention. (A) And (b) is process drawing which shows one Embodiment of the manufacturing method of the semiconductor device by this invention. (A) And (b) is process drawing which shows one Embodiment of the manufacturing method of the semiconductor device by this invention. (A) And (b) is process drawing which shows one Embodiment of the manufacturing method of the semiconductor device by this invention. (A) And (b) is process drawing which shows one Embodiment of the manufacturing method of the semiconductor device by this invention. It is sectional drawing which shows the semiconductor device which concerns on the modification of embodiment. It is sectional drawing which shows the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor device 10 SOI substrate 12 Silicon substrate 14 Insulating film 16 SOI layer 22 Collector region 23 Insulating film 24 Trench 26 Collector extraction region 28 Collector extraction region 32 Base region 34 Emitter region 42 Insulating film 44 Base extraction region 46 Insulation Film 50 Emitter opening 52 Insulating film 54 Insulating film 56 Emitter extraction region 62 Collector electrode 63 Collector opening 64 Base electrode 65 Base opening 66 Emitter electrode 70 Silicon substrate R1 Photoresist

Claims (5)

A collector region and a collector pull-up region provided on the surface layer of the semiconductor substrate, a collector lead region provided between the collector region and the collector pull-up region, and a base region above the collector region A method for manufacturing a semiconductor device, comprising: an emitter region that constitutes a bipolar transistor together with the collector region and the base region;
Forming the collector region by first ion implantation;
Forming the collector extraction region by a second ion implantation,
A method of manufacturing a semiconductor device, wherein an implantation amount of the second ion implantation is larger than an implantation amount of the first ion implantation. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the semiconductor substrate is an SOI substrate. In the manufacturing method of the semiconductor device according to claim 1 or 2,
A method of manufacturing a semiconductor device in which phosphorus ions are implanted in the first and second ion implantations. A semiconductor substrate;
A collector region and a collector pull-up region provided in a surface layer of the semiconductor substrate;
A collector extraction region provided between the collector region and the collector pull-up region; and
An emitter region provided on the collector region via a base region, and forming a bipolar transistor together with the collector region and the base region,
The semiconductor device according to claim 1, wherein the collector extraction region has a higher impurity concentration than the collector region. The semiconductor device according to claim 4,
The semiconductor device, wherein the semiconductor substrate is an SOI substrate.

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