JP2002076011A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow enlargement of a collector lead-out region to prevent the dielectric strength between a collector and a base from declining caused by decrease of a distance from the end of the collector lead-out region to the base region. SOLUTION: A semiconductor device comprises a collector layer formed in a semiconductor substrate, a base region and an emitter region on a main surface of the semiconductor substrate, and a collector lead-out region connecting the collector layer and a collector electrode formed on the surface of the semiconductor substrate. A trench is formed as a region for the collector lead-out region, ion implantation is performed through the trench to form the collector lead-out region, and the trench is embedded by the collector electrode. Since there is no need to increase the energy of the ion implantation for forming a collector lead-out region, this construction allows enlargement of the collector lead-out region to prevent the collector lead-out region from enlarging in a horizontal direction, and the dielectric strength between the collector and the base from declining.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bipolar transistor and a method of manufacturing the same, and more particularly to a technique effective when applied to a semiconductor device having a high withstand voltage bipolar transistor.

[0002]

FIG. 1 is a longitudinal sectional view showing an example of a conventional bipolar transistor type semiconductor device. In a bipolar transistor, a buried insulating film 2 made of silicon oxide is formed on a semiconductor substrate 1 made of, for example, single crystal silicon. SOI (Silicon On I) in which a semiconductor layer 3 of single crystal silicon is formed through
Using a semiconductor substrate of the nsulator type, a p-type collector buried layer 4 and a p-type collector layer 5 into which, for example, boron has been epitaxially grown on the semiconductor layer 3 are formed. Alternatively, a p-type emitter region 7 doped with, for example, boron is formed in an n-type base region 6 doped with arsenic. A polycrystalline silicon film 9 is formed on emitter region 7 with an interlayer insulating film 8 interposed therebetween. Polycrystalline silicon film 9 is connected to emitter region 7 by an opening provided in interlayer insulating film 8, and emitter region 7 is formed. Are formed by solid-phase diffusion of impurities from the polycrystalline silicon film 9.

The interlayer insulating film 8 and the polycrystalline silicon film 9 are covered with an interlayer insulating film 10, and a collector electrode 11, a base electrode 12, and an emitter electrode 13 made of aluminum or tungsten are formed on the interlayer insulating film 10. The collector electrode 11 is connected to the collector lead-out region 14 through openings formed in the interlayer insulating films 10 and 8, and the collector lead-out region 14 is connected to the collector buried layer 4. Similarly, the base electrode 12 is connected to the base contact region 15 for lowering the resistance through the openings provided in the interlayer insulating films 10 and 8, the base contact region 15 is connected to the base region 6, and the emitter electrode 1
3 is connected to the polycrystalline silicon film 9.

A transistor is separated from other elements by a trench-like trench insulating film 17 reaching the field insulating film 16 and the buried insulating film 2 by selective oxidation. The space is separated by a field insulating film 18.

In this transistor, the collector layer 5 is usually formed to have a thickness of about 0.7 μm. However, when used in a semiconductor device for a tester, a withstand voltage between the collector and the emitter of about 15 V is required. In order to improve the breakdown voltage, it is necessary to increase the distance between the base region and the collector buried layer. By increasing this distance, the collector layer has a lower impurity concentration than the collector buried layer, so that the depletion layer easily extends from the base region to the collector side, and the collector-base breakdown voltage is improved.

[0006]

With such an increase in the thickness of the collector layer, the collector lead-out region is connected to the collector buried layer to reduce the collector resistance.
It is necessary to increase the film thickness. For this reason, the energy of ion implantation into the collector extraction region is increased, but when the energy of ion implantation is increased,
Since the collector lead-out region also expanded in the horizontal direction, and the distance from the end of the collector lead-out region to the base region was reduced, the withstand voltage between the collector and the base was reduced.

In order to solve this problem, it is conceivable to increase the width of the element isolation insulating film between the base region and the collector lead region. However, in this method, the capacitance between the collector and the substrate increases. Maximum cutoff frequency fT
Other problems such as a decrease in max occur, and there is also a problem that the layout area of the transistor increases.

An object of the present invention is to provide a semiconductor device which solves such a problem and improves the breakdown voltage between the collector and the base.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A collector layer is formed in a semiconductor substrate, a base region and an emitter region are formed on a main surface of the semiconductor substrate, and the collector layer and a collector electrode formed on the main surface of the semiconductor substrate are connected by a collector lead-out region. In the semiconductor device, a trench is formed in the collector lead-out region, and the trench is filled with the collector electrode.

A collector layer is formed in a semiconductor substrate, a base region and an emitter region are formed on a main surface of the semiconductor substrate, and the collector layer and a collector electrode formed on the main surface of the semiconductor substrate are connected by a collector lead-out region. ,
In a semiconductor device that separates the base region and the collector lead-out region by a field insulating film, a trench is formed in the field insulating film, and an isolation insulating film is formed by filling the trench with an insulating film.

A collector layer is formed in a semiconductor substrate, a base region and an emitter region are formed on a main surface of the semiconductor substrate, and the collector layer and a collector electrode formed on the main surface of the semiconductor substrate are connected by a collector lead-out region. In the semiconductor device, a diffusion prevention region is provided in the collector lead-out region.

A collector layer is formed in a semiconductor substrate, a base region and an emitter region are formed on a main surface of the semiconductor substrate, and the collector layer and a collector electrode formed on the main surface of the semiconductor substrate are connected by a collector lead-out region. In the method for manufacturing a semiconductor device, a step of forming a trench in a region to be the collector lead-out region, a step of introducing a dopant from the trench to form a collector lead-out region, and forming the trench by a conductive film serving as the collector electrode Embedding.

A collector layer is formed in a semiconductor substrate, a base region and an emitter region are formed on a main surface of the semiconductor substrate, and the collector layer and a collector electrode formed on the main surface of the semiconductor substrate are connected by a collector lead-out region. ,
In a method of manufacturing a semiconductor device in which the base region and the collector lead-out region are separated from each other by a field insulating film, a step of forming the field insulating film; a step of forming a trench in the field insulating film; Forming an isolation insulating film embedded therein.

(Operation) According to the structure of the present invention, it is not necessary to increase the energy of ion implantation for forming the collector extraction region, so that the collector extraction region is prevented from expanding in the horizontal direction and the withstand voltage between the collector and the base is reduced. Does not decrease.

In addition, at the time of ion implantation for forming the collector extraction region, the isolation insulating film prevents the collector extraction region from expanding in the horizontal direction, so that the breakdown voltage between the collector and the base does not decrease.

Further, at the time of ion implantation for forming the collector extraction region, the diffusion prevention region prevents the collector extraction region from expanding in the horizontal direction, and the breakdown voltage between the collector and the base does not decrease.

[0019]

Embodiments of the present invention will be described below. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

(Embodiment 1) FIG. 2 is a longitudinal sectional view showing a bipolar transistor type semiconductor device according to an embodiment of the present invention.

The semiconductor device according to the present embodiment has an SOI (Silicon On Insulator) in which a semiconductor layer 3 of single crystal silicon is formed on a semiconductor substrate 1 of single crystal silicon via a buried insulating film 2 of silicon oxide. A p-type collector buried layer 4 and a p-type collector layer 5 into which, for example, boron has been epitaxially grown in the semiconductor layer 3 are formed using a semiconductor substrate of a semiconductor type. Is formed in an n-type base region 6 into which p is introduced, for example, boron is introduced. Polycrystalline silicon film 9 is formed on emitter region 7 with interlayer insulating film 8 interposed therebetween.
The polycrystalline silicon film 9 is connected to the emitter region 7 by the opening provided in the first region, and the emitter region 7 is formed by solid-phase diffusion of impurities from the polycrystalline silicon film 9.

The interlayer insulating film 8 and the polycrystalline silicon film 9 are covered with an interlayer insulating film 10.
A collector electrode 11, a base electrode 12, and an emitter electrode 13 made of aluminum, tungsten, or the like are formed on the substrate 0, and the collector electrode 11 is connected to a collector lead-out region 14 through openings provided in the interlayer insulating films 10, 8. The collector lead-out region 14 is connected to the collector buried layer 4. Similarly, the base electrode 12 is connected to the base contact region 15 for lowering the resistance through the openings provided in the interlayer insulating films 10 and 8, the base contact region 15 is connected to the base region 6, and the emitter electrode 1
3 is connected to the polycrystalline silicon film 9.

The transistor is separated from other elements by a trench-like trench insulating film 17 reaching the field insulating film 16 and the buried insulating film 2 by selective oxidation. The space is separated by a field insulating film 18.

The collector lead-out region 14 is provided for increasing the concentration by ion implantation and connecting the collector buried layer 4 and the collector electrode 11 with low resistance. In the present embodiment, the collector lead-out region 14 is provided. A trench or a hole-like trench is provided at the center of the trench, and the trench is filled with the collector electrode 11. By providing this trench, the distance between the surface of the collector lead-out region 14 and the collector buried layer 4 is reduced, so that it is not necessary to increase the energy at the time of ion implantation for forming the collector lead-out region 14, and the collector lead-out region 14 14 can be reduced in the horizontal direction, and a decrease in breakdown voltage due to the proximity of the collector lead-out region 14 and the base region 6 can be prevented.

The contact area between collector electrode 11 and collector lead-out region 14 is increased by the trench, so that the contact resistance of collector electrode 11 can be reduced. Since the purpose of this trench is to reduce ion implantation energy, it is not necessary to reach the collector buried layer 4. If the trench is too deep, it becomes difficult to fill the trench when forming the collector electrode 11, and a separate process for filling is required, which may increase the number of processes.

In the bipolar transistor of the conventional structure and the bipolar transistor of the present embodiment, when the collector-base breakdown voltage is set to the same condition as 15 V,
In the transistor of the conventional structure, the distance between the collector and the base is required to be 1.5 μm, but in the transistor of the present embodiment, it can be set to 1.0 μm. Therefore, the capacity between the collector and the substrate can be reduced. FIG. 3 shows the relationship between the collector current Ic and the cut-off frequency fT. In the bipolar transistor of the present embodiment, the maximum cut-off frequency is improved from 3.5 GHz to 4.1 GHz as compared with the bipolar transistor having the conventional structure. are doing.

Next, a method of manufacturing the semiconductor device shown in FIG. 2 will be described with reference to FIGS.

First, a semiconductor layer 3 is formed by epitaxial growth on a semiconductor layer 3 of an SOI (Silicon On Insulator) type semiconductor substrate, for example, a p-type collector buried layer 4 into which boron is introduced and a p-type collector layer 5. Then, a trench-shaped trench insulating film 17 reaching the field insulating film 16 and the buried insulating film 2 by selective oxidation is formed, separated from other elements, and the regions where the base region and the collector lead-out region are formed are separated from each other. A field insulating film 18 is formed, and a trench in the shape of a groove or a hole is provided in the center of the region serving as the collector lead-out region. This state is shown in FIG.

Next, ion implantation is performed through the trench in the region to be the collector extraction region to form the collector extraction region 14. By providing this trench, the distance between the surface of the collector lead-out region 14 and the collector buried layer 4 is reduced, so that it is not necessary to increase the energy at the time of ion implantation for forming the collector lead-out region 14, and the collector lead-out region 14 14 can be reduced in the horizontal direction, and a decrease in breakdown voltage due to the proximity of the collector lead-out region 14 and the base region 6 can be prevented. This state is shown in FIG.

Next, an n-type base region 6 into which, for example, phosphorus or arsenic is introduced is formed on the collector layer 5, and a part of the base contact region 1 having a high impurity concentration is formed in a part of the base region 6.
5 is formed, a polycrystalline silicon film 9 is formed via an interlayer insulating film 8 covering the semiconductor substrate, and the polycrystalline silicon film 9 is formed through an opening provided in the interlayer insulating film 8 on the emitter region 7.
The emitter region 7 is formed by solid-phase diffusion of impurities from the substrate. Subsequently, the interlayer insulating film 8 and the polycrystalline silicon film 9
Forming an interlayer insulating film 10 covering the base contact region 1
5. An opening for exposing the polycrystalline silicon film 9 and the collector lead-out region 14 is formed. This state is shown in FIG.

Thereafter, a conductor film using aluminum, tungsten, or the like is formed on the interlayer insulating film 10 and the conductor film is patterned to form the collector electrode 1.
1, the base electrode 12 and the emitter electrode 13 are formed and FIG.
The state shown in FIG.

(Embodiment 2) FIG. 7 is a longitudinal sectional view showing a bipolar transistor type semiconductor device according to another embodiment of the present invention.

The semiconductor device according to the present embodiment has an SOI (Silicon On Insulator) in which a semiconductor layer 3 of single crystal silicon is formed on a semiconductor substrate 1 of single crystal silicon via a buried insulating film 2 of silicon oxide. A p-type collector buried layer 4 and a p-type collector layer 5 into which, for example, boron has been epitaxially grown in the semiconductor layer 3 are formed using a semiconductor substrate of a semiconductor type. Is formed in an n-type base region 6 into which p is introduced, for example, boron is introduced. Polycrystalline silicon film 9 is formed on emitter region 7 with interlayer insulating film 8 interposed therebetween.
The polycrystalline silicon film 9 is connected to the emitter region 7 by the opening provided in the first region, and the emitter region 7 is formed by solid-phase diffusion of impurities from the polycrystalline silicon film 9.

The interlayer insulating film 8 and the polycrystalline silicon film 9 are covered with an interlayer insulating film 10.
A collector electrode 11, a base electrode 12, and an emitter electrode 13 using aluminum, tungsten, or the like are formed on the substrate 0, and the collector electrode 11 is connected with low resistance through openings provided in the interlayer insulating films 10, 8. Extraction region 14 which has been highly concentrated by ion implantation
Is connected to the collector buried layer 4. Similarly, the base electrode 1 is passed through openings provided in the interlayer insulating films 10 and 8.
2 is connected to a base contact region 15 for reducing the resistance, the base contact region 15 is connected to the base region 6, and the emitter electrode 13 is connected to the polycrystalline silicon film 9.

The transistor is separated from other elements by a trench insulating film 17 reaching the buried insulating film 16 and the field insulating film 16 by selective oxidation. The space is separated by a field insulating film 18. In the present embodiment, the field insulating film 18 is provided with a trench in the form of a trench, and is filled with an insulator such as silicon oxide.
Is formed, and by providing the isolation insulating film 19,
Since the diffusion of the collector lead-out region 14 in the horizontal direction can be prevented, it is possible to prevent a decrease in breakdown voltage due to the proximity of the collector lead-out region 14 and the base region 6.

Next, a method of manufacturing the semiconductor device shown in FIG. 7 will be described with reference to FIGS.

First, a semiconductor layer is formed by epitaxial growth on a semiconductor layer 3 of an SOI (Silicon On Insulator) type semiconductor substrate, and a semiconductor layer to be a p-type collector layer 5 into which, for example, is introduced is formed. To form a p-type collector buried layer 4 by ion implantation, and form field insulating films 16 and 18 by selective oxidation. This state is shown in FIG.

Next, the field insulating film 1 is formed by selective oxidation.
A groove reaching the buried insulating film 2 from the gate insulating film 2 is formed, and a groove-shaped trench reaching the collector layer 5 from the field insulating film 18 separating the base region 6 and the collector lead-out region 14 is formed. The groove formed in the field insulating film 18 is
Although it is shallower than the groove formed in the field insulating film 16, in the etching for forming the groove, since the side surface of the groove is inclined,
Since the depth is limited by the interval between the grooves, a planar pattern of the groove formed in the field insulating film 16 is formed as a groove-shaped trench extending from the field insulating film 18 to the collector layer 5. By making the grooves formed in the field insulating film 18 narrower than the plane pattern, both grooves having different depths can be formed in the same etching step.
There is no increase in the number of steps. This state is shown in FIG.

Next, trenches formed in the field insulating films 16 and 18 are buried with silicon oxide or the like to form a trench insulating film 17 and an isolation insulating film 19. This state is shown in FIG. Thereafter, the steps shown in FIGS. 5 and 6 can be applied to the subsequent steps.

(Embodiment 3) FIG. 11 is a longitudinal sectional view showing a bipolar transistor type semiconductor device according to another embodiment of the present invention.

The semiconductor device according to the present embodiment has an SOI (Silicon On Insulator) in which a semiconductor layer 3 of single crystal silicon is formed on a semiconductor substrate 1 of single crystal silicon via a buried insulating film 2 of silicon oxide. A p-type collector buried layer 4 and a p-type collector layer 5 into which, for example, boron has been epitaxially grown in the semiconductor layer 3 are formed using a semiconductor substrate of a semiconductor type. Is formed in an n-type base region 6 into which p is introduced, for example, boron is introduced. Polycrystalline silicon film 9 is formed on emitter region 7 with interlayer insulating film 8 interposed therebetween.
The polycrystalline silicon film 9 is connected to the emitter region 7 by the opening provided in the first region, and the emitter region 7 is formed by solid-phase diffusion of impurities from the polycrystalline silicon film 9.

The interlayer insulating film 8 and the polycrystalline silicon film 9 are covered with an interlayer insulating film 10.
A collector electrode 11, a base electrode 12, and an emitter electrode 13 using aluminum, tungsten, or the like are formed on the substrate 0, and the collector electrode 11 is connected with low resistance through openings provided in the interlayer insulating films 10, 8. Extraction region 14 which has been highly concentrated by ion implantation
Is connected to the collector buried layer 4. Similarly, the base electrode 1 is passed through openings provided in the interlayer insulating films 10 and 8.
2 is connected to a base contact region 15 for reducing the resistance, the base contact region 15 is connected to the base region 6, and the emitter electrode 13 is connected to the polycrystalline silicon film 9.

In this embodiment, the diffusion prevention region 20 is provided in the collector lead-out region 14. As the diffusion prevention region 20, the boron forming the collector lead-out region 14 is smaller than the atomic radius of silicon constituting the semiconductor substrate, so that the diffusion proceeds through the interstitial position.
Therefore, prior to the introduction of boron ions, by occupying the interstitial positions of silicon with other implanted atoms, the migration of boron ions can be prevented. Therefore, by providing the diffusion prevention region 20, the diffusion of the collector lead-out region 14 in the horizontal direction can be prevented.
Can be prevented from lowering the withstand voltage due to the proximity of.

As ions to be implanted to form the diffusion preventing region 20, those having an atomic radius smaller than that of silicon must be selected. In addition, when the diffusion preventing region 20 becomes an n-type conductive region by the implanted ions,
A high-concentration pn junction is formed with the p-type collector lead-out region 14, so that the collector-base breakdown voltage decreases. Conversely, when the diffusion preventing region 20 becomes a p-type conductive region by the implanted ions, a high-concentration pn junction is formed with the n-type base region 6 and the collector-base breakdown voltage decreases. Therefore, it is necessary to select an ion species that does not become n-type or p-type as the ion species used for forming the diffusion prevention region 20. Those satisfying these conditions include germanium (Ge) and argon (Ar).

The transistor is separated from other elements by a trench-like trench insulating film 17 reaching the field insulating film 16 and the buried insulating film 2 by selective oxidation. The space is separated by a field insulating film 18.

Subsequently, a method of manufacturing the semiconductor device shown in FIG. 11 will be described with reference to FIGS.

First, a semiconductor layer is formed by epitaxial growth on a semiconductor layer 3 of an SOI (Silicon On Insulator) type semiconductor substrate, and a semiconductor layer serving as a p-type collector layer 5 into which is introduced, for example, boron is formed. Forming a p-type collector buried layer 4 by selective ion implantation, forming field insulating films 16 and 18 by selective oxidation, forming a groove from the field insulating film 16 to the buried insulating film 2 by selective oxidation, The trenches formed in the insulating films 16 and 18 are filled with silicon oxide or the like to form a trench insulating film 17.
Subsequently, germanium or argon is ion-implanted into a region where the collector lead-out region 14 is to be formed, thereby forming a diffusion prevention region 20. This state is shown in FIG.

Next, for example, boron ions are implanted into a region to be a collector extraction region to form a collector extraction region 14. Since the diffusion prevention region 20 is provided, the diffusion of boron by ions forming the diffusion prevention region 20 is suppressed.
At the time of ion implantation for formation, it is possible to reduce the diffusion of the collector lead-out region 14 in the horizontal direction, and it is possible to prevent a decrease in withstand voltage due to the proximity of the collector lead-out region 14 and the base region 6. This state is shown in FIG.

Next, an n-type base region 6 into which, for example, phosphorus or arsenic is introduced is formed on the collector layer 5, and a part of the base contact region 1 having a high impurity concentration is formed in a part of the base region 6.
5 is formed, a polycrystalline silicon film 9 is formed via an interlayer insulating film 8 covering the semiconductor substrate, and the polycrystalline silicon film 9 is formed through an opening provided in the interlayer insulating film 8 on the emitter region 7.
The emitter region 7 is formed by solid-phase diffusion of impurities from the substrate. This state is shown in FIG.

Thereafter, an interlayer insulating film 10 covering the interlayer insulating film 8 and the polycrystalline silicon film 9 is formed, and the base contact region 15, the polycrystalline silicon film 9, and the collector lead region 1 are formed.
An opening for exposing 4 is formed, a conductor film using aluminum or tungsten or the like is formed on interlayer insulating film 10, and this conductor film is patterned to form collector electrode 11, base electrode 12, emitter electrode 13 Is formed to obtain the state shown in FIG.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

For example, the semiconductor substrate used in the present invention is not limited to an SOI substrate, but may be of various forms such as a semiconductor substrate having a semiconductor layer such as an epitaxial layer formed on a semiconductor substrate, and a semiconductor substrate formed of a single body. May be included. In the above-described embodiment, the present invention has been described with respect to a pnp type bipolar transistor. However, an npn type bipolar transistor, a GST (Gate Selfalign Transistor)
The present invention can be applied to a transistor having an or) structure. Further, in the above-described embodiment, solid-phase diffusion is used for forming the emitter region. However, the emitter region is formed by diffusion from a phosphorus or arsenic-doped polycrystalline silicon film, and boron-doped polycrystalline silicon is formed. A two-layer polycrystalline silicon structure in which a base region is formed by diffusion from a film may be employed. Further, the emitter region may be formed by introducing another impurity without using solid-phase diffusion for forming the emitter region.

[0053]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, since it is not necessary to increase the energy of ion implantation for forming the collector extraction region, there is an effect that the collector extraction region can be prevented from expanding in the horizontal direction. (2) According to the present invention, at the time of ion implantation for forming the collector extraction region, there is an effect that the horizontal expansion of the collector extraction region can be prevented by the isolation insulating film. (3) According to the present invention, at the time of ion implantation for forming the collector extraction region, there is an effect that the diffusion prevention region can prevent the collector extraction region from expanding in the horizontal direction. (4) According to the present invention, the effects (1), (2), and (3) have an effect of preventing a decrease in withstand voltage between the collector and the base. (5) According to the present invention, there is an effect that it is not necessary to increase the width of the element isolation insulating film between the base region and the collector lead-out region. (6) According to the present invention, due to the effect (5), the maximum cutoff frequency f due to the increase in the capacitance between the collector and the substrate.
There is an effect that a decrease in Tmax can be prevented. (7) According to the present invention, the effect (5) has an effect that an increase in the layout area of the transistor can be prevented.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a main part of a conventional semiconductor device.

FIG. 2 is a longitudinal sectional view illustrating a main part of a semiconductor device according to an embodiment of the present invention;

FIG. 3 is a graph for comparing characteristics of a conventional semiconductor device and a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 5 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 6 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 7 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention.

FIG. 8 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention for each process.

FIG. 9 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention for each process.

FIG. 10 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention for each process.

FIG. 11 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention.

FIG. 12 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention for each process.

FIG. 13 is a vertical sectional view showing a main part of a semiconductor device according to another embodiment of the present invention for each process.

FIG. 14 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention for each process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor base, 2 ... Buried insulating film, 3 ... Semiconductor layer, 4 ...
Collector buried layer, 5: collector layer, 6: base region, 7
... Emitter region, 8,10 ... Interlayer insulating film, 9 ... Polycrystalline silicon film, 11 ... Collector electrode, 12 ... Base electrode, 1
3 ... emitter electrode, 14 ... collector lead-out area, 15
... base contact region, 16, 18 ... field insulating film, 17 ... trench insulating film, 19 ... isolation insulating film, 20 ...
Diffusion prevention area.

Continued on the front page (72) Inventor Takayuki Iwasaki 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Yoichi Tamaki 6-16, Shinmachi, Ome-shi, Tokyo 3 shares (72) Inventor Yoshinobu Chida 1 Nishiyokote-cho, Takasaki-shi, Gunma 1 Inside Hitachi Eastern Semiconductor Co., Ltd. (72) Inventor Kosuke Tsuji 5--22 Kamimizuhoncho, Kodaira-shi, Tokyo No. 1 F-term in Hitachi Ultra-LII Systems Co., Ltd. (Reference) 5F003 AP05 AP06 AZ03 BA11 BA25 BA27 BA97 BC02 BC08 BE07 BE08 BG03 BG10 BH18 BH99 BJ03 BP23 BP31 5F032 AA09 AA14 AA35 AA44 BB01 DA

Claims (5)

[Claims] 1. A collector layer is formed in a semiconductor substrate,
In a semiconductor device having a base region and an emitter region formed on a main surface of a semiconductor substrate and connecting the collector layer and a collector electrode formed on the main surface of the semiconductor substrate by a collector lead region, a trench is formed in the collector lead region. A semiconductor device, wherein the trench is filled with the collector electrode. 2. A collector layer is formed in a semiconductor substrate,
A base region and an emitter region are formed on the main surface of the semiconductor substrate, and the collector layer and a collector electrode formed on the main surface of the semiconductor substrate are connected by a collector extraction region,
A semiconductor device for separating a base region and a collector lead-out region by a field insulating film, wherein a trench is formed in the field insulating film, and a separating insulating film is formed by filling the trench with an insulating film. apparatus. 3. A collector layer is formed in a semiconductor substrate,
In a semiconductor device having a base region and an emitter region formed on a main surface of a semiconductor substrate and connecting the collector layer and a collector electrode formed on the main surface of the semiconductor substrate by a collector lead region, a diffusion prevention region is provided in the collector lead region. A semiconductor device, which is provided. 4. A collector layer is formed in a semiconductor substrate,
In a method for manufacturing a semiconductor device, a base region and an emitter region are formed on a main surface of a semiconductor substrate, and the collector layer and a collector electrode formed on the main surface of the semiconductor substrate are connected by a collector lead region. Forming a trench in a region, forming a collector lead-out region by introducing impurities from the trench, and embedding the trench with a conductive film serving as the collector electrode. Production method. 5. A collector layer is formed in a semiconductor substrate,
A base region and an emitter region are formed on the main surface of the semiconductor substrate, and the collector layer and a collector electrode formed on the main surface of the semiconductor substrate are connected by a collector extraction region,
In a method of manufacturing a semiconductor device in which the base region and the collector lead-out region are separated by a field insulating film, a step of forming the field insulating film; a step of forming a trench in the field insulating film; Forming a separation insulating film buried by the method.