JP2007273848A - Semiconductor device fabrication method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for ensuring improved etching control in terms of semiconductor fabrication method containing an insulating film dry etching process. <P>SOLUTION: This method forms a treatment film 12 which serves as an insulating film having a carbon element, on a stopper film 11 in an infrastructure 10. This method forms a mask pattern 13a on the treatment film, forms a hardened portion 12a on the treatment film by injecting energy such as an electron beam to the treatment film with the mask pattern set as a mask, and then forms a groove 12b by providing anisotropic etching to the hardened portion of the treatment film with the mask pattern set as a mask. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device that performs microfabrication on a semiconductor substrate, and more particularly to a method for manufacturing a semiconductor device including an etching process.

  The low-k material (low dielectric constant material), which is an interlayer insulating film that is being introduced in the manufacture of highly integrated semiconductor devices, is generally more difficult to control etching, and the processing depth cannot be controlled. A so-called piercing phenomenon is likely to occur. The same applies to the spread of processing in the horizontal direction as well as the vertical direction.

  In general, the processing depth of an insulating film is controlled by a method of processing a workpiece up to a position directly above the stopper film using an etching selection ratio between the film to be processed and a stopper film positioned therebelow. Here, when both the film to be processed and the stopper film are low-k materials, the above phenomenon is remarkable. This is because the low-k material tends to have a higher etching rate as described above than the non-low-k material such as an insulating film using TEOS (tetraethylorthosilicate) as a raw material. This is because they tend to be too high.

In addition, the manufacturing method of the semiconductor device which has an etching process relevant to this application has a thing disclosed by the following patent document, for example. Patent Document 1 discloses a double damascene type via contact, and Patent Document 2 discloses a structure using a low relative dielectric constant film among them. Patent Document 3 also discloses a semiconductor device having a double damascene structure. In this disclosure, via lithography is performed after formation of a hard mask groove. Both disclose a general technical level with respect to the contents of the present application.
JP 2000-3959 A JP 2002-217289 A JP 2000-349152 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device manufacturing method capable of improving etching process controllability in a semiconductor device manufacturing method including an etching step.

  A method of manufacturing a semiconductor device according to one embodiment of the present invention includes a step of forming a mask pattern on a film to be processed, and energy injection toward the film to be processed using the mask pattern as a mask to cure the film to be processed Forming a part, and etching the hardened part of the film to be processed using the mask pattern as a mask.

  According to the present invention, etching process controllability can be improved in a method of manufacturing a semiconductor device including an etching step.

  In the method for manufacturing a semiconductor device according to one embodiment of the present invention, a mask pattern is formed on a film to be processed, and energy is injected into the film to be processed using this mask to form a hardened portion in the film to be processed. Then, the cured portion of the film to be processed is etched using the same mask. That is, in this etching, the process controllability is improved because it is an etching of a hardened portion.

  As an embodiment, the film to be processed can be a material whose density is increased by the energy injection. Generally, physical and chemical changes occur in the film to be processed by energy injection, but in this case, a material that hardens and increases in density is used.

  Further, as an embodiment, the film to be processed has a relative dielectric constant of less than 3.0, and has a relative dielectric constant of less than 3.0 below the film to be processed in contact with the film to be processed. It can be assumed that a lower layer film made of a material different from the film to be processed is formed in advance. This is a case where both the film to be processed and the film below it (lower layer film: stopper film) are so-called low dielectric constant materials. In such a case, the contents of the present application are particularly useful. The relative dielectric constant of less than 3.0 is based on one of the general classification criteria.

  As an embodiment, the energy injection can be performed by electron beam irradiation. This is a typical method of energy injection.

  Here, it is preferable that the film thickness and density of the mask pattern are set to such a film thickness and density that electrons do not penetrate through irradiation with the electron beam. That is, the film thickness and density of the mask pattern in this case are set so that the lower film to be processed is not affected by the electron beam irradiation.

  Further, here, a lower layer film made of a material different from the processed film is previously formed on the lower side of the processed film in contact with the processed film, and the thickness and density of the lower layer film are It can be said that the film thickness and the density are set so that electrons do not penetrate through irradiation with the electron beam. This is because the function as a stopper film is further enhanced by limiting the lower layer film in this way. That is, when there is another film below the stopper film, the other film is prevented from being affected by electron beam irradiation.

  Further, as an embodiment, the energy injection can be performed by irradiation with light in an ultraviolet to visible region (wavelength 150 nm to 500 nm). It is another typical method of energy injection. The reason why the wavelength is set to 150 nm to 500 nm is that a more effective curing action can be expected when the material of the film to be processed of the semiconductor device is assumed.

  Here, the film to be processed has a composition containing a carbon element, and the irradiated light has a wavelength having a function of cutting a bond of the carbon element with respect to the composition of the film to be processed, and the mask The pattern may include a material having an absorption band including the wavelength having the effect. In the case where the film to be processed of the semiconductor device has a composition containing a carbon element, the film to be processed can be effectively cured by using light having a wavelength that acts to cut the bond between the carbon elements. Further, the mask pattern absorbs this wavelength so as not to affect the underlying film to be processed.

  Here, it can be assumed that the film to be processed is a SiOC-based material and the irradiated light has a wavelength of approximately 422 nm. In the case of a SiOC-based material, irradiation with light having a wavelength of approximately 422 nm can effectively break the bond between carbon elements, and the composition of the film to be processed increases in the proportion of SiO and hardens.

  As an embodiment, the etching may be performed by an RIE (reactive ion etching) method or a CDE (chemical dry etching) method. An anisotropic etching can be performed by the RIE method or the CDE method. Good controllability in the horizontal direction.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 and FIG. 2 are process drawings schematically showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. The steps proceed in the order of FIGS. 1 and 2, and in these drawings, the steps proceed in the order of (a), (b), and (c), or in the order of (a) and (b). In FIG. 1 and FIG. 2, the same or equivalent parts are denoted by the same reference numerals. This embodiment is an example for principle and general explanation.

  First, as shown in FIG. 1A, a laminated structure including a stopper film 11, a film to be processed 12, and a hard mask film 13 is formed on the lower structure portion 10. The lower structure portion 10 is a portion where at least a semiconductor substrate is included and various structures (for example, transistor elements and wiring structures) are formed thereon. The stopper film 11 and the processed film 12 are each made of, for example, a low-k material, and the hard mask film 13 is a film of a non-low-k material.

  More specifically, for example, the stopper film 11 is an insulating film based on the composition of SiC, the film to be processed 12 is an insulating film containing the composition of SiOC, and the hard mask film 13 is an insulating film using TEOS as a raw material (hereinafter, “ Also referred to as a “TEOS film”. These insulating films 11, 12, and 13 can be formed by, for example, a plasma CVD (chemical vapor deposition) method, a reactive sputtering method using a Si target and an O-based or N-based gas, vacuum deposition, or coating. The processed film 12 may actually have a multilayer structure as well as a single layer structure as shown.

  Generally, the element types contained in the stopper film 11 or the hard mask film 13 include Si, O, C, H, N, F, Ti, Co, W, Ta, Ru, Al, Cu, Mo, and Ge. , B, P, As, Mn, Br, Zn, Ni, Cr, Sn, Sb, In, Hf, Ag, Pt, and Zr. Moreover, the element seed | species which the to-be-processed film 12 contains can mention each element except a metal element among these elements.

  Next, as shown in FIG. 1B, a resist film 14 having a predetermined pattern is formed on the hard mask film 13. A well-known photolithography technique can be used for patterning the resist film 14. The pattern of the resist film 14 corresponds to the pattern to be processed of the processed film 12.

Subsequently, the hard mask film 13 is etched using the patterned resist film 14 as a mask. For this processing, for example, anisotropic etching such as CDE method or IRE method can be used. As the etching gas, when the hard mask film 13 is a TEOS film, for example, a gas containing an O-based gas or an NH ₃ -based gas can be used. The power, pressure, and gas flow rate during etching are adjusted so that the selection ratio between the hard mask film 13 and the film to be processed 12 can be secured. After etching the hard mask film 13, the resist film 14 can be removed. Thereby, as shown in FIG. 1C, the hard mask 13a is formed on the film 12 to be processed.

  Next, as shown in FIG. 2A, an electron beam (hereinafter also referred to as EB) is irradiated toward the film 12 to be processed using the hard mask 13a as a mask. As a result, a cured portion 12a is generated in the processed film 12 in accordance with the pattern of the hard mask 13a. The irradiation energy of the electron beam and the gas atmosphere at the time of irradiation are appropriately set so that the film to be processed 12 is cured in a range corresponding to the pattern of the hard mask 13a. The irradiation energy can be set to 2 to 3 keV, for example. This curing is due to the fact that when the film to be processed 12 is an insulating film containing a composition of SiOC, carbon bonds are cut at the molecular level and the proportion of SiO increases. The density increases as the proportion of SiO increases.

The thickness and density of the hard mask 13a are set so that electrons do not penetrate through the electron beam irradiation and do not affect the lower film 12 to be processed. More specifically, the film thickness and the density are set so as to satisfy, for example, “film thickness (μm) × density (g / cm ² )> A × V ^B ”. Here, A and B are constants, and V is an acceleration voltage (kV). The constant A is, for example, a value in the range of 0.01 <A <0.1 (0.0667 as an example), and the constant B is, for example, a value in the range of 1 <B <2 (as an example, 1.667). It is determined that the electron beam irradiation device and other conditions are fixed.

  It is preferable to set the thickness and density of the stopper film 11 located under the film 12 to be processed in the same way as the hard mask 13a. This is also because there is a concern that electrons may penetrate through the workpiece film 12 and the stopper film 11 by electron beam irradiation. Such penetration of electrons adversely affects the lower structural portion 10. In order to enhance the effect of preventing the penetration of electrons, the stopper film 11 may have a multilayer structure made of different materials instead of the single-layer structure shown in the figure. In the case of a multilayer structure, the film thickness can be made to correspond to the total film thickness, and the density can be made to correspond to the above-described film thickness and density, respectively.

  Next, the hardened portion 12a of the film 12 to be processed is removed by etching using the hard mask 13a as a mask to form an etched portion 12b (FIG. 2B). For this etching, for example, anisotropic etching such as CDE method or IRE method can be used. As the etching gas, when the film 12 to be processed is an insulating film containing a composition of SiOC, for example, a gas containing a gas such as a CF-based material or a CO-based material can be used. In general, a gas containing an element such as C, F, O, N, Ar, Cl, Br, H, or B can be used as a reaction gas. The power, pressure, and gas flow rate during etching are adjusted so that the selection ratio between the cured portion 12a of the film 12 to be processed and the stopper film 11 can be secured.

  In the etching shown in FIG. 2B, since the region of the hardened portion 12a formed in the film to be processed 12 is etched, the etching rate can be suppressed low. That is, the process controllability in the depth direction is improved, and even if the stopper film 11 is a Low-k film, the formation of a punch-through site with respect to this film can be suppressed. Therefore, it is a suitable etching method in a process in which an interlayer insulating film that is being introduced in the manufacture of highly integrated semiconductor devices is a low-k material. In general, when a low-k material is cured with EB or the like, there is a side effect that the dielectric constant of the portion increases. However, in this embodiment, the cured portion 12a is removed, so that it has an adverse effect as a manufactured semiconductor device. Don't be.

  Next, another embodiment of the present invention will be described with reference to FIGS. FIG. 3 and FIG. 4 are process diagrams schematically showing a method for manufacturing a semiconductor device according to another embodiment of the present invention. The steps proceed in the order of FIGS. 3 and 4, and in these drawings, the steps proceed in the order of (a), (b), and (c), or in the order of (a) and (b). 3 and 4, the same or equivalent parts are denoted by the same reference numerals, and the same or equivalent parts are used in the same or equivalent parts as those already described in FIGS. 1 and 2. . The description of the same or equivalent parts as those already described will be omitted unless they are added. This embodiment is also an example for the principle and general explanation.

  This embodiment is the same as the above-described embodiment in that a cured portion is formed in the film to be processed 12, and irradiation with light having a wavelength in the ultraviolet or visible region is used as the curing method. This will be described below. First, as shown in FIG. 3A, a laminated structure including a stopper film 11 and a film to be processed 12 is formed on the lower structure portion 10.

  Next, as shown in FIG. 3B, a resist film 15 having a predetermined pattern is formed on the film 12 to be processed. A well-known photolithography technique can be used for patterning the resist film 15. The pattern of the resist film 15 corresponds to the pattern to be processed of the processed film 12.

Next, as shown in FIG. 3C, light is irradiated toward the film 12 to be processed using the resist film 15 as a mask. As a result, a cured portion 12 a is generated in the processed film 12 in accordance with the pattern of the resist film 15. The wavelength of light can be approximately 422 nm when the film to be processed 12 is an insulating film containing a composition of SiOC, more specifically, when the film to be processed is SiOCH having a Si—CH ₃ bond. As a result, carbon bonds are broken at the molecular level, and the proportion of SiO is increased, resulting in a cured portion 12a. The density increases as the proportion of SiO increases. The wavelength of the irradiated light can be set to a wavelength at which the hardening effect appears more in consideration of the composition of the film 12 to be processed. Generally, the wavelength can be set to 150 nm to 500 nm (ultraviolet to visible range).

  As the material of the resist film 15, a material having a property that the wavelength of light to be irradiated becomes an absorption band is used. This is to prevent adverse effects on the film 12 to be processed located therebelow. That is, generally, assuming that the material of the film to be processed 12 is determined first, the wavelength of the light to be irradiated according to this material is determined as a wavelength with a large curing action of the film to be processed 12. Then, a resist film 15 made of a material that absorbs the wavelength is selected.

  Next, as shown in FIG. 4A, the cured portion 12a of the film 12 to be processed is removed by etching using the resist film 15 as a mask to form an etched portion 12b. In this etching, anisotropic etching such as CDE method or IRE method can be used as in the above embodiment. The etching gas is the same as in the above embodiment. After the formation of the etching site 12b, the resist film 15 is removed (FIG. 4B).

  Also in the etching in this embodiment, since the region of the hardened portion 12a formed in the film to be processed 12 is etched, the etching rate can be suppressed low. That is, the process controllability in the depth direction is improved, and even if the stopper film 11 is a Low-k film, the formation of a punch-through site with respect to this film can be suppressed. Therefore, it is a suitable etching method in a process in which an interlayer insulating film that is being introduced in the manufacture of highly integrated semiconductor devices is a low-k material. Also in this embodiment, the side effect that the dielectric constant of the cured portion increases does not adversely affect the manufactured semiconductor device because the cured portion 12a is removed.

  Next, a method for manufacturing a semiconductor device according to still another embodiment of the present invention will be described with reference to FIGS. 5, 6, and 7 are process diagrams schematically showing a cross-sectional view of a semiconductor device manufacturing method according to still another embodiment of the present invention. The process proceeds in the order of FIG. 5, FIG. 6, and FIG. 7, and the processes proceed in the order of (a), (b), and (c) in these drawings. In these drawings, the same or equivalent parts are denoted by the same reference numerals.

  This embodiment is an example of wiring formation by a so-called dual damascene process. As will be described later, electron beam irradiation is used for curing the film to be processed. As a premise, the following description will be given on the assumption that the structure shown in FIG. In the structure shown in FIG. 5A, an element formation site 50, interlayer insulating films 51 and 52, a lower wiring 53, a stopper film 54, processed films 55 and 56, and a hard mask film 57 are formed as shown. Yes.

  Supplementing FIG. 5A, the element formation portion 50 is a portion where at least a semiconductor substrate is included and an element such as a transistor element is formed thereon. The lower layer wiring 53 is a wiring extending in a direction perpendicular to the drawing sheet, and is made of, for example, Cu, and is electrically connected to an upper layer wiring (not shown) formed later through a via (not shown). The interlayer insulating films 51 and 52 (thicknesses are, for example, 100 nm and 50 nm, respectively) are interlayer insulating films that satisfy the same vertical position as the vertical position of the lower layer wiring 53.

  The stopper film 54 (thickness, for example, 50 nm), the processing film 55 (thickness, for example, 100 nm), and the processing film 56 (thickness, for example, 150 nm) are the stopper film 11, the processing film 12, and the hard mask film 13 in FIG. These are films corresponding to the above. That is, the film to be processed 55 and the stopper film 54 are films of Low-k material, respectively. Note that a via is formed in the processed portion of the processed film 55, and an upper layer wiring is formed in the processed portion of the processed film 56. The hard mask film 57 (thickness, for example, 75 nm) is a film serving as a mask for processing the upper processed film 56 in a predetermined manner.

  Following the state shown in FIG. 5A, a resist film 58 having a predetermined pattern is formed on the hard mask film 57 (FIG. 5B). A well-known photolithography technique can be used for patterning the resist film 58. The pattern of the resist film 58 corresponds to the pattern to be processed of the upper layer side processed film 56 (upper layer wiring pattern: width, for example, 200 nm).

Subsequently, the hard mask film 57 is etched using the patterned resist film 58 as a mask to form a hard mask 57a (FIG. 5C). For this processing, for example, anisotropic etching such as CDE method or IRE method can be used. As the etching gas, when the hard mask film 57 is a TEOS film, for example, a gas containing an O-based gas or an NH ₃ -based gas can be used. The power, pressure, and gas flow rate during etching are adjusted so that the selection ratio between the hard mask film 57 and the processed film 56 can be secured. After the hard mask 57a is formed, the resist film 58 is removed.

  Next, as shown in FIG. 6A, a resist film 59 in which a via pattern is formed is formed on the upper surface, and the processed film 56 is etched using the resist film 59 as a mask to process the processed film 56. A via pattern 56a (with a diameter of, for example, 100 nm) is formed. A well-known photolithography technique can be used for the patterning of the resist film 59. For the etching of the film 56 to be processed, anisotropic etching such as CDE method or IRE method can be used. After the via pattern 56a is formed on the film 56, the resist film 59 is removed.

  Next, as shown in FIG. 6B, the processing target film 56 is used as a mask to irradiate the target processing film 55 with an electron beam. As a result, a hardened portion 55 a is generated in the processed film 55 according to the via pattern 56 a of the processed film 56. For the stopper film 54 positioned under the film 55 to be processed, it is preferable that the thickness and density are set in advance as described above. This is to prevent electrons from penetrating from the stopper film 54 to the lower layer wiring 53 through the film 55 to be processed by electron beam irradiation.

  Next, the cured portion 55a of the processed film 55 is removed by etching using the processed film 56 as a mask to form a via hole 55b (FIG. 6C). For this etching, for example, anisotropic etching such as CDE method or IRE method can be used. As the etching gas, when the film 55 to be processed is an insulating film containing a composition of SiOC, for example, a gas containing a CF-based gas or a CO-based gas can be used. The power, pressure, and gas flow rate during etching are adjusted so that the selection ratio between the cured portion 55a of the film 55 to be processed and the stopper film 54 can be secured.

  Next, as shown in FIG. 7, the processed film 56 is etched using the hard mask 57a as a mask to form an upper wiring trench 56b. For this etching, for example, anisotropic etching such as CDE method or IRE method can be used. At this time, the power, pressure, and gas flow rate during etching are adjusted so that the selection ratio between the processed film 56 and the processed film 55 can be secured. Thereafter, although not shown, the stopper film 54 exposed to the via hole 55b is removed, and a buried portion made of Cu, for example, is formed in the via hole 55b and the upper wiring trench 56b. Thereby, an upper layer wiring that is electrically connected to the lower layer wiring 53 can be formed in the upper layer wiring trench 56b.

  In this embodiment, in the etching shown in FIG. 6C, the region of the hardened portion 55a formed in the film to be processed 55 is etched, so that the etching rate can be kept low. That is, the process controllability in the depth direction is improved, and even if the stopper film 54 is a Low-k film, the formation of a punch-through site with respect to this film can be suppressed. Therefore, it is suitable in a wiring formation process of a highly integrated semiconductor device in which a low-k material is used as an interlayer insulating film.

The process drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention with a typical cross section. FIG. 2 is a continuation diagram of FIG. 1, which is a process diagram schematically showing a cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Process drawing which shows the manufacturing method of the semiconductor device which concerns on another embodiment of this invention with a typical cross section. FIG. 4 is a continuation diagram of FIG. 3, which is a process chart showing in a schematic cross section a method for manufacturing a semiconductor device according to another embodiment of the present invention. Process drawing which shows the manufacturing method of the semiconductor device which concerns on another embodiment of this invention with a typical cross section. FIG. 6 is a continuation diagram of FIG. 5, and is a process diagram schematically showing a cross-sectional view of a method for manufacturing a semiconductor device according to still another embodiment of the present invention. FIG. 7 is a continuation diagram of FIG. 6, and is a process chart showing a method for manufacturing a semiconductor device according to still another embodiment of the present invention in a schematic cross section.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Substructure part, 11 ... Stopper film | membrane, 12 ... Processed film, 12a ... Hardening part, 12b ... Etching removal part, 13 ... Hard mask film | membrane, 13a ... Hard mask, 14 ... Resist film, 15 ... Resist film, DESCRIPTION OF SYMBOLS 50 ... Element formation part, 51 ... Interlayer insulation film, 52 ... Interlayer insulation film, 53 ... Lower layer wiring, 54 ... Stopper film, 55 ... Processed film (interlayer insulation film), 55a ... Hardening part, 55b ... Via hole, 56 ... Film to be processed (interlayer insulating film), 56a ... via pattern, 56b ... trench for upper layer wiring, 57 ... hard mask film, 57a ... hard mask, 58 ... resist film, 59 ... resist film.

Claims (5)

Forming a mask pattern on the film to be processed;
Using the mask pattern as a mask to inject energy toward the processed film to form a hardened portion in the processed film; and
Etching the cured portion of the film to be processed using the mask pattern as a mask. A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 1, wherein the energy injection is performed by electron beam irradiation.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the thickness and density of the mask pattern are set to such a thickness and density that electrons do not penetrate through irradiation of the electron beam.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the energy injection is performed by irradiation with light in an ultraviolet or visible region (wavelength of 150 nm to 500 nm). The film to be processed is a composition containing a carbon element,
The irradiated light is a wavelength having an action of cutting a carbon element bond with respect to the composition of the film to be processed;
The method of manufacturing a semiconductor device according to claim 4, wherein the mask pattern includes a material having an absorption band including the wavelength having the action.

Images