JP2007258708A - 基板計測のための縮小されたスクライブレーンの使用を有するリソグラフィ装置およびデバイス製造方法 - Google Patents
基板計測のための縮小されたスクライブレーンの使用を有するリソグラフィ装置およびデバイス製造方法 Download PDFInfo
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Abstract
【解決手段】パターンがパターニングデバイスから基板上に転写されるデバイス製造方法およびリソグラフィ装置では、計測ターゲットが第1波長の放射を使用して基板計測の実行を可能にする工程で基板上に提供される。続いて、計測ターゲットが導電材料のグリッド内で変換され、グリッドは第1波長より小さいグリッド開口部を有する。次に、計測ターゲットがあったスクライブレーン内のスペースは、覆い隠されて、基板の別の層または処理ステップで再度使用されてもよい。
【選択図】なし
Description
Claims (11)
- パターンをパターニングデバイスから基板に転写するように構成されたリソグラフィ装置であって、
第1波長を使用する特定の工程のための基板計測を可能にする、ウェーハ上の計測ターゲットを提供し、
前記第1波長より小さいグリッド開口部を有する導電材料のグリッド内で、前記計測ターゲットを変換する、リソグラフィ装置。 - 前記導電材料は金属である、請求項1に記載のリソグラフィ装置。
- 前記導電材料はドープされた半導体材料である、請求項1に記載のリソグラフィ装置。
- 前記計測ターゲットの前記変換は、前記基板の更なる処理中に実行される、請求項1に記載のリソグラフィ装置。
- 前記基板計測は、オーバーレイ計測、最小寸法計測、またはアライメント計測を含む、請求項1に記載のリソグラフィ装置。
- パターンをパターニングデバイスから基板上に転写することを含むデバイス製造方法であって、
第1波長の放射を使用して基板計測を実行可能にする工程において、計測ターゲットを前記基板上に提供することと、
前記第1波長より小さいグリッド開口部を有する導電材料のグリッド内で、前記計測ターゲットを変換することを有する、方法。 - 前記導電材料は金属である、請求項6に記載のデバイス製造方法。
- 前記導電材料はドープされた半導体材料である、請求項6に記載のデバイス製造方法。
- 前記変換は、前記基板の更なる処理中に実行される、請求項6に記載のデバイス製造方法。
- 前記基板計測は、オーバーレイ計測、最小寸法計測、またはアライメント計測を含む、請求項6に記載のデバイス製造方法。
- 請求項6に記載の方法に従って製造されるデバイス。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US11/384,836 US7486408B2 (en) | 2006-03-21 | 2006-03-21 | Lithographic apparatus and device manufacturing method with reduced scribe lane usage for substrate measurement |
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JP2007258708A true JP2007258708A (ja) | 2007-10-04 |
JP4541374B2 JP4541374B2 (ja) | 2010-09-08 |
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JP2007064637A Active JP4541374B2 (ja) | 2006-03-21 | 2007-03-14 | 基板計測のための縮小されたスクライブレーンの使用を有するリソグラフィ装置およびデバイス製造方法 |
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