JP2007234985A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the concentration of a catalyst element included in a crystalline semiconductor layer of a thin film transistor. <P>SOLUTION: The method for manufacturing a semiconductor device comprises: a process for preparing an amorphous semiconductor film 104a to which a catalyst element 105 for accelerating crystallization is at least partially added; a process for crystallizing at least a part of the amorphous semiconductor film 104a by treating the amorphous semiconductor film 104a by first heat treatment to obtain a crystalline semiconductor film 104p including crystalline region; a process for forming a reflection prevention layer 108 for exposing at least a part of the crystalline region on the surface of the crystalline region; a process for forming a recrystallized region 104r by recrystallizing the exposed portion out of the crystalline region by irradiating the crystalline semiconductor film 104p with a laser beam and forming a gettering region 104g including an amorphous semiconductor on the portion covered with the reflection prevention layer out of the crystalline semiconductor film 104p; and a process for moving at least a part of the catalyst element 105 in the recrystallized region to the gettering region by treating the crystalline semiconductor film 104p by second heat treatment. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device including a thin film transistor (hereinafter abbreviated as “TFT”).

  In recent years, high-resolution liquid crystal display devices and organic EL display devices, high-speed, high-resolution contact image sensors, three-dimensional ICs, etc. have been developed on insulating substrates such as glass and insulating films. Attempts have been made to form high performance semiconductor devices. In particular, a liquid crystal display device in which a pixel portion and a driving circuit are provided on the same substrate has been used not only as a monitor for a personal computer (PC) but also in various applications, and has entered the general household. I'm starting. For example, instead of CRT (Cathode-ray Tube), a liquid crystal display is introduced as a television, and a liquid crystal front projector for watching movies and playing games as an entertainment has been introduced into ordinary households. The market size of display devices is growing at a considerable rate. Furthermore, development of a system-on-panel in which a logic circuit such as a memory circuit or a clock generation circuit is built on a glass substrate is being promoted.

  If you try to display a high-resolution image, the amount of information to be written to the pixels will increase, and if that information is not written in a short time, a high-definition image with such an enormous amount of information can be displayed as a moving image. Impossible. For this reason, the TFT used in the driver circuit is required to operate at a higher speed. In order to enable high-speed operation, it is required to form a TFT using a crystalline semiconductor film having good crystallinity that can provide high field effect mobility.

  As a method for obtaining a high-quality crystalline semiconductor film on a glass substrate, the present inventors add a metal element (catalyst element) having an action of promoting crystallization to an amorphous semiconductor film, and then perform heat treatment. As a result, we have developed a technology that can provide a good semiconductor film with uniform crystal orientation by low-temperature and short-time heat treatment.

  However, a TFT manufactured using a crystalline silicon film obtained by using a catalytic element as a semiconductor layer as it is has a problem that off-current suddenly increases. In the crystalline silicon film, the catalyst element segregates irregularly, and it has been confirmed that such segregation is particularly remarkable at the grain boundary. This segregated catalytic element is considered to be a current escape path (leakage path), causing a sudden increase in off-current. Therefore, it is necessary to reduce the concentration of the catalytic element in the semiconductor film by moving the catalytic element from the semiconductor film after the crystalline silicon film manufacturing process.

  Note that in this specification, removing a catalytic element from a semiconductor film or a predetermined region (a channel region or an active region) of the semiconductor film is referred to as “gettering”. The “active region” of the TFT refers to a region of the island-like semiconductor layer where electrons or holes move during the operation of the TFT, and includes a source and drain region, a channel region, an LDD region, etc., and has a gettering function. The area (“gettering area”) is not included.

  According to a conventionally used gettering method, a gettering region is formed in a crystalline semiconductor film, and a catalytic element is moved thereto, so that an island-like semiconductor layer of a TFT, an active region of a TFT, The catalyst element concentration in the channel region is reduced. Such gettering methods include the following two methods, for example, focusing on the relationship between the island-like semiconductor layer and the gettering region.

  (A) A gettering region is formed in the semiconductor layer, and the catalytic element is moved there, so that only a portion where the remaining of the catalytic element is particularly problematic in the semiconductor layer (such as a channel region) is gettered.

  (B) A gettering region is formed in a region other than the region to be an island-shaped semiconductor layer in the crystalline semiconductor film, and the catalytic element is moved there.

  In the above method (A), for example, as proposed in Patent Documents 1 to 4, after the crystalline silicon film is patterned to form a plurality of island-like semiconductor layers each serving as a TFT, the island-like semiconductor is formed. A gettering region is formed in a part of the layer. Next, by performing heat treatment, the catalyst element contained in the channel region or the active region in the island-shaped semiconductor layer is moved to the gettering region.

  Among them, the technique proposed in Patent Document 1 uses an amorphous region formed by amorphizing a part of the island-like semiconductor layer as the gettering region. Further, in the methods proposed in Patent Documents 2 to 4, an element belonging to Periodic Table Group 5 B having an action of moving a catalyst element (referred to as a “gettering element”, typically phosphorus, arsenic, etc .: It is also an impurity element imparting n-type). Specifically, Patent Document 2 discloses that a gettering region is formed by doping the gettering element in a region to be a source and drain region of an island-shaped semiconductor layer. Furthermore, according to the method proposed in Patent Documents 3 and 4 by the present applicant, a gettering region is formed by doping a gettering element in a region other than a region to be an active region in the island-like semiconductor layer, The catalytic element in the active region of the semiconductor layer is moved to the gettering region.

  The method (A) has an advantage that the manufacturing process can be simplified because gettering can be performed by using a doping process for forming the source / drain regions. However, since heat treatment for gettering is performed after the island-shaped semiconductor layer is formed, shrinkage or warpage may occur in the glass substrate. If it is going to avoid this, the heating temperature and heating time for gettering will be restricted.

  On the other hand, in the method (B) described above, as proposed in Patent Document 5, for example, a crystalline semiconductor film crystallized using a catalytic element is formed, and then the crystalline semiconductor film is patterned. First, gettering is performed on a region to be an island-shaped semiconductor layer in the crystalline semiconductor film. Specifically, a gettering region is formed by selectively introducing a group 5 B element such as phosphorus into a part of the crystalline silicon film. Next, by performing heat treatment, the catalytic element in the crystalline semiconductor film is moved to the gettering region. Thereafter, the crystalline semiconductor film is patterned to remove the gettering region and use the region other than the gettering region in the crystalline semiconductor film (that is, the region where the catalytic element concentration is reduced) to form the island-shaped semiconductor layer Form.

  According to the above method (B), the heat treatment for gettering is performed before the island-shaped semiconductor layer is formed. Therefore, the heat treatment conditions for gettering are limited in order to avoid shrinkage or warping of the glass substrate. This is not necessary and sufficient gettering can be performed.

  Hereinafter, an example of a method for manufacturing a TFT using the gettering technique disclosed in Patent Document 5 will be described with reference to the drawings.

  First, as shown in FIG. 5A, a base film (silicon oxide film) 202 and a silicon film (a-Si film) 203 having an amorphous structure are formed in this order on the surface of the substrate 201 on which the TFT is formed. After the formation, a catalytic element (nickel) containing layer 204 is formed on the surface of the a-Si film 203.

  Subsequently, the substrate 201 is subjected to a heat treatment (first heat treatment) in an inert atmosphere, for example, in a nitrogen atmosphere to crystallize the a-Si film 203. Thereby, as shown in FIG. 5B, a crystalline silicon film 205 is obtained.

  By irradiating the obtained crystalline silicon film 205 with laser light, as shown in FIG. 5C, a crystalline silicon film 206 in which the crystallinity of the crystalline silicon film 205 is further improved is formed.

  Next, a resist layer 207 is formed on a region (gettering region) 210 where nickel is to be reduced in the crystalline silicon film 206, and this is used as a mask to getter the crystalline silicon film 206. Doping of element (phosphorus) is performed. As a result, as shown in FIG. 5D, phosphorus is doped in the portion of the crystalline silicon film 206 that is not covered with the resist layer 207 to form gettering regions 208 and 209.

  After removing the resist layer 207, as shown in FIG. 5E, heat treatment for gettering is performed to move nickel remaining in the gettering region 210 to the gettering regions 208 and 209. As a result, the nickel concentration in the gettering region 210 can be reduced.

  Next, as shown in FIG. 5F, the crystalline silicon film 206 is patterned to remove the gettering regions 208 and 209, thereby obtaining an island-shaped semiconductor layer 212 with a reduced nickel concentration.

Thereafter, although not shown, a gate insulating film and a gate electrode are formed on the island-shaped semiconductor layer 212, and a channel region, a source and a drain region are formed on the island-shaped semiconductor layer 212, thereby manufacturing a TFT. be able to.
JP-A-8-213317 JP-A-8-330602 JP 2004-214507 A JP 2005-251794 A Japanese Patent Laid-Open No. 10-270363

  However, according to the method disclosed in Patent Document 5, the doping mask (resist layer) 207 is formed in order to cause a region other than the region to be the island-shaped semiconductor layer in the crystalline silicon film 206 to function as a gettering region. And a doping step for introducing a gettering element (phosphorus) into the crystalline silicon film 206 are added. Therefore, there is a problem that the manufacturing process becomes complicated and the manufacturing cost increases.

  The present invention has been made in view of the above problems, and an object of the present invention is to reduce the concentration of a catalytic element contained in a crystalline semiconductor layer of a thin film transistor without complicating the manufacturing process in a semiconductor device including the thin film transistor. There is.

  The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device including a thin film transistor, and (a) a step of preparing an amorphous semiconductor film to which a catalytic element for promoting crystallization is added at least partially. And (b) performing a first heat treatment on the amorphous semiconductor film to crystallize at least a part of the amorphous semiconductor film to obtain a crystalline semiconductor film including a crystalline region. And (c) forming an antireflection layer that exposes at least a part of the crystalline region on the crystalline region, and (d) irradiating the crystalline semiconductor film with a laser to thereby form the crystalline region. Forming a recrystallized region by recrystallizing an exposed portion of the crystal, and forming a gettering region including an amorphous semiconductor in a portion of the crystalline semiconductor film covered with the antireflection layer And (e) By performing the second heat treatment with respect to the serial crystalline semiconductor film includes a step of moving at least a portion of the catalyst element in the recrystallized region to the gettering region.

  In a preferred embodiment, the step (c) is a step of forming an antireflection layer that exposes a region of the crystalline region where an island-like semiconductor layer is to be formed on the crystalline region.

  The antireflection layer may include silicon oxide.

  The antireflection layer may be a silicon oxide layer, and the thickness of the silicon oxide layer may be 100 nm or less.

  In a preferred embodiment, after the step (e), (f) removing the antireflection layer and the gettering region to form an island-shaped semiconductor layer including at least a part of the recrystallized region. In addition.

  In a preferred embodiment, after the step (f), (g) a step of forming an insulating film on the island-shaped semiconductor layer; and (h) a getter having a gettering capability in a part of the island-shaped semiconductor layer. A step of forming another gettering region by adding a ring element; and (i) performing a third heat treatment on the island-shaped semiconductor layer to thereby form the other island-shaped semiconductor layer. And a step of moving at least a part of the catalytic element in a region other than the gettering region to the other gettering region.

  The step (h) may be a step of forming another gettering region by adding the gettering element to a region other than a region to be an active region of the island-shaped semiconductor layer.

  Between the step (g) and the step (h), (g ′) the gate insulating film located on a region other than the region which becomes the active region in the island-like semiconductor layer is selectively thinned or selectively The step (h) further includes a gettering region by adding a gettering element to a region where the gate insulating film on the island-like semiconductor layer is thinned or removed. It may be a process to do.

  Preferably, before the step (i), the method further includes a step of doping an impurity element into a region of the island-shaped semiconductor layer in which a source and drain region is to be formed, and the third heat treatment Then, the impurity element doped in the island-like semiconductor layer is activated.

  The catalyst element may include one or more elements selected from Ni, Co, Sn, Pb, Pd, Fe, and Cu.

  According to the present invention, the concentration of the catalytic element in the crystalline semiconductor layer formed using the catalytic element can be reduced by a simpler process than before. Accordingly, defects due to the catalytic element remaining in the crystalline semiconductor layer can be reduced, and a semiconductor device including a highly reliable and high performance thin film transistor can be provided.

  In the method for manufacturing a semiconductor device according to the present invention, a gettering region is formed in the crystalline semiconductor film by utilizing a step of recrystallizing the crystalline semiconductor film by laser irradiation. Therefore, it is possible to suppress an increase in the number of manufacturing steps and manufacturing costs due to gettering. The “semiconductor device” in this specification only needs to include a thin film transistor having a semiconductor layer as an active layer, and includes a thin film transistor, an active matrix substrate, a liquid crystal display device, and the like.

(First embodiment)
Hereinafter, a first embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. In this embodiment, an island-like crystalline silicon layer (island-like semiconductor layer) having a reduced catalytic element concentration is formed from a crystalline silicon film crystallized using a catalytic element, and a TFT is formed using the island-like crystalline silicon layer (island-like semiconductor layer). Make it.

  FIGS. 1A to 1E and FIGS. 2A to 2D are process cross-sectional views for explaining a method for forming an island-shaped semiconductor layer in the present embodiment, and FIGS. d) is a top view corresponding to the process shown to Fig.2 (a)-(d), respectively. Note that for the sake of simplicity, a process of forming a single island-shaped semiconductor layer from a crystalline semiconductor film is illustrated, but a plurality of island-shaped semiconductor layers are typically formed from a crystalline semiconductor film.

  First, as shown in FIG. 1A, base films 102 and 103 and an amorphous silicon (a-Si) film 104a are formed in this order on the surface of a substrate 101 on which a TFT is to be formed.

The substrate 101 only needs to have an insulating surface, and may be, for example, a low alkali glass substrate or a quartz substrate. In this embodiment, a low alkali glass substrate is used as the substrate 101. In this case, the substrate 101 may be heat-treated in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. The base films 102 and 103 are provided to prevent impurity diffusion from the substrate 101, and may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. In this embodiment, a silicon oxynitride film is formed as a lower first base film 102 by using, for example, a material gas of SiH ₄ , NH ₃ , and N ₂ O by a plasma CVD method. Further, as the second base film 103, a silicon oxide film is similarly formed on the first base film 102 using TEOS and oxygen as material gases by plasma CVD. At this time, the thickness of the first base film (silicon oxynitride film) 102 is preferably 25 to 400 nm, for example, 100 nm. The thickness of the second base film (silicon oxide film) 103 is preferably 25 to 300 nm, for example, 100 nm. In the present embodiment, a base film composed of two layers is formed, but the base film may be a single layer of a silicon oxide film, for example.

  The a-Si film 104a can be formed by a known method such as a plasma CVD method or a sputtering method. The thickness of the a-Si film 104a is, for example, 20 to 150 nm, preferably 30 to 80 nm. In the present embodiment, an a-Si film having a thickness of 50 nm is formed by plasma CVD.

  Note that it is preferable that the base films 102 and 103 and the a-Si film 104a be continuously formed without being exposed to an air atmosphere using a multi-chamber plasma CVD apparatus. As a result, it is possible to prevent contamination of the interface between the base film 103 and the a-Si film 104a (which becomes a back channel in the TFT), and to reduce variation in characteristics and threshold voltage of the TFT to be manufactured. it can.

Subsequently, as shown in FIG. 1B, a catalytic element 105 is added on the surface of the a-Si film 104a. In the present embodiment, nickel is used as the catalyst element 105. In addition, nickel is added to the a-Si film 104a by holding a solution in which nickel is dissolved on the a-Si film 104a, and then uniformly extending the solution onto the substrate 101 by a spinner and drying the solution. . Nickel acetate can be used as the solute of the solution, and water can be used as the solvent. Further, the nickel concentration in the solution is adjusted to be, for example, 5 ppm in terms of weight. The amount of catalytic element added by this process is extremely small. The concentration of the catalytic element on the surface of the a-Si film 104a is controlled by a total reflection X-ray fluorescence (TRXRF) method, and is, for example, about 5 × 10 ¹² atoms / cm ² .

  In addition to nickel (Ni), the catalyst element 105 may be one or more selected from iron (Fe), cobalt (Co), tin (Sn), lead (Pb), palladium (Pd), and copper (Cu). It may be an element. Although the catalytic effect is smaller than these elements, ruthenium (Ru), rhodium (Rh), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), and the like also function as the catalytic element 105. As a method for adding the catalyst element 105 to the a-Si film 104a, a gas phase method such as a plasma doping method, a vapor deposition method, or a sputtering method may be used in addition to a method of applying a solution containing the catalyst element. it can. The method of applying a solution containing a catalytic element is advantageous because the amount of the catalytic element added can be easily controlled and a trace amount of the catalytic element can be easily added.

  Thereafter, the substrate 101 is subjected to heat treatment (first heat treatment) in an inert atmosphere, for example, in a nitrogen atmosphere. As this heat treatment, it is preferable to perform an annealing treatment at 550 to 620 ° C. for 30 minutes to 4 hours. In this embodiment, as an example, heat treatment is performed at 590 ° C. for 1 hour. By this heat treatment, nickel 105 added to the surface of the a-Si film 104a is diffused into the a-Si film 104a, and silicidation occurs, and crystallization of the a-Si film 104a proceeds using this as a nucleus. As a result, as shown in FIG. 1C, the a-Si film 104a is crystallized into a crystalline silicon film 104p. Note that although crystallization is performed here by heat treatment using a furnace, crystallization may be performed by an RTA (Rapid Thermal Annealing) apparatus using a lamp or the like as a heat source.

  Prior to the heat treatment, the surface of the a-Si film 104a may be slightly oxidized with ozone water or the like in order to improve the wettability of the surface of the a-Si film 104a during spin coating.

  The crystal plane orientation of the crystalline silicon film 104a thus obtained is mainly composed of the <111> crystal zone plane, and among them, (110) plane orientation and (211) plane orientation are 50% of the whole. These areas are occupied. Moreover, the domain diameter of the crystal domain (substantially the same plane orientation region) is 2 to 10 μm.

Subsequently, as shown in FIG. 1D, after a film 107 having an antireflection effect is formed on the crystalline silicon film 104p, a resist layer 109 is formed. In the present embodiment, the resist layer 109 is provided so as to cover a region other than the region to be the island-shaped semiconductor layer in the crystalline silicon film 104p. Note that the resist layer 109 may be provided so as to expose at least a part of the crystalline region in the crystalline silicon film 104p, and the planar shape thereof is not particularly limited. The film 107 may be a single layer or may have a stacked structure. In the present embodiment, a SiO ₂ film (single layer) having a thickness of about 100 nm or less (for example, 50 nm) is used.

  Thereafter, as shown in FIG. 1E, the film 107 is etched using the resist layer 109 as a mask to obtain the antireflection layer 108. As a result, a region to be an island-shaped semiconductor layer in the crystalline silicon film 104p is exposed.

  Next, by irradiating the crystalline silicon film 104p with laser light, as shown in FIGS. 2A and 3A, a recrystallized region 104r having higher crystallinity than the crystalline silicon film 104p, Then, a gettering region 104g containing amorphous silicon is formed.

  The above process will be described in more detail. Of the crystalline silicon film 104p obtained by solid phase crystallization, the portion exposed from the antireflection layer 108 (that is, the region that becomes the island-like semiconductor layer) is reduced in crystal defects by the melting and solidifying process by laser irradiation. Thus, the recrystallized region 104r made of a higher quality crystalline silicon film is obtained. Even after this laser irradiation step, the crystal plane orientation and crystal domain state before laser irradiation are maintained as they are, and no significant change is observed in the EBSP measurement. On the other hand, in the region covered with the antireflection layer 108 in the crystalline silicon film 104p, the action of the antireflection layer 108 increases the effective laser irradiation energy, thereby reducing the crystallinity of the crystalline silicon film 104p. As a result, a gettering portion 104g having lower crystallinity than the crystalline silicon film 104p is obtained. The obtained gettering portion 104g includes an amorphous region at least partially.

  In this step, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) is used as the laser light, but a KrF excimer laser (wavelength 248 nm) may be applied instead. The beam size of the laser light is formed to be a long shape on the surface of the substrate 101, and the entire surface of the substrate can be irradiated by scanning sequentially in a direction perpendicular to the long direction. At this time, when scanning is performed so that parts of the beams overlap, laser irradiation is performed a plurality of times at an arbitrary point on the crystalline silicon film 104p, so that laser irradiation can be performed more uniformly.

In the crystalline silicon film 104p, the irradiation energy of the laser light applied to the portion exposed from the antireflection layer 108 is too low if the crystallinity improving effect is small, and if too high, the crystalline silicon film 104p obtained in the previous step is too high. Therefore, it is necessary to set an appropriate range, for example, 300 to 400 mJ / cm ² . Further, the effective laser irradiation energy applied to the portion of the crystalline silicon film 104p covered with the antireflection layer 108 is controlled to, for example, 300 mJ / cm ² or more in order to make the crystalline silicon film 104p amorphous. Need to be done. This effective laser irradiation energy can be controlled by the wavelength of the laser light, the material and thickness of the antireflection layer 108, and the like.

  Subsequently, as shown in FIGS. 2B and 3B, the second heat treatment is performed to move the catalytic element in the recrystallization region 104r to the gettering region 104g. As described above, since the gettering region 104g includes an amorphous region, the catalytic element remaining in the recrystallization region 104r can be moved to the amorphous region by performing heat treatment.

  The reason why the catalytic element can move to the amorphous region is that the free energy of the catalytic element in the amorphous region is lower than that of the crystalline region, so that the catalytic element easily diffuses into the amorphous region, This is because, in the mass region, a dangling bond or a lattice defect forms a segregation site for trapping the catalyst element, so that a gettering action of moving and trapping the catalyst element to the segregation site can be obtained.

As the second heat treatment, it is preferable to perform annealing for several minutes to several hours at a temperature of 400 ° C. to 800 ° C. More preferably, annealing is performed at a temperature of 550 ° C. to 750 ° C. for 0.5 minutes to 10 minutes. By this step, the concentration of the catalytic element in the recrystallization region 104r can be reduced to, for example, about 1 × 10 ¹⁶ atoms / cm ³ or less.

  In this embodiment, the gettering is performed with the antireflection layer 108 left on the gettering region 104g. However, after the laser irradiation process, the antireflection layer 108 is removed and then the same gettering is performed. Can also be done.

  Thereafter, as shown in FIGS. 2C and 3C, a resist layer 110 covering at least a part of the recrystallized region 104r is formed on the recrystallized region 104r. The antireflection layer 108 is exposed from the resist layer 110. As illustrated, the resist layer 110 in the present embodiment has a planar shape corresponding to the planar shape of the recrystallized region 104r. The resist layer 110 is preferably thicker than the gettering region 104g, and the thickness is, for example, not less than 0.5 μm and not more than 2 μm.

Subsequently, the antireflection layer 108 and the gettering region 104g are etched using the resist layer 110 as a mask. In this embodiment, an etchant (for example, BHF) used for etching the antireflection layer 108 is different from an etchant (for example, CF ₄ + O ₂ ) used for etching the gettering region 104g. Therefore, it is necessary to perform etching (second etching) on the gettering region 104g after performing etching (first etching) on the antireflection layer 108 using the same mask (resist layer 110). Note that in the case where the resist layer 110 is formed so as to cover a part of the recrystallization region 104r, a portion of the recrystallization region 104r that is not covered with the resist layer 110 is also gettered by the second etching. It is removed together with the ring region 104g.

  Thereafter, when the resist layer 110 is removed, an island-shaped semiconductor layer 112 made of a recrystallized crystalline semiconductor is obtained, as shown in FIGS. 2D and 3D.

  A TFT is manufactured using the island-shaped semiconductor layer 112 thus obtained. A method for manufacturing a TFT from the island-shaped semiconductor layer 112 is not particularly limited, and a known method can be used.

  According to the above method, the concentration of the catalytic element in the region that becomes the island-like semiconductor layer of the TFT in the crystalline silicon film 104p can be reduced by gettering using the amorphous silicon region. Further, in the steps shown in FIGS. 2A and 3A, when the crystalline silicon film 104p is irradiated with a laser, the antireflection layer 108 is used so as to correspond to the position of the crystalline silicon film 104p. Since the effective laser irradiation energy can be controlled, the crystalline silicon film 104p can be recrystallized and the gettering region 104g can be formed. As described above, the gettering region 104g is formed by utilizing the recrystallization process of the crystalline silicon film 104p by laser irradiation. Thus, for example, as in the method disclosed in Patent Document 5 (FIG. 5), the gettering region It is not necessary to separately perform the step of forming (for example, the step shown in FIG. 5D), and the manufacturing process can be simplified as compared with the prior art.

(Second Embodiment)
The second embodiment of the semiconductor device manufacturing method according to the present invention will be described below.

  In the present embodiment, a method similar to the method described in the first embodiment with reference to FIGS. 1A to 1E, FIGS. 2A to 2D, and FIGS. 3A to 3D. After the island-like semiconductor layer 112 is formed, a gettering region is formed in the island-like semiconductor layer 112 and further gettering is performed, and a catalytic element is formed from the region that becomes the channel region or the active region in the island-like semiconductor layer 112. Is further reduced.

  In this embodiment, gettering performed before patterning the crystalline semiconductor film (that is, gettering as described with reference to FIGS. 2B and 3B) is performed as “first gettering”. The additional gettering performed by forming a gettering region in the island-like semiconductor layer 112 obtained by patterning the crystalline semiconductor film is referred to as “second gettering”.

  According to the method of the present embodiment, even if the catalyst element that has not been removed from the recrystallization region 104r by the first gettering remains in the active region and the channel region in the island-like semiconductor layer 112, The remaining catalytic element can be moved to the gettering region formed in the island-shaped semiconductor layer 112 by the gettering of 2. As described above, since gettering is performed in two stages, the concentration of the catalytic element in the active region and the channel region in the island-like semiconductor layer 112 can be further reduced, and the decrease in the reliability of the TFT due to the catalytic element can be more effectively suppressed.

  The second gettering method in the present embodiment is not particularly limited, but the second gettering method is performed using a step of doping the island-like semiconductor layer 112 with an impurity and an activation annealing step of activating the doped impurity. It is preferable to perform the gettering because an increase in the number of manufacturing steps can be suppressed.

  In the second gettering, for example, as disclosed in Patent Document 3 by the present applicant and Patent Document 4 by the present applicant, gettering is performed in a region other than the region serving as the active region of the TFT in the island-shaped semiconductor layer 112. A ring region may be formed to reduce the catalytic element in the region that becomes the active region. In the methods disclosed in Patent Documents 3 and 4, after a gate insulating film provided on a region to be a gettering region in the island-like semiconductor layer is selectively thinned or removed, the gettering element is then removed from the island-like semiconductor layer. By doping the gettering region, a gettering region is formed by a simpler process. Further, since it is not necessary to remove the gettering region after gettering, not only the number of steps can be reduced, but also the catalyst element remaining after gettering can be prevented from being silicided again in the subsequent heat treatment step.

  Alternatively, as disclosed in Patent Document 2, a gettering element is formed by doping a region of the island-like semiconductor layer 112 that becomes a source and drain region of a TFT with a gettering element, and the region that becomes a channel region The catalytic element may be reduced.

  Hereinafter, an example of a method for manufacturing an n-channel TFT from the island-shaped semiconductor layer 112 will be described with reference to FIGS. In this example, as in the methods disclosed in Patent Documents 3 and 4, a gettering region is formed in a region other than the region to be an active region in the island-shaped semiconductor layer 112, and second gettering is performed.

  First, as shown in FIG. 4A, a gate insulating film 120 that covers the island-like semiconductor layer 112 is formed. The island-like semiconductor layer 112 is formed by the same method as described above with reference to FIGS. 1A to 1E, FIGS. 2A to 2D, and FIGS. 3A to 3D. The The gate insulating film 120 is preferably a silicon oxide film (thickness: 20 to 150 nm). Here, a silicon oxide film having a thickness of 100 nm is used. Here, the silicon oxide film is formed by using TEOS (Tetra Ethoxy Ortho Silicate) as a raw material and decomposing / depositing it with RF at a substrate temperature of 150 to 600 ° C., preferably 300 to 450 ° C. together with oxygen. Do. After forming the silicon oxide film, in order to improve the bulk characteristics of the gate insulating film 120 and the interface characteristics between the crystalline silicon film and the gate insulating film 120, a few minutes to several times at 500 to 700 ° C. in an inert gas atmosphere. Time annealing may be performed. The gate insulating film 120 may be a single layer of an insulating film containing other silicon or may have a stacked structure.

  Next, as shown in FIG. 4B, a gate electrode (thickness: for example, 300 to 500 nm) 122 is formed on the gate insulating film 120. The gate electrode 122 is obtained by forming a conductive film on the gate insulating film 120 and etching the conductive film. As a material of the conductive film, for example, an element selected from the group consisting of tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the element as a main component, or the element A combined alloy film (typically, a Mo—W alloy film or a Mo—Ta alloy film) can be used. Note that the gate electrode 122 may have a stacked structure as shown in Patent Document 4, for example, a conductive film (A) made of a conductive nitride metal film and a conductive film (B) made of a metal film. A two-layer structure including As a material of the conductive film (B), tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, molybdenum nitride (MoN), tungsten silicide, titanium silicide, molybdenum silicide, or the like may be used.

  Next, as shown in FIG. 4C, an n-type impurity (phosphorus) 124 is implanted into the island-like semiconductor layer 112 at a high concentration by ion doping using the gate electrode 122 as a mask. Through this step, high-concentration phosphorus 124 is implanted into the region 126 of the island-like semiconductor layer 112 that is not covered with the gate electrode 122. In this step, the region 128 that is masked by the gate electrode 122 and is not implanted with phosphorus 124 later becomes a channel region of the TFT.

  As shown in FIG. 4D, a mask 130 made of resist is formed on the gate insulating film 120 so as to cover the gate electrode 122 and a part of the region 126, and this is used to form the gate insulating film 120. Etching is performed. Thus, the selectively etched gate insulating film 120 is formed. At this time, a portion (outer edge portion) of the semiconductor layer 112 is exposed by the mask 130 and the gate insulating film 120.

  Next, a rare gas element (Ar in this embodiment) 132 is ion-doped from above the substrate 101. By this step, as shown in FIG. 4E, a rare gas element (gettering element) 132 is implanted into the exposed region of the TFT active region, and a gettering region 134 is formed. A region covered with the mask 130 and the gate insulating film 120 is not doped with the rare gas element 132, and becomes a source and drain region 136 of a later TFT. As the rare gas element at this time, one or more kinds of rare gas elements selected from Ar, Kr, and Xe can be used. Further, by this step, the gettering region 134 is strongly doped in the absence of the gate insulating film, so that the crystallinity is completely destroyed and becomes amorphous.

  Next, after removing the mask 130, heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere. In this heat treatment step, as shown in FIG. 4F, in the gettering region 134 formed outside the source and drain regions 136, crystal defects caused by amorphization and a highly doped rare gas The element 132 moves nickel existing in the channel region 128 and the source / drain region 136 from the channel region 128 to the source / drain region 136 and then to the gettering region 134 in a direction indicated by an arrow (first step). 2 gettering).

  In this manner, the catalytic element remaining in the active region of the island-like semiconductor layer 112 after the first gettering can be gettered, and generation of a leakage current due to segregation of the catalytic element can be further suppressed. In addition, since the gettering region 134 is formed in a region different from the source region or the drain region 136 in the active region of the TFT, there is a problem that resistance increases in the source region or the drain region of the TFT due to the amorphousization. Does not occur.

  In the second gettering, a general heating furnace may be used, but RTA (Rapid Thermal Annealing) is more preferable. In particular, a system in which high temperature inert gas is blown onto the substrate surface and the temperature is raised and lowered instantaneously is suitable. As specific processing conditions, a holding temperature of 550 to 750 ° C. and a holding time of about 30 seconds to 10 minutes are appropriate conditions. It is preferable that the temperature increase rate and the temperature decrease rate are both 100 ° C./min or more. By such heat treatment, the n-type impurity (phosphorus) 124 doped in the source / drain region 136 is also activated at the same time, and the sheet resistance value of the source / drain region 136 is reduced to 1 kΩ / □ or less. Resisted. However, the gettering region 134 remains with the amorphous component maintained.

  Subsequently, as shown in FIG. 4G, a silicon oxide film or a silicon nitride film is formed as an interlayer insulating film 142, a contact hole is formed, and a TFT electrode / wiring 144 is formed of a metal material. Thereafter, annealing is performed at 350 ° C. for 1 hour in a nitrogen atmosphere or a hydrogen mixed atmosphere at 1 atm to obtain the thin film transistor 150. Further, if necessary, a protective film made of a silicon nitride film or the like may be provided on the thin film transistor 150 for the purpose of protecting the thin film transistor 150.

  In the above method, phosphorus is used as the gettering element when performing the second gettering, but arsenic or antimony may be used instead. Further, in the above method, a part of the gate insulating film 120 is selectively removed, but instead, a part of the gate insulating film 120 is selectively thinned and the gettering region 134 is formed using this. May be. Furthermore, an LDD region may be formed between the channel region 128 and the source / drain region 136 in the island-shaped semiconductor layer 112 as necessary.

  According to this embodiment, the catalyst element concentration in the active region of the TFT can be more efficiently reduced by the first and second gettering. Therefore, compared to a method in which gettering is performed only once, an increase in off-current due to insufficient gettering can be suppressed, so that TFT characteristics and reliability can be further improved. Moreover, the defect rate in a manufacturing process can be improved.

  Further, in the present embodiment, the second gettering is performed on the island-shaped semiconductor layer 112 whose catalyst element concentration has already been reduced. Therefore, it is possible to relax the heat treatment conditions during the second gettering, so that it is possible to suppress a decrease in TFT characteristics due to the heat treatment. Further, if the gettering region 134 for the second gettering is not removed even after the TFT is completed as in the method described above with reference to FIG. 4, the concentration of the catalytic element in the gettering region 134 can be reduced. It is advantageous.

  As a second gettering method according to the present embodiment, as disclosed in Patent Document 2, a gettering element is doped into a region to be a source / drain region of a TFT in the island-like semiconductor layer 112 to obtain a getter. A method of forming a ring region may be used. Even in this case, since the second gettering is performed on the island-like semiconductor layer 112 in which the catalyst element concentration has already been reduced, the amount of gettering element doped in the region to be the source / drain region is reduced. It becomes possible. Accordingly, an increase in electrical resistance in the source / drain region due to counter-doping or the like can be suppressed.

  As the catalyst element used in Embodiments 1 and 2, one or more elements selected from Ni, Co, Sn, Pb, Pd, Fe, and Cu can be used. One or more elements selected from these exhibit the effect of promoting crystallization in a trace amount.

The catalytic element does not act alone, but acts on crystal growth by bonding to the silicon film and silicidation. At this time, the crystal structure of the silicide acts as a kind of template during crystallization of the amorphous silicon film, and promotes crystallization of the amorphous silicon film. When Ni is used as the catalyst element, Ni forms a silicide of _two Si and NiSi ₂ . NiSi ₂ exhibits a meteorite-type crystal structure, which is very similar to the diamond structure of single crystal silicon. Moreover, NiSi ₂ has a lattice constant of 5.406 、, which is very close to the lattice constant of 5.430 に お け る in the diamond structure of crystalline silicon. Therefore, NiSi ₂ is optimal as a template for crystallizing an amorphous silicon film. Therefore, among the elements exemplified above, when Ni is used in particular, the effect of promoting the most remarkable crystallization can be obtained.

  In the semiconductor device obtained by the method of Embodiments 1 and 2, at least the channel region in the TFT is formed from a crystalline semiconductor film whose crystal plane orientation is mainly composed of <111> crystal zone planes. It is preferable. More preferably, at least the channel region of the semiconductor layer has a crystal plane orientation mainly composed of <111> crystal zone planes, and the plane orientation ratio is particularly ( It is formed from a crystalline semiconductor film in which 50% or more of the entire region is occupied by (110) plane orientation and (211) plane orientation.

  The methods of the first and second embodiments include a semiconductor device provided with a TFT, for example, a CMOS circuit, an active matrix substrate, various display devices such as a liquid crystal display device and an organic EL display device, and such a display device as a display unit. Widely applicable to appliances. When applied to an active matrix liquid crystal display device, it is advantageous that not only a pixel switching TFT but also a TFT constituting a peripheral driver circuit portion can be formed using the island-shaped semiconductor layer 112 with reduced catalytic elements. It is.

  The present invention is not limited to the above-described embodiment, and various modifications based on the technical idea of the present invention are possible. For example, in addition to the pure silicon film shown in the above embodiment, a mixed film of germanium and silicon (silicon / germanium film) or a pure germanium film can be used as the semiconductor film in the present invention.

As a method for introducing the catalytic element (nickel) 105 into the amorphous silicon film 104a, a method in which a solution in which nickel salt is dissolved is applied to the surface of the amorphous silicon film 104a is employed. A method may be used in which nickel 105 is introduced into the surface of the base film before film formation, and nickel 105 is diffused from the lower layer of the amorphous silicon film 104a to perform crystal growth. In addition, various other methods can be used for introducing nickel 105. For example, there is a method in which an SOG (spin on glass) material is used as a solvent for dissolving a nickel salt and is diffused from an SiO ₂ film. Furthermore, a method of forming a thin film by a sputtering method, a vapor deposition method, a plating method, a method of directly introducing by an ion doping method, or the like can be used.

  Further, a catalytic element is selectively added to only a part of the amorphous silicon film 104a to form a catalytic element addition region. In the first heat treatment, the catalytic element addition region is laterally extended from the catalytic element addition region to the periphery thereof. Crystallization of the amorphous silicon film 104a may be advanced by crystal growth. This makes it possible to obtain a good crystalline silicon film in which the crystal growth direction is almost uniform, so that the current drive capability of the TFT can be increased.

  According to the present invention, in a method of manufacturing a semiconductor device using a crystalline semiconductor film crystallized using a catalytic element, a crystalline semiconductor layer with a reduced concentration of the catalytic element is formed by a simpler process than before. Can be formed. Therefore, a semiconductor device having excellent electrical characteristics and reliability can be obtained.

  Furthermore, when additional gettering is performed after the crystalline semiconductor layer is formed, gettering efficiency can be further improved and the reliability of the semiconductor device can be improved. In addition, since the variation in characteristics is suppressed by improving the gettering efficiency, it is possible to greatly reduce defects in the manufacturing process.

  The present invention can be applied to a method of manufacturing an active matrix liquid crystal display device, an organic EL display device, a contact image sensor, a three-dimensional IC, and the like. In particular, it is suitably used for high-definition small and medium display panels.

(A)-(e) is process sectional drawing for demonstrating the manufacturing method of TFT in 1st Embodiment by this invention. (A)-(d) is process sectional drawing for demonstrating the manufacturing method of TFT in 1st Embodiment by this invention. (A)-(d) is a top view for demonstrating the manufacturing method of TFT in 1st Embodiment by this invention. (A)-(g) is process sectional drawing for demonstrating the manufacturing method of TFT in 2nd Embodiment by this invention. (A)-(f) is process sectional drawing for demonstrating the manufacturing method of the conventional TFT.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Substrate 102, 103 Underlayer film 104a Amorphous semiconductor film 104p Crystalline semiconductor film 104r Recrystallized region 104g Gettering region 105 Catalytic element 108 Antireflection layer 109, 110 Resist layer 112 Island-like semiconductor layer 120 Gate insulating film 122 Gate Electrode 124 Impurity (phosphorus)
128 channel region 130 mask 132 gettering element 134 gettering region 136 source region and drain region 142 interlayer insulating film 144 electrode / wiring 150 thin film transistor

Claims (10)

A method of manufacturing a semiconductor device including a thin film transistor,
(A) preparing an amorphous semiconductor film to which a catalytic element for promoting crystallization is added at least partially;
(B) performing a first heat treatment on the amorphous semiconductor film to crystallize at least a part of the amorphous semiconductor film to obtain a crystalline semiconductor film including a crystalline region;
(C) forming an antireflection layer exposing at least a part of the crystalline region;
(D) performing laser irradiation on the crystalline semiconductor film to recrystallize an exposed portion of the crystalline region to form a recrystallized region; Forming a gettering region containing an amorphous semiconductor in a portion covered with an antireflection layer;
(E) performing a second heat treatment on the crystalline semiconductor film to move at least a part of the catalytic element in the recrystallization region to the gettering region. Manufacturing method.   2. The semiconductor device according to claim 1, wherein the step (c) is a step of forming an antireflection layer exposing a region of the crystalline region where an island-shaped semiconductor layer is to be formed on the crystalline region. Manufacturing method.   The method of manufacturing a semiconductor device according to claim 1, wherein the antireflection layer contains silicon oxide.   The method for manufacturing a semiconductor device according to claim 3, wherein the antireflection layer is a silicon oxide layer, and the thickness of the silicon oxide layer is 100 nm or less. 2. The method further comprises: (f) after the step (e), (f) removing the antireflection layer and the gettering region to form an island-shaped semiconductor layer including at least a part of the recrystallized region. 5. A method for manufacturing a semiconductor device according to any one of items 1 to 4. After the step (f) (g) forming an insulating film on the island-like semiconductor layer;
(H) forming another gettering region by adding a gettering element having gettering capability to a part of the island-shaped semiconductor layer;
(I) By performing a third heat treatment on the island-shaped semiconductor layer, at least a part of the catalytic element in a region other than the other gettering region in the island-shaped semiconductor layer The method for manufacturing a semiconductor device according to claim 5, further comprising a step of moving to the gettering region.   The step (h) is a step of forming another gettering region by adding the gettering element to a region other than a region to be an active region of the island-shaped semiconductor layer. A method for manufacturing a semiconductor device. Between the step (g) and the step (h) (g ′) The gate insulating film located on a region other than the region which becomes the active region in the island-shaped semiconductor layer is selectively thinned or selectively Further comprising removing,
The step (h) is a step of forming another gettering region by adding a gettering element to a region where the gate insulating film on the island-like semiconductor layer is thinned or removed. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. Before the step (i), the method further includes a step of doping an impurity element into a region of the island-shaped semiconductor layer where the source and drain regions are to be formed,
The method for manufacturing a semiconductor device according to claim 6, wherein the impurity element doped in the island-shaped semiconductor layer is activated by the third heat treatment.   The semiconductor device according to claim 1, wherein the catalyst element includes one or more elements selected from Ni, Co, Sn, Pb, Pd, Fe, and Cu.

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