JP4115406B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device including a thin film transistor (hereinafter abbreviated as “TFT”) and a method for manufacturing the same.

  In recent years, high-resolution liquid crystal display devices and organic EL display devices, high-speed, high-resolution contact image sensors, three-dimensional ICs, etc. have been developed on insulating substrates such as glass and insulating films. Attempts have been made to form high performance semiconductor devices. In particular, a liquid crystal display device in which a pixel portion and a driving circuit are provided on the same substrate has been used not only as a monitor for a personal computer (PC) but also in various applications, and has entered the general household. I'm starting. For example, instead of CRT (Cathode-ray Tube), a liquid crystal display is introduced as a television, and a liquid crystal front projector for watching movies and playing games as an entertainment has been introduced into ordinary households. The market size of display devices is growing at a considerable rate. Furthermore, development of a system-on-panel in which a logic circuit such as a memory circuit or a clock generation circuit is built on a glass substrate is being promoted.

  If you try to display a high-resolution image, the amount of information to be written to the pixels will increase, and if that information is not written in a short time, a high-definition image with such an enormous amount of information can be displayed as a moving image. Impossible. For this reason, the TFT used in the driver circuit is required to operate at a higher speed. In order to enable high-speed operation, it is required to form a TFT using a crystalline semiconductor film having good crystallinity that can provide high field effect mobility.

  As a method for obtaining a high-quality crystalline semiconductor film on a glass substrate, the present inventors add a metal element (catalyst element) having an action of promoting crystallization to an amorphous semiconductor film, and then perform heat treatment. As a result, we have developed a technology that can provide a good semiconductor film with uniform crystal orientation by low-temperature and short-time heat treatment.

  However, a TFT manufactured using a crystalline silicon film obtained by using a catalytic element as a semiconductor layer as it is has a problem that off-current suddenly increases. In the crystalline silicon film, the catalyst element segregates irregularly, and it has been confirmed that such segregation is particularly remarkable at the grain boundary. This segregated catalytic element is considered to be a current escape path (leakage path), causing a sudden increase in off-current. Therefore, it is necessary to reduce the concentration of the catalytic element in the semiconductor film by moving the catalytic element from the semiconductor film after the crystalline silicon film manufacturing process. Note that in this specification, removing a catalytic element from a semiconductor film or a predetermined region (a channel region or an active region) of the semiconductor film is referred to as “gettering”.

  Various methods have been proposed in the past for performing gettering. For example, Patent Document 1 discloses a method of forming an amorphous region (amorphous region) as a gettering region in a part of a crystalline silicon film crystallized using a catalytic element. Yes. According to the method of Patent Document 1, by performing heat treatment on a crystalline silicon film in which an amorphous region is formed, a catalytic element is moved (getter) to a lattice defect in the amorphous region. Ring). In addition, a method for forming such an amorphous region other than the semiconductor element formation region in the crystalline silicon film, and a region in the crystalline silicon film that becomes a source region or a drain region of the TFT are used as a gettering region. Is disclosed.

  However, in the method of forming an amorphous silicon film other than the semiconductor element formation region in the crystalline silicon film, the process is complicated and the cost is increased due to the additional process for gettering. According to the method of using a source region or a drain region as a gettering region, the manufacturing process can be simplified, so the above problem is improved. However, the amorphous region does not function as a source region or a drain region. Therefore, an additional step of activating the amorphous region using a laser beam or the like is necessary. The laser irradiation apparatus used in this additional process is expensive, has a complicated apparatus structure, and is not easy to maintain. Therefore, since the manufacturing cost increases in terms of the apparatus, it is an apparatus that should not be used as much as possible except for essential processes.

  On the other hand, instead of using lattice defects in the amorphous region for gettering, an element belonging to Group B of the periodic table having a function of moving a catalytic element (typically phosphorus, arsenic, etc .: n-type) A method of using (which is also an impurity element imparting) has been proposed.

  For example, Patent Document 2 focuses on the gettering action of phosphorus, and proposes a method of performing gettering by moving a catalytic element from the channel formation region of the TFT to the source and drain regions. In this method, a TFT semiconductor layer is formed from a crystalline silicon film crystallized using a catalytic element. In the case of manufacturing an N-channel TFT using this semiconductor layer, the catalyst element in the channel formation region is moved to the source and drain regions by doping phosphorus in the source and drain regions and then performing heat treatment. On the other hand, in the case of manufacturing a P-channel TFT, the source and drain regions are doped with phosphorus used for gettering and boron with a concentration higher than the concentration of phosphorus. Thereafter, the catalyst element is moved to the source and drain regions by heat treatment.

  Since the method of Patent Document 2 does not use a laser irradiation device, it does not have the above-described device problems. However, it is difficult to mass-produce thin film transistors using the method of Patent Document 2. The reason will be described below.

  In the method of Patent Document 2, in an n-channel TFT, an element belonging to Group 5 B imparting n-type doped in a source region and a drain region (phosphorus or the like) alone acts as a gettering element. In a p-type TFT, an element belonging to Group B that imparts p-type (boron or the like) does not act as a gettering element, and therefore n-type is imparted as a gettering element to the source region and drain region of the p-channel TFT. It is necessary to add an element belonging to group B. That is, in a p-channel TFT, it is necessary to invert a region doped with an n-type impurity element at a high concentration to p-type (called counter-doping) in order to getter the catalyst element. In the semiconductor layer of the TFT, the electrical resistance of the source region and the drain region becomes a parasitic resistance when the TFT is turned on, and the current value of the TFT is reduced. However, in order to invert the n-type to the p-type, it is necessary to add a p-type impurity element having a concentration of 1.5 to 3 times the n-type impurity element. Therefore, when the amount of an element belonging to Group B that imparts n-type is increased in order to increase the gettering effect, the amount of an element that belongs to Group B that imparts p-type is also reversed. It was necessary to increase the concentration to a high level, which greatly pressed the processing capacity of the doping apparatus.

  Further, Patent Document 3 selectively introduces a Group 5 B element such as phosphorus into a part of a crystalline silicon film crystallized using a catalytic element, and performs heat treatment in a temperature range that does not exceed the strain point of the substrate. This discloses a method of moving (gettering) a catalytic element to a region into which a Group 5 B element has been introduced. After this gettering step, the region where the Group 5 B element is introduced (gettering region) is removed, and the region other than the Group 5 B element is introduced, that is, the region where the catalytic element is removed. An active region of the semiconductor device is formed.

In the method of Patent Document 3, the gettering region is provided in a region other than the region that becomes the semiconductor layer of the TFT in the crystalline silicon film, so that it is not necessary to perform the counter-doping described above. However, in this method, an extra step for gettering is added, and further, a step of removing the gettering region is increased. As a result, the manufacturing process becomes complicated and the manufacturing cost increases. Further, the TFT completed by the method of Patent Document 3 does not have a gettering region in the semiconductor layer. When the gettering region has been completely removed, if there is a catalyst element remaining after gettering, such a catalyst element may be re-silicidized and deposited in a heat treatment step after gettering. .
JP-A-8-213317 JP-A-8-330602 Japanese Patent Laid-Open No. 10-270363

  The present invention has been made in view of the above problems, and an object of the present invention is to reduce the concentration of a catalytic element contained in an active region in a crystalline semiconductor layer without reducing the performance of the thin film transistor in a semiconductor device including the thin film transistor. It is to reduce sufficiently. Moreover, it is manufacturing such an apparatus at a low cost without increasing the number of processes.

  The semiconductor device of the present invention is a semiconductor device including at least an N-channel thin film transistor, and the N-channel thin film transistor includes a semiconductor layer including a crystalline region including a channel region, a source region, and a drain region, and the semiconductor A gate insulating film formed on at least the channel region, the source region and the drain region of a layer, and a gate electrode formed so as to face the channel region through the gate insulating film, The semiconductor layer further includes a gettering region containing a catalytic element at a higher concentration than the source region and the drain region, and the gate insulating film is not formed on the gettering region, or the gate insulating film Is also formed on the gettering region, the source region and the drain The thickness of the gate insulating film on frequency is greater than the thickness of the gate insulating film on the gettering region.

  Another semiconductor device of the present invention is a semiconductor device including an N-channel thin film transistor and a P-channel thin film transistor, and each of the N-channel thin film transistor and the P-channel thin film transistor includes a channel region, a source region, and a drain region. A semiconductor layer having a crystalline region, a gate insulating film formed on at least the channel region, the source region, and the drain region of the semiconductor layer, and facing the channel region through the gate insulating film The semiconductor layer further includes a gettering region containing a catalytic element at a higher concentration than the source region and the drain region, and the gate insulating film includes the N-channel thin film transistor Formed on the gettering region in Or the gate insulating film is also formed on the gettering region in the N-channel thin film transistor, and the thickness of the gate insulating film on the source region and the drain region in the N-channel TFT. Is larger than the thickness of the gate insulating film on the gettering region in the N-channel thin film transistor.

  In a preferred embodiment, the structure of the gate electrode in the N-channel thin film transistor is different from the structure of the gate electrode in the P-channel thin film transistor.

  In a preferred embodiment, the gate electrode in the N-channel thin film transistor is formed on the first conductive layer and the first conductive layer, and has a channel direction larger than the channel direction size of the first conductive layer. A second conductive layer having a size, wherein the gate electrode in the P-channel type thin film transistor is formed on the first conductive layer and the first conductive layer, and is approximately equal to a size of the first conductive layer in a channel direction. A second conductive layer having the same channel direction size is included.

  In a preferred embodiment, the channel region of the N-channel thin film transistor overlaps the first conductive layer and the second conductive layer of the gate electrode, and the gate of the semiconductor layer of the N-channel thin film transistor. A region of the electrode that overlaps with the first conductive layer but does not overlap with the second conductive layer contains N-type impurities at a lower concentration than the source and drain regions.

  The thickness of the gate insulating film on the gettering region in the P-channel thin film transistor may be the same as the thickness of the gate insulating film on the source and drain regions in the P-channel thin film transistor.

  A thickness of the gate insulating film on the gettering region in the N-channel thin film transistor may be the same as a thickness of the gate insulating film on the source region and the drain region of the P-channel thin film transistor.

  A thickness of the gate insulating film on the gettering region in the N-channel thin film transistor may be the same as a thickness of the gate insulating film on the gettering region in the P-channel thin film transistor.

  The gettering region is preferably formed in a region other than a region where electrons or holes move during the operation of the thin film transistor.

  The gettering region is preferably not in contact with the channel region.

  The gettering region is formed at an outer edge portion of the semiconductor layer, the thin film transistor is electrically connected to another thin film transistor by a wiring, and the thin film, the transistor, and the wiring are connected to each other in the source region or the drain region. It may be performed in at least a part of the area.

  In the gettering region, it is preferable that the proportion of the amorphous component is larger and the proportion of the crystalline component is smaller than that of the source and drain regions and / or the channel region.

  The ratio Pa / Pc between the TO phonon peak Pa of the amorphous semiconductor and the TO phonon peak Pc of the crystalline semiconductor in the Raman spectrum of the gettering region is the ratio Pa of the source and drain regions and / or the channel formation region. It is preferably larger than / Pc.

  The gettering region of the N-channel thin film transistor preferably includes an impurity element belonging to Group B of the periodic table that imparts n-type at a higher concentration than the source region or the drain region of the N-channel thin film transistor. .

  The gettering region of the N-channel thin film transistor and the P-channel thin film transistor includes an impurity element belonging to Group B of the Periodic Table imparting n-type and an impurity element belonging to Group B of the Periodic Table imparting p-type. May be included.

The gettering region includes an impurity element imparting the n type conductivity in a concentration of 1 × 10 ¹⁹ / cm ³ or more 3 × 10 ²¹ / cm ³ or less, 1 impurity element imparting the p-type × 10 ¹⁹ / It may be contained at a concentration of cm ³ or more and 3 × 10 ²¹ / cm ³ or less.

  The catalytic element included in the gettering region may include one or more elements selected from Ni, Co, Sn, Pb, Pd, Fe, and Cu.

The concentration of the catalytic element in the gettering region may be 5 × 10 ¹⁸ atoms / cm ³ or more.

  In a preferred embodiment, at least the channel region in the semiconductor layer is mainly composed of a region in which a <111> crystal zone plane of the crystal is oriented.

  In the semiconductor layer, at least the channel region is mainly composed of a region where the <111> crystal zone plane of the crystal is oriented, and 50% or more of the region where the <111> crystal zone plane is oriented is a (110) plane. It may be an oriented or (211) plane oriented region.

  In the semiconductor layer, at least the channel region may have a plurality of crystal domains, and the domain diameter of the crystal domains may be 2 μm or more and 10 μm or less.

  The gate electrode may be formed of one or more elements selected from W, Ta, Ti, and Mo, or alloy materials of the elements.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including an N-channel thin film transistor and a P-channel thin film transistor, and an amorphous semiconductor to which a catalytic element for promoting crystallization is added at least partially A step of preparing a film, and performing a first heat treatment on the amorphous semiconductor film, thereby crystallizing at least a part of the amorphous semiconductor film and forming a crystalline semiconductor film including a crystalline region Obtaining a plurality of island-like semiconductor layers each having a crystalline region by patterning the crystalline semiconductor film; and forming a gate insulating film on the island-like semiconductor layer; A step of depositing a first conductive film on the gate insulating film, a step of depositing a second conductive film on the first conductive film, the first conductive film and the second conductive film, A step of providing a gate electrode having a laminated structure having a stepped cross section by patterning to form a first conductive layer and a second conductive layer having a smaller size in the channel direction than the first conductive layer. And the region of the island-like semiconductor layer that becomes the active layer of the N-channel type thin film transistor is exposed to the region that becomes the gettering region and the whole of the island-like semiconductor layer that becomes the active layer of the P-channel type thin film transistor. Forming a first mask so as to cover a region to be a region and a drain region and a gate electrode of the N-channel thin film transistor, and using the first mask and the gate electrode of the P-channel thin film transistor as a mask; A process of doping an impurity element imparting p-type into the semiconductor layer in the exposed region Etching the first conductive layer using the second conductive layer as a mask only in the gate electrode of the P-channel thin film transistor exposed by the first mask, and the first of the gate insulating films. A step of thinning or removing a portion exposed by the mask, a step of removing the first mask, an entire island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor, and an activity of the P-channel thin film transistor A second mask is formed so that a region to be a gettering region of the island-shaped semiconductor layer to be a layer is exposed, and a region to be a source region and a drain region of the P-channel thin film transistor and the gate electrode of the P-channel thin film transistor are covered. And forming the second mask and the gate electrode of the N-channel thin film transistor. Doping an impurity element imparting n-type to the semiconductor layer in the exposed region as a mask, and performing the second heat treatment, the catalyst element in the island-shaped semiconductor layer And moving at least a part of the gettering region to the gettering region.

  Another method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including an N-channel thin film transistor and a P-channel thin film transistor, and is an amorphous material in which a catalytic element for promoting crystallization is added at least partially. Preparing a crystalline semiconductor film; and performing a first heat treatment on the amorphous semiconductor film to crystallize at least a part of the amorphous semiconductor film, thereby forming a semiconductor film including a crystalline region Obtaining a plurality of island-like semiconductor layers each having a crystalline region by patterning the semiconductor film; forming a gate insulating film on the island-like semiconductor layer; and A process of depositing a first conductive film on the gate insulating film, a process of depositing a second conductive film on the first conductive film, and a pattern of the first conductive film and the second conductive film. Forming a gate electrode having a laminated structure having a stepped cross section by forming the first conductive layer and a second conductive layer having a smaller size in the channel direction than the first conductive layer. And exposing the entire region of the island-shaped semiconductor layer serving as the active layer of the P-channel thin film transistor and the region serving as the gettering region of the island-shaped semiconductor layer serving as the active layer of the N-channel thin-film transistor, Forming a first mask so as to cover the source and drain regions of the island-shaped semiconductor layer and the gate electrode of the N-channel thin film transistor, and the P-channel exposed by the first mask Etching the first conductive layer using only the second conductive layer as a mask only at the gate electrode of the thin film transistor A step of thinning or removing a portion of the gate insulating film exposed by the first mask, and a gate electrode of the first mask and a P-channel thin film transistor as a mask. A step of doping the semiconductor layer in the region with an impurity element imparting p-type, a step of removing the first mask, an entire island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor, and a P-channel The region that becomes the gettering region of the island-like semiconductor layer that becomes the active layer of the p-channel thin film transistor is exposed, and the region that becomes the source region and drain region of the p-channel thin film transistor and the gate electrode of the p-channel thin film transistor are covered. 2 mask forming process, and a gate for the second mask and the N-channel thin film transistor. The semiconductor layer in the exposed region is doped with an impurity element imparting n-type and a second heat treatment is performed on the semiconductor layer in the island-shaped semiconductor layer using a copper electrode as a mask. Moving at least a portion of the catalytic element to the gettering region.

  Still another method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including an N-channel thin film transistor and a P-channel thin film transistor, in which a catalyst element that promotes crystallization is added at least partially. A step of preparing a crystalline semiconductor film, and a semiconductor film including a crystalline region by crystallizing at least a part of the amorphous semiconductor film by performing a first heat treatment on the amorphous semiconductor film Obtaining a plurality of island-like semiconductor layers each having a crystalline region by patterning the semiconductor film, forming a gate insulating film on the island-like semiconductor layer, and A step of depositing a first conductive film on the gate insulating film; a step of depositing a second conductive film on the first conductive film; and the first conductive film and the second conductive film. Step of providing a gate electrode having a laminated structure having a stepped cross section by forming the first conductive layer and a second conductive layer having a smaller size in the channel direction than the first conductive layer by turning. And the region that becomes the gettering region of the island-shaped semiconductor layer that becomes the active layer of the N-channel thin film transistor and the whole of the island-shaped semiconductor layer that becomes the active layer of the P-channel thin film transistor are exposed, and the source region of the N-channel thin film transistor And a step of forming a first mask so as to cover a region to be a drain region and the gate electrode of the N-channel thin film transistor, and only in the gate electrode of the P-channel thin film transistor exposed by the first mask Etching the first conductive layer using the second conductive layer as a mask; and A step of doping an impurity element imparting p-type to the semiconductor layer in a region exposed from the gate electrode of the gate electrode and the P-channel type thin film transistor, and the first of the gate insulating films A step of thinning or removing a portion exposed from the mask, a step of removing the first mask, an entire island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor, and an activity of the P-channel thin film transistor A second mask is formed so that a region to be a gettering region of the island-shaped semiconductor layer to be a layer is exposed, and a region to be a source region and a drain region of the P-channel thin film transistor and the gate electrode of the P-channel thin film transistor are covered. And the second mask and the gate electrode of the N-channel thin film transistor are masked. The catalyst element in the island-shaped semiconductor layer is obtained by performing a step of doping an impurity element imparting n-type to the semiconductor layer in a region exposed from the semiconductor layer and a second heat treatment. And moving at least a part of the gettering region to the gettering region.

  The step of etching the first conductive layer using the second conductive layer as a mask only in the gate electrode of the P-channel thin film transistor exposed by the first mask includes the first mask of the gate insulating film. It may be performed after the step of thinning or removing the exposed region.

  Etching the first conductive layer using the second conductive layer as a mask only at the gate electrode of the P-channel thin film transistor exposed by the first mask, and the first mask of the gate insulating film The step of thinning or removing the exposed region may be performed continuously in the same etching apparatus.

  Etching the first conductive layer using the second conductive layer as a mask only at the gate electrode of the P-channel thin film transistor exposed by the first mask, and removing the first mask These may be performed continuously in the same etching apparatus.

  The step of thinning or removing the region of the gate insulating film exposed from the first mask and the step of removing the first mask are performed continuously in the same etching apparatus. May be.

  Etching the first conductive layer using the second conductive layer as a mask only at the gate electrode of the P-channel thin film transistor exposed by the first mask, and the first mask of the gate insulating film The step of thinning or removing the exposed region and the step of removing the first mask may be performed continuously in the same etching apparatus.

  Etching the first conductive layer using the second conductive layer as a mask only at the gate electrode of the P-channel thin film transistor exposed by the first mask, and the first mask of the gate insulating film The step of thinning or removing the exposed region may be performed simultaneously.

  Etching the first conductive layer using the second conductive layer as a mask only at the gate electrode of the P-channel thin film transistor exposed by the first mask, and removing the first mask Done at the same time.

  The step of thinning or removing the region exposed from the first mask in the gate insulating film and the step of removing the first mask may be performed simultaneously.

  Etching the first conductive layer using the second conductive layer as a mask only at the gate electrode of the P-channel thin film transistor exposed by the first mask, and the first mask of the gate insulating film The step of thinning or removing the exposed region and the step of removing the first mask may be performed simultaneously.

  In a preferred embodiment, the first conductive film and the second conductive film are patterned to form the first conductive layer, and a second conductive layer having a smaller size in the channel direction than the first conductive layer. Forming a gate electrode having a layered structure having a stepped cross section by etching the second conductive film so as to have a first taper angle; and the first conductive film And the second conductive film etched so as to have the first taper angle is further selectively etched to provide a second taper angle larger than the first taper angle. Etching so as to have a taper angle of.

  Etching the second conductive film so as to have a first taper angle; etching the first conductive film; and etching the first conductive film so as to have the first taper angle. The step of etching the conductive film 2 further selectively so as to have a second taper angle larger than the first taper angle is continuously performed in the etching apparatus. It may be done.

  In the step of doping the semiconductor layer in the region exposed by using the second mask and the gate electrode of the N-channel thin film transistor as a mask, the step of doping the gate electrode with the impurity element imparting n-type is performed. The doping may be performed across the first conductive layer using two conductive layers as a mask.

  In a preferred embodiment, the step of doping the semiconductor layer in the region exposed from the second mask and the gate electrode of the N-channel thin film transistor with an impurity element imparting n-type, Doping the impurity element imparting the n-type at a low concentration across the first conductive layer using the second conductive layer of the gate electrode as a mask; and masking the first conductive layer of the gate electrode And a step of doping the impurity element imparting the n-type at a high concentration.

  Doping the impurity element imparting the n-type at a low concentration across the first conductive layer using the second conductive layer of the gate electrode as a mask; and masking the first conductive layer of the gate electrode As described above, the step of doping the impurity element imparting n-type at a high concentration may be performed continuously in the same doping apparatus.

  Doping the impurity element imparting the n-type at a low concentration across the first conductive layer using the second conductive layer of the gate electrode as a mask; and masking the first conductive layer of the gate electrode As described above, the step of doping the impurity element imparting n-type at a high concentration may be performed at the same time.

  By patterning the first conductive film and the second conductive film to form the first conductive layer and a second conductive layer having a smaller size in the channel direction than the first conductive layer, The step of providing the stacked gate electrode having a stepped cross section may be performed by an inductively coupled plasma etching method.

  By patterning the first conductive film and the second conductive film to form the first conductive layer and a second conductive layer having a smaller size in the channel direction than the first conductive layer, The step of providing a gate electrode having a stacked structure having a stepped cross section may be performed by a reactive ion etching method.

  The gettering region is preferably formed in a region other than a region where electrons or holes move.

  The gettering region is preferably formed so as to be in contact with the source region or the drain region and not to be in contact with the channel region.

  After the second heat treatment, a step of forming a wiring in contact with a contact portion including at least a part of the source region or the drain region may be further included.

  By the second heat treatment, the n-type impurity and / or the p-type impurity doped in at least the source region and the drain region in the island-like semiconductor layer can be activated.

  In a preferred embodiment, the step of preparing the amorphous semiconductor film includes a step of forming a mask having an opening on the amorphous semiconductor film, and the catalytic element is passed through the opening. Adding to selected areas of the membrane.

  The catalyst element may include at least one element selected from the group consisting of Ni, Co, Sn, Pb, Pd, Fe, and Cu.

  A step of irradiating the semiconductor film with laser light may be further included after the first heat treatment.

  An electronic apparatus according to the present invention includes any one of the above semiconductor devices.

  In a preferred embodiment, a display unit is provided that performs a display operation using the semiconductor device.

  According to the present invention, catalytic elements remaining in an active region of a crystalline semiconductor layer formed using a catalytic element, particularly a channel forming region and a junction between a channel forming region and a source region or a drain region can be sufficiently reduced. In particular, in an N-channel TFT, it is possible to form a gettering region having excellent gettering capability while suppressing increase in resistance of the source and drain regions. Therefore, a semiconductor device including a highly reliable and high-performance thin film transistor can be provided. Furthermore, according to the present invention, the semiconductor device can be manufactured by a simple process.

  As a mechanism for gettering, when the solid solubility of a certain region of the crystalline semiconductor film with respect to the catalytic element is increased as compared with the other region, the catalytic element moves to the predetermined region (the first region) Gettering action) and when a defect or local segregation site that traps the catalytic element is formed in one region of the crystalline semiconductor film, the catalytic element moves and is trapped in that region (Second gettering action).

  As in the methods disclosed in Patent Documents 2 and 3, when an element (gettering element) belonging to Group 5B of the periodic table having the action of moving the catalytic element is introduced into the crystalline silicon film, the gettering element is introduced. The solid solubility with respect to the catalytic element in the selected region is increased. That is, the gettering movement is performed using the first gettering action. On the other hand, in the method disclosed in Patent Document 1, since the lattice defects in the amorphous region become local segregation sites for trapping the catalytic element, gettering using the second gettering action is performed. Is called. In addition, since the free energy of the catalytic element in the amorphous region is lower than that in the crystalline region, the catalytic element easily diffuses into the amorphous region.

  Here, as one of effective methods for simplifying the gettering process, the catalytic element is moved to the region to be the source region or the drain region of the TFT semiconductor layer as described above, and the catalytic element is moved from the channel region. In addition to the above-mentioned problems, it has been found that such a method has a big problem. In order to enhance the gettering capability in the gettering region, it is necessary to sufficiently draw out the first gettering action and the second gettering action. However, it is difficult to sufficiently enhance the gettering action in a region that becomes a source region or a drain region of the TFT in the crystalline semiconductor film. This is because, in order to increase the gettering efficiency, it is effective to introduce a large amount of gettering elements into the gettering region (regions to be the source and drain regions) and to make the region amorphous. Such a process greatly deteriorates the resistance value of the gettering region. This is because it is difficult to make such a gettering region function as a source region and a drain region after the gettering step.

  When a large amount of gettering element is ion-implanted into the crystalline semiconductor film, the crystal in the implanted region breaks down and becomes amorphous. The amorphization at this time is started from the upper surface side of the semiconductor film, and when it is completely amorphized to the lower surface side, it does not recover even if heat treatment is performed thereafter. In the conventional method using the source region and the drain region as the gettering regions, it is necessary to recover the crystal of the gettering region after ion implantation to some extent and lower the resistance in the subsequent heat treatment. For this reason, in such a method, it is difficult to increase the gettering efficiency by injecting a large amount of gettering element, and it is necessary to suppress the injection amount to a level that can recover the crystal. However, if the amount of gettering element implanted is small, the gettering ability is greatly reduced, and therefore, the control of the amount of gettering element implanted is the biggest problem.

  When the above method is actually applied to a driver-integrated liquid crystal display device, the source region and the drain region become amorphous in a part of the substrate and become high resistance. It became defective and a driver failure occurred. Further, in other parts of the substrate, the amount of gettering elements introduced is small, resulting in insufficient gettering, and line defects and point defects are generated due to an increase in leakage current during the off operation. As described above, the process margin is extremely small and it cannot be applied to mass production.

  In the method of Patent Document 1, an amorphous region does not function as a source and drain region, so an additional step of activation using laser light or the like is required. However, as described above, the laser irradiation apparatus is expensive and has a complicated apparatus structure and poor maintainability, resulting in an increase in manufacturing cost and a decrease in the yield rate. In addition, laser irradiation alone cannot recover crystal defects generated at the junctions between the channel region, the source region, and the drain region, leading to deterioration in reliability and an increase in leakage current during off operation. Further, in the conventional method using such a source region and a drain region as a gettering region as they are, the junction between the channel region and the source / drain region is formed between the gettering region and the non-gettering region. It is also a boundary, and segregation of the catalytic element existing at the junction between the channel region and the drain region cannot be removed.

  Further, if the gettering region (source region and drain region) in an amorphous state is finally crystallized as in the method of Patent Document 1, the subsequent gettering action is reduced, and heat treatment is performed. In some cases, the catalytic element once moved in step 1 may flow backward in the subsequent steps. Even if such a backflow of the catalytic element is prevented in the manufacturing process, a considerable amount of heat is generated by driving the TFT, and the catalytic element once moved to the gettering region moves to the channel region when driving the TFT. In some cases, problems occur in reliability. Therefore, when a gettering region is provided in the active layer of the TFT, the region maintains the same gettering state even when the TFT is completed, and keeps the same level of gettering capability as in the gettering step. I know that is desirable.

  The present invention has been made to solve the problems of the conventional gettering method as described above. Hereinafter, the configuration of an embodiment of an apparatus according to the present invention will be described with reference to the drawings.

  A semiconductor device 15 illustrated in FIG. 1 includes an N-channel thin film transistor 10n and a P-channel thin film transistor 10p. Each of these thin film transistors 10n and 10p includes semiconductor layers 13n and 13p having crystalline regions including channel regions 7n and 7p, source regions and drain regions 9n and 9p, and at least channel regions 7n and 7p of the semiconductor layers 13n and 13p. The gate insulating film 3 formed on the source and drain regions 9n and 9p, and the gate electrodes 5n and 5p formed to face the channel regions 7n and 7p with the gate insulating film 3 interposed therebetween. The semiconductor layers 13n and 13p of the N-channel thin film transistor 10n and the P-channel thin film transistor 10p further have gettering regions 11n and 11p containing a catalytic element at a higher concentration than the source and drain regions 9n and 9p. In the N-channel thin film transistor 10n, the thickness of the gate insulating film 3 on the gettering regions 11n and 11p is smaller than the thickness of the gate insulating film 3 on the source and drain regions 9n and 9p. Alternatively, the gate insulating film 3 may not be formed on the gettering region 11n of the N-channel thin film transistor 10n.

  Although the semiconductor device 15 includes the N-channel and P-channel thin film transistors 10n and 10p, the semiconductor device of the present invention only needs to include at least the N-channel thin film transistor.

  As described above, the present embodiment is characterized in that the semiconductor layers 13n and 13p of the TFT have the gettering regions 11n and 11p in addition to the source and drain regions 9n and 9p. The gate insulating film 3 provided on the gettering region 11n is configured to be thinner than the source and drain regions 9n. That is, the gate insulating film 3 is selectively thinned and the gettering region 11n is formed in that portion. In the top gate type TFT, the impurity element is generally implanted into the semiconductor layers 13n and 13p through the upper gate insulating film 3. This is through doping for the so-called gate insulating film 3. At this time, the concentration of the impurity element implanted into the semiconductor layers 13n and 13p, and the crystal state (amorphization degree) in the region, the ion implantation conditions (mainly acceleration voltage and dose), and the gate insulating film 3 It depends on the thickness.

  In other words, in this embodiment, dedicated regions 11n and 11p for gettering are provided in regions other than the regions to be the source and drain regions 9n and 9p in the semiconductor layers 13n and 13p, and the semiconductor layers 13n and 13p are provided on the semiconductor layers 13n and 13p. A gate insulating film 3 is provided. At this time, at least in the N-channel type thin film transistor 10n, the thickness of the portion of the gate insulating film 3 located above the source and drain regions 9n where low resistance is required is the gettering region where gettering capability is required. The gate insulating film 3 is provided so as to be larger than the thickness of the portion located on 11n, and through doping treatment is performed over the gate insulating film. Thereby, the gettering region 11n and the source and drain regions 9n can be in different doping states. As a result, the source and drain regions 9n are not affected by gettering and are formed in a substantially separated process, so that the addition amount of n-type impurities and p-type impurities can be optimized for the purpose of reducing resistance. Further, the amount of implantation of the gettering region 11n, the degree of amorphization, and the like can be optimized only for the purpose of gettering, separately from the source and drain regions 9n.

  Therefore, as compared with the conventional method using the source / drain regions as the gettering regions, the gettering method according to the present embodiment can increase the process margin while maintaining the shortening and simplification of the process. Ring ability can be greatly increased. In addition, the throughput of the doping apparatus can be improved. Further, unlike the conventional method in which the source / drain regions are used as gettering regions, the source / drain regions 9n, 9p are also non-gettering regions, so that the junction between the channel regions 7n, 7p and the source / drain regions 9n, 9p. The portion can also be completely gettered, the increase in leakage current during off operation, which is a problem in TFT characteristics, can be suppressed almost completely, and higher reliability can be secured at the same time.

  The N-channel thin film transistor 10n and the P-channel thin film transistor 10p preferably have different TFT structures. The reason will be described below.

  In view of the reliability of the thin film transistor, particularly in the case of an N-channel TFT, a method of reducing the concentration of electric field applied to a low-concentration N-type impurity region (LDD region) between the source and drain regions and the channel region. Is known to be effective. Even if gettering is slightly insufficient for deterioration due to hot carriers, leakage current suppression during off operation, etc., the margin for reliability can be expanded by providing the LDD region. At this time, in order to further improve the reliability, a structure (Gate-drain Overlapped LDD; GOLD structure) in which an LDD region is set so as to partially overlap the gate electrode is particularly effective. However, when the GOLD structure is used, the parasitic capacitance of the thin film transistor increases, which may cause a signal delay. Therefore, it is better not to apply the GOLD structure to a P-channel TFT that can secure sufficient reliability even with a normal structure. Thus, the optimum TFT structure differs between the N-channel TFT and the P-channel TFT.

  However, in a conventional semiconductor device, these TFTs are usually formed in the same process, so changing the TFT structure depending on the type of TFT conductivity type leads to complicated manufacturing processes and high costs. There was a problem.

  On the other hand, in the embodiment described below, the N-channel type thin film transistor 10n and the P-channel type thin film transistor 10p have gate electrodes 5n and 5p having different structures from each other. Different TFT structures can be created.

  For example, the gate electrodes 5n and 5p have a two-layer structure including a lower layer formed from a first conductive film and an upper layer formed from a second conductive film, and the gate electrode 5n of the N-channel thin film transistor 10n. Then, the width of the lower first conductive layer is larger than the width of the upper second conductive layer, and in the gate electrode 5p of the P-channel type thin film transistor 10p, the width of the lower first conductive layer and the width of the upper second conductive layer. And may be substantially the same. At this time, in the semiconductor layer 13n of the N-channel type thin film transistor 10n, a region that overlaps only with the first conductive layer of the gate electrode 5n is an LDD region containing an N-type impurity at a low concentration. The region overlapping the two conductive layers may be the channel region 7n. As a result, a low-concentration N-type impurity region (LDD region) that overlaps the gate electrode can be provided between the source and drain regions 9n and the channel region 7n in the N-channel thin film transistor 10n. Can be relaxed. In addition, a margin for reliability can be expanded even if gettering is slightly insufficient in deterioration due to hot carriers, leakage current suppression during off operation, and the like. On the other hand, in the P-channel type thin film transistor 10p, there is no P-type impurity region overlapping with the gate electrode 5p, so that a signal delay due to an increase in parasitic capacitance is not caused. Note that the P-channel thin film transistor 10p can secure sufficient reliability even if it does not have an LDD structure.

  The semiconductor device 15 having the above configuration can be manufactured, for example, by the following method.

  First, an amorphous semiconductor film to which a catalytic element for promoting crystallization is added at least partially is prepared. Next, a first heat treatment is performed on the amorphous semiconductor film, whereby at least part of the amorphous semiconductor film is crystallized to obtain a semiconductor film including a crystalline region. Thereafter, by patterning the semiconductor film including the crystalline region, a plurality of island-like semiconductor layers each having the crystalline region are formed. Next, after forming a gate insulating film over the island-shaped semiconductor layer, a first conductive film is deposited over the gate insulating film, and a second conductive film is deposited over the first conductive film. Next, the first conductive film and the second conductive film are patterned (etched) to form a gate electrode having a first conductive layer and a second conductive layer. For example, a gate electrode having a stepped stacked structure in which the width of the second conductive layer is narrower than the width of the first conductive layer is formed. Subsequently, the region that becomes the gettering region of the island-like semiconductor layer that becomes the active layer of the N-channel TFT and the entire island-like semiconductor layer that becomes the active layer of the P-channel TFT are exposed, and the source of the N-channel TFT is exposed. A first mask is formed so as to cover the region to be the region and the drain region and the gate electrode. Using the first mask and the gate electrode of the P-channel TFT as a mask, a region exposed from the mask of the semiconductor layer is doped with an impurity element imparting p-type. Thereafter, only the gate electrode of the P-channel TFT exposed by the first mask is used to etch the first conductive layer using the second conductive layer as a mask. Subsequently, a region exposed by the first mask in the gate insulating film is etched to reduce the thickness or remove the first mask. Further, the entire island-like semiconductor layer that becomes the active layer of the N-channel TFT and the region that becomes the gettering region of the island-like semiconductor layer that becomes the active layer of the P-channel TFT are exposed, and the source region and drain of the P-channel TFT are exposed. A second mask is formed so as to cover the region to be the region and the gate electrode. Using this second mask and the gate electrode of the N-channel TFT as a mask, an impurity element imparting n-type conductivity is doped into a region of the semiconductor layer exposed from the mask. Subsequently, at least a part of the catalytic element in the island-shaped semiconductor layer is moved to the gettering region by performing a second heat treatment.

  In this specification, an “active layer” of a TFT is formed of an island-shaped semiconductor layer made of a crystalline semiconductor film, and includes a channel region, a source and drain region, a gettering region, an LDD region, and the like. Point to. On the other hand, the “active region” of the TFT includes a source and drain region, a channel region, an LDD region, and the like in the crystalline semiconductor layer, and does not include a gettering region.

  Since the device of this embodiment is manufactured by the above-described method, the thinning process of the gate insulating film for improving the gettering efficiency and the process of separately forming the structures of the N-channel TFT and the P-channel TFT are mutually used. Can be shared. Thereby, the process of manufacturing a high-performance and high-reliability semiconductor device according to the present invention can be greatly simplified.

  Here, using the first mask and the gate electrode of the P-channel TFT as a mask, a step of doping an impurity element imparting p-type into a region of the semiconductor layer that exposes the mask (step A), A step of etching the first conductive layer using the second conductive layer as a mask (step B) only at the gate electrode of the P-channel TFT exposed by the first mask, and the first mask of the gate insulating film is exposed. There are no particular problems even if the order of the four steps, ie, the step of etching or thinning or removing the region (Step C) and the step of removing the first mask (Step D) are changed. In addition, any two or all of the processes B, C, and D can be shared, and can be regarded as a single process on the process by performing continuous processing in the same etching apparatus, and further simultaneous processing. Further process simplification and cost reduction can be achieved.

  In the present embodiment, in the P-channel TFT, the thickness of the gate insulating film on the gettering region and the thickness of the gate insulating film on the source region and the drain region may be substantially the same. Further, the thickness of the gate insulating film on the gettering region in the N-channel TFT may be the same as the thickness of the gate insulating film on the source region and the drain region of the P-channel TFT. Further, the thickness of the gate insulating film on the gettering region in the N-channel TFT may be the same as the thickness of the gate insulating film on the gettering region of the P-channel TFT.

  According to the present embodiment, the generation of leakage current due to segregation of catalytic elements can be suppressed, and the margin of reliability can be expanded in terms of device structure, which makes it possible to make tradeoffs such as an increase in unnecessary parasitic capacitance and addition of processes. It can be realized without any form. In addition, since the semiconductor film crystallized using the catalytic element exhibits good crystallinity, the TFT in this embodiment can obtain high field effect mobility.

  In addition, since the gettering region in the semiconductor layer is disposed in a region other than the region where electrons or holes move during the operation of the thin film transistor, as described above, the gettering region completely serves as the source / drain region in the semiconductor layer. The gettering region can be optimized as a dedicated region only for the purpose of gettering regardless of resistance or the like. However, it is desirable that the gettering region be formed so as not to be adjacent to the channel formation region. In this way, as described above, the junction between the channel region and the source and drain regions can be completely gettered.

  The gettering region may be formed in the outer edge portion of the semiconductor layer, and the wiring for electrically connecting the thin film transistor may be connected to at least a part of the source region or the drain region (contact portion). Alternatively, the wiring for electrically connecting the thin film transistors may be connected to a region including a part of the gettering region and a part of the source region or the drain region. By making such a connection, an electron or hole path can be secured without going through the gettering region, and as described above, the gettering region can be dedicated and optimized. The method for manufacturing a device having such wiring further includes, for example, a step of forming a wiring connected to a contact portion including at least a part of the source region or the drain region after the second heat treatment.

  In this embodiment, an impurity element imparting n-type and an impurity element imparting p-type are used as gettering elements. Thus, the source region and the drain region can be formed at the same time, no additional process for gettering is required, and the manufacturing process can be greatly shortened. In the N-channel TFT in this embodiment, the concentration of the impurity element belonging to Group 5B of the periodic table imparting n-type contained in the gettering region is higher than the concentration of the impurity element contained in the source region or the drain region. high. This is because the source and drain regions and the gettering region are formed in relatively different doping states due to the difference in thickness of the gate insulating film. Therefore, although a region other than the gettering region in the semiconductor layer contains a gettering element (n-type impurity), a large amount of gettering element is introduced into the gettering region by utilizing the difference in thickness of the gate insulating film. Thus, the gettering region can have a stronger gettering action than other regions. As a result, not only the channel region but also the source and drain regions are gettered.

  In the present embodiment, an impurity element belonging to Group B of the periodic table for imparting n-type and a periodic table of Group B for imparting p-type are provided in the gettering regions of the N-channel TFT and the P-channel TFT. And impurity elements belonging to. In a P-channel TFT, only a p-type impurity forming the source and drain regions does not have a gettering action, and therefore an n-type impurity having a gettering action is used as a gettering element. In the case of an n-type impurity element, the solid solubility with respect to the catalytic element in the introduction region increases, and the first gettering action described above is caused. However, by using a p-type impurity element at the same time in addition to the n-type impurity element, the effect as a gettering element is further increased. When the gettering region is doped not only with the group 5 B element but also with the group 3 B element, the gettering mechanism is changed, and in addition to the first gettering action in the case of phosphorus alone, the first is obtained by utilizing defects and local strains. 2 gettering action becomes dominant. As a result, the gettering ability is increased, and a larger gettering effect can be obtained. Specifically, when P (phosphorus) is used as the element selected from Group 5B and B (boron) is used as the element selected from Group 3B element, a higher effect can be obtained.

The concentration of the impurity element imparting n-type in the gettering region, 1 × there ^{10 19 ~3 × 10 21 / cm} 3, the concentration of the impurity element imparting ^{p-type, 1 × 10 19 ~3 × 10} 21 / Preferably it is cm ³ . If the concentration of each impurity element is within the above range, sufficient gettering efficiency can be obtained. Even if these concentrations are above the above range, the gettering efficiency is saturated, and there is no merit in that extra processing time is required.

  The gettering region in this embodiment typically includes more amorphous components and less crystalline components than other regions in the semiconductor layer (channel formation region, source region, and drain region). Have. That is, in the doping step for forming the gettering region, the amorphous portion of the island-like semiconductor layer that overlaps the thinned gate insulating film is made to progress more than the region that becomes the source region and the drain region. Since the free energy of the catalytic element in the amorphous region is lower than that in the crystalline region, the catalytic element is likely to diffuse into the amorphous region. Further, in the amorphous region, a dangling bond or a lattice defect forms a segregation site for trapping the catalytic element, and thus has a second gettering action of moving the catalytic element to the segregation site and trapping. is doing. In the present embodiment, the TFT semiconductor layer has a gettering region separately from the source region and the drain region, and the gettering region is arranged so as not to prevent the movement of carriers (electrons or holes) of the TFT. . Therefore, even if the gettering region becomes amorphous and has a high resistance, the TFT is not affected at all. As a result, an amorphous gettering region having a high gettering capability that has been difficult to use in the past can be formed in the semiconductor layer.

As a specific measurement and evaluation means of the crystalline state of the gettering region, the channel formation region, and the source / drain region, the ratio Pa between the TO phonon peak Pa of the amorphous semiconductor and the TO phonon peak Pc of the crystalline semiconductor in the Raman spectrum. It is effective to use / Pc. In the case of a semiconductor layer made of a silicon film, the peak Pc due to TO phonon of crystalline Si appears in the vicinity of 520 cm ^−1, and the peak Pa due to the TO phonon of amorphous Si broadens in the vicinity of 480 cm ⁻¹ reflecting the density of states. Appears in various shapes. As described above, when the gettering region is configured to have a larger Pa / Pc than the channel formation region and the source and drain regions, high gettering efficiency can be ensured, and the gettering effect as described above can be obtained. Obtainable. Further, in the above manufacturing method, after forming a state in which Pa / Pc in the gettering region is larger than Pa / Pc in the source and drain regions, the state is maintained even after the second heat treatment. It is desirable. If the TFT is completed while maintaining this state, the gettering region always maintains the same level of gettering capability as in the gettering process even when driving the TFT, and the back diffusion of the catalytic element from the gettering region is prevented. Therefore, the reliability of the TFT can be improved.

  In the manufacturing method described above, when the n-channel TFT and the p-channel TFT are simultaneously formed, the process of forming the source and drain regions of each TFT (that is, the n-type doping process and the p-type doping process) is utilized well. Thus, in addition to the gettering region of the p-channel TFT, a gettering region of the n-channel TFT is formed simultaneously. Therefore, the manufacturing process can be simplified. As described above, the p-type impurity itself does not function as a gettering element, but has a strong gettering action when present together with an n-type impurity. Therefore, by forming a gettering region doped with n-type impurities and p-type impurities in the semiconductor layer of the n-channel TFT, the gettering capability of the n-channel TFT can be further enhanced.

  Further, the gate insulating film on the gettering region of the n-channel TFT is selectively thinned. For this reason, the gettering region is introduced with more n-type impurities than the source / drain regions, and receives more doping damage, resulting in more amorphization and crystal defects. Therefore, the gettering ability of the gettering region can be improved by selectively thinning the gate insulating film.

  In the conventional manufacturing method, since the gate insulating film is not selectively thinned, even if the gettering region is formed separately from the source and drain regions in the semiconductor layer, the gettering region is intended to increase the gettering capability. If a gettering element (n-type impurity) is doped in a large amount, the same amount of n-type impurity is also doped in the source and drain regions. The amount of n-type impurities intended for gettering is excessive for the source and drain regions. When such a large amount of n-type impurity is doped, the source and drain regions are made amorphous due to the doping damage, rather than being lowered in resistance, and become extremely high in resistance. The same problem occurs in the case of p-type impurities, but the increase in resistance of the source and drain regions is more conspicuous by doping with n-type impurities, and becomes a serious problem particularly in n-channel TFTs.

  On the other hand, in the present invention, doping suitable for each purpose can be performed simultaneously by making the thickness of the gate insulating film different between the gettering region and the source and drain regions. That is, the gettering region overlapping with the thin gate insulating film is doped with a larger amount of n-type impurity or p-type impurity than the source and drain regions, and amorphization progresses due to doping damage at that time. The ring area is in the best state. On the other hand, in the source and drain regions overlapping with the thick gate insulating film, the doping damage during these dopings is small, and the resistance is reduced while maintaining the crystalline state.

  The present inventors obtained profile data of n-type impurities in a doping apparatus by SIMS (secondary ion mass spectrometry). FIG. 12 is a graph showing an example thereof.

  FIG. 12 is a concentration profile in the film thickness direction when phosphorus is doped as an n-type impurity in the silicon oxide film. The horizontal axis of the graph shown in FIG. 12 is the depth from the surface, and the zero point is the outermost surface of the silicon oxide film. From FIG. 12, it can be seen that the phosphorus concentration at the position where the depth from the surface is 500 mm (50 nm) is about five times the phosphorus concentration at the position where the depth from the surface is 1000 mm (100 nm). Therefore, for example, when the thickness of the gate insulating film on the source and drain regions is set to 100 nm, the thickness of the gate insulating film on the gettering region is reduced to 50 nm, and phosphorus is doped as an n-type impurity, gettering is performed. The concentration of phosphorus in the region is about 5 times the concentration of phosphorus in the source and drain regions. In addition, since the upper gate insulating film is thin, phosphorus ions are implanted into the gettering region at a higher acceleration voltage than the source and drain regions under the thick gate insulating film. Therefore, in the gettering region, the impact energy of individual ions is large, the crystallinity is further lost, and amorphization proceeds. On the other hand, in the source and drain regions, since the gate insulating film is thick, phosphorus is not excessively implanted, and the impact energy of ions at the time of implantation is low. Can be maintained. In this manner, the gettering region and the source and drain regions can be easily formed in a crystalline state suitable for each purpose.

  Furthermore, according to the manufacturing method described above, the gate insulating film on the gettering region can be thinned or removed to increase the gettering capability, and the margin for remaining catalyst elements can be increased to improve the reliability of the apparatus. it can. More specifically, in the above-described manufacturing method, the first conductive film and the second conductive film are deposited on the gate insulating film, and the first conductive film and the second conductive film are patterned (etched). A gate electrode having a stepped stacked structure is formed such that the width of the second conductive layer made of the second conductive film is narrower than that of the first conductive layer made of the first conductive film. By forming the gate electrode having such a structure, the LDD region can be formed in a self-aligned manner with respect to the gate electrode during doping. As a result, in addition to improving reliability or reducing off-state current, the size of the semiconductor element can be reduced and the degree of integration can be increased.

  Here, in the step of patterning the first conductive film and the second conductive film to form a gate electrode having a stepped stacked structure, the second conductive film is etched so as to have the first taper angle. Etching the first conductive film (process E), etching the first conductive film (process F), and selectively etching the second conductive film etched to have the first taper angle. And a step (step G) of performing etching so as to have a second taper angle that is larger than the first taper angle. As a result, the gate electrode having the stepped stacked structure can be easily formed with good controllability.

  Moreover, it is preferable that the said process E, F, and G is performed continuously within an etching apparatus. Thereby, the gate electrode having the stepped laminated structure can be easily formed without increasing the number of manufacturing processes. Further, the manufacturing cost can be reduced.

  In the manufacturing method described above, in the step of doping an impurity element imparting n-type into a region exposed from the mask of the semiconductor layer using the second mask and the gate electrode of the N-channel TFT as a mask. The doping may be performed across the first conductive layer using the second conductive layer of the gate electrode as a mask. Alternatively, using the second mask and the gate electrode of the N-channel TFT as a mask, a step of doping an impurity element imparting n-type into a region exposed from the mask in the semiconductor layer may be performed by Using the second conductive layer as a mask, doping the impurity element imparting n-type over the first conductive layer at a low concentration, and using the first conductive layer of the gate electrode as a mask, the impurity element imparting n-type And a step of doping at a high concentration. By performing such a process, the LDD region overlapping with the gate electrode can be formed by utilizing the difference in the channel width of the conductive layer between the first conductive layer and the second conductive layer (the length of the stepped portion). It can be formed in a self-aligning manner.

  Using the second conductive layer of the gate electrode as a mask, doping the impurity element imparting n-type over the first conductive layer at a low concentration, and applying the n-type using the first conductive layer of the gate electrode as a mask The step of doping the impurity element at a high concentration is preferably performed continuously in the same doping apparatus. Thereby, the acceleration voltage at the time of doping can be set to the film thickness of each object, a process with high controllability can be executed, and a substantial increase in the number of steps can be prevented.

  Further, the step of doping the impurity element imparting n-type over the first conductive layer with a low concentration using the second conductive layer of the gate electrode as a mask, and the n-type using the first conductive layer of the gate electrode as a mask The step of doping the impurity element to be applied at a high concentration is preferably performed at the same time. When variation in the thicknesses of the first conductive layer and the gate insulating film can be reduced, the doping acceleration voltage is adjusted to the optimum value, and the profile difference is used to perform the above two steps in one doping step. Can be performed simultaneously. In this case, the process is most efficient, and there is no increase in processing time even when compared with the case where no LDD is created.

  The step of patterning (etching) the conductive film in this embodiment to form a gate electrode can be performed by an ICP (Inductively Coupled Plasma) etching method or an RIE (reactive ion etching) method. When these etching methods are used, the conductive film can be processed with high accuracy so as to have a predetermined taper angle. In particular, the stacked first conductive film and second conductive film can be etched stepwise with high etching accuracy, which is advantageous.

  In addition, it is preferable to activate n-type impurities and / or p-type impurities doped in at least the source region and the drain region in the island-shaped semiconductor layer by the second heat treatment. In this way, by performing gettering and activation simultaneously in the second heat treatment process, the process can be shortened and an additional process by gettering, which was a problem in the prior art, can be omitted. As a result, the manufacturing process can be simplified and the manufacturing cost can be reduced.

  In addition, it is preferable to use an element selected from W, Ta, Ti, and Mo, or one or more kinds of alloy materials containing the above elements as the material of the gate electrode. In this embodiment, after the gate electrode is formed, the second heat treatment for gettering is performed. This heat treatment needs to be performed at a high temperature of 500 ° C. or higher. Therefore, the material for the gate electrode is desirably a refractory metal as exemplified above from the viewpoint of heat resistance.

  In this embodiment, the step of preparing the amorphous semiconductor film includes a step of forming a mask having an opening on the amorphous semiconductor film, and a catalyst element selected through the opening. And a step of adding to the region. In this case, after the catalytic element is selectively added to the amorphous semiconductor film, in the first heat treatment, crystal growth is performed in the lateral direction from the region where the catalytic element is selectively added to the periphery thereof. A crystalline semiconductor film is formed. Therefore, it is possible to obtain a good crystalline semiconductor film in which the crystal growth direction is substantially aligned in one direction, and it is possible to further increase the current driving capability of the TFT.

  As the catalyst element, one or more elements selected from Ni, Co, Sn, Pb, Pd, Fe, and Cu can be used. One or more elements selected from these exhibit the effect of promoting crystallization in a trace amount.

The catalytic element does not act alone, but acts on crystal growth by bonding to the silicon film and silicidation. At this time, the crystal structure of the silicide acts as a kind of template during crystallization of the amorphous silicon film, and promotes crystallization of the amorphous silicon film. When Ni is used as the catalyst element, Ni forms a silicide of _two Si and NiSi ₂ . NiSi ₂ exhibits a meteorite-type crystal structure, which is very similar to the diamond structure of single crystal silicon. Moreover, NiSi ₂ has a lattice constant of 5.406 、, which is very close to the lattice constant of 5.430 に お け る in the diamond structure of crystalline silicon. Therefore, NiSi ₂ is optimal as a template for crystallizing an amorphous silicon film. Therefore, among the elements exemplified above, when Ni is used in particular, the effect of promoting the most remarkable crystallization can be obtained.

Since the apparatus of this embodiment is manufactured using a crystalline semiconductor film manufactured using a catalytic element, a catalytic element that promotes crystallization of the amorphous semiconductor film exists in the gettering region. ing. The concentration of the catalytic element present in the gettering region is, for example, 5 × 10 ¹⁸ atoms / cm ³ or more. At this time, the concentration of the catalytic element in the channel region is reduced, for example, to a range of about 1 × 10 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ³ . That is, the concentration of the catalytic element in the channel region is reduced to the above range by the gettering step, and as a result, the catalytic element concentration in the gettering region is increased by 2 to 4 orders of magnitude compared to the catalytic element concentration in the channel region.

  At least the channel region of the semiconductor layer is preferably formed of a crystalline semiconductor film whose crystal plane orientation is mainly constituted by <111> crystal zone planes. More preferably, at least the channel region of the semiconductor layer has a crystal plane orientation mainly composed of <111> crystal zone planes, and the plane orientation ratio is particularly ( It is formed from a crystalline semiconductor film in which 50% or more of the entire region is occupied by (110) plane orientation and (211) plane orientation.

  In general, when an amorphous semiconductor film is crystallized without using a catalytic element, the plane orientation of the crystalline semiconductor film is affected by the influence of the insulator underlying the semiconductor film (especially in the case of amorphous silicon dioxide). , (111). On the other hand, when a catalyst element is added to the amorphous semiconductor film and crystallized as in the present embodiment, unique growth as shown in FIG. 13A is performed. In FIG. 13A, 61 is a base insulator, 62 is an amorphous semiconductor film in an uncrystallized region, 63 is a crystalline semiconductor film, and 64 is a semiconductor compound of a catalytic element serving as a driving force for crystal growth. is there. The catalytic element compound 64 exists at the forefront of crystal growth, and the adjacent amorphous regions 62 are crystallized one after another toward the right side of the drawing. At this time, the catalytic element compound 64 is in the <111> direction. It has the property of growing strongly toward As a result, as the plane orientation of the obtained crystalline semiconductor film, a <111> crystal zone plane appears as shown in FIG.

  The <111> crystal zone plane is shown in FIG. In FIG. 13B, the horizontal axis is the inclination angle from the (−110) plane, and the vertical axis is the surface energy. The group 65 is a crystal plane that becomes a <111> crystal zone plane. The (100) plane and the (111) plane are not <111> crystal zone planes, but are shown for comparison. FIG. 13C shows a standard triangle of crystal orientation. Here, the distribution of the <111> crystal zone plane is as shown by the broken line in FIG. The numbers are typical pole indices. In the crystalline semiconductor film in this embodiment, among these <111> crystal zone planes, the (110) plane or (211) plane is predominantly oriented, and this plane dominates when it accounts for 50% or more of the entire plane. Sex is obtained. These two crystal planes have a very high hole mobility compared to the other planes, can improve the performance of P-channel TFTs that are inferior to N-channel TFTs, and are easily balanced in semiconductor circuits. There are benefits.

  FIG. 14 shows a plane orientation distribution of the crystalline semiconductor film obtained by using the catalyst element in the present embodiment. FIG. 14 shows the result of EBSP measurement, in which the crystal orientation is specified separately for each minute region, and these are connected and mapped. FIG. 14A shows a plane orientation distribution in the crystalline semiconductor film of the present invention, and FIG. 14B shows a plane between adjacent mapping points based on the data in FIG. Those having an inclination angle of azimuth or less (here, 5 ° or less) are separately painted with the same color, and the distribution of individual crystal domains is highlighted. FIG. 14C shows the standard triangle of the crystal orientation described above with reference to FIG. As can be seen from FIG. 14C, the crystalline semiconductor film according to the present invention shows a plane orientation almost on the <111> crystal zone plane, and is particularly strongly oriented in the (110) plane and the (211) plane. I can see that The size of each crystal domain (substantially the same plane orientation region) shown in FIG. 14B is distributed in the range of 2 to 10 μm. Thus, in the apparatus of this embodiment, it is preferable that the domain diameter of the crystal domain (substantially the same plane orientation region) of the crystalline semiconductor film constituting the semiconductor layer is 2 to 10 μm. The above-described plane orientation, the ratio of plane orientation, and the domain diameter of the crystal domain are values measured by EBSP measurement.

  In the method for manufacturing the device of this embodiment, it is desirable to irradiate the crystalline semiconductor film with laser light after the first heat treatment. When a crystalline semiconductor film is irradiated with laser light, a crystal grain boundary part and a minute residual amorphous region (uncrystallized region) are intensively processed due to a difference in melting point between the crystalline part and the amorphous part. . A crystalline silicon film crystallized by introducing a catalytic element is formed of columnar crystals, and the inside thereof is in a single crystal state. Therefore, when the crystal grain boundary is processed by laser light irradiation, a high-quality crystalline semiconductor film close to a single crystal state can be obtained over the entire surface of the substrate, so that crystallinity is greatly improved. As a result, the on-characteristics of the TFT are greatly improved, and a semiconductor device superior in current drive capability can be realized.

  Hereinafter, the configuration of an apparatus according to the present invention and an embodiment of a manufacturing method thereof will be described more specifically with reference to the drawings.

(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS. In the present embodiment, a manufacturing process of a driver monolithic active matrix liquid crystal display device in which a peripheral drive circuit is integrally formed on the same substrate as a pixel TFT will be described. In other words, in the present embodiment, a CMOS structure circuit in which an n-channel TFT and a p-channel TFT are complemented on a glass substrate and a pixel TFT (N-channel type) that switches the pixel electrode are simultaneously provided. It is formed.

First, as shown in FIG. 2A, base films 102 and 103 are formed on a surface of a substrate 101 on which a TFT is to be formed. The substrate 101 only needs to have an insulating surface, and may be, for example, a low alkali glass substrate or a quartz substrate. In this embodiment, a low alkali glass substrate is used as the substrate 101. In this case, the substrate 101 may be heat-treated in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. The base films 102 and 103 are provided to prevent impurity diffusion from the substrate 101, and may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. In the present embodiment, a silicon oxynitride film is formed as the lower first base film 102 by using, for example, a plasma gas CVD method using a material gas of SiH ₄ , NH ₃ , and N ₂ O. Further, as the second base film 103, a silicon oxide film is similarly formed on the first base film 102 using TEOS and oxygen as material gases by plasma CVD. At this time, the thickness of the first base film (silicon oxynitride film) 102 is preferably 25 to 400 nm, for example, 100 nm. The thickness of the second base film (silicon oxide film) 103 is preferably 25 to 300 nm, for example, 100 nm. In the present embodiment, a base film composed of two layers is formed, but the base film may be a single layer of a silicon oxide film, for example.

  Next, a silicon film (a-Si film) 104 having an amorphous structure is formed by a known method such as a plasma CVD method or a sputtering method. The thickness of the a-Si film 104 is, for example, 20 to 150 nm, preferably 30 to 80 nm. In this embodiment, an amorphous silicon film having a thickness of 50 nm is formed by plasma CVD. Furthermore, in this embodiment, the base films 102 and 103 and the a-Si film 104 are continuously formed without being exposed to the air atmosphere using a multi-chamber plasma CVD apparatus. As a result, it is possible to prevent contamination at the interface between the base film 103 and the a-Si film 104 (which becomes a back channel in a TFT), and to reduce variation in characteristics and threshold voltage of the TFT to be manufactured. it can.

Thereafter, a small amount of a catalytic element (nickel in this embodiment) 105 is added onto the surface of the a-Si film 104 (FIG. 2A). This small amount of nickel 105 is added by holding the solution in which nickel is dissolved on the a-Si 104 and then uniformly extending the solution onto the substrate 101 by a spinner and drying it. In this embodiment, nickel acetate is used as the solute of the solution, and water is used as the solvent. Further, the nickel concentration in the solution is adjusted to be, for example, 5 ppm in terms of weight. The amount of catalytic element added by this process is extremely small. The concentration of the catalytic element on the surface of the a-Si 104 is controlled by a total reflection X-ray fluorescence analysis (TRXRF) method, and is, for example, about 5 × 10 ¹² atoms / cm ² .

  In addition to nickel (Ni), the catalyst element 105 may be one or more selected from iron (Fe), cobalt (Co), tin (Sn), lead (Pb), palladium (Pd), and copper (Cu). It may be an element. Although the catalytic effect is smaller than these elements, ruthenium (Ru), rhodium (Rh), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), etc. also function as the catalytic element 105. Further, as a method for adding the catalytic element 105 to the a-Si film 104, a gas phase method such as a plasma doping method, a vapor deposition method, or a sputtering method may be used in addition to a method of applying a solution containing the catalytic element. it can. The method of applying a solution containing a catalytic element is advantageous because the amount of catalytic element added can be easily controlled and a very small amount of catalytic element can be easily added.

  Subsequently, the substrate 101 is heat-treated in an inert atmosphere, for example, in a nitrogen atmosphere. As this heat treatment, it is preferable to perform an annealing treatment at 550 to 620 ° C. for 30 minutes to 4 hours. In this embodiment, as an example, heat treatment is performed at 590 ° C. for 1 hour. By this heat treatment, nickel 105 added to the surface of the a-Si film 104 is diffused into the a-Si film 104 and silicidation occurs, and the crystallization of the a-Si film 104 proceeds using this as a nucleus. As a result, as shown in FIG. 2B, the a-Si film 104 is crystallized into a crystalline silicon film 104a. Note that although crystallization is performed here by heat treatment using a furnace, crystallization may be performed by an RTA (Rapid Thermal Annealing) apparatus using a lamp or the like as a heat source.

  Prior to the heat treatment, the surface of the a-Si 204 may be slightly oxidized with ozone water or the like in order to improve the wettability of the surface of the a-Si film 104 during spin coating. After that, first heat treatment is performed on the substrate 101 in an inert atmosphere, for example, in a nitrogen atmosphere (FIG. 5B). At this time, annealing is performed at 530 to 600 ° C. for 30 minutes to 8 hours. In this example, as an example, heat treatment was performed at 550 ° C. for 4 hours. In this heat treatment, nickel 205 added to the surface of the a-Si film 204 is diffused into the a-Si film 204 and silicidation occurs, and the crystallization of the a-Si film 204 proceeds using this as a nucleus. . As a result, the a-Si film 204 is crystallized to become a crystalline silicon film 204a. Note that although crystallization is performed here by heat treatment using a furnace, crystallization may be performed by an RTA (Rapid Thermal Annealing) apparatus using a lamp or the like as a heat source. The crystal plane orientation of the crystalline silicon film 204a thus obtained is mainly composed of the <111> crystal zone plane, and among them, (110) plane orientation and (211) plane orientation are 50% of the whole. These areas are occupied. Moreover, the domain diameter of the crystal domain (substantially the same plane orientation region) is 2 to 10 μm.

  Subsequently, as shown in FIG. 2C, the crystalline silicon film 104a obtained by the heat treatment is irradiated with a laser beam 106, whereby the crystalline silicon film 104a is further recrystallized and crystallinity is improved. The formed crystalline silicon film 104b is formed. As the laser light at this time, an XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) or a KrF excimer laser (wavelength 248 nm) can be applied. The beam size of the laser light at this time is shaped to be a long shape on the surface of the substrate 101, and the entire surface of the substrate is recrystallized by sequentially scanning in the direction perpendicular to the long direction. . At this time, scanning is performed so that parts of the beams overlap each other, so that laser irradiation is performed a plurality of times at any one point of the crystalline silicon film 104a, thereby improving uniformity. If the energy of the laser beam at this time is too low, the crystallinity improvement effect is small, and if it is too high, the crystalline state of the crystalline silicon film 104a obtained in the previous step is reset, so it is necessary to set it within an appropriate range. There is. Thus, the crystalline silicon film 104a obtained by solid-phase crystallization is reduced in crystal defects by a melting and solidifying process by laser irradiation, and becomes a higher quality crystalline silicon film 104b. Even after this laser irradiation step, the crystal plane orientation and crystal domain state before laser irradiation are maintained as they are, and no significant change is observed in the EBSP measurement. However, a ridge is generated on the surface of the crystalline silicon film 104b, and the average surface roughness Ra is 2 to 10 nm.

  Thereafter, unnecessary portions of the crystalline silicon film 104b are removed, and element isolation is performed. By this step, as shown in FIG. 2D, island-like crystalline silicon films (semiconductor layers) 107n, 107p, and 107g that will later become active regions (source and drain regions, channel regions) of the TFT are formed. . The semiconductor layer 107n becomes a later n-channel TFT, the semiconductor layer 107p becomes a p-channel TFT, and the semiconductor layer 107g becomes a pixel TFT.

Here, the p-type layer is formed on the entire surface of the semiconductor layers 107n and 107p to be n-channel TFTs and p-channel TFTs at a concentration of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ / cm ³ for the purpose of controlling the threshold voltage. Boron (B) may be added as an impurity element imparting. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of an amorphous silicon film. For the purpose of controlling the threshold value of only the n-channel TFT, the p-channel TFT semiconductor layer 107p is covered with a photoresist so that only the n-channel TFT semiconductor layer 107n or the pixel TFT semiconductor layer 107g is covered. Boron may be added at a low concentration. Note that boron is not necessarily added, but boron is preferably added to the semiconductor layer 107n in order to keep the threshold voltage of the n-channel TFT within a predetermined range.

  Subsequently, as shown in FIG. 3A, a gate insulating film 108 covering these semiconductor layers 107n, 107p, and 107g is formed. The gate insulating film 108 is preferably a silicon oxide film (thickness: 20 to 150 nm). Here, a silicon oxide film having a thickness of 100 nm is used. Here, the silicon oxide film is formed by using TEOS (Tetra Ethoxy Ortho Silicate) as a raw material, decomposed and deposited by RF plasma CVD method with oxygen at a substrate temperature of 150 to 600 ° C., preferably 300 to 450 ° C. Do. After the formation of the silicon oxide film, in order to improve the bulk characteristics of the gate insulating film 108 itself and the interface characteristics between the crystalline silicon film and the gate insulating film 108, a few minutes at 500 to 700 ° C. in an inert gas atmosphere Annealing for several hours may be performed. The gate insulating film 108 may be a single layer of an insulating film containing other silicon or may have a stacked structure.

  Next, a conductive film (A) 109 and a conductive film (B) 110 are formed to form a gate electrode. In this embodiment, a conductive film (A) 109 made of a conductive nitride metal film and a conductive film (B) 110 made of a metal film are stacked. The conductive film (B) 110 is an element selected from the group consisting of tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the element as a main component, or a combination of the elements. Or an alloy film (typically, a Mo—W alloy film or a Mo—Ta alloy film). The conductive film (A) 109 can be formed using tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, or molybdenum nitride (MoN). Alternatively, tungsten silicide, titanium silicide, or molybdenum silicide may be used as a material for the conductive film (A) 109. In order to reduce the resistance of the conductive film (B) 110, the impurity concentration in the conductive film (B) 110 is preferably reduced, and in particular, the oxygen concentration is preferably reduced to 30 ppm or less. For example, in the case of the conductive film (B) 110 formed from tungsten (W), when the oxygen concentration is 30 ppm or less, a specific resistance value of 20 μΩcm or less can be realized.

  The thickness of the conductive film (A) 109 is, for example, 10 to 50 nm, preferably 20 to 30 nm. The conductive film (B) 110 has a thickness of, for example, 200 to 400 nm, preferably 250 to 350 nm. In this embodiment, a tantalum nitride (TaN) film with a thickness of 30 nm is used as the conductive film (A) 109, and a tungsten (W) film with a thickness of 350 nm is used as the conductive film (B) 110. All of these conductive films are formed by sputtering. When these conductive films are formed using a sputtering method, if an appropriate amount of Xe or Kr is added to the sputtering gas Ar, the internal stress of the formed conductive film is relieved and peeling of the conductive film is prevented. be able to.

  Next, as shown in FIG. 3A, resist masks 111n, 111p, and 111g are formed so as to cover a part of each semiconductor layer, and a gate electrode of each TFT is formed.

First, a first etching process is performed on the conductive film (A) 109 and the conductive film (B) 110 under a first etching condition. The first etching conditions in this embodiment can be set as follows. In an ICP (Inductively Coupled Plasma) etching method, CF ₄ , Cl _2, and O ₂ are used as etching gases, and the respective gas flow ratios are set to 25/25/10 (sccm). Etching is performed by generating 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa to generate plasma. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. By conducting the first etching, the conductive film (B) (W film) 110 is patterned, and the end portion is tapered. As a result, as shown in FIG. 3B, conductive layers (B) 112n, 112p, and 112g are formed on each semiconductor layer.

Thereafter, the second etching is performed under the second etching condition without removing the masks 111n, 111p, and 111g. The second etching condition can be set as follows, for example. CF ₄ and Cl ₂ are used as etching gases, the respective gas flow ratios are set to 30/30 (sccm), and 500 W of RF (13.56 MHz) power is supplied to the coil-type electrode at a pressure of 1 Pa to generate plasma. For about 30 seconds. 20 W RF (13.56 MHz) power is also applied to the substrate side, and a substantially negative self-bias voltage is applied. When the conductive film (A) (TaN film) 109 is patterned using the gas mixture of CF ₄ and Cl _{2 under} such conditions (second etching), the gate electrode lower layer 113n made of the conductive film (B), 113p and 113g are formed. This state corresponds to the state shown in FIG. Here, the photoresist masks 111n, 111p, and 111g are reduced in thickness by the etching process, and the width is narrower than the initial one.

Further, the third etching process is performed under the third etching condition without removing the masks 111n, 111p, and 111g. For example, the third etching condition can be set as follows. CF ₄ , Cl _2, and O ₂ are used as etching gases, the gas flow ratio is 20/20/20 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa. To apply a substantially negative self-bias voltage. When etching is performed under the third etching condition, the conductive layers (A) (W layers) 112n, 112p, and 112g are selectively etched with anisotropy. At this time, the gate electrode lower layer (TaN layer) 113n, 113p, 113g is not etched, and only the W layer is etched in the lateral direction. As a result, upper layers 114n, 114p, and 114g of the gate electrode are formed from the conductive layer (A). The ends of the upper layers (W layers) 114n, 114p, and 114g of the gate electrode stand upright, and the taper angle at the ends is 80 to 90 °. In this manner, as shown in FIG. 3C, the gate electrodes 140n, 140p, 140g having a stacked structure including the W layers 114n, 114p, 114g and the TaN layers 113n, 113p, 113g are formed. Complete. Here, the gate electrode 140g of the pixel TFT has a dual gate structure in which two TFTs are connected in series for the purpose of reducing a leakage current when the TFT is turned off. That is, two gate electrodes 140g are formed so as to cover one semiconductor layer 107g. The gate structure of the pixel TFT may be a triple gate or quad gate structure in which the number of gate electrodes 140g (the number of TFTs connected in series) is further increased.

Next, as shown in FIG. 4A, a low-concentration impurity (phosphorus) 115 is implanted into the semiconductor layers 107n, 107p, and 107g by the ion doping method using the gate electrodes 140n, 140p, and 140g as a mask. At this time, the acceleration voltage is set for the gate insulating film 108 and the gate electrode lower layer 113. Therefore, the low-concentration n-type impurity 115 is not implanted into portions of the semiconductor layers 107n, 108p, and 107g that overlap with the gate electrode lower layers 113n, 113p, and 113g. As the doping gas, phosphine (PH ₃ ) is used, the acceleration voltage is set to 40 to 80 kV, for example, 60 kV, and the dose amount is set to 1 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² , for example, 1 × 10 ¹³ cm ⁻² . Through this process, low-concentration phosphorus 115 is implanted into the region 116 of the semiconductor layers 107n, 107p, and 107g that is not covered with the gate electrodes 140n, 140p, and 140g.

  Next, as shown in FIG. 4B, in the n-channel TFT and the pixel TFT, a doping mask 117n made of photoresist covers the gate electrodes 140n and 140g and exposes the outer edges of the semiconductor layers 107n and 107g. 117g is provided. At this time, no mask is provided above the p-channel TFT, and the entire TFT is exposed.

  Subsequently, a fourth etching process is performed on the gate electrode 140p of the p-channel TFT. In the fourth etching, the gate electrode lower layer (TaN layer) 113p is selectively etched using the gate electrode upper layer (W layer) 114p as a mask. As a result, the width of the upper W layer 114p and the lower TaN layer 118p of the gate electrode 140p of the p-channel TFT becomes the same, so that the p-channel TFT has a different shape from the n-channel TFT.

The etching conditions in the fourth etching can be set as follows, for example. CF ₄ and Cl ₂ are used as etching gases, and the respective gas flow ratios are set to 30/30 (sccm). Further, 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma, and etching is performed for about 30 seconds. 20 W RF (13.56 MHz) power is also applied to the substrate side, and a substantially negative self-bias voltage is applied. Under such conditions, only the gate electrode lower layer (TaN layer) 113p can be selectively etched.

Subsequently, as shown in FIG. 4C, gate insulation is performed using the resist masks 117n and 117g used in the fourth etching process for the gate electrode of the p-channel TFT and the gate electrode 140p of the p-channel TFT as a mask. By etching the film 108, a gate insulating film 119 which is selectively thinned is formed. In the present embodiment, CHF ₃ is used as an etching gas by an RIE (reactive ion etching) method, for example, etching of about 50 nm is performed. For the selective etching of the gate insulating film 119, a normal plasma etching method, an ICP (Inductively Coupled Plasma) etching method, or the like can be applied, and other fluorocarbons such as CF ₄ and SF ₆ are used as an etching gas. System gases can also be used. In this embodiment, the gate insulating film 108 is etched by a dry process, but wet etching using hydrofluoric acid or the like may be used.

  Through the above process, the region of the gate insulating film 119 that is not covered with the masks 117n and 117g and the gate electrode 140p of the p-channel TFT is thinned. In this embodiment, since the etching amount in this step is set to 50 nm, for example, the thickness of the gate insulating film 119 in the selectively thinned region is about 50 nm. Note that the amount of etching of the gate insulating film 119 at this time may be determined conveniently by the practitioner, and the gate insulating film in the opening may be completely removed.

Next, using the resist masks 117n and 117g and the gate electrode 140p of the p-channel TFT used in the above steps as masks, an impurity (boron) 120 imparting p-type is implanted into each semiconductor layer by an ion doping method. Diborane (B ₂ H ₆ ) is used as a doping gas, the acceleration voltage is 40 kV to 80 kV, for example 60 kV, and the dose is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² , for example 5 × 10 ¹⁶ cm ⁻² . To do. Through this step, boron is implanted at a high concentration into the regions 121n and 121g exposed from the masks 117n and 117g in the semiconductor layers 107n and 107g of the n-channel TFT and the pixel TFT. Further, in the p-channel TFT semiconductor layer 107p, boron 120 is implanted at a high concentration into a region 122 other than the channel region 123p overlapping with the gate electrode 140p. The region 122 is p-type because the n-type impurity phosphorus implanted at a low concentration in the previous step is inverted by a high-concentration p-type impurity (boron). At this time, the concentration in the film of the p-type impurity element (boron) 120 in the regions 121n and 121g and the region 122 is 1 × 10 ^{19 to} 3 × 10 ²¹ / cm ³ .

  Subsequently, after removing the resist masks 117n and 117g, as shown in FIG. 5A, a doping mask 124g made of a photoresist is formed on the semiconductor layer 107g of the pixel TFT so as to largely cover the gate electrode 140g. Is provided. Further, a doping mask 124p made of a photoresist is provided so as to cover the gate electrode 140p of the p-channel type TFT further and to expose the outer edge portion of the semiconductor layer 107p. At this time, no mask is provided above the n-channel TFT, and the entire TFT is exposed.

Thereafter, an n-type impurity (phosphorus) 125 is implanted into each of the semiconductor layers 107n, 107p, and 107g by ion doping using the resist masks 124p and 124g and the gate electrode 140n of the n-channel TFT as a mask. In the present embodiment, phosphine (PH ₃ ) is used as the doping gas. Further, phosphorus 125 is doped in two steps by changing the acceleration voltage and the dose. In the first doping, the acceleration voltage is set to 40 to 80 kV, for example, 60 kV, and the dose is set to 1 × 10 ¹⁵ to 2 × 10 ¹⁶ cm ⁻² , for example, 6 × 10 ¹⁵ cm ⁻² . In the second doping, the acceleration voltage is set to 80 to 100 kV, for example, 90 kV, and the dose amount is set to 5 × 10 ^{12 to} 5 × 10 ¹⁴ cm ⁻² , for example, 1 × 10 ¹⁴ cm ⁻² . These two doping steps may be performed continuously in the same doping chamber.

  In the first doping process, high-concentration phosphorus is implanted into the regions exposed from the gate electrode 140n and the resist masks 124p and 124g in the semiconductor layers 107n, 107p, and 107g, and the high-concentration n-type impurity regions 128n and 128g. 129n, 129p, and 129g are formed. At this time, in the pixel TFT semiconductor layer 107g, the region 128 that is covered with the resist mask 124g and is not doped with high-concentration phosphorus remains as a region into which low-concentration phosphorus is implanted, thereby forming a conventional LDD region. . Thereby, it is possible to suppress the leakage current particularly during the off operation. In the pixel TFT semiconductor layer 107g, a region overlapping with the gate electrode 140g is a channel region 123g. In the p-channel TFT semiconductor layer 107p, the region 122 covered with the resist mask 124p and not doped with high-concentration phosphorus remains as a region into which only boron is implanted, and the source and drain of the p-channel TFT It becomes an area.

  Also, in the second doping step, low concentration phosphorus is implanted through the gate electrode lower layer 113n in the region of the semiconductor layer 107n of the n-channel TFT that does not overlap with the upper layer 114n of the gate electrode 140n. An n-type impurity region 127 is formed. In this second doping step, the region overlying the upper layer 114n of the gate electrode 140n in the semiconductor layer 107n is masked by the upper layer 114n of the gate electrode, so that phosphorus does not reach and is not doped. As a result, in the semiconductor layer 107n of the n-channel TFT, the region where phosphorus is implanted at a low concentration becomes an LDD region 127 overlapping with the gate electrode 140n. Since the overlap length of the LDD region 127 is determined by the length of the gate electrode lower layer 113n exposed from the gate electrode upper layer 114n, the LDD region is formed in a self-aligned manner. Further, in the n-channel TFT semiconductor layer 107n, a region where phosphorus is not implanted by being masked by the upper layer 104n of the gate electrode becomes a later channel formation region 123n. By doing in this way, hot carrier tolerance can be improved greatly and the reliability of TFT can be improved greatly.

  In this embodiment, the low acceleration voltage and high dose doping step for forming the high concentration region is performed first, but the doping step for forming the low concentration region may be performed. In this embodiment, the doping process is performed twice. However, the acceleration voltage and the dose amount are adjusted, and the ion range difference corresponding to the thickness of the lower layer of the gate electrode is used to perform the doping process once. It is also possible to make a high concentration region and a low concentration region separately in the doping process.

  Here, in the above-described step of doping with high-concentration phosphorus, an upper layer is formed in each of the semiconductor layers 107n, 107p, and 107g in a region not covered with the gate electrode 140n of the N-channel TFT and the masks 124p and 124g. Phosphorus is doped through the gate insulating film 119. Depending on the thickness of the gate insulating film 119 existing on the gate insulating film 119, the doping state of phosphorus is different between the region where the gate insulating film is thinned and the other region. It will be very different.

  The doping profile at this time is shown in FIG. The regions 128n and 128g are doped with phosphorus through the gate insulating film 109 having a thickness of 100 nm. Therefore, the silicon film having the depth of 1000 to 1500 mm (100 to 150 nm) in FIG. The concentration of phosphorus doped therein. On the other hand, in the regions 129n, 129p, and 129g in which the gate insulating film 109 is thinned, the thickness of the upper gate insulating film is, for example, 50 nm. The position of 100 nm) is the concentration of phosphorus doped in the silicon films of the regions 129n, 129p, and 129g. Therefore, a large concentration difference occurs between the regions 128n and 128g and the regions 129n, 129p, and 129g despite the same doping process. In this embodiment, the actual amount of phosphorus doped in the regions 129n, 129p, and 129g that overlap the thinned portion of the gate insulating film 119 overlaps with the portion of the gate insulating film 119 that is not thinned. It is 5 times or more of the areas 128n and 128g. In addition, in the regions 129n, 129p, and 129g, phosphorus ions are contained in the semiconductor layer at a relatively higher acceleration voltage than the regions 128n and 128g where the upper gate insulating film is thicker because the upper gate insulating film is thinner. Injected. For this reason, the impact energy of each ion is large, the crystallinity is broken, and it is made more amorphous. On the other hand, in the regions 128n and 128g, the impact energy of ions at the time of implantation is relaxed by the gate insulating film 109, so that the amorphous state does not occur and the crystalline state can be maintained.

In the n-channel TFT and the pixel TFT, the regions 128n and 128g become source and drain regions of the later TFT, and the regions 129n and 129g become gettering regions. Also in the p-channel TFT, a high-concentration impurity (phosphorus) is implanted at the same level as the gettering regions 129n and 129g of the n-channel TFT and the pixel TFT, and the amorphous region 129p is a gettering region. It becomes. On the other hand, the region covered with the resist mask 124p and not doped with high-concentration phosphorus remains as a p-type impurity region, and forms the source and drain regions 122 of the p-channel TFT. The gettering regions 129n, 129p, and 129g are in a state in which high-concentration phosphorus is added in addition to boron 120 in the previous step. In this way, the gettering region and the source / drain region can be easily formed in a state suitable for each purpose. In the present embodiment, the n-type impurity element (phosphorus) concentration in the film in the gettering regions 129n, 129p, and 129g is 1 × 10 ^{19 to} 3 × 10 ²¹ / cm ³ . Further, the n-type impurity element (phosphorus) concentration in the LDD region 127 of the n-channel TFT is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ . When it is in such a range, it can function as an LDD region.

Next, after removing the resists 124p and 124g used as masks in the previous step, heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere. In this heat treatment step, as shown in FIG. 5B, the gettering regions 129n, 129p, and 129g formed outside the source and drain regions 128n, 122, and 128g in the respective semiconductor layers 107n, 107p, and 107g are high. Phosphorus and boron doped in the concentration increase the solid solubility of nickel in the region, and further form segregation sites for nickel. In addition, the regions 129n, 129p, and 129g are made amorphous at the time of doping due to the effect of thinning the upper gate insulating film, and the free energy with respect to nickel is reduced, and crystal defects and dangling bonds (dangling bonds) Also functions as a nickel segregation site. These synergistically enhance the gettering effect. In the semiconductor layer 107n of the n-channel TFT, nickel existing in the channel region 123n, the LDD region 127, and the source / drain region 128n is changed from the channel region to the LDD region, The source and drain regions and the gettering region 129n are moved in the direction indicated by the arrow 130 in FIG. Similarly, in the semiconductor layer 107g of the pixel TFT, nickel existing in the channel region 123g, the LDD region 126, and the source / drain region 128g is changed from the channel region to the LDD region, further the source and drain regions, and the gettering region 129g. To the direction indicated by the arrow 130. The source and drain regions 128n and 128g doped only with phosphorus also have a gettering effect, but the ability of the gettering regions 129n and 129g doped with more phosphorus and amorphous and doped with boron is overwhelming. Since it is high, nickel is collected in the gettering regions 129n and 129g. Also in the p-channel TFT semiconductor layer 107p, the gettering region 129p formed outside the source / drain regions has a very high gettering capability, similar to the gettering region 129n of the n-channel TFT, Similarly, nickel existing in the channel region 123p, the source and drain regions 122 is moved from the channel region to the source / drain regions and then to the gettering region 129p in the direction indicated by the arrow 130. In the second heat treatment step for gettering, the catalyst element moves to the gettering regions 129n, 129p, and 129g, so that the catalyst element has a concentration of 5 × 10 ¹⁸ / cm ³ or more.

  Through the above steps, the catalyst element remaining in the channel formation region of the TFT semiconductor layer and the junction between the channel formation region and the source region or drain region can be gettered, and the generation of leakage current due to segregation of the catalyst element is suppressed. be able to. In addition, since the gettering region is formed in a region different from the source region or the drain region in the active layer of the TFT, the resistance increases in the source region or the drain region of the TFT due to the amorphousization of the gettering region. The problem can be solved.

  The heat treatment in the second heat treatment step may be performed using a general heating furnace, but is more preferably performed by RTA (Rapid Thermal Annealing). In particular, a system in which high temperature inert gas is blown onto the substrate surface and the temperature is raised and lowered instantaneously is suitable. Specifically, it is preferable that the holding temperature is 600 to 750 ° C. and the holding time is about 30 seconds to 20 minutes. Both the rate of temperature increase and the rate of temperature decrease are preferably 100 ° C./min or more.

  In this heat treatment step, n-type impurities (phosphorus) doped in the source and drain regions 128n and 128g and the LDD regions 127 and 126 of the n-channel TFT and the pixel TFT, and the source and drain regions of the p-channel TFT Activation of the p-type impurity (boron) doped in 122 is also performed at the same time. As a result, the sheet resistance value of the source / drain regions 128n and 128g of the n-channel TFT and the pixel TFT is about 0.5 to 1 kΩ / □, and the sheet resistance value of the LDD region 127 of the n-channel TFT is 30 to 30 k. The sheet resistance value of the LDD region 126 of the pixel TFT is 50 to 100 kΩ / □ at 60 kΩ / □. The sheet resistance value of the source and drain regions 122 of the p-channel TFT is about 1 to 1.5 kΩ / □. However, since the gettering regions 129n, 129p, and 129g are almost amorphous, the crystal is not recovered by the above heat treatment, and a state having an amorphous component is maintained. Although the resistances of the gettering regions 129n, 129p, and 129g are extremely high, these regions are not a problem because they are formed as regions different from the source region or the drain region so as not to prevent the carrier movement in the TFT.

  After the second heat treatment step, when the ratio Pa / Pc between the amorphous Si TO phonon peak Pa and the crystalline Si TO phonon peak Pc in the Raman spectral spectrum of each region is measured by laser Raman spectroscopy, gettering is performed. The Pa / Pc of the region is larger than Pa / Pc in the channel region and the source and drain regions. This measurement can also be performed from the back side of the substrate when a transparent glass substrate or the like is used as in this embodiment. Since no further high temperature process is performed after this heat treatment process, the above Pa / Pc relationship is maintained even after the TFT is completed.

Next, as illustrated in FIG. 5C, an interlayer insulating film is formed. A silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed to a thickness of 400 to 1500 nm (typically 500 to 1000 nm). In this embodiment, a silicon nitride film 131 having a thickness of 200 nm and a silicon oxide film 132 having a thickness of 700 nm are stacked to form an interlayer insulating film having a two-layer structure. Such an interlayer insulating film can be formed continuously. For example, after the silicon nitride film 131 is formed using SiH ₄ and NH ₃ as source gases using a plasma CVD method, the silicon oxide film 132 is formed using TEOS and O ₂ as sources. The interlayer insulating film is not limited to the laminated film including the silicon nitride film 131 and the silicon oxide film 132, and may have a single layer or a laminated structure including an insulating film containing other silicon. Moreover, you may have organic insulating films, such as an acryl, in the upper layer.

  Subsequently, a heat treatment is performed at 300 to 500 ° C. for about 30 minutes to 4 hours to hydrogenate the semiconductor layer. This hydrogenation step is a step of deactivating by supplying hydrogen atoms to the interface between the active region and the gate insulating film and terminating dangling bonds that degrade the TFT characteristics. In this embodiment, heat treatment is performed at 410 ° C. for 1 hour in a nitrogen atmosphere containing about 3% hydrogen. If the amount of hydrogen contained in the interlayer insulating film (particularly the silicon nitride film 131) is sufficient, the effect can be obtained even if heat treatment is performed in a nitrogen atmosphere. Hydrogenation may be performed using other means, for example, plasma hydrogenation (using hydrogen excited by plasma).

  Next, a contact hole is formed in the interlayer insulating film, and a TFT electrode and a wiring 133 are formed by a two-layer film of a metal material, for example, titanium nitride and aluminum. The titanium nitride film is provided as a barrier film for the purpose of preventing aluminum from diffusing into the semiconductor layer. At this time, a pixel electrode made of a transparent conductive film such as ITO is provided on the other drain electrode of the pixel TFT. In this case, the other electrode constitutes a source bus line, a video signal is supplied via the source bus line, and necessary charges are written to the pixel electrode based on the gate signal of the gate bus line.

  Finally, annealing is performed at 350 ° C. for 1 hour, and the n-channel thin film transistor 134, the p-channel thin film transistor 135, and the pixel thin film transistor 136 illustrated in FIG. 5C are completed. Further, if necessary, contact holes are provided also on the gate electrode lower layer 114n and the upper layer 114p, and necessary electrodes are connected by the wiring 133. For the purpose of protecting the TFT, a protective film made of a silicon nitride film or the like may be provided on each TFT.

The characteristics of each TFT manufactured by the above method will be described. The n-channel thin film transistor 134 has a high field effect mobility of 250 to 300 cm ² / Vs, and the p-channel thin film transistor 135 has a high field effect mobility of 120 to 150 cm ² / Vs. The threshold voltage of the n-channel thin film transistor 134 is about 1V, and the threshold voltage of the p-channel thin film transistor 135 is about −1.5V. Thus, these TFTs exhibit very good characteristics. On the other hand, in the pixel thin film transistor 136, there is no abnormal increase in leakage current at the time of TFT off operation, which is frequently seen in the conventional example, and 0. A very low leakage current value of several pA or less is stably shown. This value is completely different from that of a conventional TFT manufactured without using a catalyst element, and the manufacturing yield can be greatly improved. Further, even when a durability test by repeated measurement or bias or temperature stress is performed, the characteristics are hardly deteriorated, and the reliability is very high as compared with the conventional TFT.

  When an inverter chain on a driver, a ring oscillator, or the like is formed using a CMOS structure circuit in which an n-channel thin film transistor 134 and a p-channel thin film transistor 135 are complementarily formed by the above method, a signal is generated more than a conventional CMOS structure circuit. Low delay, high reliability, and stable circuit characteristics. In addition, when each TFT manufactured by the above method is applied to a liquid crystal display panel, display unevenness is smaller than that of a liquid crystal display panel using a TFT manufactured by a conventional method, pixel defects due to TFT leakage are extremely small, and a high contrast ratio is high. Is obtained.

(Second Embodiment)
A second embodiment according to the present invention will be described. In the present embodiment, a process of manufacturing a circuit having a CMOS structure in which an n-channel TFT and a p-channel TFT are complementary to each other on a glass substrate will be described.

  6 and 7 are cross-sectional views showing a manufacturing process of the TFT of this embodiment, and the process proceeds in the order of FIGS. 6 (A) to (G) and FIGS. 7 (A) to (E).

  As shown in FIG. 6A, the first base film 202 made of a silicon oxynitride film and the silicon oxide film are formed on the surface of the glass substrate 201 on which the TFT is formed, by the same method as in the first embodiment. A second base film 203 is sequentially formed, and then an a-Si film 204 having a thickness of, for example, 50 nm is formed.

  Next, as shown in FIG. 6B, a small amount of nickel 205 is added to the surface of the a-Si film 204 by the same method as in the first embodiment.

  Subsequently, a first heat treatment is performed, and the a-Si film 204 is crystallized in a solid state using the nickel 205 added to the a-Si film 204 as a catalyst to obtain a crystalline silicon film 204a. Then, as shown in FIG. 6C, the crystallinity of the crystalline silicon film 204a is improved by irradiating the laser beam 206 with the same method as in the first embodiment described above, so that a higher quality crystalline material is obtained. A silicon film 204b is obtained.

  Thereafter, unnecessary portions of the crystalline silicon film 204b are removed, and element isolation is performed. By this step, as shown in FIG. 6D, island-shaped crystalline silicon layers 207n and 207p, which will be semiconductor layers of n-channel TFTs and p-channel TFTs later, are formed. Here, for the purpose of controlling the threshold voltage over the entire surface of the semiconductor layer of the n-channel TFT and the p-channel TFT or only for the n-channel TFT, an impurity element that imparts a low concentration p-type ( B etc.) may be added.

  Next, as shown in FIG. 6E, for example, the thickness is set to cover the island-shaped crystalline silicon layers 207n and 207p, which are the semiconductor layers of the TFT, by the same method as in the first embodiment. A 100 nm silicon oxide film is formed as the gate insulating film 208. Subsequently, a conductive film (A) 209 and a conductive film (B) 210 made of a refractory metal are formed by sputtering. In this embodiment, a tantalum nitride (TaN) film with a thickness of 30 nm is used as the conductive film (A) 209, and a tungsten (W) film with a thickness of 350 nm is used as the conductive film (B) 210.

  Next, as shown in FIG. 6E, photoresist masks 211n and 211p are formed, and gate electrodes of the respective TFTs are formed by the same method as in the first embodiment. First, a first etching process is performed under a first etching condition. As a result, the conductive film (B) 210 (W film) is etched, and the ends thereof are tapered (conductive layers (B) 212n and 212p). Subsequently, a second etching process is performed under a second etching condition to etch the conductive film (A) 209 (TaN film). Thus, as shown in FIG. 6F, the conductive layer (B) 210 is formed from the conductive layers (B) 212n and 212p having a trapezoidal cross section and the conductive layer (A) 209. Gate electrode lower layers 213n and 213p having substantially the same width as the layer (B) are obtained.

  Further, the third etching process is performed under the third etching condition without removing the masks 211n and 211p. Thus, the conductive layers (B) (W layers) 212n and 212p are selectively etched with anisotropy. At this time, the gate electrode lower layers (TaN layers) 213n and 213p are not etched, and only the W layers 212n and 212p are etched in the lateral direction. As a result, as shown in FIG. 6G, the tapered portions at the ends of the W layers 212n and 212p formed by the first etching are almost upright, and the W layers (gate electrode upper layers) 214n and 214p and the TaN layer Stepped gate electrodes 240n and 240p having a stacked structure of 213n and 213p are completed.

Next, as shown in FIG. 7A, a photoresist doping mask 215 is provided so as to cover the gate electrode 240n of the n-channel TFT and expose the outer edge portion of the semiconductor layer 207n. At this time, a mask is not provided above the p-channel TFT, and the entire p-channel TFT is exposed. In this state, an impurity (boron) 216 imparting p-type to the semiconductor layers 207n and 207p is formed by ion doping using the resist mask 215 and the upper layer (W layer) 214p of the gate electrode 240p of the p-channel TFT as a mask. inject. Diborane (B ₂ H ₆ ) is used as the doping gas, the acceleration voltage is 60 kV to 90 kV, for example 80 kV, and the dose is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² , for example 7 × 10 ¹⁶ cm ⁻² . To do. Through this step, boron is implanted at a high concentration into the region 217n exposed from the mask 215 in the semiconductor layer 207n of the n-channel TFT. Of the semiconductor layer 207p of the p-channel TFT, a region 218 that does not overlap with the upper layer (W layer) 214p of the gate electrode 240p penetrates the gate insulating film 208 and the lower layer (TaN layer) 213p of the gate electrode 240p to form boron. 216 is injected. Here, the region where the boron is not implanted under the upper layer (W layer) 214p of the gate electrode is the later channel region 219p.

Since boron has a smaller atomic weight than phosphorus, it has a high ion penetration capability, and doping is performed through the gate insulating film 208 and the lower layer (TaN layer) 213p of the gate electrode 240p even at a relatively low acceleration voltage. However, the boron concentration in the film is different between a region overlapping the lower layer (TaN layer) 213p of the gate electrode and a region not overlapping. The boron concentration in the region not overlapping with the TaN layer 213p is higher, but boron is also implanted into the region overlapping with the TaN layer 213p (the lower region of the TaN layer) at a level that cannot be said to be low. Therefore, by this step, a region of the p-channel TFT semiconductor layer 207p that overlaps with the upper layer (W layer) 214p of the gate electrode 240p and is not implanted with boron becomes a channel region 219p. Further, the concentration in the film of the p-type impurity element (boron) in the region 217n and the region not overlapping the gate electrode lower layer (TaN layer) 213p in the region 218 is 1 × 10 ^{19 to} 3 × 10 ^21. / Cm ³ .

  Subsequently, as shown in FIG. 7B, the fourth etching is performed only on the gate electrode 240p of the p-channel TFT by using the resist mask 215 used in the above-described p-type impurity doping step as it is. Processing and thinning etching of the gate insulating film 208 are performed. In the fourth etching process for the gate electrode 240p of the p-channel TFT, the gate electrode lower layer (TaN layer) 213p is selectively etched using the gate electrode upper layer (W layer) 214p as a mask. As a result, the gate electrode 240p of the p-channel TFT has the same width as the upper layer (W layer) 214p and the lower layer (TaN layer) 221 and has a different shape from the gate electrode 240n of the n-channel TFT. Further, by thinning etching of the gate insulating film 208, a region exposed from the mask 215 and the gate electrode 240p (214p / 213p or 214p / 221) of the p-channel TFT is selectively thinned. In this embodiment, since the etching amount in the thin film etching is adjusted to be about 30 nm, the thickness of the thinned region of the selectively thinned gate insulating film 220 is about 70 nm. Yes. Note that the gate insulating film 208 in a region exposed from the mask 215 and the gate electrode 240p of the p-channel TFT may be completely removed by this etching. After the etching, the resist mask 215 is removed.

  Here, either the fourth etching process for the gate electrode 240p of the p-channel TFT described above or the thinning etching of the gate insulating film 208 may be performed first. Thereby, the shape of the obtained gate insulating film 220 differs depending on whether the gate insulating film 220 is thinned using the lower layer 213p of the gate electrode 240p as a mask or the thinned gate electrode lower layer 221 after the fourth etching. Such a difference in shape does not affect the object, function, and effect of the present invention. Further, these two etching steps and the removal step of the resist 215 may be continuously performed in the same etching apparatus. Furthermore, some or all of these three steps may be simultaneously processed as the same step.

In the case of simultaneous processing, for example, the step of thinning the gate insulating film 208 and the step of removing the resist mask may be performed simultaneously. At this time, a plasma etching process may be performed using, for example, oxygen gas and CF ₄ gas as the etching gas in combination with the ashing process of the resist mask cured by the above-described doping process. Although the resist mask 215 can be removed using only oxygen gas, the silicon oxide film which is the gate insulating film 208 can be etched by adding a fluorocarbon gas such as CF ₄ . The etching rate of the gate insulating film 208 can be controlled by the amount of CF ₄ gas introduced at this time. After the resist mask 215 is removed, etching also proceeds to the region covered with the resist mask 215. In order to prevent this, the CF ₄ gas may be stopped and the ashing using only oxygen gas may be switched during the etching. Further, in the case where the fourth etching process of the gate electrode 240p is simultaneously performed in addition to the thinning process and the resist mask removing process, for example, CF ₄ , Cl _2, and oxygen are used as an etching gas, and ICP etching is performed. This can be done by law. At this time, the etching rate of the TaN layer 213p of the gate electrode 240p, the gate insulating film 208, and the resist 215 can be changed depending on the flow rate ratio of each etching gas. .

Next, as shown in FIG. 7C, a doping mask 222 made of a photoresist is newly provided so as to cover the gate electrode 240p of the p-channel type TFT a little larger and to expose the outer edge portion of the semiconductor layer 207p. . At this time, no mask is provided above the n-channel TFT, and the entire TFT is exposed. Thereafter, an n-type impurity (phosphorus) 223 is implanted into each of the semiconductor layers 207n and 207p by ion doping using the resist mask 222 and the gate electrode 240n of the n-channel TFT as a mask. As the doping gas, phosphine (PH ₃ ) is used, the acceleration voltage is set to 50 to 80 kV, for example, 65 kV, and the dose amount is set to 1 × 10 ¹⁵ to 2 × 10 ¹⁶ cm ⁻² , for example, 5 × 10 ¹⁵ cm ⁻² .

  By this doping step, high concentration phosphorus is implanted through the gate insulating film 220 into a region exposed from the gate electrode 240n and the resist mask 222 in the semiconductor layers 207n and 207p. Regions 225, 226n, and 226p are formed. Further, low concentration phosphorus is implanted into the region of the n-channel TFT semiconductor layer 207n that does not overlap with the upper layer 214n of the gate electrode 240n, thereby forming a low concentration n-type impurity region 224. . As a result, a region in which phosphorus is implanted at a low concentration in the semiconductor layer 207n of the n-channel TFT becomes an LDD region 224 overlapping with the gate electrode 240n. The overlap length of the LDD region 224 with the gate electrode 240n is determined by the length of the lower layer 213n exposed from the upper layer 214n. Thus, the LDD region 224 is formed in a self-aligned manner. The region masked by the upper layer 204n of the gate electrode 240n and not implanted with phosphorus becomes a later channel formation region 223n, which is under the thinned region of the gate insulating film 220 and is implanted with phosphorus and boron. The region becomes the gettering region 226n, and the region where only phosphorus is implanted at a high concentration becomes the source and drain regions 225. In the p-channel TFT semiconductor layer 207p, the region 218 covered with the resist mask 222 and not doped with high-concentration phosphorus remains as a region into which only boron is implanted, and the source and drain regions of the p-channel TFT. Thus, the region into which phosphorus and boron are implanted becomes a gettering region 226p. As described above, in this embodiment, by adjusting the doping conditions, the LDD region, the source and drain regions, and the gettering region can be formed separately in one doping step.

  Here, phosphorus 223 is doped through the gate insulating film 220 which is selectively thinned into the respective semiconductor layers 207n and 207p. Therefore, the concentration of phosphorus implanted into each region of the semiconductor layers 207n and 207p varies greatly depending on the thickness of the gate insulating film 220 existing on the regions. In the regions 226n and 226p below the thinned portion of the gate insulating film 220, the concentration of phosphorus is higher than that of the region 225 below the thick portion of the gate insulating film 220, and the upper gate insulating film Since the phosphorus ions 223 are implanted into the semiconductor layer at a relatively higher acceleration voltage than the region 225, the impact energy of each ion is large and the crystallinity is further broken. On the other hand, since the region 225 is implanted through a thick gate insulating film, the impact energy of ions at the time of implantation is relaxed, and a good crystal state can be maintained.

  Next, after removing the resist 222 used as a mask in the above-described process, this substrate is subjected to heat treatment (second heat treatment process) in an inert atmosphere, for example, in a nitrogen atmosphere. In this heat treatment step, as shown in FIG. 7D, the gettering regions 226n and 226p formed outside the source and drain regions 225 and 218 in the respective semiconductor layers 207n and 207p are highly doped. Phosphorus and boron increase the solid solubility of nickel in the gettering regions 226n and 226p, and further form segregation sites for nickel. In the gettering regions 226n and 226p, since the upper gate insulating film is thinned, the gettering regions 226n and 226p become amorphous during doping, and the free energy with respect to nickel is reduced. As a result, crystal defects and dangling bonds also function as nickel segregation sites. These synergistically enhance the gettering effect of the gettering regions 226n and 226p.

In the semiconductor layer 207n of the n-channel TFT, nickel existing in the channel region 219n, the LDD region 224, and the source and drain regions 225 is changed from the channel region 219n to the LDD region 224, further the source and drain regions 225, and the gettering region. Move to 226n in the direction indicated by the arrow 227 in FIG. The source and drain regions 225 doped only with phosphorus also have a gettering effect, but the gettering region 226n doped with more phosphorus and made amorphous and also doped with boron is the source and drain regions. Since it has an overwhelmingly higher gettering capability than 225, nickel can be collected in the gettering region 226n. Also in the p-channel TFT semiconductor layer 207p, the gettering region 226p formed outside the source and drain regions has a high gettering capability like the gettering region 226n of the n-channel TFT, and the channel region 219p. The nickel existing in the source and drain regions 225 is moved from the channel region 219p to the source and drain regions 218 and the gettering region 226p in the same direction as indicated by the arrow 227. The catalyst element moves to the gettering regions 226n and 226p by the second heat treatment step for gettering, and therefore the concentration of the catalyst element in the gettering regions 226n and 226p is 5 × 10 ¹⁸ / cm ³ or more. Become.

  In the second heat treatment step, n-type impurities (phosphorus) doped in the source and drain regions 225 and LDD regions 224 of the n-channel TFT and the source and drain regions 218 of the p-channel TFT are doped. The activation of the p-type impurity (boron) is also performed at the same time, and the resistance is reduced. However, since the crystals in the gettering regions 226n and 226p are almost amorphous, the crystal is not recovered by the above heat treatment, and contains an amorphous component. Although the resistance of the gettering regions 226n and 226p is extremely high, it is not a problem because it is formed as a region different from the source region or the drain region so as not to prevent the movement of carriers as a TFT.

  Next, as illustrated in FIG. 7E, an interlayer insulating film is formed. The interlayer insulating film of this embodiment has a two-layer structure in which a silicon nitride film 228 having a thickness of 200 nm and a silicon oxide film 229 having a thickness of 700 nm are stacked. After the formation of the interlayer insulating film, heat treatment is preferably performed at 300 to 500 ° C. for about 1 hour. As a result, hydrogen atoms are supplied from the interlayer insulating film (especially the silicon nitride film 228) to the interface between the semiconductor layer and the gate insulating film, terminating dangling bonds (dangling bonds) that deteriorate TFT characteristics, and inactive. Make it.

  Next, contact holes are formed in the interlayer insulating films 228 and 229, and TFT electrodes and wirings 230 are formed using a two-layer film of a metal material, for example, titanium nitride and aluminum. The titanium nitride film is provided as a barrier film for the purpose of preventing aluminum from diffusing into the semiconductor layer. Finally, annealing is performed at 350 ° C. for 1 hour, and the n-channel thin film transistor 231 and the p-channel thin film transistor 232 shown in FIG. 7E) are completed. If necessary, contact holes are provided also on the gate electrodes 240n and 240p, and necessary electrodes are connected by the wiring 230. For the purpose of protecting the TFT, a protective film made of a silicon nitride film or the like may be provided on each TFT.

  The field-effect mobility and the threshold voltage of each thin film transistor 231 and 232 manufactured according to the above embodiment show good characteristics similar to those of the first embodiment.

  In this embodiment, in the fabrication process of the n-channel TFT and the p-channel TFT, the formation of the gettering region and the formation of the gate electrode of the p-channel TFT are simultaneously performed using the respective source and drain region forming steps. Therefore, it is not necessary to separately perform processes (photolithographic process, doping process, annealing process) for forming the gettering region and forming the gate electrode of the p-channel TFT. As a result, the manufacturing process can be simplified and the manufacturing cost of the semiconductor device can be reduced. In addition, the yield rate can be improved. When a circuit such as an inverter chain or a ring oscillator is formed by using a CMOS structure circuit in which the n-channel thin film transistor 231 and the p-channel thin film transistor 232 that are manufactured in this embodiment are complementarily formed, the obtained circuit is High reliability and stable circuit characteristics.

  In the first and second embodiments, the gettering region only needs to be disposed outside the source and drain regions. Hereinafter, an example of arrangement of gettering regions in the TFT semiconductor layer will be described with reference to plan views shown in FIGS.

  Various shapes of gettering regions can be formed in the semiconductor layers of the n-channel TFT, the p-channel TFT, and the pixel TFT in the first and second embodiments. Further, the areas of the gettering region in the semiconductor layer of the n-channel TFT and the gettering region in the semiconductor layer of the p-channel TFT are approximately equal, and the distance from the gettering region to the channel region is approximately equal, The efficiency of gettering with respect to the catalytic elements of the channel type TFT and the p channel type TFT can be more reliably aligned.

  Note that the areas of the gettering region in the semiconductor layer of the n-channel TFT and the gettering region in the semiconductor layer of the p-channel TFT are substantially equal to each other in that the width of the semiconductor layer (channel region) is W, When the area S of the gettering region is defined, the ratio S / W of the width W of the semiconductor layer (channel region) and the area S of the gettering region is approximately equal in the n-channel TFT and the p-channel TFT.

  8A to 8D are plan views illustrating the configuration of the semiconductor layer 30 and the gate electrode 35. In these drawings, the same components are denoted by the same reference numerals. The semiconductor layer 30 has a channel formation region formed in a region overlapping with the gate electrode 35, source and drain regions 31 and 32 on both sides of the channel formation region, and a gettering region. The source and drain regions 31 and 32 have contact portions 36 and 37, respectively. In this specification, a portion where a wiring for electrically connecting each TFT is connected to a semiconductor layer is referred to as a contact portion.

  In the structure shown in FIG. 8A, the gettering regions 33a and 34a are arranged in a rectangular shape extending in a direction parallel to the gate electrode 35 at a position away from the channel formation region (outer edge portion of the semiconductor layer). That is, the long side of the rectangle is parallel to the gate electrode. In addition, the rectangular corner portion is arranged so as to hang over the corner portion of the semiconductor layer 30.

  In the structure shown in FIG. 8B, the gettering regions 33 b and 34 b are rectangular shapes extending in a direction perpendicular to the gate electrode 35 at positions away from the channel formation region below the gate electrode 35 (outer edge portion of the semiconductor layer). Arranged. In addition, the rectangular corner portion is arranged so as to hang over the corner portion of the semiconductor layer 30.

  In the configuration shown in FIG. 8C, the gettering regions 33 c and 34 c are rectangular shapes extending in a direction parallel to the gate electrode 35 at positions away from the channel formation region below the gate electrode 35 (outer edge portion of the semiconductor layer). And a complicated shape formed by combining the gate electrode 35 and a rectangle extending in the vertical direction. The corner portion of this shape is arranged so as to hang over the corner portion of the semiconductor layer 30. In this case, since the area of the gettering region can be made larger than in the configuration of FIG. 8A or FIG. 8B, the gettering efficiency for the catalytic element can be further increased.

  In any of the configurations shown in FIGS. 8A to 8C, the gettering region is disposed at a position where the current flowing between the contact portions formed in the source region or the drain regions 31 and 32 is not hindered. ing.

  For example, the gettering regions 33 a and 34 a shown in FIG. 8A do not hinder current flowing between the contact portion 36 formed in the source region 31 and the contact portion 37 formed in the drain region 32. Placed in position. Similarly, the gettering regions 33b and 34b shown in FIG. 8B do not hinder the current flowing between the contact portion 36 connected to the source region 31 and the contact portion 37 formed in the drain region 32. Placed in position. Further, the gettering regions 33c and 34c shown in FIG. 8C do not hinder the current flowing between the contact portion 36 formed in the source region 31 and the contact portion 37 formed in the drain region 32. Is arranged.

  The configuration shown in FIG. 8D is basically the same as the configuration shown in FIG. 8C, but differs in that the gettering regions 33d and 34d are applied to part of the contact portions 36 and 37. Yes. Thereby, the area of the gettering regions 33d and 34d can be further expanded, and the gettering efficiency of the gettering regions 33d and 34d can be improved. Basically, there is no problem if the gettering regions 33d and 34d cover a part of the contact portions 36d and 37d, but the area where the gettering region and the contact portion overlap is at most half or less of the contact portions 36d and 37d. It is necessary to pay attention to. Accordingly, the design distance between the contact portions 36d and 37d and the gettering regions 33d and 34d is a suitable design distance in consideration of the alignment accuracy of the exposure apparatus used in the photolithography process corresponding to each region formation. It is necessary to decide.

  In addition, the structure of this invention is not limited to the structure shown to FIG. 8 (A)-(D). The gettering region can be arranged at any position as long as it does not affect (does not inhibit) the current flowing between the source region and the drain region.

  FIG. 9A illustrates the configuration of the semiconductor layer 30 and the gate electrode 35 in the case where a plurality of gate electrodes 35 cross the semiconductor layer 30 and a plurality of channel formation regions are formed in the semiconductor layer 30. FIG. The semiconductor layer 30 has a plurality of channel forming regions formed under the gate electrode 35, source and drain regions 31, 32 on both sides thereof, and gettering regions 33e, 34e, 38e. The gettering regions 33e and 34e are arranged on the outer edge portion of the semiconductor layer 30 and have the same shape as the gettering regions 33a to 33d and 34a to 34d shown in FIGS. Yes. Although the gettering regions 33e and 34e may cover a part of the contact portions 36 and 37, basically, the area where the gettering region and the contact portion overlap is at most less than half the area of the contact portions 36 and 37. Keep in mind that on the other hand. The gettering region 38e is formed between the source and region 31 (or drain region 32) located between the plurality of gate electrodes 35. The gettering region 38e is also arranged so as not to hinder the flow of current. Preferably, they are arranged so as not to overlap with contact portions 39 formed between gate electrodes 35.

  FIG. 9B is also a plan view showing a configuration in the case where a plurality of gate electrodes 35 cross the semiconductor layer 30 and a plurality of channel formation regions are formed in the semiconductor layer 30. In the structure shown in FIG. 9B, two TFTs are connected in series while sharing the semiconductor layer 30, and the connecting portion does not have a contact portion. That is, there is no need to take out an electrical signal from the connecting portion. The TFT having such a configuration is actually used in a circuit such as a clocked inverter or a latch circuit. The semiconductor layer 30 has a plurality of channel formation regions formed below the gate electrode 35, source and drain regions 31, 32 on both sides thereof, and gettering regions 33f, 34f, 38f. The gettering regions 33f and 34f are arranged on the outer edge portion of the semiconductor layer 30 and have the same shape as the gettering regions 33a to 33d and 34a to 34d shown in FIGS. Yes. On the other hand, the gettering region 38f is disposed between the source region 31 (or the drain region 32) formed between the plurality of gate electrodes 35. The gettering region 38f is arranged at a position where the current flowing from the contact portion 36 to the contact portion 37 is not hindered at least in the connecting portion.

  The shape of the TFT semiconductor layer 30 differs depending on the amount of current required for the TFT. As shown in FIGS. 8 and 9, the width of the channel region is narrower than that of the source and drain regions, and the wedge shape is obtained when the source and drain regions and the channel region have the same width. In either case, the present invention can be similarly applied.

In addition, no matter which shape of the gettering region is applied, the catalytic element moves to the gettering region due to the heat treatment for gettering. The concentration is typically 5 × 10 ¹⁸ / cm ³ or more.

(Third embodiment)
A third embodiment of the present invention will be described with reference to FIG. In this embodiment, the amorphous semiconductor film is crystallized by a method different from the method described in the first embodiment. FIG. 10 is a cross-sectional view showing a manufacturing process in this embodiment, and the manufacturing process sequentially proceeds according to FIGS. 10A to 10E.

  First, as in the first and second embodiments, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like is formed on a substrate (a glass substrate in this embodiment) 401 in order to prevent impurity diffusion from the substrate. A base film is formed. In this embodiment, a silicon nitride film is formed as the lower first base film 402, and a silicon oxide film is formed thereon as the second base film 403. Next, an a-Si film 404 having a thickness of 30 to 80 nm is formed by the same method as in the first and second embodiments. The base insulating films 402 and 403 and the amorphous semiconductor film 404 may be continuously formed without being released to the atmosphere.

  Next, a mask insulating film (thickness: about 200 nm) 405 formed from a silicon oxide film is formed. As shown in FIG. 10A, the mask insulating film 405 has an opening 400 for adding a catalytic element to the semiconductor film 104.

  Next, as shown in FIG. 10B, an aqueous solution (nickel acetate aqueous solution) containing 100 ppm of the catalytic element (nickel in this embodiment) in terms of weight is applied by a spin coating method to form the catalytic element layer 406. To do. At this time, in the opening 400 of the mask insulating film 405, the catalytic element layer 406 selectively contacts the a-Si film 404, and a catalytic element addition region 400s is formed.

  In this embodiment, nickel is added using a spin coating method, but a thin film (nickel film in this embodiment) formed from a catalytic element is formed on the a-Si film 404 by vapor deposition or sputtering. Then, nickel may be added.

  Next, heat treatment is performed at 500 to 650 ° C. (preferably 550 to 600 ° C.) for 6 to 20 hours (preferably 8 to 15 hours). In this embodiment, a heat treatment is performed at 570 ° C. for 14 hours. As a result, as shown in FIG. 10C, crystal nuclei are generated in the catalytic element addition region 400s, and the a-Si film 404 in the catalytic element addition region 400s is first crystallized to become a crystallization region 404a. Furthermore, crystallization proceeds in a direction parallel to the substrate 401 (direction indicated by an arrow 407) starting from the crystallization region 404a, and a crystalline silicon film 404b having a uniform macroscopic crystal growth direction is formed. At this time, the nickel 406 existing on the mask 405 is blocked by the mask film 405 and does not reach the underlying a-Si film 404. Therefore, the a-Si film 404 is crystallized only by nickel introduced in the catalytic element addition region 400s. A region where the lateral crystal growth does not reach remains as an amorphous region 404c. However, depending on the layout, a boundary may be generated by colliding with a crystal growth region in the lateral direction from an adjacent opening, and in this case, it is not an amorphous region.

  After removing the silicon oxide film 405 used as the mask, as shown in FIG. 10D, the crystalline silicon film 404b is irradiated with laser light, and the crystallinity is the same as in the first and second embodiments. Improvements may be made. Thereby, the crystalline silicon film 404b obtained by the crystal growth in the lateral direction is further improved in quality and becomes a crystalline silicon film 404d.

  Subsequently, the crystalline silicon film 404d in the laterally grown region is etched into a predetermined shape to form a semiconductor layer 409 of the later TFT.

  The crystallization method in this embodiment can be applied to the crystallization process in the first and second embodiments. As a result, a high-performance TFT having a high current driving capability can be realized.

(Fourth embodiment)
The semiconductor device of this embodiment is an active matrix substrate. 11A and 11B are block diagrams of the active matrix substrate of this embodiment.

  FIG. 11A shows a circuit configuration for performing analog driving. In this embodiment, a semiconductor device having a source side driver circuit 50, a pixel portion 51, and a gate side driver circuit 52 is shown. Note that in this specification, a drive circuit refers to a generic name including a source side processing circuit and a gate side drive circuit.

  The source side driving circuit 50 includes a shift register 50a, a buffer 50b, and a sampling circuit (transfer gate) 50c. Further, the gate side driving circuit 52 is provided with a shift register 52a, a level shifter 52b, and a buffer 52c. Further, if necessary, a level shifter circuit may be provided between the sampling circuit and the shift register.

  In the present embodiment, the pixel unit 51 includes a plurality of pixels, and each of the plurality of pixels includes a TFT element.

  Although not shown, a gate side drive circuit may be further provided on the opposite side of the gate side drive circuit 22 with the pixel portion 51 interposed therebetween.

  FIG. 11B shows a circuit configuration for performing digital driving. This embodiment shows a semiconductor device having a source side driver circuit 53, a pixel portion 54, and a gate side driver circuit 55. In the case of digital driving, as shown in FIG. 10B, a latch (A) 53b and a latch (B) 53c may be provided instead of the sampling circuit. The source side driving circuit 53 includes a shift register 53a, a latch (A) 53b, a latch (B) 53c, a D / A converter 53d, and a buffer 53e. The gate side driving circuit 55 includes a shift register 55a, a level shifter 55b, and a buffer 55c. If necessary, a level shifter circuit may be provided between the latch (B) 53c and the D / A converter 53d.

  In addition, the said structure is realizable according to the manufacturing process shown in above-mentioned Embodiment 1-3. In this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of the present invention, a memory and a microprocessor can be formed.

(Fifth embodiment)
The semiconductor device of this embodiment is an active matrix type liquid crystal display device or organic EL display device using the CMOS circuit or pixel portion formed in the above-described embodiment, and all electric appliances having such a display device as a display portion. It is.

  Such electric appliances include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Is mentioned.

  In this embodiment, a crystalline semiconductor film having good crystallinity using a catalyst element can be formed, and the catalyst element can be sufficiently gettered. In addition, a structure can be easily made according to required characteristics and purposes by using an n-channel TFT and a p-channel TFT. Accordingly, a CMOS circuit in which the hot carrier resistance of the n-channel TFT is increased and the parasitic capacitance of the p-channel TFT is suppressed can be obtained. As a result, both the characteristics of the n-channel TFT and the p-channel TFT can be improved, so that a reliable CMOS driving circuit having a stable and reliable circuit characteristic can be realized. Further, even in a pixel switching TFT in which a leakage current during an off operation is a problem, a TFT in a sampling circuit of an analog switch unit, etc., generation of a leakage current that is considered to be due to segregation of a catalytic element can be sufficiently suppressed. As a result, a good display without display unevenness is possible. In addition, since the display is good without display unevenness, it is not necessary to use a light source more than necessary, and wasteful power consumption can be reduced. Therefore, an electric appliance (a mobile phone, a portable book, a display) that can reduce power consumption can be realized.

  As described above, the scope of application of the present invention is extremely wide and can be applied to electric appliances in various fields. Moreover, the electric appliance of 5th Embodiment is realizable using the display apparatus produced combining the 1st-4th embodiment.

  As mentioned above, although embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, Various deformation | transformation based on the technical idea of this invention is possible.

  For example, in addition to the pure silicon film shown in the above-described embodiment, a mixed film of germanium and silicon (silicon / germanium film) or a pure germanium film can be used as the semiconductor film targeted by the present invention.

In addition, as a method of introducing nickel, a method of applying a solution in which a nickel salt is dissolved on the surface of the amorphous silicon film was adopted, but before the amorphous silicon film was formed, nickel was introduced on the surface of the base film, Alternatively, nickel may be diffused from the lower layer of the amorphous silicon film to cause crystal growth. Various other methods can be used for introducing nickel. For example, there is a method in which an SOG (spin on glass) material is used as a solvent for dissolving a nickel salt and is diffused from an SiO ₂ film. Further, a method of forming a thin film by a sputtering method, a vapor deposition method, a plating method, a method of directly introducing by an ion doping method, or the like can be used.

  Furthermore, in the above-described embodiment, phosphorus is used in the gettering step, but arsenic and antimony may be used in addition to that.

  According to the present invention, a catalytic element remaining in an active region of a crystalline semiconductor film having a good crystallinity manufactured using a catalytic element, particularly a channel forming region or a junction between a channel forming region and a source region or a drain region A sufficiently reduced semiconductor device is provided.

  In the present invention, since the gate insulating film is partially thinned or removed in the N-channel TFT, the doping conditions of the n-type impurity element for the source and drain regions and the gettering region can be optimized. Therefore, the gettering capability of the gettering region can be improved while suppressing the increase in resistance of the source and drain regions.

  Further, by changing the structures of the n-channel TFT and the p-channel TFT, the characteristics required for each TFT can be made compatible.

  Furthermore, according to the present invention, the semiconductor device can be manufactured by a simple process equivalent to the conventional one without adding a process.

  In the present invention, since the gettering region is not removed in the TFT manufacturing process, the completed TFT has a gettering region in the semiconductor layer. As described above, the TFT in the present invention has gettering ability throughout the manufacturing process and after completion, and therefore, reprecipitation of silicide can be prevented in any heat treatment process after the gettering process.

  If a TFT having an active region sufficiently gettered according to the present invention is used, a high-performance semiconductor device having stable characteristics with reduced leakage current, high reliability and little characteristic variation, and integration High-performance high-performance semiconductor devices can be realized. In addition, the manufacturing process of such a high-performance semiconductor element can be simplified and the manufacturing cost can be reduced. Furthermore, the yield rate can be greatly improved in the manufacturing process.

  The present invention can be applied to an active matrix liquid crystal display device, an organic EL display device, a contact image sensor, a three-dimensional IC, and the like. When the present invention is applied to an active matrix substrate and a liquid crystal display device using the same, the switching characteristics of the pixel switching TFT required for the active matrix substrate and the high performance required for the TFT constituting the peripheral drive circuit section are improved.・ We can satisfy high integration at the same time. Therefore, when the present invention is applied to a driver monolithic active matrix substrate in which the active matrix portion and the peripheral drive circuit portion are formed on the same substrate, it is particularly advantageous because the module can be made compact, high performance and low cost. It is.

It is sectional drawing which shows typically the structure of TFT in embodiment by this invention. (A)-(D) are process cross-sectional schematic diagrams for demonstrating the manufacturing method of TFT in 1st Embodiment by this invention. (A)-(C) are process cross-sectional schematic diagrams for demonstrating the manufacturing method of TFT in 1st Embodiment by this invention. (A)-(C) are process cross-sectional schematic diagrams for demonstrating the manufacturing method of TFT in 1st Embodiment by this invention. (A)-(C) are process cross-sectional schematic diagrams for demonstrating the manufacturing method of TFT in 1st Embodiment by this invention. (A)-(G) are process cross-sectional schematic diagrams for demonstrating the manufacturing method of TFT in 2nd Embodiment by this invention. (A)-(E) are process cross-sectional schematic diagrams for demonstrating the manufacturing method of TFT in 2nd Embodiment by this invention. (A)-(D) are top views which show the example of arrangement | positioning of the gettering area | region in the 1st and 2nd embodiment by this invention. (A) And (B) is a top view which shows the example of arrangement | positioning of the gettering area | region in the 1st and 2nd embodiment by this invention. (A)-(E) are process cross-sectional schematic diagrams for demonstrating the manufacturing method of TFT in 3rd Embodiment by this invention. (A) And (B) is a block diagram of the active matrix substrate of 4th Embodiment by this invention. It is a graph which shows the density | concentration profile of the n-type impurity doped by the silicon oxide film. (A) is a figure which shows a crystal growth, and (B) is a figure which shows a <111> crystal zone plane, when adding a catalytic element to an amorphous semiconductor film and crystallizing, (C) Is a diagram showing a standard triangle of crystal orientation. (A) And (B) is a figure which shows the surface orientation distribution of the crystalline semiconductor film obtained by utilizing a catalyst element, (C) is a figure which shows the standard triangle of a crystal orientation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 3 Gate insulating film 5n, 5p Gate electrode 7n, 7p Channel region 9n, 9p Source region and drain region 10n, 10p Thin film transistor 11n, 11p Gettering region 13n, 13p Semiconductor layer 15 Semiconductor device

Claims (34)

A method of manufacturing a semiconductor device including an N-channel thin film transistor and a P-channel thin film transistor,
Preparing an amorphous semiconductor film to which a catalytic element for promoting crystallization is added at least in part;
Performing a first heat treatment on the amorphous semiconductor film to crystallize at least a part of the amorphous semiconductor film to obtain a crystalline semiconductor film including a crystalline region;
Forming a plurality of island-like semiconductor layers each having a crystalline region by patterning the crystalline semiconductor film;
Forming a gate insulating film on the island-like semiconductor layer;
Depositing a first conductive film on the gate insulating film;
Depositing a second conductive film on the first conductive film;
And patterning and wherein the first conductive film second conductive film, by forming a first conductive layer, a second conductive layer having the smaller channel direction size than the first conductive layer, Providing a gate electrode having a laminated structure having a stepped cross section;
Of the island-like semiconductor layer that becomes the active layer of the N-channel thin film transistor, the region that becomes the gettering region and the entire island-like semiconductor layer that becomes the active layer of the P-channel thin film transistor are exposed, and the active layer of the N-channel thin film transistor Forming a first mask so as to cover a region to be a source region and a drain region of the island-shaped semiconductor layer and a gate electrode of an N-channel thin film transistor;
Using the first mask and the gate electrode of the P-channel thin film transistor as a mask, a region serving as a gettering region of an island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor, an active layer of the P-channel thin film transistor, Doping an impurity element imparting p-type into a source region, a drain region, and a region to be a gettering region in the island-shaped semiconductor layer to be formed ;
Etching the first conductive layer using only the second conductive layer as a mask only at the gate electrode of the P-channel type thin film transistor exposed by the first mask;
Thinning or removing a portion of the gate insulating film exposed by the first mask;
Removing the first mask;
The entire island-shaped semiconductor layer serving as the active layer of the N-channel thin film transistor and the region serving as the gettering region of the island-shaped semiconductor layer serving as the active layer of the P-channel thin film transistor are exposed to form an active layer of the P-channel thin film transistor. forming a second mask to cover the gate electrode region and the P-channel type thin film transistor comprising a source region and a drain region of the island-like semiconductor layer,
Wherein the gate electrode of the second mask and the N-channel thin film transistor as a mask, the source region of the island-shaped semiconductor layer to be the active layer of the N-channel thin film transistor, a drain region and a gettering region and a region, P-channel Doping an impurity element imparting n-type to a region to be a gettering region of an island-shaped semiconductor layer to be an active layer of a thin film transistor ;
Performing a second heat treatment to move at least a part of the catalytic element in the island-like semiconductor layer to the gettering region ,
The step of doping the impurity element imparting n-type is performed after the step of thinning or removing the portion of the gate insulating film exposed by the first mask,
The amorphous semiconductor film is an amorphous silicon film or an amorphous silicon / germanium film, the catalytic element is nickel, the impurity element imparting n-type is phosphorus, and the p-type is imparted. manufacturing method of the impurity element to a semiconductor device Ru boron der. A method of manufacturing a semiconductor device including an N-channel thin film transistor and a P-channel thin film transistor,
Preparing an amorphous semiconductor film to which a catalytic element for promoting crystallization is added at least in part;
Performing a first heat treatment on the amorphous semiconductor film to crystallize at least a part of the amorphous semiconductor film to obtain a crystalline semiconductor film including a crystalline region;
Forming a plurality of island-like semiconductor layers each having a crystalline region by patterning the semiconductor film;
Forming a gate insulating film on the island-like semiconductor layer;
Depositing a first conductive film on the gate insulating film;
Depositing a second conductive film on the first conductive film;
And patterning and wherein the first conductive film second conductive film, by forming a first conductive layer, a second conductive layer having the smaller channel direction size than the first conductive layer, Providing a gate electrode having a laminated structure having a stepped cross section;
A region serving as a gettering region of an island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor and an entire island-shaped semiconductor layer serving as an active layer of the P-channel thin film transistor are exposed to become an active layer of the N-channel thin film transistor. Forming a first mask so as to cover a region to be a source region and a drain region of the island-shaped semiconductor layer and the gate electrode of the N-channel thin film transistor;
Etching the first conductive layer using only the second conductive layer as a mask only at the gate electrode of the P-channel type thin film transistor exposed by the first mask;
Thinning or removing a portion of the gate insulating film exposed by the first mask;
Using the first mask and the gate electrode of the P-channel thin film transistor as a mask, a region serving as a gettering region and an active layer of the P-channel thin film transistor in the island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor source regions of the island-shaped semiconductor layer, to a drain region and a gettering region as a region, a step of doping an impurity element imparting p-type,
Removing the first mask;
The entire island-shaped semiconductor layer serving as the active layer of the N-channel thin film transistor and the region serving as the gettering region of the island-shaped semiconductor layer serving as the active layer of the P-channel thin film transistor are exposed to form an active layer of the P-channel thin film transistor. Forming a second mask so as to cover the source region and drain region of the island-shaped semiconductor layer and the gate electrode of the P-channel thin film transistor;
Using the second mask and the gate electrode of the N-channel thin film transistor as a mask, a region serving as a source region, a drain region, and a gettering region in an island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor, and a P-channel type Doping an impurity element imparting n-type into a region to be a gettering region of an island-shaped semiconductor layer to be an active layer of a thin film transistor ;
Performing a second heat treatment to move at least a part of the catalytic element in the island-like semiconductor layer to the gettering region ,
The step of doping the impurity element imparting n-type is performed after the step of thinning or removing a portion of the gate insulating film exposed by the first mask,
The amorphous semiconductor film is an amorphous silicon film or an amorphous silicon / germanium film, the catalytic element is nickel, the impurity element imparting n-type is phosphorus, and the p-type is imparted. manufacturing method of the impurity element to a semiconductor device Ru boron der. A method of manufacturing a semiconductor device including an N-channel thin film transistor and a P-channel thin film transistor,
Preparing an amorphous semiconductor film to which a catalytic element for promoting crystallization is added at least in part;
Performing a first heat treatment on the amorphous semiconductor film to crystallize at least a part of the amorphous semiconductor film to obtain a crystalline semiconductor film including a crystalline region;
Forming a plurality of island-like semiconductor layers each having a crystalline region by patterning the semiconductor film;
Forming a gate insulating film on the island-like semiconductor layer;
Depositing a first conductive film on the gate insulating film;
Depositing a second conductive film on the first conductive film;
And patterning and wherein the first conductive film second conductive film, by forming a first conductive layer, a second conductive layer having the smaller channel direction size than the first conductive layer, Providing a gate electrode having a laminated structure having a stepped cross section;
A region serving as a gettering region of an island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor and an entire island-shaped semiconductor layer serving as an active layer of the P-channel thin film transistor are exposed to become an active layer of the N-channel thin film transistor. Forming a first mask so as to cover a region to be a source region and a drain region of the island-shaped semiconductor layer and the gate electrode of the N-channel thin film transistor;
Etching the first conductive layer using only the second conductive layer as a mask only in the gate electrode of the P-channel type thin film transistor exposed by the first mask;
Using the first mask and the gate electrode of the P-channel thin film transistor as a mask, a region serving as a gettering region of an island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor, an active layer of the P-channel thin film transistor, Doping an impurity element imparting p-type into a source region, a drain region, and a region to be a gettering region in the island-shaped semiconductor layer to be formed ;
Thinning or removing a portion of the gate insulating film exposed from the first mask;
Removing the first mask;
The entire island-shaped semiconductor layer serving as the active layer of the N-channel thin film transistor and the region serving as the gettering region of the island-shaped semiconductor layer serving as the active layer of the P-channel thin film transistor are exposed to form an active layer of the P-channel thin film transistor. forming a second mask to cover the gate electrode region and the P-channel type thin film transistor comprising a source region and a drain region of the island-like semiconductor layer,
Using the second mask and the gate electrode of the N-channel thin film transistor as a mask, a region serving as a source region, a drain region, and a gettering region in an island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor, and a P-channel type to a region which becomes a gettering region of the island-shaped semiconductor layer to be the active layer of the TFT, a step of doping an impurity element imparting n-type,
Including performing a second heat treatment to move at least a part of the catalytic element in the island-shaped semiconductor layer to the gettering region ,
The step of doping the impurity element imparting n-type is performed after the step of thinning or removing a portion of the gate insulating film exposed by the first mask,
The amorphous semiconductor film is an amorphous silicon film or an amorphous silicon / germanium film, the catalytic element is nickel, the impurity element imparting n-type is phosphorus, and the p-type is imparted. manufacturing method of the impurity element to a semiconductor device Ru boron der. The step of etching the first conductive layer using the second conductive layer as a mask only in the gate electrode of the P-channel thin film transistor exposed by the first mask includes the first mask of the gate insulating film. the method of manufacturing a semiconductor device according to any one of claims 1 to 3, a region that is more exposed is performed after the thinning or removing. Etching the first conductive layer using the second conductive layer as a mask only at the gate electrode of the P-channel thin film transistor exposed by the first mask, and the first mask of the gate insulating film the step of thinning or removing regions that are more exposed, the method of manufacturing a semiconductor device according to any one of claims 1, 2 and 4 are carried out continuously in the same etching apparatus. Etching the first conductive layer using the second conductive layer as a mask only at the gate electrode of the P-channel thin film transistor exposed by the first mask, and removing the first mask the method of manufacturing a semiconductor apparatus according to any one of claims 1, 3 and 4 are carried out continuously in the same etching apparatus. The step of thinning or removing the region exposed from the first mask in the gate insulating film and the step of removing the first mask are continuously performed in the same etching apparatus. the method of manufacturing a semiconductor device according to any one of claims 1, 3 and 4. Etching the first conductive layer using the second conductive layer as a mask only at the gate electrode of the P-channel thin film transistor exposed by the first mask, and the first mask of the gate insulating film a step of thinning or remove areas are more exposed, said the first step of removing the mask, the semiconductor device according to claim 1 or 4 is continuously performed in the same etching apparatus Production method. Etching the first conductive layer using the second conductive layer as a mask only at the gate electrode of the P-channel thin film transistor exposed by the first mask, and the first mask of the gate insulating film the step of thinning or removing regions that are more exposed, the method of manufacturing a semiconductor device according to any one of claims 1, 2 and 4 are performed simultaneously. Etching the first conductive layer using the second conductive layer as a mask only at the gate electrode of the P-channel thin film transistor exposed by the first mask, and removing the first mask the method of manufacturing a semiconductor device according to claim 1 or 3 are carried out simultaneously. A step of thinning or remove areas are exposed from the first mask of the gate insulating film, wherein the first step of removing the mask, any claims 1, 3 and 4 are performed simultaneously A method for manufacturing the semiconductor device according to claim 1. Etching the first conductive layer using the second conductive layer as a mask only at the gate electrode of the P-channel thin film transistor exposed by the first mask, and the first mask of the gate insulating film a step of thinning or removing regions that are more exposed, wherein the first step of removing the mask, the method of manufacturing a semiconductor device according to claim 1 or 4 are performed simultaneously. And patterning and wherein the first conductive film second conductive film, by forming a first conductive layer, a second conductive layer having the smaller channel direction size than the first conductive layer, The step of providing a gate electrode having a laminated structure having a stepped cross section is as follows:
Etching the second conductive film to have a first taper angle;
Etching the first conductive film;
The second conductive film etched to have the first taper angle is further selectively etched so as to have a second taper angle that is larger than the first taper angle. the method of manufacturing a semiconductor device according to any one of claims 1 to 12 comprising the step of etching. Etching the second conductive film so as to have a first taper angle; etching the first conductive film; and etching the first conductive film so as to have the first taper angle. The step of etching the conductive film 2 further selectively so as to have a second taper angle larger than the first taper angle is continuously performed in the etching apparatus. The method for manufacturing a semiconductor device according to claim 13, which is performed. In the step of doping the semiconductor layer in the region exposed by using the second mask and the gate electrode of the N-channel thin film transistor as a mask, the step of doping the gate electrode with the impurity element imparting n-type is performed. the second conductive layer as a mask, the past the first conductive layer, a method of manufacturing a semiconductor device according to any one of claims 1 to 14 in which the doping is carried out. Using the second mask and the gate electrode of the N-channel thin film transistor as a mask, the step of doping an impurity element imparting n-type into the semiconductor layer in a region exposed therefrom,
Doping the impurity element imparting the n-type at a low concentration across the first conductive layer using the second conductive layer of the gate electrode as a mask;
Examples masking the first conductive layer of the gate electrode, a manufacturing method of a semiconductor device according to any of claims 1 to 15 comprising the step of doping the impurity element imparting the n-type high concentration. Doping the impurity element imparting the n-type at a low concentration across the first conductive layer using the second conductive layer of the gate electrode as a mask; and masking the first conductive layer of the gate electrode The method for manufacturing a semiconductor device according to claim 16 , wherein the step of doping the impurity element imparting n-type at a high concentration is performed continuously in the same doping apparatus. Doping the impurity element imparting the n-type at a low concentration across the first conductive layer using the second conductive layer of the gate electrode as a mask; and masking the first conductive layer of the gate electrode The method for manufacturing a semiconductor device according to claim 16 , wherein the step of doping the impurity element imparting n-type at a high concentration is performed simultaneously. And patterning and wherein the first conductive film second conductive film, by forming a first conductive layer, a second conductive layer having the smaller channel direction size than the first conductive layer, step of providing a gate electrode of a laminated structure having a stepped cross-section, a method of manufacturing a semiconductor device according to any of claims 1 18 which is carried out by inductively coupled plasma etching method. And patterning and wherein the first conductive film second conductive film, by forming a first conductive layer, a second conductive layer having the smaller channel direction size than the first conductive layer, step of providing a gate electrode of a laminated structure having a stepped cross-section, a method of manufacturing a semiconductor device according to any of claims 1 18, which is performed by a reactive ion etching method. The gettering region, method of manufacturing a semiconductor device according to any one of claims 1 20 for electrons or holes are formed in a region other than the region to be moved. The gettering region, the contact with the source region or the drain region, a method of manufacturing a semiconductor device according to any of claims 1 21 which is formed so as not to contact with said channel region. After the second heat treatment, the manufacture of a semiconductor device according to any of the contact portion and the further encompasses claim 1 the step of forming a contact wiring 22 including at least a portion of the source region or the drain region Method. By the second heat treatment, among the island-shaped semiconductor layer, the activation of the impurity element imparting impurity element and the p-type imparting the n-type doped with at least the source and drain regions according Item 24. A method for manufacturing a semiconductor device according to any one of Items 1 to 23 . The step of preparing the amorphous semiconductor film includes
Forming a mask having an opening on the amorphous semiconductor film;
The method of manufacturing a semiconductor device according to any of claims 1 24, including the step of adding the catalytic element through the opening to a selected region of the amorphous semiconductor film. Wherein after the first heat treatment, the method of manufacturing a semiconductor device according semiconductor film in the laser beam from further comprising claim 1 the step of irradiating the one of 25. Produced by the method according to any of claims 1 26, a semiconductor device including an N-channel type thin film transistor and P-channel type thin film transistor,
The N-channel thin film transistor and the P-channel thin film transistor are respectively
A semiconductor layer having a crystalline region including a channel region, a source region and a drain region;
At least the channel region of the semiconductor layer, and the gate insulating film formed on said source region and said drain region,
And a said gate electrode formed so as to face the channel region via the gate insulating film,
The semiconductor layer includes the catalytic element,
The semiconductor layer of the N-channel thin film transistor is formed from the island-shaped semiconductor layer that becomes an active layer of the N-channel thin film transistor, and the semiconductor layer of the P-channel thin film transistor is an active layer of the P-channel thin film transistor. Formed from the island-like semiconductor layer to be a layer ,
The gettering region, the channel region, viewed including the catalyst element at a higher concentration than the source region and the drain region,
The gate insulating film is not formed on the gettering region in the N-channel thin film transistor, or the gate insulating film is also formed on the gettering region in the N-channel thin film transistor, the thickness of the gate insulating film on the source region and the drain region in the N-channel type thin film transistor, the N much larger than the thickness of the gate insulating film on the gettering region in the channel thin film transistor,
The gettering region of the N-channel thin film transistor contains phosphorus at a higher concentration than the source region or drain region of the N-channel thin film transistor,
The gate electrode in the N-channel thin film transistor is formed on the first conductive layer and the first conductive layer, and has a size in a channel direction smaller than a size in a channel direction of the first conductive layer. Two conductive layers,
The gate electrode in the P-channel type thin film transistor is formed on the first conductive layer and the first conductive layer, and has a size in the channel direction substantially the same as the size in the channel direction of the first conductive layer. A semiconductor device including a second conductive layer . The channel region of the N-channel thin film transistor overlaps the first conductive layer and the second conductive layer of the gate electrode,
Of the semiconductor layer of the N-channel thin film transistor, a region that overlaps the first conductive layer of the gate electrode but does not overlap the second conductive layer has an N-type impurity at a lower concentration than the source and drain regions. 28. The semiconductor device according to claim 27 . Wherein in the gettering region, the semiconductor device according to the source and drain regions, and than the previous SL channel region, claim ratio of the proportion of the amorphous component more crystalline components is small 27 or 28. The ratio of the ratio Pa / Pc between the amorphous semiconductor TO phonon peak Pa in the Raman spectrum and crystalline semiconductors TO phonon peak Pc gettering region, said source and drain regions, and before SL channel forming region the semiconductor device according to any one of Pa / Pc claim 27 greater than 29. At least the channel region in the semiconductor layer, <111> crystal zone planes of the crystal is mainly composed of a region oriented semiconductor device according to any of claims 27 30. In the semiconductor layer, at least the channel region is mainly composed of a region where the <111> crystal zone plane of the crystal is oriented, and 50% or more of the region where the <111> crystal zone plane is oriented is a (110) plane. a orientation or (211) -oriented regions, the semiconductor device according to any of claims 27 31. Wherein at least the channel region in the semiconductor layer has a plurality of crystalline domains, domain diameter of the crystalline domain is 2μm or more 10μm or less, the semiconductor device according to any of claims 27 32. The first conductive layer of the gate electrode of the N-channel thin film transistor and the P-channel thin film transistor is formed of tungsten nitride, tantalum nitride, titanium nitride, or molybdenum nitride, and the second conductive layer is formed of W, Ta, Ti, 34. The semiconductor device according to claim 27 , wherein the semiconductor device is formed of a metal film containing an element selected from the group consisting of Mo , an alloy film containing the element as a main component, or an alloy film combining the elements. .