JP4115441B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4115441B2
JP4115441B2 JP2004316248A JP2004316248A JP4115441B2 JP 4115441 B2 JP4115441 B2 JP 4115441B2 JP 2004316248 A JP2004316248 A JP 2004316248A JP 2004316248 A JP2004316248 A JP 2004316248A JP 4115441 B2 JP4115441 B2 JP 4115441B2
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insulating film
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gettering
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直樹 牧田
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シャープ株式会社
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  The present invention relates to a semiconductor device including a thin film transistor (hereinafter abbreviated as “TFT”) and a method for manufacturing the same.

  In recent years, high-resolution liquid crystal display devices and organic EL display devices, high-speed, high-resolution contact image sensors, three-dimensional ICs, etc. have been developed on insulating substrates such as glass and insulating films. Attempts have been made to form high performance semiconductor devices. In particular, a liquid crystal display device in which a pixel portion and a driving circuit are provided on the same substrate has been used not only as a monitor for a personal computer (PC) but also in various applications, and has entered the general household. I'm starting. For example, instead of CRT (Cathode-ray Tube), a liquid crystal display is introduced as a television, and a liquid crystal front projector for watching movies and playing games as an entertainment has been introduced into ordinary households. The market size of display devices is growing at a considerable rate. Furthermore, development of a system-on-panel in which a logic circuit such as a memory circuit or a clock generation circuit is built on a glass substrate is being promoted.

  If you try to display a high-resolution image, the amount of information to be written to the pixels will increase, and if that information is not written in a short time, a high-definition image with such an enormous amount of information can be displayed as a moving image. Impossible. For this reason, the TFT used in the driver circuit is required to operate at a higher speed. In order to enable high-speed operation, it is required to form a TFT using a crystalline semiconductor film having good crystallinity that can provide high field effect mobility.

  As a method for obtaining a high-quality crystalline semiconductor film on a glass substrate, the present inventors add a metal element (catalyst element) having an action of promoting crystallization to an amorphous semiconductor film, and then perform heat treatment. As a result, we have developed a technology that can provide a good semiconductor film with uniform crystal orientation by low-temperature and short-time heat treatment.

  However, a TFT manufactured using a crystalline silicon film obtained by using a catalytic element as a semiconductor layer as it is has a problem that off-current suddenly increases. In the crystalline silicon film, the catalyst element segregates irregularly, and it has been confirmed that such segregation is particularly remarkable at the grain boundary. This segregated catalytic element is considered to be a current escape path (leakage path), causing a sudden increase in off-current. Therefore, it is necessary to reduce the concentration of the catalytic element in the semiconductor film by moving the catalytic element from the semiconductor film after the crystalline silicon film manufacturing process. Note that in this specification, removing a catalytic element from a semiconductor film or a predetermined region (a channel region or an active region) of the semiconductor film is referred to as “gettering”.

  Various methods have been proposed in the past for performing gettering. For example, Patent Document 1 discloses a method of forming an amorphous region (amorphous region) as a gettering region in a part of a crystalline silicon film crystallized using a catalytic element. Yes. According to the method of Patent Document 1, by performing heat treatment on a crystalline silicon film in which an amorphous region is formed, a catalytic element is moved (getter) to a lattice defect in the amorphous region. Ring). In addition, a method for forming such an amorphous region other than the semiconductor element formation region in the crystalline silicon film, and a region in the crystalline silicon film that becomes a source region or a drain region of the TFT are used as a gettering region. Is disclosed.

  However, in the method of forming an amorphous silicon film other than the semiconductor element formation region in the crystalline silicon film, the process is complicated and the cost is increased due to the additional process for gettering. According to the method of using a source region or a drain region as a gettering region, the manufacturing process can be simplified, so the above problem is improved. However, the amorphous region does not function as a source region or a drain region. Therefore, an additional step of activating the amorphous region using a laser beam or the like is necessary. The laser irradiation apparatus used in this additional process is expensive, has a complicated apparatus structure, and is not easy to maintain. Therefore, since the manufacturing cost increases in terms of the apparatus, it is an apparatus that should not be used as much as possible except for essential processes.

  On the other hand, instead of using lattice defects in the amorphous region for gettering, an element belonging to Group B of the periodic table having a function of moving a catalytic element (typically phosphorus, arsenic, etc .: n-type) A method of using (which is also an impurity element imparting) has been proposed.

  For example, Patent Document 2 focuses on the gettering action of phosphorus, and proposes a method of performing gettering by moving a catalytic element from the channel formation region of the TFT to the source and drain regions. In this method, a TFT semiconductor layer is formed from a crystalline silicon film crystallized using a catalytic element. In the case of manufacturing an N-channel TFT using this semiconductor layer, the catalyst element in the channel formation region is moved to the source and drain regions by doping phosphorus in the source and drain regions and then performing heat treatment. On the other hand, when manufacturing a P-channel TFT, the source and drain regions are doped with phosphorus used for gettering and boron with a concentration higher than the concentration of phosphorus. Thereafter, the catalyst element is moved to the source and drain regions by heat treatment.

  Since the method of Patent Document 2 does not use a laser irradiation device, it does not have the above-described device problems. However, it is difficult to mass-produce thin film transistors using the method of Patent Document 2. The reason will be described below.

  In the method of Patent Document 2, in an N-channel TFT, an element belonging to Group 5 B imparting n-type doped in a source region and a drain region (phosphorus or the like) alone acts as a gettering element. In a type TFT, an element belonging to Group 3 B that imparts p-type (boron or the like) does not act as a gettering element, and therefore n-type is imparted as a gettering element to the source region and drain region of a P-channel TFT. It is necessary to add an element belonging to group B. That is, in the P-channel TFT, it is necessary to invert the region added with the n-type impurity element at a high concentration to the p-type (called counter-doping) in order to getter the catalyst element. In the semiconductor layer of the TFT, the electrical resistance of the source region and the drain region becomes a parasitic resistance when the TFT is turned on, and the current value of the TFT is reduced. However, in order to invert the n-type to the p-type, it is necessary to add a p-type impurity element having a concentration of 1.5 to 3 times the n-type impurity element. Therefore, when the amount of an element belonging to Group B that imparts n-type is increased in order to increase the gettering effect, the amount of an element that belongs to Group B that imparts p-type is also reversed. It was necessary to increase the concentration to a high level, which greatly pressed the processing capacity of the doping apparatus.

  In general, in a method in which a source region or a drain region is used as a gettering region, as in the method disclosed in Patent Document 2, the characteristics of a semiconductor element may be deteriorated by a catalytic element. For example, in a TFT element, a defective TFT having a large leak current when the TFT is off appears. Analyzing the cause of defects in such TFTs, there is a silicide compound due to the catalytic element at the junction between the channel formation region and the gettering region such as the drain region, that is, at the boundary between the gettering region and the non-gettering region. Has been confirmed. That is, it has been found that the phenomenon that the leakage current increases when the TFT is turned off by the catalytic element is caused by segregation of the catalytic element present at the junction between the channel region and the drain region. Therefore, when the source region or the drain region is used as the gettering region, the manufacturing process can be simplified, but it is difficult to fundamentally solve the problem of increasing the leakage current at the time of the TFT off operation by the catalytic element.

  Further, Patent Document 3 selectively introduces a Group 5 B element such as phosphorus into a part of a crystalline silicon film crystallized using a catalytic element, and performs heat treatment in a temperature range that does not exceed the strain point of the substrate. This discloses a method of moving (gettering) a catalytic element to a region into which a Group 5 B element has been introduced. After this gettering step, the region where the Group 5 B element is introduced (gettering region) is removed, and the region other than the Group 5 B element is introduced, that is, the region where the catalytic element is removed. An active region of the semiconductor device is formed.

In the method of Patent Document 3, the gettering region is provided in a region other than the region that becomes the semiconductor layer of the TFT in the crystalline silicon film, so that it is not necessary to perform the counter-doping described above. However, in this method, an extra step for gettering is added, and further, a step of removing the gettering region is increased. As a result, the manufacturing process becomes complicated and the manufacturing cost increases. Further, the TFT completed by the method of Patent Document 3 does not have a gettering region in the semiconductor layer. When the gettering region has been completely removed, if there is a catalyst element remaining after gettering, such a catalyst element may be re-silicidized and deposited in a heat treatment step after gettering. .
JP-A-8-213317 JP-A-8-330602 Japanese Patent Laid-Open No. 10-270363

  As described above, according to the conventional method, the device characteristics deteriorate due to the catalytic element added to the amorphous semiconductor film in order to obtain a good crystalline semiconductor film by a practical process excellent in mass productivity. It was not able to suppress enough.

  The present invention has been made in view of the above problems, and an object of the present invention is to reduce the concentration of a catalytic element contained in an active region in a crystalline semiconductor layer without reducing the performance of the thin film transistor in a semiconductor device including the thin film transistor. It is to reduce sufficiently. Moreover, it is manufacturing such an apparatus at a low cost without increasing the number of processes.

  The semiconductor device of the present invention is a semiconductor device including at least one thin film transistor, and the at least one thin film transistor includes a semiconductor layer including a crystalline region including a channel region, a source region, and a drain region, and the semiconductor layer A gate insulating film formed on at least the channel region, the source region, and the drain region, and a gate electrode formed to face the channel region with the gate insulating film interposed therebetween, The layer further includes a gettering region containing a catalytic element at a higher concentration than the source region and the drain region, and at least a portion of the gate insulating film located between the gate electrode and the semiconductor layer is a first layer. 1 insulating film and formed on the first insulating film and having a different composition or density from the first insulating film The gate insulating film is also formed on the gettering region, and the gate insulating film on the gettering region is at least of the gate insulating film. It is thinner than the portion located between the gate electrode and the semiconductor layer.

  In a preferred embodiment, the gate insulating film on the gettering region is thinner than the gate insulating film on the source and drain regions in the gate insulating film.

  The gate insulating film on the gettering region may be formed of an insulating film that is at least one or more fewer than at least a portion of the gate insulating film located between the gate electrode and the semiconductor layer.

  The gate insulating film on the gettering region may be composed of an insulating film that is at least one layer lower than the gate insulating film on the source and drain regions.

  In a preferred embodiment, at least a portion of the gate insulating film located between the gate electrode and the semiconductor layer has a two-layer structure including the first and second insulating films. The first insulating film is formed on at least the channel region, the source region, the drain region, and the gettering region of the semiconductor layer, and the second insulating film is not formed on the gettering region. Alternatively, the second insulating film is formed on the gettering region, and the second insulating film on the gettering region is between the gate electrode and the semiconductor layer in the second insulating film. Thinner than the part located in

  The gate insulating film on the source and drain regions preferably has a two-layer structure composed of the first and second insulating films.

  Preferably, the first insulating film and the second insulating film are made of silicon oxide or silicon nitride, and the composition ratios of silicon in the first insulating film and the second insulating film are different from each other.

  The first insulating film may contain silicon oxide as a main component, and the second insulating film may contain silicon nitride as a main component.

  The catalyst element included in the gettering region may include one or more elements selected from Ni, Co, Sn, Pb, Pd, Fe, and Cu.

The concentration of the catalytic element in the gettering region is preferably 5 × 10 18 atoms / cm 3 or more.

  The gettering region is preferably formed in a region other than a region where electrons or holes move during operation of the at least one thin film transistor in the semiconductor layer.

  Preferably, the gettering region is formed so as not to contact at least the channel region.

  In the gettering region, it is preferable that the proportion of the amorphous component is larger and the proportion of the crystalline component is smaller than that of the source and drain regions and / or the channel region.

  The gettering region may include an impurity element belonging to Group B of the periodic table imparting n-type and an impurity element belonging to Group B of the periodic table imparting p-type.

The gettering region includes an impurity element imparting the n type conductivity in a concentration of 1 × 10 19 / cm 3 or more 3 × 10 21 / cm 3 or less, 1 impurity element imparting the p-type × 10 19 / It may be contained at a concentration of cm 3 or more and 3 × 10 21 / cm 3 or less.

  In the semiconductor layer, at least the channel region is preferably mainly composed of a region in which the <111> crystal zone plane of the crystal is oriented.

  In the semiconductor layer, at least the channel region may have a plurality of crystal domains, and the domain diameter of the crystal domains may be 2 μm or more and 10 μm or less.

  The gate electrode may be formed of one or more elements selected from W, Ta, Ti, and Mo, or alloy materials of the elements.

  A low concentration impurity region may be further provided between the channel region of the semiconductor layer and the source and drain regions.

  In a preferred embodiment, the at least one thin film transistor is an N-channel thin film transistor.

  The gettering region may include an impurity element belonging to Group B of the periodic table that imparts n-type at a higher concentration than the source region or the drain region.

  In a preferred embodiment, the P channel thin film transistor further includes a semiconductor layer including a crystalline region including a channel region, a source region, and a drain region, and a gate formed on the semiconductor layer. An insulating film; and a gate electrode formed so as to face the channel region with the gate insulating film interposed therebetween, wherein the semiconductor layer contains a catalytic element at a higher concentration than the source region and the drain region. A ring region, and a portion of the gate insulating film located between the gate electrode and the semiconductor layer has a stacked structure including the first insulating film and the second insulating film; In the thin film transistor, the gate insulating film on the gettering region is formed of the N channel type and the P channel. Thinner than the portion located between the semiconductor layer and the gate electrode of the gate insulating film in the mold the thin-film transistor.

  In a preferred embodiment, in the N-channel and P-channel thin film transistors, at least a portion of the gate insulating film located between the gate electrode and the semiconductor layer is composed of the first and second insulating films. The first insulating film is formed on at least the channel region, the source region, the drain region, and the gettering region of the semiconductor layer, and the P-channel thin film transistor has a two-layer structure. The second insulating film is not formed on the gettering region, the source region, and the drain region, or the second insulating film is formed on the gettering region, the source region, and the drain region. Formed on the gettering region, the source and the drain region Of the second insulating film is thinner than the portion located between the semiconductor layer and the gate electrode of the second insulating film.

  A method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device including a thin film transistor, the step of preparing an amorphous semiconductor film to which a catalytic element for promoting crystallization is added at least partially, Performing a first heat treatment on the amorphous semiconductor film to crystallize at least a part of the amorphous semiconductor film to obtain a crystalline semiconductor film including a crystalline region; and the crystalline semiconductor By patterning the film, a step of forming an island-shaped semiconductor layer having a crystalline region and a stacked insulating film including two insulating films having different compositions or densities are formed on the island-shaped semiconductor layer. Forming a channel on a region to be a gettering region by thinning a portion of the stacked insulating film located on at least a region to be a gettering region of the island-shaped semiconductor layer A step of forming a gate insulating film thinner than a region to be a region, a step of adding a gettering element having a gettering capability to at least a region to be the gettering region in the island-shaped semiconductor layer, and the island-shaped region Performing a second heat treatment on the semiconductor layer to move at least a part of the catalytic element in the island-shaped semiconductor layer to the gettering region.

  The step of forming the gate insulating film may include a step of removing at least an uppermost layer of a portion of the stacked insulating film located on a region to be a gettering region of the island-shaped semiconductor layer.

  In the step of forming the gate insulating film, at least the lowermost layer of the stacked insulating film may be left without being removed.

  In a preferred embodiment, the step of forming the laminated insulating film includes a step of forming a lower insulating film on the semiconductor layer, and a composition or density different from the composition or density of the lower insulating film on the lower insulating film. Forming a gate insulating film, wherein the step of forming the gate insulating film includes forming a thin film on a portion of the upper insulating film that is located on a region serving as a gettering region of the island-shaped semiconductor layer. Or a step of removing or removing.

  The step of thinning or removing at least the portion of the island-like semiconductor layer located on the region that becomes the gettering region of the upper insulating film is preferably performed using the lower insulating film as an etching stopper.

  In a preferred embodiment, the step of forming the gate insulating film is a step of forming a thinner gate insulating film on a region to be a gettering region of the island-like semiconductor layer than on a region to be a source and drain region. A step (A) of adding an impurity element to the source and drain regions of the island-shaped semiconductor layer through the gate insulating film, and including at least the gettering region of the island-shaped semiconductor layer; The step of adding a gettering element having a gettering capability to the region to be formed includes the step of adding the impurity element as the gettering element to the region to be the gettering region of the island-like semiconductor layer through the gate insulating film. Including the step (B) of adding, the steps (A) and (B) using the same mask in the same etching apparatus. Divide.

  Another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including an N-channel thin film transistor and a P-channel thin film transistor, and is an amorphous material in which a catalytic element for promoting crystallization is added at least partially. Preparing a crystalline semiconductor film, and performing a first heat treatment on the amorphous semiconductor film to crystallize at least a part of the amorphous semiconductor film and include a crystalline region A step of obtaining a film; a step of patterning the crystalline semiconductor film to form a plurality of island-like semiconductor layers each having a crystalline region; and a lower insulating film and the lower layer on the island-like semiconductor layer Forming a laminated insulating film including the lower and upper insulating films by forming an upper insulating film having a composition or density different from that of the insulating film in this order; and the laminated insulating film A step of forming a gate electrode, a region serving as a gettering region of an island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor, and an entire island-shaped semiconductor layer serving as an active layer of the P-channel thin film transistor. Forming a first mask that exposes and covers the source and drain regions of the N-channel thin film transistor and the gate electrode of the N-channel thin film transistor; and the first mask and the P-channel thin film transistor Using the gate electrode as a mask, the step of doping the semiconductor layer in a region exposed from the gate electrode with an impurity element imparting p-type through the stacked insulating film, and the first insulating layer out of the first insulating layer The region exposed from the mask and the gate electrode of the P-channel thin film transistor is removed. Forming a gate insulating film including a first insulating film formed from a lower insulating film and a second insulating film formed from an upper insulating film by thinning, and an active layer of the N-channel thin film transistor A region serving as a gettering region of the island-shaped semiconductor layer serving as an active layer of the P-channel thin film transistor and a region serving as a source region and a drain region of the P-channel thin film transistor, and a P-channel Forming a second mask covering the gate electrode of the thin film transistor, and an impurity imparting n-type to the region exposed from the second mask in the island-like semiconductor layer through the gate insulating film By doping the element, the N-channel thin film transistor is formed on the island-shaped semiconductor layer that becomes the active layer of the N-channel thin film transistor. And forming a gettering region in each of the N-channel type and P-channel type thin film transistors in an island-like semiconductor layer that becomes an active layer of the N-channel type and P-channel type thin film transistors. And a step of moving at least part of the catalytic element in the island-shaped semiconductor layer to the gettering region by performing a second heat treatment.

  Still another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including an N-channel thin film transistor and a P-channel thin film transistor, in which a catalyst element that promotes crystallization is added at least partially. Preparing a crystalline semiconductor film, and performing a first heat treatment on the amorphous semiconductor film, thereby crystallizing at least a part of the amorphous semiconductor film and including a crystalline region Obtaining a semiconductor film; patterning the crystalline semiconductor film to form a plurality of island-like semiconductor layers each having a crystalline region; a lower insulating film on the island-like semiconductor layer; and Forming a laminated insulating film including the lower layer and the upper insulating film by forming an upper insulating film having a composition or density different from that of the lower insulating film in this order; A step of forming a gate electrode on the edge film; and a region of the island-like semiconductor layer that becomes an active layer of the N-channel thin film transistor, a region that becomes a gettering region, and A step of forming a first mask that exposes the whole and covers a region to be a source region and a drain region of the N-channel thin film transistor and a gate electrode of the N-channel thin film transistor; The first insulating film formed from the lower insulating film and the second insulating film formed from the upper insulating film by removing or thinning the region exposed from the gate electrode of the mask 1 and the P-channel thin film transistor Forming a gate insulating film including the first mask and the P-channel thin film transistor A step of doping the island-shaped semiconductor layer with an impurity element imparting p-type to the island-shaped semiconductor layer through the first insulating film using a gate electrode as a mask; and the entire island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor; A region that becomes a gettering region of an island-shaped semiconductor layer that becomes an active layer of the P-channel thin film transistor is exposed, and a region that becomes a source region and a drain region of the P-channel thin film transistor and the gate electrode of the P-channel thin film transistor are covered. A step of forming a second mask, and doping an impurity element imparting n-type through a gate insulating film into a region exposed from the second mask in the island-like semiconductor layer, A source region in the N-channel thin film transistor is formed on the island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor. Forming a drain region and a gettering region in each of the N-channel and P-channel thin film transistors in an island-like semiconductor layer that is an active layer of the N-channel and P-channel thin film transistors; And a step of moving at least a part of the catalytic element in the island-shaped semiconductor layer to the gettering region by performing the heat treatment.

  Still another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including an N-channel thin film transistor and a P-channel thin film transistor, in which a catalyst element that promotes crystallization is added at least partially. Preparing a crystalline semiconductor film, and performing a first heat treatment on the amorphous semiconductor film, thereby crystallizing at least a part of the amorphous semiconductor film and including a crystalline region Obtaining a semiconductor film; patterning the crystalline semiconductor film to form a plurality of island-like semiconductor layers each having a crystalline region; a lower insulating film on the island-like semiconductor layer; and Forming a laminated insulating film including the lower layer and the upper insulating film by forming an upper insulating film having a composition or density different from that of the lower insulating film in this order; A step of forming a gate electrode on the edge film; and a region of the island-like semiconductor layer that becomes an active layer of the N-channel thin film transistor, a region that becomes a gettering region, and an island-like semiconductor layer that becomes an active layer of the P-channel thin film transistor Forming a first mask that is entirely exposed to cover a source region and a drain region of the N-channel thin film transistor and a gate electrode of the N-channel thin film transistor; and the first mask and the P-channel A step of doping an impurity element imparting p-type to the island-like semiconductor layer through the stacked insulating film using the gate electrode of a thin film transistor as a mask, and the first mask of the upper insulating film, The region exposed from the gate electrode of the P-channel thin film transistor is removed or thinned. Forming a gate insulating film including a first insulating film formed from a lower insulating film and a second insulating film formed from an upper insulating film, and an island-shaped semiconductor serving as an active layer of the N-channel thin film transistor A region serving as a source region, a drain region, and a gettering region in the layer, and a region serving as a gettering region in the island-shaped semiconductor layer serving as an active layer of the P-channel thin film transistor, Forming a second mask covering a region to be an LDD region, a region to be a source and drain region of the P-channel thin film transistor, and the gate electrode of the P-channel thin film transistor; and Among them, an impurity element imparting n-type is provided to the region exposed from the second mask through a gate insulating film. Doping forms the source and drain regions of the N-channel thin film transistor in the island-like semiconductor layer that becomes the active layer of the N-channel thin film transistor, and also becomes the active layer of the N-channel and P-channel thin film transistors. A step of forming a gettering region in each of the N-channel and P-channel thin film transistors in the island-shaped semiconductor layer, and a second heat treatment, thereby performing at least a part of the catalytic element in the island-shaped semiconductor layer Moving to the gettering region.

  Still another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including an N-channel thin film transistor and a P-channel thin film transistor, in which a catalyst element that promotes crystallization is added at least partially. Preparing a crystalline semiconductor film, and performing a first heat treatment on the amorphous semiconductor film, thereby crystallizing at least a part of the amorphous semiconductor film and including a crystalline region Obtaining a semiconductor film; patterning the crystalline semiconductor film to form a plurality of island-like semiconductor layers each having a crystalline region; a lower insulating film on the island-like semiconductor layer; and Forming a laminated insulating film including the lower layer and the upper insulating film by forming an upper insulating film having a composition or density different from that of the lower insulating film in this order; A step of forming a gate electrode on the edge film; and a region of the island-like semiconductor layer that becomes an active layer of the N-channel thin film transistor, a region that becomes a gettering region, and an island-like semiconductor layer that becomes an active layer of the P-channel thin film transistor A step of forming a first mask that covers the entire region and serves as a source region and a drain region of the N-channel thin film transistor and a gate electrode of the N-channel thin film transistor; The first insulating film formed from the lower insulating film and the second insulating film formed from the upper insulating film are removed by removing or thinning the region exposed from the gate electrode of the first mask and the P-channel thin film transistor. Forming a gate insulating film including a film, the first mask, and the P-channel thin film transistor Doping an impurity element imparting p-type to the island-like semiconductor layer through the first insulating film using the gate electrode as a mask, and an island-like semiconductor layer serving as an active layer of the N-channel thin film transistor Among them, a region that becomes a source region, a drain region, and a gettering region, and a region that becomes a gettering region in an island-like semiconductor layer that becomes an active layer of the P-channel thin film transistor are exposed, and an LDD region of the N-channel thin film transistor Forming a second mask that covers a region to be, a region to be a source and drain region of the P-channel thin film transistor, and the gate electrode of the P-channel thin film transistor; An impurity element imparting n-type conductivity is exposed to the region exposed from the second mask through the gate insulating film. Doping forms the source and drain regions of the N-channel thin film transistor in the island-like semiconductor layer that becomes the active layer of the N-channel thin film transistor, and also becomes the active layer of the N-channel and P-channel thin film transistors. A step of forming a gettering region in each of the N-channel and P-channel thin film transistors in the island-shaped semiconductor layer, and a second heat treatment, thereby performing at least a part of the catalytic element in the island-shaped semiconductor layer Moving to the gettering region.

  In a preferred embodiment, the step of forming the gate insulating film includes the step of etching the upper insulating film under an etching condition such that an etching rate for the upper insulating film is higher than an etching rate for the lower insulating film. Including.

  The step of forming the gate insulating film may include a step of etching the upper insulating film using the lower insulating film as an etching stopper film.

  The step of forming the laminated insulating film may include a step of forming a lower insulating film mainly composed of silicon oxide and a step of forming an upper insulating film mainly composed of silicon nitride.

  The step of forming the laminated insulating film may include a step of forming the upper insulating film without exposing to the atmosphere after forming the lower insulating film.

  The steps of forming a source region and a drain region in the N-channel type thin film transistor and forming a gettering region in each of the N-channel type and P-channel type thin film transistors include an island-shaped semiconductor that becomes an active layer of the N-channel type thin film transistor Compared to the regions that become the source region and the drain region in the layer, in the island-shaped semiconductor layer that becomes the active layer of the N-channel and P-channel thin film transistors, the region that becomes the gettering region is more susceptible to crystal breakdown. It is preferable to include a step of doping the impurity element imparting the n-type under doping conditions that are easily crystallized.

  The steps of forming a source region and a drain region in the N-channel type thin film transistor and forming a gettering region in each of the N-channel type and P-channel type thin film transistors are compared with the source region and the drain region of the N-channel type thin film transistor. In the gettering region of the N-channel and P-channel thin film transistors, the ratio Pa / Pc between the TO phonon peak Pa of the amorphous semiconductor and the TO phonon peak Pc of the crystalline semiconductor in the Raman spectrum is increased. A step of forming a source region and a drain region in the N-channel thin film transistor and a gettering region in each of the N-channel and P-channel thin film transistors may be formed.

  Even after the second heat treatment step, in the gettering region of the N-channel and P-channel thin film transistors, the amorphous semiconductor TO of the Raman spectrum is compared with the source and drain regions of the N-channel thin film transistor. It is preferable that the state where the ratio Pa / Pc between the phonon peak Pa and the TO phonon peak Pc of the crystalline semiconductor is large is maintained.

  The gettering region is preferably formed in a region other than a region where electrons or holes move in the island-like semiconductor layer.

  The gettering region is preferably formed so as to be in contact with the source region or the drain region and not to be in contact with the channel region and the LDD region.

  After the second heat treatment step, a step of forming a wiring electrically connected to a contact portion including at least a part of the source region or the drain region may be further included.

  In the second heat treatment step, at least the n-type impurity and / or the p-type impurity doped in at least the source region and the drain region of the island-shaped semiconductor layer can be activated.

  In a preferred embodiment, the step of preparing an amorphous semiconductor film to which at least a part of the catalyst element for promoting crystallization is added includes the step of forming a mask having an opening on the amorphous semiconductor film. And adding the catalytic element to a selected region of the amorphous semiconductor film through the opening.

  The catalyst element may include at least one element selected from the group consisting of Ni, Co, Sn, Pb, Pd, Fe, and Cu.

  A step of irradiating the semiconductor film with laser light may be further included after the first heat treatment step.

  An electronic apparatus according to the present invention includes the semiconductor device. In addition, a display unit that performs a display operation using the semiconductor device may be provided.

  According to the present invention, catalytic elements remaining in an active region of a crystalline semiconductor layer formed using a catalytic element, particularly a channel forming region and a junction between a channel forming region and a source region or a drain region can be sufficiently reduced. In particular, in an N-channel TFT, it is possible to form a gettering region having excellent gettering capability while suppressing increase in resistance of the source and drain regions. Therefore, a semiconductor device including a highly reliable and high-performance thin film transistor can be provided. Furthermore, according to the present invention, the semiconductor device can be manufactured by a simple process.

  As a mechanism for gettering, when the solid solubility of a certain region of the crystalline semiconductor film with respect to the catalytic element is increased as compared with the other region, the catalytic element moves to the predetermined region (the first region) Gettering action) and when a defect or local segregation site that traps the catalytic element is formed in one region of the crystalline semiconductor film, the catalytic element moves and is trapped in that region (Second gettering action).

  As in the methods disclosed in Patent Documents 2 and 3, when an element (gettering element) belonging to Group 5B of the periodic table having the action of moving the catalytic element is introduced into the crystalline silicon film, the gettering element is introduced. The solid solubility with respect to the catalytic element in the selected region is increased. That is, the gettering movement is performed using the first gettering action. On the other hand, in the method disclosed in Patent Document 1, since the lattice defects in the amorphous region become local segregation sites for trapping the catalytic element, gettering using the second gettering action is performed. Is called. In addition, since the free energy of the catalytic element in the amorphous region is lower than that in the crystalline region, the catalytic element easily diffuses into the amorphous region.

  Here, as one of effective methods for simplifying the gettering process, the catalytic element is moved to the region to be the source region or the drain region of the TFT semiconductor layer as described above, and the catalytic element is moved from the channel region. In addition to the above-mentioned problems, it has been found that such a method has a big problem. In order to enhance the gettering capability in the gettering region, it is necessary to sufficiently draw out the first gettering action and the second gettering action. However, it is difficult to sufficiently enhance the gettering action in a region that becomes a source region or a drain region of the TFT in the crystalline semiconductor film. This is because, in order to increase the gettering efficiency, it is effective to introduce a large amount of gettering elements into the gettering region (regions to be the source and drain regions) and to make the region amorphous. Such a process greatly deteriorates the resistance value of the gettering region. This is because it is difficult to make such a gettering region function as a source region and a drain region after the gettering step.

  When a large amount of gettering element is ion-implanted into the crystalline semiconductor film, the crystal in the implanted region breaks down and becomes amorphous. The amorphization at this time is started from the upper surface side of the semiconductor film, and when it is completely amorphized to the lower surface side, it does not recover even if heat treatment is performed thereafter. In the conventional method using the source region and the drain region as the gettering regions, it is necessary to recover the crystal of the gettering region after ion implantation to some extent and lower the resistance in the subsequent heat treatment. For this reason, in such a method, it is difficult to increase the gettering efficiency by injecting a large amount of gettering element, and it is necessary to suppress the injection amount to a level that can recover the crystal. However, if the amount of gettering element implanted is small, the gettering ability is greatly reduced, and therefore, the control of the amount of gettering element implanted is the biggest problem.

  When the above method is actually applied to a driver-integrated liquid crystal display device, the source region and the drain region become amorphous in a part of the substrate and become high resistance, and the on-characteristic of the TFT formed in that part is high. A failure occurred and a driver failure occurred. Further, in other parts of the substrate, the amount of gettering elements introduced is small, resulting in insufficient gettering, and line defects and point defects are generated due to an increase in leakage current during the off operation. As described above, since the process margin is extremely small, it cannot be applied to mass production of the liquid crystal display device.

  In the method of Patent Document 1, an amorphous region does not function as a source and drain region, so an additional step of activation using laser light or the like is required. However, as described above, the laser irradiation apparatus is expensive and has a complicated apparatus structure and poor maintainability, resulting in an increase in manufacturing cost and a decrease in the yield rate. In addition, laser irradiation alone cannot recover crystal defects generated at the junctions between the channel region, the source region, and the drain region, leading to deterioration in reliability and an increase in leakage current during off operation. Further, in the conventional method using such a source region and a drain region as a gettering region as they are, the junction between the channel region and the source / drain region is formed between the gettering region and the non-gettering region. It is also a boundary, and segregation of the catalytic element existing at the junction between the channel region and the drain region cannot be removed.

  Further, if the gettering region (source region and drain region) in an amorphous state is finally crystallized as in the method of Patent Document 1, the subsequent gettering action is reduced, and heat treatment is performed. In some cases, the catalytic element once moved in step 1 may flow backward in the subsequent steps. Even if such a backflow of the catalytic element is prevented in the manufacturing process, a considerable amount of heat is generated by driving the TFT, and the catalytic element once moved to the gettering region moves to the channel region when driving the TFT. In some cases, problems occur in reliability. Therefore, when a gettering region is provided in the active layer of the TFT, the region maintains the same gettering state even when the TFT is completed, and keeps the same level of gettering capability as in the gettering step. I know that is desirable.

  The present invention has been made to solve the problems of the conventional gettering method as described above. Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described with reference to the drawings. Note that the “semiconductor device” in this specification only includes a thin film transistor including a semiconductor layer as an active layer, and includes a thin film transistor, an active substrate, a liquid crystal display device, and the like.

  The semiconductor device of this embodiment includes the thin film transistor 10 shown in FIG. The thin film transistor 10 is formed on the substrate 1, and is formed on the semiconductor layer 13 having a crystalline region including the channel region 7, the source and drain regions 9, and the gettering region 11, and the semiconductor layer 13. And a gate electrode 5 formed so as to face the channel region 7 with the gate insulating film 3 interposed therebetween. The gate insulating film 3 covers at least the channel region 7, the source and drain regions 9, and the gettering region 11 in the semiconductor layer 13. In the present embodiment, at least a portion of the gate insulating film 3 located between the gate electrode 5 and the semiconductor layer 13 is composed of a plurality of insulating films including two layers having different compositions or densities, and gettering is performed. The gate insulating film 3 on the region 11 is characterized in that it is thinner than at least a portion of the gate insulating film 3 located between the gate electrode 5 and the semiconductor layer 13. Preferably, the thickness of the gate insulating film 3 on the gettering region 11 is smaller than the thickness of the gate insulating film 3 on the source and drain regions 9.

  In the thin film transistor 10, the gate insulating film 3 includes a first insulating film 3 a that covers the semiconductor layer 13, and a second insulating film 3 b that is formed on the first insulating film 3 a and covers at least the channel region 7. Although it has a layer structure, it is sufficient if it includes two layers having different compositions or densities, and it may have a laminated structure of three or more layers.

  In the present embodiment, the gettering region 11 is provided in the semiconductor layer 13 of the thin film transistor 10 in addition to the source region and the drain region 9. Further, the thickness of the gate insulating film 3 provided on the gettering region 11 is configured to be thinner than that on the channel region 7. That is, the gate insulating film 3 is selectively thinned, and the gettering region 11 is formed in that portion. In the top gate TFT, the impurity element is implanted into the semiconductor layer 13 generally over the gate insulating film 3. This is through doping for the so-called gate insulating film 3. At this time, the concentration of the impurity element implanted into the semiconductor layer 13 and the crystal state (amorphization degree) in the region are determined according to the ion implantation conditions (mainly acceleration voltage and dose) and the gate insulating film 3. It depends on the thickness.

  In other words, in the present embodiment, a dedicated region 11 for gettering is provided in a region other than the regions to be the source and drain regions 9 in the semiconductor layer 13, and the gate insulating film 3 is provided on the semiconductor layer 13. At this time, for example, the thickness of the portion of the gate insulating film 3 located on the source and drain regions 9 requiring low resistance is located on the gettering region 11 requiring gettering capability. When the gate insulating film 3 is provided so as to be larger than the thickness of the portion, and through doping treatment is performed through the gate insulating film, the gettering region 11 and the source and drain regions 9 can be in different doping states.

  In the present embodiment, the gettering region 11 is formed in the semiconductor layer 13 other than the region (active region) where electrons or holes move during the operation of the thin film transistor 10. Further, the gettering region 11 is formed at a position not adjacent to at least the channel region 7.

  In this specification, an “active layer” of a TFT is formed of an island-like semiconductor layer made of a crystalline semiconductor film, and includes a channel region, a source and drain region, a gettering region, an LDD region, and the like. Point to. On the other hand, the “active region” of the TFT includes a source and drain region, a channel region, an LDD region, and the like in the crystalline semiconductor layer, and does not include a gettering region.

  As a result, the source and drain regions 9, which are regions where electrons or holes move during the operation of the thin film transistor 10, are not affected by gettering and are formed in a substantially separated process. It is possible to optimize the addition amount of the type impurity and the p-type impurity. Also, the implantation amount and the degree of amorphization of the gettering region 11 can be optimized only for the purpose of gettering, separately from the source and drain regions 9. Therefore, as compared with the conventional method using the source / drain regions as the gettering regions, the gettering method according to the present embodiment can increase the process margin while maintaining the shortening and simplification of the process. Ring ability can be greatly increased. In addition, the throughput of the doping apparatus can be improved.

  Further, unlike the conventional method in which the source and drain regions are used as gettering regions, the source and drain regions 9 are also non-gettering regions, so that gettering at the junction between the channel region 7 and the source and drain regions 9 is performed. Since it can be carried out better than the conventional method, it is possible to almost completely suppress an increase in leakage current during off operation, which is a problem in TFT characteristics, and at the same time, it is possible to ensure higher reliability.

  In the present embodiment, as described above, at least the gate insulating film 3 in the region corresponding to the channel region 7 is composed of two or more insulating films having different compositions or densities. The gate insulating film 3 on the gettering region 11 is thinner than the gate insulating film 3 in the channel region 7. For example, the portion of the gate insulating film 3 that is located on the gettering region 11 may be composed of a layer that is less than the portion that is located on the channel region 7 or the gate insulating film 3. Of these, the portion located on the gettering region 11 may be composed of a layer that is more or less than the portion located on the source region and the drain region 9.

  A semiconductor device provided with the thin film transistor 10 can be manufactured, for example, by the following method.

  First, a first heat treatment is performed on an amorphous semiconductor film to which a catalyst element that promotes crystallization is added at least partially. Thereby, at least a part of the amorphous semiconductor film is crystallized to obtain a semiconductor film including a crystalline region. Next, by patterning the semiconductor film including the crystalline region, an island-shaped semiconductor layer including the crystalline region is formed. Subsequently, a plurality of insulating films having different compositions or densities are stacked on the island-shaped semiconductor layer, thereby forming an insulating film (laminated insulating film) having a stacked structure.

  Of the stacked insulating film, at least a portion of the island-like semiconductor layer located above the region to be a gettering region is selectively etched to be thinned. At this time, it is preferable that at least an uppermost insulating film located on a region serving as a gettering region among the insulating films having a stacked structure is removed by etching. In addition, it is preferable that at least a lowermost insulating film of the insulating film having a stacked structure is not etched and remains on a region serving as a gettering region. In this way, a thinner gate insulating film is formed on the gettering region than on other regions.

  Thereafter, at least a gettering region of the island-like semiconductor layer is doped with a gettering element having gettering ability. Next, by performing a second heat treatment on the island-shaped semiconductor layer, at least a part of the catalyst element in the island-shaped semiconductor layer is moved to the gettering region.

  As described above, in this embodiment, the gate insulating film having a thickness on the gettering region smaller than the thickness on the source region and the drain region is formed. For this purpose, the gate insulating film on the gettering region is formed. An etching process for locally thinning the film is necessary. At this time, as proposed in the unpublished Japanese Patent Application No. 2004-56358 specification by the present applicant, if selective etching is performed on an insulating film having a single-layer structure, the distance between the substrates and the substrate surface are reduced. The variation in the etching amount cannot be avoided, and the thickness of the gate insulating film located on the gettering region may vary greatly. When the thickness of the gate insulating film on the gettering region varies, the amount of gettering elements entering the gettering region and the crystal state of the gettering region vary, and the gettering capability varies. As a result, there is a problem that it is difficult to perform stable gettering processing.

  On the other hand, in this embodiment, the selective etching as described above is performed on an insulating film having a laminated structure of two or more layers having different densities or compositions. Therefore, the lower layer of the layer to be removed can be used as an etching stopper by changing the etching rate when each layer constituting the insulating film is etched. As a result, the thickness of the gate insulating film on the gettering region can be controlled uniformly, so that the capability of the gettering region is enhanced and stabilized, and a stable gettering effect can be always obtained.

  The simplest configuration of the gate insulating film in this embodiment is a case where the gate insulating film has a two-layer structure, and a sufficiently high effect can be obtained with a simple manufacturing process. The gate insulating film having a two-layer structure is located on a region to be a gettering region at least after the island-shaped semiconductor layer in the upper insulating film after forming a laminated insulating film composed of a lower insulating film and an upper insulating film. It can be obtained by selectively removing or thinning the portion. Preferably, the upper insulating film located on the gettering region is etched using the lower insulating film as an etching stopper.

  Thereby, at least a portion corresponding to the channel region of the gate insulating film is configured by two layers of insulating films having different compositions or densities, and a portion corresponding to the gettering region is a region corresponding to the channel region. A thin film transistor including only the lower insulating film among the insulating films can be manufactured. Note that the portion of the gate insulating film corresponding to the source region and the drain region is preferably composed of two layers of insulating films having different compositions or densities, like the portion of the gate insulating film corresponding to the channel region.

  Here, the thin film transistor in this embodiment may include a low concentration impurity region (LDD region) at the junction between the channel formation region of the semiconductor layer and the source or drain region. The LDD region is provided to alleviate electric field concentration applied to the junction, to reduce leakage current during off operation and to improve hot carrier resistance. Even in such a case, the junction between the channel region and the LDD region and the junction between the LDD region and the source and drain regions can be sufficiently gettered.

  The semiconductor device of the present embodiment only needs to include at least one thin film transistor (TFT) as described above, and may include, for example, a plurality of TFTs. For example, a device in which an N-channel TFT and a P-channel TFT are configured to be complementary may be used, and such a device can be suitably used for a CMOS circuit. In such a semiconductor device, a portion of a gate insulating film of an N-channel TFT and a P-channel TFT that is located between a gate electrode and a semiconductor layer (typically, gate insulation on a channel region in each TFT). The film) and the gate insulating film on the channel region are composed of two or more insulating films having different compositions or densities. The semiconductor layers of the N-channel TFT and the P-channel TFT each have a gettering region, and the gate insulating film on the gettering region in the N-channel TFT is a gate insulating film of the N-channel TFT and the P-channel TFT. Is thinner than the portion located between the gate electrode and the semiconductor layer.

  Of the gate insulating films of the N-channel TFT and the P-channel TFT, a portion located between the gate electrode and the semiconductor layer has a two-layer structure including the first insulating film and the second insulating film formed thereon. In the case where the gate insulating film is provided, the gate insulating film on the gettering region, the source region, and the drain region in the P-channel TFT may be thinner than the above portion of the gate insulating film. May be.

  In the present embodiment, it is preferable to achieve both lowering the resistance of the source region and the drain region and ensuring the gettering capability in the gettering region, but it is difficult to achieve both in the case of an N-channel TFT. In an N-channel TFT, phosphorus is generally used as an N-type impurity. However, since the mass of phosphorus is larger than the mass of boron generally used as a P-type impurity, when a semiconductor layer is doped with phosphorus, a semiconductor is used. Damage to the layer is significant and may cause crystal destruction. As described above, it is desirable that crystal breakage occurs in the gettering region. However, when crystal breakage occurs in the source region and the drain region, the crystal does not recover by subsequent activation annealing, and the resistance increases. As a result, the source and drain regions may not function. Therefore, in the case of manufacturing a semiconductor device having a structure in which a P-channel TFT and an N-channel TFT are combined, a configuration in which the gate insulating film on the gettering region is selectively thinned is positively applied to the N-channel TFT. Therefore, it is preferable to reduce the resistance of the source region and the drain region, to ensure the gettering capability in the gettering region, and to simplify the manufacturing process.

  A semiconductor device in which the above structure is applied to an N-channel TFT can be manufactured by, for example, the following method (first method).

  First, at least a part of the amorphous semiconductor film is crystallized by performing a first heat treatment on the amorphous semiconductor film to which a catalytic element that promotes crystallization is added at least partly. A semiconductor film including a region is obtained. By patterning the obtained semiconductor film, a plurality of island-like semiconductor layers each having a crystalline region are formed. Next, a lower insulating film and an upper insulating film are formed in this order on the island-shaped semiconductor layer to form a stacked insulating film having a stacked structure.

  After the gate electrode is formed on the stacked insulating film, the region serving as the gettering region of the island-shaped semiconductor layer serving as the N-channel TFT and the entire island-shaped semiconductor layer serving as the P-channel TFT are exposed, and the N-channel type is exposed. A first mask is formed so as to cover a region to be a source region and a drain region of the TFT and a gate electrode. Subsequently, using the first mask and the gate electrode of the P-channel TFT as a mask, the p-type is applied to the semiconductor layer in the exposed region through the laminated insulating film (upper insulating film / lower insulating film) Doping with impurity elements.

  Thereafter, the upper insulating film in the region exposed from the first mask and the gate electrode of the P-channel TFT is removed by etching. Thereby, a gate insulating film is obtained.

  Next, the entire island-shaped semiconductor layer to be the N-channel TFT and the region to be the gettering region of the island-shaped semiconductor layer to be the P-channel TFT are exposed, and the regions to be the source and drain regions of the P-channel TFT A second mask is formed so as to cover the gate electrode. Using the second mask and the gate electrode of the N-channel TFT as a mask, the gate insulating film (second insulating film / In the gettering region of the N-channel TFT and the gettering region of the P-channel TFT, the impurity element imparting n-type is doped through the first insulating film. Thereafter, by performing a second heat treatment, at least a part of the catalyst element in the island-shaped semiconductor layer is moved to the gettering region.

  In the first method, the step of doping N-type impurities or P-type impurities for forming the source and drain regions of the N-channel TFT and P-channel TFT and the doping step of forming the gettering region are performed simultaneously. By doing so, the process is simplified. In addition, by using the mask used at the time of doping as it is and etching the insulating film, the process can be simplified without adding a step for gettering.

  Instead of the first method, the following method (second method) may be used.

  First, at least a part of the amorphous semiconductor film is crystallized by performing a first heat treatment on the amorphous semiconductor film to which a catalytic element that promotes crystallization is added at least partly. A semiconductor film including a region is obtained. By patterning the obtained semiconductor film, a plurality of island-like semiconductor layers each having a crystalline region are formed. A laminated insulating film is formed by forming a lower insulating film and an upper insulating film in this order on the island-like semiconductor layer.

  Next, after forming a gate electrode over the stacked insulating film, a region serving as a gettering region of the island-shaped semiconductor layer serving as the N-channel TFT and an entire island-shaped semiconductor layer serving as the P-channel TFT are exposed, and the N-channel A first mask is formed so as to cover a region to be a source region and a drain region of the type TFT and a gate electrode. Subsequently, the upper insulating film exposed from the first mask and the gate electrode of the P-channel TFT is removed by etching. Thereby, a gate insulating film is obtained.

  Thereafter, using the first mask and the gate electrode of the P-channel TFT as a mask, the semiconductor layer in the exposed region is doped with an impurity element imparting p-type through the first insulating film.

  Next, the entire island-shaped semiconductor layer serving as the N-channel TFT and the region serving as the gettering region of the island-shaped semiconductor layer serving as the P-channel TFT are exposed, and the region serving as the source region and drain region of the P-channel TFT, and A second mask is formed so as to cover the gate electrode. Using the second mask and the gate electrode of the N-channel TFT as a mask, the gate insulating film (second insulating film / In the gettering region of the N-channel TFT and the gettering region of the P-channel TFT, the impurity element imparting n-type is doped through the first insulating film. Thereafter, by performing a second heat treatment, at least a part of the catalyst element in the island-shaped semiconductor layer is moved to the gettering region.

  Of the two manufacturing methods described above, in the first method, the insulating film is selectively etched after p-type impurity doping. In the second method, after the insulating film is selectively etched, Doping with p-type impurities is performed. According to the second method, when the p-type impurity is doped into the semiconductor layer, the thickness of the gate insulating film is selectively small. Therefore, the first insulation under the gate insulating film is formed in a predetermined region of the semiconductor layer. Doped only through the membrane. Therefore, the acceleration voltage at the time of p-type impurity doping can be set small, and the margin as a manufacturing apparatus becomes large.

  In addition to the first and second methods, the following methods (third method and fourth method) can also be used.

  In the third method, the plurality of island-shaped semiconductor layers, the stacked insulating film, and the gate electrode are formed by the same method as described above. Next, a region to be a gettering region of an island-shaped semiconductor layer to be an N-channel TFT and an entire island-shaped semiconductor layer to be a P-channel TFT are exposed, and a region to be a source region and a drain region of the N-channel TFT and A first mask is formed so as to cover the gate electrode. Using the first mask and the gate electrode of the P-channel TFT as a mask, p-type is applied to the semiconductor layer in the exposed region through the stacked insulating film (second insulating film / first insulating film). Doping with impurity elements.

  Thereafter, the upper insulating film exposed from the first mask and the gate electrode of the P-channel TFT is removed by etching. Thereby, a gate insulating film is formed.

  Next, a region that becomes a source region and a drain region and a gettering region of the N-channel TFT and a region that becomes a gettering region of the island-shaped semiconductor layer that becomes the P-channel TFT are exposed, and the LDD of the N-channel TFT is exposed. A second mask is formed so as to cover the region, the region serving as the source region and drain region of the P-channel TFT, and the gate electrode. With respect to the semiconductor layer in the region exposed from the second mask, the source region and drain region of the N-channel TFT have the N-channel TFT over the gate insulating film (second insulating film / first insulating film). In the gettering region and the gettering region of the P-channel TFT, an impurity element imparting n-type is doped through the first insulating film. Thereafter, by performing a second heat treatment, at least a part of the catalyst element in the island-shaped semiconductor layer is moved to the gettering region.

  In the fourth method, the plurality of island-shaped semiconductor layers, the stacked insulating film, and the gate electrode are formed by the same method as described above. Next, a region to be a gettering region of an island-shaped semiconductor layer to be an N-channel TFT and an entire island-shaped semiconductor layer to be a P-channel TFT are exposed, and a region to be a source region and a drain region of the N-channel TFT and A first mask is formed so as to cover the gate electrode. The upper insulating film in the region exposed from the first mask and the gate electrode of the P-channel TFT is removed by etching. Thereby, a gate insulating film is obtained.

  Thereafter, using the first mask and the gate electrode of the P-channel TFT as a mask, the semiconductor layer in the exposed region is doped with an impurity element imparting p-type through the first insulating film. Subsequently, the source and drain regions and the gettering region of the N-channel TFT and the region of the island-like semiconductor layer that becomes the P-channel TFT are exposed, and the LDD of the N-channel TFT is exposed. A second mask is formed so as to cover the region, the region serving as the source region and drain region of the P-channel TFT, and the gate electrode. With respect to the semiconductor layer in the region exposed from the second mask, the source region and drain region of the N-channel TFT have the N-channel TFT over the gate insulating film (second insulating film / first insulating film). In the gettering region and the gettering region of the P-channel TFT, an impurity element imparting n-type is doped through the first insulating film. After that, by performing a second heat treatment, at least a part of the catalyst element in the island-shaped semiconductor layer is moved to the gettering region.

  In the third and fourth methods, the LDD region is formed in the N-channel TFT. Since the LDD region is formed at the same time as the gettering region using a mask for forming the gettering region, it is possible to reduce the off-current of the N-channel TFT and increase the reliability without increasing the number of steps. Become.

  In the semiconductor device obtained by the first to fourth methods exemplified above, the gate insulating film on the source region and the drain region of the N-channel TFT is the gate insulating film in the N-channel TFT or P-channel TFT. Similar to the portion located between the gate electrode and the semiconductor layer, it is composed of two insulating films having different compositions or densities. In addition, the gate insulating film on the gettering region and the gate insulating film on the source region and the drain region in the P-channel TFT are formed between the gate electrode and the semiconductor layer in the gate insulating film in the N-channel TFT and the P-channel TFT. It is comprised only by the lower layer insulating film (1st insulating film) of the part located in between.

  In the step of selectively etching the upper insulating film in the laminated insulating film, if etching is performed until the upper insulating film is completely removed, only the first insulating film is formed on the gettering region as described above. In this case, the portion of the upper insulating film located on the gettering region may be thinned by the above etching process for the upper insulating film. A gate insulating film thinner than that on the drain region can be formed.

  Thus, in the semiconductor device and the manufacturing method thereof according to the present embodiment, the N-type impurity itself acts as a gettering element. Therefore, in particular, in a method of manufacturing a semiconductor device having an N-channel TFT, the step of adding a gettering element and the step of doping an N-type impurity for forming source and drain regions are performed using the same mask. This can be done by doping with an element. Note that a P-channel TFT does not have a gettering capability only with a P-type impurity, and therefore it is necessary to perform an N-type impurity implantation step into the gettering region separately from the P-type impurity doping step.

  In this embodiment, it is preferable that both the N-type impurity element and the P-type impurity element are doped in the gettering regions of the N-channel TFT and the P-channel TFT. That is, the gettering region includes, as gettering elements, an impurity element belonging to Group B of the Periodic Table imparting n-type and an impurity element belonging to Group B of the Periodic Table imparting p-type. Preferably it is. Even when the gettering region contains only the n-type impurity element, the solid solubility of the catalyst element in the n-type impurity element introduction region is increased, and the first gettering action described above is caused. However, when the gettering region includes a p-type impurity element in addition to the n-type impurity element, the effect as the gettering element is further increased. More specifically, when the gettering region is doped not only with the Group 5 B element but also with the Group 3 B element, the gettering mechanism changes, and in addition to the first gettering action in the case of only phosphorus, defects and local strains are obtained. The second gettering action using the dominates. Therefore, the gettering ability is enhanced and a larger gettering effect can be obtained. Although the gettering element is not particularly limited, the highest gettering effect can be obtained by selecting P (phosphorus) from the group 5 B element and selecting B (boron) from the group 3 B element. In addition, since these elements are also used as impurity elements doped in the source and drain regions, when these elements are selected as gettering elements, the source regions and drains are added by a process and impurity doping to add the gettering elements. A doping step that also serves as a step of forming a region can be performed. Therefore, it is not necessary to add a step of adding a gettering element separately, and the manufacturing process can be greatly shortened.

The gettering region contains an impurity element imparting n-type at a concentration of 1 × 10 19 / cm 3 or more and 3 × 10 21 / cm 3 or less, and an impurity element imparting p-type is 1 × 10 19. It is preferably contained at a concentration of not less than / cm 3 and not more than 3 × 10 21 / cm 3 . By adjusting the concentration of the impurity element within the above range, high gettering efficiency can be obtained. Although the concentration of the impurity element may be higher than the above range, the gettering efficiency is saturated, which is disadvantageous in that extra processing time is required.

  In the semiconductor device of this embodiment, an impurity element belonging to Group 5B of the periodic table imparting n-type is introduced into the gettering region of the N-channel TFT from the source region or the drain region of the N-channel thin film transistor. Is preferably contained at a high concentration. In this embodiment, in the N-channel TFT, the doping state of the source region and the drain region and the doping state of the gettering region are made different from each other by utilizing the difference in thickness of the gate insulating film. Therefore, an n-type impurity which is a gettering element is doped in a region other than the gettering region in the semiconductor layer, but the gettering region doped with the gettering element through a thinner gate insulating film includes A larger amount of gettering element is introduced than other regions doped through the thicker gate insulating film. As a result, the gettering region exhibits a strong gettering action, and the gettering of the source and drain regions can also be performed.

  In the gettering region, it is preferable that the amorphous component is large and the crystalline component is small compared to the channel formation region, the source region, or the drain region. In order to form such a gettering region, the step of doping an n-type impurity element is performed in a gettering region of an N-channel TFT and a P-channel TFT as compared with a source region and a drain region of an N-channel TFT. It is preferable that the etching is performed under doping conditions such that the crystal breakage further progresses and becomes amorphous.

  Therefore, in the doping step for forming the gettering region, the amorphous state in the portion of the island-like semiconductor layer located under the thinned gate insulating film (that is, the portion that becomes the gettering region) is changed into the source. It is preferable to proceed more than the amorphization in the portion to be the region and the drain region. This is because the free energy of the catalytic element is lower than the crystalline region in the region where the amorphization is sufficiently advanced (amorphous region), and thus the catalytic element is likely to diffuse into the amorphous region. Further, in the amorphous region, a second gettering action is caused in which a dangling bond or a lattice defect forms a segregation site for trapping the catalytic element, and the catalytic element is moved and trapped there. In the present embodiment, the TFT semiconductor layer has a gettering region separately from the source region and the drain region, and the gettering region is arranged so as not to prevent the movement of carriers (electrons or holes) of the TFT. Therefore, even if the gettering region becomes amorphous and has a high resistance, the TFT characteristics are not lowered accordingly. Therefore, an amorphous gettering region having higher gettering capability than the conventional one can be formed in the semiconductor layer.

The crystalline state in each region of the semiconductor layer can be evaluated by determining the ratio Pa / Pc between the TO phonon peak Pa of the amorphous semiconductor and the TO phonon peak Pc of the crystalline semiconductor in the Raman spectrum. When the semiconductor layer is formed using a silicon (Si) film, a peak Pc due to TO phonon of crystalline Si appears in the vicinity of 520 cm −1, and a peak Pa due to TO phonon of amorphous Si indicates its state density. Reflecting, it appears in a broad shape in the vicinity of 480 cm −1 . The ratio Pa / Pc between the TO phonon peak Pa of the amorphous semiconductor and the TO phonon peak Pc of the crystalline semiconductor in the Raman spectroscopy spectrum in the gettering region is larger than the ratio Pa / Pc in the channel formation region and the source / drain regions. Such control is advantageous because high gettering efficiency can be ensured. In the manufacturing method of the present embodiment, the ratio Pa / Pc between the TO phonon peak Pa of the amorphous semiconductor and the TO phonon peak Pc of the crystalline semiconductor in the Raman spectrum in the gettering region is the ratio Pa in the source region and the drain region. It is desirable that the above state be maintained even after the second heat treatment described above is performed after each region is formed so as to be larger than / Pc. If the TFT is completed while maintaining the above state, it becomes possible to always maintain the same level of gettering ability as in the gettering process even when driving the TFT, and the reverse diffusion of the catalytic element from the gettering region can be prevented. Therefore, the reliability of the semiconductor device can be improved.

  In the present embodiment, when an N-channel TFT and a P-channel TFT are formed simultaneously, an n-type doping process and a p-type doping process for forming respective source and drain regions are used to form a P-channel. In addition to the type TFT, it is preferable to form a gettering region in the N-channel type TFT at the same time, which can greatly simplify the manufacturing process. As described above, the p-type impurity itself does not function as a gettering element, but has a strong gettering action when present together with the n-type impurity in the semiconductor layer. Therefore, when a gettering region doped with n-type impurities and p-type impurities is formed in the semiconductor layer of the N-channel TFT, the gettering capability of the N-channel TFT can be further enhanced. In addition, since the upper gate insulating film is selectively thinned in the gettering region of the N-channel TFT, more n-type impurities are introduced as compared with the source and drain regions. The doping damage to the crystal is large and the amorphization is progressing, and many crystal defects are generated. Therefore, higher gettering capability can be realized.

  According to the conventional semiconductor device, since the gate insulating film on the gettering region is not selectively thinned, even when the gettering region is formed separately from the source and drain regions in the TFT semiconductor layer, the gettering capability is improved. If the gettering region is doped with a large amount of n-type impurity, which is a gettering element, for the purpose of increasing, the same amount of n-type impurity is also doped in the source and drain regions. As described above, when an excessive amount of n-type impurity is doped in the source and drain regions, the resistance in the source and drain regions is not lowered, but amorphization occurs due to the doping damage, resulting in extremely high resistance. The same applies to the case of doping with a p-type impurity, but the increase in resistance due to doping damage is more conspicuous in the case of doping with an n-type impurity, and becomes a big problem particularly in an N-channel TFT.

  On the other hand, in this embodiment, the gate insulating film on the gettering region and the gate insulating film on the source and drain regions are made different in thickness, so that doping corresponding to the purpose is performed in each region. Is possible. Since the gate insulating film on the gettering region is thin, the gettering region is more heavily doped with n-type impurities and p-type impurities than the source and drain regions, and as a result, amorphousization proceeds due to doping damage. The high gettering ability can be exhibited. On the other hand, since the gate insulating film on the source and drain regions is thick, doping damage at the time of doping is small in the source and drain regions, and low resistance can be realized while maintaining the crystalline state.

  The present inventors obtained profile data of n-type impurities in a doping apparatus by SIMS (secondary ion mass spectrometry). FIG. 12 is a graph showing an example thereof.

  FIG. 12 is a concentration profile in the film thickness direction when phosphorus is doped as an n-type impurity in the silicon oxide film. The horizontal axis of the graph shown in FIG. 12 is the depth from the surface, and the zero point is the outermost surface of the silicon oxide film. From FIG. 12, it can be seen that the phosphorus concentration at the position where the depth from the surface is 500 mm (50 nm) is about five times the phosphorus concentration at the position where the depth from the surface is 1000 mm (100 nm). Therefore, for example, when the thickness of the gate insulating film on the source and drain regions is set to 100 nm, the thickness of the gate insulating film on the gettering region is reduced to 50 nm, and phosphorus is doped as an n-type impurity, gettering is performed. The concentration of phosphorus in the region is about 5 times the concentration of phosphorus in the source and drain regions. In addition, since the upper gate insulating film is thin, phosphorus ions are implanted into the gettering region at a higher acceleration voltage than the source and drain regions under the thick gate insulating film. Therefore, in the gettering region, the impact energy of individual ions is large, the crystallinity is further lost, and amorphization proceeds. On the other hand, in the source and drain regions, since the gate insulating film is thick, phosphorus is not excessively implanted, and the impact energy of ions at the time of implantation is low. Can be maintained. In this manner, the gettering region and the source and drain regions can be easily formed in a crystalline state suitable for each purpose.

  In this embodiment, when etching the laminated insulating film, the step of removing the upper insulating film in the region exposed from the first mask and the gate electrode of the P-channel TFT by etching is performed by the etching rate of the upper insulating film. Is preferably performed under such conditions that the etching rate is higher than the etching rate of the lower insulating film. Accordingly, a highly reliable gate insulating film with reduced thickness variation can be formed as compared with a case where a single-layer insulating film is selectively thinned. At this time, the ratio of the etching rate of the lower insulating film to the etching rate of the upper insulating film, the higher the etching selectivity, the higher the controllability for etching only the upper insulating film and leaving the lower insulating film without etching. improves. More preferably, in the step of removing the upper insulating film by etching, the lower insulating film is used as an etching stopper film. If the lower insulating film functions as an etching stopper, the lower insulating film can be almost completely left, so that the thickness of the gate insulating film on the gettering region is substantially the same as the thickness of the lower insulating film. Can be controlled stably.

  The gate insulating film in this embodiment is composed of two or more layers. Each layer of the gate insulating film is preferably formed using a silicon oxide film or a silicon nitride film. When these films are used, conditions such as reliability, electrical characteristics, and coverage required for the gate insulating film can be satisfied. In that case, when the composition ratio of silicon (that is, the composition ratio of oxygen and / or nitrogen) in at least two layers constituting the gate insulating film is different from each other, it is advantageous when performing etching as described above.

  Alternatively, the gate insulating film may have a multilayer structure including a film mainly containing silicon oxide and a film mainly containing silicon nitride. Preferably, it has a two-layer structure including a first insulating film mainly composed of silicon oxide and a second insulating film mainly composed of silicon nitride. It is preferable to use a silicon oxide film as the first insulating film in contact with the channel region because high electrical characteristics can be obtained. Further, when a silicon nitride film is used as the second insulating film, the silicon nitride film has a dielectric constant 1.5 to 2 times that of the silicon oxide film, so that the dielectric constant of the gate insulating film can be increased. High TFT characteristics can be obtained. In addition, hydrogen contained in the silicon nitride film terminates crystal defects and dangling bonds in the silicon film (semiconductor layer), and has an effect of improving crystal characteristics.

  When forming the gate insulating film as described above, first, a laminated insulating film is formed on the semiconductor layer. At this time, a plurality of layers constituting the laminated insulating film are continuously exposed to the atmosphere without being exposed to the atmosphere. It is desirable to be formed. Disadvantages of having two or more layers of the gate insulating film include the formation of interface states due to contamination at the laminated interface, etc. In the process of forming the laminated insulating film, for example, after forming the lower insulating film If the upper insulating film is continuously formed without being exposed to the atmosphere, the interface between the lower insulating film and the upper insulating film can be kept clean, and the generation of interface states can be prevented. Moreover, since it can shorten a tact also when it sees from a manufacturing apparatus surface, it is advantageous.

  In the present embodiment, the gettering region is formed in a region other than a region where electrons or holes move. The gettering region is preferably formed at a position adjacent to the source region or drain region of the thin film transistor and not adjacent to the channel region or LDD region. More preferably, the gettering region is formed in the outer edge portion of the semiconductor layer, and the wiring for electrically connecting the plurality of thin film transistors and the semiconductor layer are connected in at least a part of the source region or the drain region. . Further, the wiring for electrically connecting the plurality of thin film transistors and the peninsula layer may be connected to each other in a region including a part of the gettering region and a source region and / or a drain region. By making such connections, the thin film transistor can secure an electron or hole path without going through the gettering region, and can be dedicated and optimized as the gettering region as described above. A semiconductor device having such a structure can be manufactured by forming a wiring in contact with a portion including at least a part of the source region or the drain region after the above-described second heat treatment.

  In this embodiment, the second heat treatment for gettering activates n-type impurities and / or p-type impurities doped in at least the source region and the drain region of the island-like semiconductor layer. Is preferred. This second heat treatment step allows gettering and activation to be performed at the same time, so that the manufacturing process can be shortened and an additional step for gettering, which is essential in the conventional manufacturing process, can be omitted. Can do. As a result, the manufacturing process can be simplified and the manufacturing cost can be reduced.

  As described above, in the present embodiment, the second heat treatment for gettering (temperature: for example, 500 ° C. or more) needs to be performed after the formation of the gate electrode. It is desirable to use a refractory metal. Specifically, the gate electrode is preferably formed of one or more kinds of elements selected from W, Ta, Ti, and Mo, or alloy materials containing these elements.

  The crystalline semiconductor film in this embodiment can be suitably formed as follows. First, a mask having an opening is formed over the amorphous semiconductor film. Next, a catalytic element is added to the selected region of the amorphous semiconductor film through the opening. In this way, an amorphous semiconductor film to which a catalytic element is selectively added is obtained. When the first heat treatment is performed on the amorphous semiconductor film, crystal growth proceeds in the lateral direction from the region where the catalytic element is selectively added in the amorphous semiconductor film to the periphery thereof. As a result, a good crystalline semiconductor film in which the crystal growth direction is aligned in almost one direction is formed. Forming the crystalline semiconductor film by such a method is advantageous because the current driving capability of the TFT can be further increased.

  As the catalyst element, one or more elements selected from Ni, Co, Sn, Pb, Pd, Fe, and Cu can be used. One or more elements selected from these exhibit the effect of promoting crystallization in a trace amount.

The catalytic element does not act alone, but acts on crystal growth by bonding to the silicon film and silicidation. At this time, the crystal structure of the silicide acts as a kind of template during crystallization of the amorphous silicon film, and promotes crystallization of the amorphous silicon film. When Ni is used as the catalyst element, Ni forms a silicide of two Si and NiSi 2 . NiSi 2 exhibits a meteorite-type crystal structure, which is very similar to the diamond structure of single crystal silicon. Moreover, NiSi 2 has a lattice constant of 5.406 、, which is very close to the lattice constant of 5.430 に お け る in the diamond structure of crystalline silicon. Therefore, NiSi 2 is optimal as a template for crystallizing an amorphous silicon film. Therefore, among the elements exemplified above, when Ni is used in particular, the effect of promoting the most remarkable crystallization can be obtained.

Since the apparatus of this embodiment is manufactured using a crystalline semiconductor film manufactured using a catalytic element, a catalytic element that promotes crystallization of the amorphous semiconductor film exists in the gettering region. ing. The concentration of the catalytic element present in the gettering region is, for example, 5 × 10 18 atoms / cm 3 or more. At this time, the concentration of the catalytic element in the channel region is reduced, for example, to a range of about 1 × 10 15 to 1 × 10 17 atoms / cm 3 . That is, the concentration of the catalytic element in the channel region is reduced to the above range by the gettering step, and as a result, the catalytic element concentration in the gettering region is increased by 2 to 4 orders of magnitude compared to the catalytic element concentration in the channel region.

  At least the channel region of the semiconductor layer is preferably formed of a crystalline semiconductor film whose crystal plane orientation is mainly constituted by <111> crystal zone planes. More preferably, at least the channel region of the semiconductor layer has a crystal plane orientation mainly composed of <111> crystal zone planes, and the plane orientation ratio is particularly ( It is formed from a crystalline semiconductor film in which 50% or more of the entire region is occupied by (110) plane orientation and (211) plane orientation.

  In general, when an amorphous semiconductor film is crystallized without using a catalytic element, the plane orientation of the crystalline semiconductor film is affected by the influence of the insulator underlying the semiconductor film (especially in the case of amorphous silicon dioxide). , (111). On the other hand, when a catalyst element is added to the amorphous semiconductor film and crystallized as in the present embodiment, unique growth as shown in FIG. 13A is performed. FIG. 13A is a diagram illustrating crystal growth of an amorphous semiconductor film formed over the base insulator 61. As shown in the figure, the catalytic compound semiconductor compound 64 serves as a driving force for crystal growth of the uncrystallized region 62 in the amorphous semiconductor film. That is, the catalytic element compound 64 is present at the forefront of crystal growth, and the adjacent amorphous regions 62 are crystallized one after another toward the right side of the drawing sheet, so that the crystalline semiconductor film 63 is formed. Sometimes the catalytic element compound 64 has a property of growing strongly in the <111> direction. As a result, as the plane orientation of the obtained crystalline semiconductor film, a <111> crystal zone plane appears as shown in FIG.

  The <111> crystal zone plane is shown in FIG. In FIG. 13B, the horizontal axis is the inclination angle from the (−110) plane, and the vertical axis is the surface energy. The group 65 is a crystal plane that becomes a <111> crystal zone plane. The (100) plane and the (111) plane are not <111> crystal zone planes, but are shown for comparison. FIG. 13C shows a standard triangle of crystal orientation. Here, the distribution of the <111> crystal zone plane is as shown by the broken line in FIG. The numbers are typical pole indices. In the crystalline semiconductor film in this embodiment, among these <111> crystal zone planes, the (110) plane or (211) plane is predominantly oriented, and this plane dominates when it accounts for 50% or more of the entire plane. Sex is obtained. These two crystal planes have a very high hole mobility compared to the other planes, can improve the performance of P-channel TFTs that are inferior to N-channel TFTs, and are easily balanced in semiconductor circuits. There are benefits.

  FIG. 14 shows a plane orientation distribution of the crystalline semiconductor film obtained by using the catalyst element in the present embodiment. FIG. 14 shows the result of EBSP measurement, in which the crystal orientation is specified separately for each minute region, and these are connected and mapped. FIG. 14A shows a plane orientation distribution in the crystalline semiconductor film of the present invention, and FIG. 14B shows a plane between adjacent mapping points based on the data in FIG. Those having an inclination angle of azimuth or less (here, 5 ° or less) are separately painted with the same color, and the distribution of individual crystal domains is highlighted. FIG. 14C shows the standard triangle of the crystal orientation described above with reference to FIG. As can be seen from FIG. 14C, the crystalline semiconductor film according to the present invention shows a plane orientation almost on the <111> crystal zone plane, and is particularly strongly oriented in the (110) plane and the (211) plane. I can see that The size of each crystal domain (substantially the same plane orientation region) shown in FIG. 14B is distributed in the range of 2 to 10 μm. Thus, in the apparatus of this embodiment, it is preferable that the domain diameter of the crystal domain (substantially the same plane orientation region) of the crystalline semiconductor film constituting the semiconductor layer is 2 to 10 μm. The above-described plane orientation, the ratio of plane orientation, and the domain diameter of the crystal domain are values measured by EBSP measurement.

  In the semiconductor device manufacturing method of this embodiment, it is desirable to irradiate the crystalline semiconductor film with laser light after the first heat treatment. When a crystalline semiconductor film is irradiated with laser light, a crystal grain boundary part and a minute residual amorphous region (uncrystallized region) are intensively processed due to a difference in melting point between the crystalline part and the amorphous part. . A crystalline silicon film crystallized by introducing a catalytic element is formed of columnar crystals, and the inside thereof is in a single crystal state. Therefore, when the crystal grain boundary is processed by laser light irradiation, a high-quality crystalline semiconductor film close to a single crystal state can be obtained over the entire surface of the substrate, so that crystallinity is greatly improved. As a result, the on-characteristics of the TFT are greatly improved, and a semiconductor device superior in current drive capability can be realized.

  As described above, according to the present embodiment, it is possible to suppress the occurrence of a leakage current due to segregation of the catalytic element. Good characteristics can be obtained in a TFT requiring a leakage current. In addition, since a semiconductor film crystallized using a catalytic element exhibits good crystallinity, good characteristics can be obtained even when the TFT according to this embodiment is used as an element of a drive circuit that requires high field effect mobility. Can be obtained.

  Hereinafter, the configuration of an apparatus according to the present invention and an embodiment of a manufacturing method thereof will be described more specifically with reference to the drawings.

(First embodiment)
A first embodiment according to the present invention will be described with reference to FIGS. In the present embodiment, a manufacturing process of a driver monolithic active matrix liquid crystal display device in which a peripheral drive circuit is integrally formed on the same substrate as a pixel TFT will be described. That is, in the present embodiment, a CMOS structure circuit in which an N-channel TFT and a P-channel TFT are configured in a complementary manner on a glass substrate and a pixel TFT (N-channel type) for switching and driving a pixel electrode are simultaneously provided. It is formed.

First, as shown in FIG. 2A, base films 102 and 103 are formed on a surface of a substrate 101 on which a TFT is to be formed. The substrate 101 only needs to have an insulating surface, and may be, for example, a low alkali glass substrate or a quartz substrate. In this embodiment, a low alkali glass substrate is used as the substrate 101. In this case, the substrate 101 may be heat-treated in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. The base films 102 and 103 are provided to prevent impurity diffusion from the substrate 101, and may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. In this embodiment, a silicon oxynitride film is formed as a lower first base film 102 by using, for example, a material gas of SiH 4 , NH 3 , and N 2 O by a plasma CVD method. Further, as the second base film 103, a silicon oxide film is similarly formed on the first base film 102 using TEOS and oxygen as material gases by plasma CVD. At this time, the thickness of the first base film (silicon oxynitride film) 102 is preferably 25 to 400 nm, for example, 100 nm. The thickness of the second base film (silicon oxide film) 103 is preferably 25 to 300 nm, for example, 100 nm. In the present embodiment, a base film composed of two layers is formed, but the base film may be a single layer of a silicon oxide film, for example.

  Next, a silicon film (a-Si film) 104 having an amorphous structure is formed by a known method such as a plasma CVD method or a sputtering method. The thickness of the a-Si film 104 is, for example, 20 to 150 nm, preferably 30 to 80 nm. In this embodiment, an amorphous silicon film having a thickness of 50 nm is formed by plasma CVD. Furthermore, in this embodiment, the base films 102 and 103 and the a-Si film 104 are continuously formed without being exposed to the air atmosphere using a multi-chamber plasma CVD apparatus. As a result, it is possible to prevent contamination at the interface between the base film 103 and the a-Si film 104 (which becomes a back channel in a TFT), and to reduce variation in characteristics and threshold voltage of the TFT to be manufactured. it can.

Thereafter, a small amount of a catalytic element (nickel in this embodiment) 105 is added onto the surface of the a-Si film 104 (FIG. 2A). This small amount of nickel 105 is added by holding a solution in which nickel is dissolved on the a-Si film 104, and then uniformly extending the solution onto the substrate 101 by a spinner and drying it. In this embodiment, nickel acetate is used as the solute of the solution, and water is used as the solvent. Further, the nickel concentration in the solution is adjusted to be, for example, 5 ppm in terms of weight. The amount of catalytic element added by this process is extremely small. The concentration of the catalytic element on the surface of the a-Si film 104 is managed by a total reflection X-ray fluorescence analysis (TRXRF) method, and is, for example, about 5 × 10 12 atoms / cm 2 .

  In addition to nickel (Ni), the catalyst element 105 may be one or more selected from iron (Fe), cobalt (Co), tin (Sn), lead (Pb), palladium (Pd), and copper (Cu). It may be an element. Although the catalytic effect is smaller than these elements, ruthenium (Ru), rhodium (Rh), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), etc. also function as the catalytic element 105. Further, as a method for adding the catalytic element 105 to the a-Si film 104, a gas phase method such as a plasma doping method, a vapor deposition method, or a sputtering method may be used in addition to a method of applying a solution containing the catalytic element. it can. The method of applying a solution containing a catalytic element is advantageous because the amount of catalytic element added can be easily controlled and a very small amount of catalytic element can be easily added.

  Subsequently, the substrate 101 is heat-treated in an inert atmosphere, for example, in a nitrogen atmosphere. As this heat treatment, it is preferable to perform an annealing treatment at 550 to 620 ° C. for 30 minutes to 4 hours. In this embodiment, as an example, heat treatment is performed at 590 ° C. for 1 hour. By this heat treatment, nickel 105 added to the surface of the a-Si film 104 is diffused into the a-Si film 104 and silicidation occurs, and the crystallization of the a-Si film 104 proceeds using this as a nucleus. As a result, as shown in FIG. 2B, the a-Si film 104 is crystallized into a crystalline silicon film 104a. Note that although crystallization is performed here by heat treatment using a furnace, crystallization may be performed by an RTA (Rapid Thermal Annealing) apparatus using a lamp or the like as a heat source.

  Prior to the heat treatment, the surface of the a-Si 204 may be slightly oxidized with ozone water or the like in order to improve the wettability of the surface of the a-Si film 104 during spin coating. After that, first heat treatment is performed on the substrate 101 in an inert atmosphere, for example, in a nitrogen atmosphere (FIG. 2B). At this time, annealing is performed at 530 to 600 ° C. for 30 minutes to 8 hours. In this example, as an example, heat treatment was performed at 550 ° C. for 4 hours. In this heat treatment, nickel 205 added to the surface of the a-Si film 104 is diffused into the a-Si film 204 and silicidation occurs, and the crystallization of the a-Si film 104 proceeds using this as a nucleus. . As a result, the a-Si film 104 is crystallized to become a crystalline silicon film 104a. Note that although crystallization is performed here by heat treatment using a furnace, crystallization may be performed by an RTA (Rapid Thermal Annealing) apparatus using a lamp or the like as a heat source. The crystal plane orientation of the crystalline silicon film 104a thus obtained is mainly composed of the <111> crystal zone plane, and among them, (110) plane orientation and (211) plane orientation are 50% of the whole. These areas are occupied. Moreover, the domain diameter of the crystal domain (substantially the same plane orientation region) is 2 to 10 μm.

  Subsequently, as shown in FIG. 2C, the crystalline silicon film 104a obtained by the heat treatment is irradiated with a laser beam 106, whereby the crystalline silicon film 104a is further recrystallized and crystallinity is improved. The formed crystalline silicon film 104b is formed. As the laser light at this time, an XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) or a KrF excimer laser (wavelength 248 nm) can be applied. The beam size of the laser light at this time is shaped to be a long shape on the surface of the substrate 101, and the entire surface of the substrate is recrystallized by sequentially scanning in the direction perpendicular to the long direction. . At this time, scanning is performed so that parts of the beams overlap each other, so that laser irradiation is performed a plurality of times at any one point of the crystalline silicon film 104a, thereby improving uniformity. If the energy of the laser beam at this time is too low, the crystallinity improvement effect is small, and if it is too high, the crystalline state of the crystalline silicon film 104a obtained in the previous step is reset, so it is necessary to set it within an appropriate range. There is. Thus, the crystalline silicon film 104a obtained by solid-phase crystallization is reduced in crystal defects by a melting and solidifying process by laser irradiation, and becomes a higher quality crystalline silicon film 104b. Even after this laser irradiation step, the crystal plane orientation and crystal domain state before laser irradiation are maintained as they are, and no significant change is observed in the EBSP measurement. However, a ridge is generated on the surface of the crystalline silicon film 104b, and the average surface roughness Ra is 2 to 10 nm.

  Thereafter, unnecessary portions of the crystalline silicon film 104b are removed and element isolation is performed, so that an island that will later become an active region (source and drain regions, channel region) of the TFT, as shown in FIG. 3A. Crystalline silicon films (semiconductor layers) 107n, 107p, and 107g are formed. The semiconductor layer 107n becomes a later N-channel TFT, the semiconductor layer 107p becomes a P-channel TFT, and the semiconductor layer 107g becomes a pixel TFT.

Here, the p-type layer is formed on the entire surface of the semiconductor layers 107n and 107p to be an N-channel TFT and a P-channel TFT at a concentration of about 1 × 10 16 to 5 × 10 17 / cm 3 for the purpose of controlling the threshold voltage. Boron (B) may be added as an impurity element imparting. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of an amorphous silicon film. For the purpose of controlling the threshold value of only the N-channel TFT, the semiconductor layer 107p of the P-channel TFT is covered with a photoresist, and only the semiconductor layer 107n of the N-channel TFT or the semiconductor layer 107g of the pixel TFT is covered. Boron may be added at a low concentration. Note that boron is not necessarily added, but boron is preferably added to the semiconductor layer 107n in order to keep the threshold voltage of the N-channel TFT within a predetermined range.

  Subsequently, as illustrated in FIG. 3B, an insulating film 109a and an insulating film 109b covering these semiconductor layers 107n, 107p, and 107g are formed in this order, and a stacked insulating film 108 having a two-layer structure is formed. The total thickness of the laminated insulating film 108 is preferably 20 to 150 nm. For example, the insulating film 109a is a silicon oxide film having a thickness of 10 to 100 nm, and the insulating film 109b is a silicon nitride film having a thickness of 10 to 100 nm. Here, a silicon oxide film with a thickness of 50 nm is used as the insulating film 109a, and a silicon nitride film with a thickness of 50 nm is used as the insulating film 109b. Therefore, the total thickness of the laminated insulating film 108 in this embodiment is 100 nm. Note that the stacked insulating film 108 only needs to have a stacked structure of two or more layers, and may have a multilayer structure of three or more layers. Alternatively, an insulating film containing silicon other than silicon oxide or silicon nitride may be used as a material for each layer included in the stacked insulating film 108.

  The silicon oxide film 109a is formed by using TEOS (Tetra Ethoxy Ortho Silicate) as a raw material and decomposing / depositing the substrate with oxygen at 150 to 600 ° C., preferably 300 to 450 ° C. by RF plasma CVD. Can do. The silicon nitride film 109 is formed using monosilane (SiH 4) and ammonia (NH 3) as source gases and nitrogen and hydrogen as carrier gases at a substrate temperature of 300 to 450 ° C. as in the formation of the silicon oxide film 109 a. It can be performed by decomposing and depositing by plasma CVD. In this embodiment, using a multi-chamber plasma CVD apparatus, the substrate 101 is placed in the chamber, and the silicon oxide film 109a and the silicon nitride film 109b are continuously formed without being exposed to the air atmosphere. As a result, it is possible to prevent contamination of the laminated interface between these insulating films 109a and 109b, and to suppress variations in characteristics and threshold voltage of the TFT to be manufactured.

  After the stacked insulating film 108 is formed, in order to improve the bulk characteristics of the insulating film 108 and to improve the interface characteristics between the semiconductor layers 107n, 107p, and 107g and the insulating film 108, 500 to 500 under an inert gas atmosphere. Annealing may be performed at a temperature of 700 ° C. for several minutes to several hours. The relative dielectric constant of the silicon oxide film 109a thus obtained is about 3.9, and the relative dielectric constant of the silicon nitride film 109b is about 6.8. Therefore, although the total thickness of the laminated insulating film 108 is 100 nm, the electrical thickness estimated from the capacitance is 0.7 to 0.8 times that in the case of a single layer of silicon oxide film. The characteristics can be substantially improved.

  Next, a refractory metal is deposited by sputtering to form a conductive film, which is patterned to form gate electrodes 110n, 110p, and 110g as shown in FIG. As a refractory metal, an element selected from the group consisting of tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the element as a main component, or an alloy combining the elements (Typically, a Mo—W alloy or a Mo—Ta alloy) can be used. Alternatively, tungsten silicide, titanium silicide, or molybdenum silicide may be used. In the present embodiment, tungsten (W) is used as the refractory metal, and the gate electrodes 110n, 110p, and 110g having a thickness of 300 to 600 nm, for example, 450 nm are formed. At this time, in order to reduce the resistance of these gate electrodes, it is preferable to reduce the impurity concentration in the gate electrodes. In particular, by reducing the oxygen concentration to 30 ppm or less, the specific resistance value of the gate electrode is suppressed to 20 μΩcm or less. be able to.

The patterning of the metal film can be performed using an ICP (Inductively Coupled Plasma) etching method. Specifically, CF 4 , Cl 2, and O 2 are used as etching gases, the respective gas flow ratios are adjusted to 25/25/10 (sccm), and 500 W is applied to the coil-type electrode at a pressure of 1 Pa. Etching is performed by generating plasma by applying power of RF (13.56 MHz). Further, 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied.

  In the present embodiment, the gate electrode 110g of the pixel TFT has a dual gate structure in which two TFTs are connected in series for the purpose of reducing a leakage current at the time of TFT off operation. Two gate electrodes 110g are formed on (semiconductor layer) 107g. The gate structure of the pixel TFT may be a triple gate structure or a quad gate structure in which the number of gate electrodes (the number of TFTs connected in series) is further increased in addition to the dual gate structure.

Next, as shown in FIG. 4A, a low concentration impurity (phosphorus) 111 is implanted into the semiconductor layers 107n, 107p, and 107g by ion doping using the gate electrodes 110n, 110p, and 110g as a mask. At this time, phosphine (PH 3 ) is used as a doping gas, the acceleration voltage is 40 to 100 kV, for example 80 kV, and the dose amount is 1 × 10 12 to 1 × 10 14 cm −2 , for example 1 × 10 13 cm −2 . To do. As a result, phosphorus 111 is implanted at a low concentration into the regions 112n, 112p, and 112g of the semiconductor layers 107n, 107p, and 107g that are not covered with the gate electrodes 110n, 110p, and 110g. Of the semiconductor layers 107n, 107p, and 107g, the regions covered with the gate electrodes 110n, 110p, and 110g and not implanted with phosphorus are the driver unit N-channel TFT and P-channel TFT, respectively. And the channel regions 113n, 113p, and 113g in the pixel TFT.

  Subsequently, as shown in FIG. 4B, a photoresist is used so as to cover the gate electrodes 110n and 110g in the subsequent N-channel TFT and the pixel TFT and to expose the outer edge portions of the semiconductor layers 107n and 107g. Masks 114n and 114g are provided. At this time, since a mask is not formed above the semiconductor layer 107p in the subsequent P-channel TFT, the entire region where the P-channel TFT is to be formed is exposed.

In this state, using the resist masks 114n and 114g and the gate electrode 110p in the later P-channel TFT as a mask, an impurity (boron) 115 imparting p-type is implanted into each semiconductor layer by an ion doping method. Diborane (B 2 H 6 ) is used as a doping gas, the acceleration voltage is set to 40 kV to 100 kV, for example, 75 kV, and the dose amount is 1 × 10 15 to 1 × 10 16 cm −2 , for example, 5 × 10 16 cm −2 . To do. Thus, boron is implanted at a high concentration into the regions (outer edge portions) 116n and 116g exposed from the masks 114n and 114g in the semiconductor layers 107n and 107g in the subsequent N-channel TFT and pixel TFT. Further, boron 115 is implanted at a high concentration into a region (a region other than the channel region 113p) 116p that is not covered with the gate electrode 110p in the semiconductor layer 107p in the subsequent P-channel TFT. In the region 116p, the n-type impurity phosphorus implanted at a low concentration in the previous step is inverted by the high-concentration p-type impurity (boron), so that the conductivity type becomes p-type. At this time, the concentration in the film of the p-type impurity element (boron) 115 in the regions 116n and 116g and the region 116p is 1 × 10 19 to 3 × 10 21 / cm 3 .

Next, as shown in FIG. 4C, using the resist masks 114n and 114g used in the p-type impurity element (boron) doping step and the gate electrode 110p of the P-channel TFT as a mask, the stacked insulating film 108 is formed. Of these, only the upper layer (silicon nitride film) 109b is etched. In this embodiment, this etching process is performed by the ICP etching method. Specifically, CF4 and O2 are used as etching gases, and the respective gas flow ratios are set to 20/40 (sccm), and 500 W RF (13.56 MHz) is applied to a coil-type electrode at a pressure of 1 Pa. Apply power and apply a substantially negative self-bias voltage. Under such conditions, the etching selectivity of the silicon nitride film 109b to the silicon oxide film 109a is about 5 to 10, and the etching can be stopped with good control by the lower silicon oxide film 109a. Further, although the exposed gate electrode 110p of the P-channel TFT may be slightly etched, the etching amount is at a level that does not cause a problem. This etching (selective etching of insulating film) step can be performed by a normal plasma etching method, an RIE (reactive ion etching) method, or the like other than the ICP etching method, and SF 6 or the like as an etching gas. Other fluorocarbon gases may be used.

  As a result of the selective etching of the silicon nitride film 109b as described above, second insulating films 117n, 117p, and 117g, which are upper layers of the gate insulating film in each TFT, are obtained from the silicon nitride film 109b. In this etching process, the underlying silicon oxide film 109a functions as an etch stopper for etching, and therefore remains almost unetched. As a result, gate insulating films 108n, 108p and 108g composed of the second insulating films 117n, 117p and 117g and the silicon oxide film (first insulating film) 109a are obtained.

  Thereafter, resist masks 114n and 114g are removed. Removal of the resist masks 114n and 114p may be performed using oxygen plasma ashing. In that case, it is advantageous to remove the resist masks 114n and 114p in the same etching apparatus in succession to the selective etching process because the manufacturing process can be simplified and the tact time can be shortened.

  Subsequently, as shown in FIG. 5A, new doping masks 118g and 118p are formed using a photoresist. The doping mask 118g is provided so as to cover the gate electrode 110g in the semiconductor layer 107g of the pixel TFT, and the doping mask 118p covers the gate electrode 110p in the P-channel TFT. Provided to expose the outer edge. A mask is not formed above the semiconductor layer 107n in the N-channel TFT.

Thereafter, n-type impurities (phosphorus) 119 are implanted into the respective semiconductor layers 107n, 107p and 107g by ion doping using the doping masks 118p and 118g and the gate electrode 110n of the N-channel TFT as a mask. Here, phosphine (PH 3 ) is used as the doping gas, the acceleration voltage is 40 to 80 kV, for example 60 kV, and the dose amount is 1 × 10 15 to 2 × 10 16 cm −2 , for example 6 × 10 15 cm −2 . To do. By this doping step, phosphorus is implanted at a high concentration into the regions exposed from the gate electrode 110n and the resist masks 118p and 118g in the semiconductor layers 107n, 107p, and 107g, so that a high concentration n-type impurity region is formed.

  In the n-type impurity doping process, the region 120 of the pixel TFT semiconductor layer 107g that is not covered with the gate electrode 110g but is covered with the resist mask 118g and not doped with high-concentration phosphorus is reduced in concentration. Phosphorus is implanted to form an LDD region in the pixel TFT. If the pixel TFT has an LDD region, it is advantageous because leakage current can be suppressed particularly during the off operation. Note that, as described above, the region covered with the gate electrode 110g in the semiconductor layer 107g of the pixel TFT is the channel region 113g. In addition, in the semiconductor layer 107g, a region covered with the upper layer (second insulating film) 117g of the gate insulating film becomes a source and drain region 122g, which is covered with the first insulating film 109a, but is covered with the second insulating film 117g. The uncovered region becomes a gettering region 123g as a result of doping with a high concentration of boron in the doping step.

  Similarly, in the semiconductor layer 107n of the driver N-channel TFT, the region covered with the gate electrode 110n and not doped with high-concentration phosphorus becomes the channel region 113n as described above. Further, the region covered with the second insulating film 117g becomes the source and drain regions 122n, and the region covered with the first insulating film 109a but not covered with the second insulating film 117g has a high concentration in the doping step. The result of doping with boron is a gettering region 123n.

  Further, in the P-channel TFT semiconductor layer 107p, a region 121 which is not covered with the gate electrode 110p but covered with the doping mask 118p and is not doped with high-concentration phosphorus is shown in FIG. 4B. Since boron is implanted at a high concentration in the type impurity doping step, it remains as a p-type impurity region and becomes the source and drain regions of the P-channel TFT. Further, a region of the semiconductor layer 107p that is not covered with the doping mask 118p becomes a gettering region 123p as a result of the high concentration phosphorus implantation in the n-type impurity doping step.

  As described above, in the step of doping high concentration phosphorus, phosphorus is not applied to the regions of the semiconductor layers 107n, 107p, and 107g that are not covered with the gate electrode 110n of the N-channel TFT and the masks 118p and 118g. Doping is performed through the gate insulating films 108n, 108p and 108g. At this time, the gate insulating film is doped through two layers of the second insulating film (silicon nitride film) and the first insulating film (silicon oxide film), or the first insulating film (oxidized film) of the gate insulating film. The state of phosphorus doping varies greatly depending on whether it is doped only through the silicon film.

  The respective doping states will be described in detail below with reference to the phosphorus doping profile shown in FIG. In FIG. 12, the horizontal axis represents the doping depth and the vertical axis represents the phosphorus concentration. In the above doping step, the doping of phosphorus into the regions 122n and 122g is performed through two layers of insulating films having a total thickness of 100 nm. Therefore, the phosphorus concentration doped into the regions 122n and 122g is as shown in FIG. It becomes equal to the phosphorus concentration when the depth is 1000 to 1500 mm (100 to 150 nm). In contrast, the doping of phosphorus into the regions 123n, 123p, and 123g is performed only through the gate insulating film lower layer (first insulating film) 109a having a thickness of 50 nm, so that the regions 123n, 123p, and 123g are doped. The phosphorus concentration is equal to the phosphorus concentration when the depth in FIG. 12 is 500 to 1000 mm (50 to 100 nm). Therefore, a large concentration difference occurs between the phosphorus concentrations in the regions 122n and 122g and the phosphorus concentrations in the regions 123n, 123p, and 123g. In this embodiment, the actual amount of phosphorus doped in the regions 123n, 123p, and 123g covered only with the first insulating film 109a is the region 122n covered with the first insulating film 109a and the second insulating films 117n and 117g. More than 5 times the actual amount of phosphorus doped into 122 g. In addition, since the upper gate insulating film is thin in the regions 123n, 123p, and 123g covered only with the first insulating film 109a, the regions 122n covered with the first insulating film 109a and the second insulating films 117n and 117g, Compared to 122 g, phosphorus ions are implanted into the semiconductor layer at a relatively high acceleration voltage. Therefore, the impact energy of each ion is large, the crystallinity is broken, and it becomes easier to become amorphous. On the other hand, in the regions 122n and 122g, the impact energy of ions at the time of implantation is relieved by the thick gate insulating film, so that the amorphous state hardly occurs and the crystalline state is maintained.

In this manner, a region where gettering capability is required and a region where low resistance is required as the source and drain regions can be easily created in a state suitable for each purpose. The n-type impurity element (phosphorus) concentration in the film in the obtained gettering regions 123n, 123p, 123g is 1 × 10 19 to 3 × 10 21 / cm 3 . Further, the n-type impurity element (phosphorus) concentration in the LDD region 120 of the pixel TFT is 1 × 10 17 to 1 × 10 19 / cm 3 . When the phosphorus concentration is in the above range, an excellent function as an LDD region can be exhibited.

  Next, after removing the doping masks 118p and 118g used in the n-type impurity doping step, a second heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere. By this heat treatment, as shown in FIG. 5B, a catalytic element (nickel) present in the active region of each semiconductor layer 107n, 107p, 107g is formed outside the source and drain regions 122n, 122p, 122g. The gettering regions 123n, 123p, and 123g are moved.

  Since the gettering regions 123n, 123p, and 123g contain phosphorus and boron at a high concentration, the solid solubility in nickel is high, and segregation sites for nickel are easily formed. Further, since the upper gate insulating film is thinned, it becomes amorphous during the above-described doping, and the free energy for nickel is reduced. For this reason, crystal defects and dangling bonds (dangling bonds) also function as nickel segregation sites. As a result, the gettering effects in the gettering regions 123n, 123p, and 123g are synergistically enhanced.

  Therefore, by the second heat treatment, nickel existing in the channel region 113n and the source and drain regions 122n in the semiconductor layer 107n of the N-channel TFT is transferred from the channel region 113n to the source and drain regions 112n and the gettering region. 123n can be moved in the direction indicated by the arrow 124 in FIG. Similarly, in the semiconductor layer 107g of the pixel TFT, nickel existing in the channel region 113g, the LDD region 120, and the source and drain region 122g is changed from the channel region 113g to the LDD region 120, and further the source and drain regions 112g, and The gettering region 123g can be moved in the direction indicated by the arrow 124. The source and drain regions 122n and 122g doped with only phosphorus also have a gettering effect, but the gettering ability of the gettering regions 123n and 123g doped with a larger amount of phosphorus to become amorphous and also doped with boron Since it is overwhelmingly higher, nickel is collected in the gettering regions 123n and 123g. Further, also in the semiconductor layer 107p of the P-channel TFT, the gettering region 123p formed outside the source and drain regions has a very high gettering capability like the gettering region 123n of the N-channel TFT. Nickel existing in the channel region 113p and the source and drain regions 121 is moved from the channel region 113p to the source / drain regions 121 and the gettering region 123p in the direction indicated by the arrow 124.

Since the catalytic element moves to the gettering regions 123n, 123p, and 123g by the second heat treatment step, that is, the gettering step, the concentration of the catalytic element in these gettering regions is, for example, 5 × 10 18 / cm. 3 or more.

  A general heating furnace may be used for the second heat treatment, but RTA (Rapid Thermal annealing) is preferably used. In particular, an RTA of a system in which a high temperature inert gas is sprayed on the substrate surface and the temperature is raised and lowered instantaneously is preferably used. Specifically, the holding temperature is 600 to 750 ° C. and the holding time is about 30 seconds to 20 minutes. It is preferable that both the temperature increase rate and the temperature decrease rate are set to 100 ° C./min or more.

  In this heat treatment step, the n-type impurity (phosphorus) doped in the source and drain regions 122n and 122g and the LDD region 120 is activated, and the source and drain regions 121 of the P-channel TFT are doped. The p-type impurity (boron) is also activated. As a result, the sheet resistance value of the source and drain regions 122n and 122g in the N-channel TFT and the pixel TFT is about 0.5 to 1 kΩ / □, and the sheet resistance value of the LDD region 120 of the pixel TFT is 50 to 100 kΩ / It becomes □. The sheet resistance value of the source and drain regions 121 of the P-channel TFT is about 1 to 1.5 kΩ / □. However, in the gettering regions 123n, 123p, and 123g, since the crystals are almost amorphous, the crystal is not recovered by the heat treatment for gettering, and the amorphous component is held as it is. Although the resistance of these gettering regions is extremely high, it is formed as a region different from the source region or the drain region so as not to hinder the movement of carriers as a TFT. The characteristic is not deteriorated.

  After the second heating step, by measuring the ratio Pa / Pc between the amorphous Si TO phonon peak Pa and the crystalline Si TO phonon peak Pc of the Raman spectrum in each region of the semiconductor layer by laser Raman spectroscopy, It can be seen that the ratio Pa / Pc in the gettering region is larger than the ratio Pa / Pc in the channel region and the source / drain regions. This measurement can also be performed from the back side of the substrate 101 when a transparent glass substrate or the like is used as the substrate 101. After the second heat treatment step, processing at a temperature higher than this cannot be performed, so the Pa / Pc relationship in each region is maintained even after the TFT is completed.

  Through the above steps, the remaining catalyst element can be gettered at the channel formation region of the TFT semiconductor layer or at the junction between the channel formation region and the source region or drain region, and leakage current due to segregation of the catalyst element can be reduced. Occurrence can be suppressed. Further, since the gettering region is formed in a region different from the source region or the drain region in the active region of the TFT, the resistance of the source region or the drain region of the TFT increases due to the amorphousization of the gettering region. Can solve the problem.

Next, as illustrated in FIG. 5C, an interlayer insulating film 126, electrodes, and wirings 127 are formed. The interlayer insulating film 126 can be formed using a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film. The thickness of the interlayer insulating film 126 is preferably 400 to 1500 nm (typically 500 to 1000 nm). In this embodiment, an interlayer insulating film 126 having a two-layer structure in which a silicon nitride film 125a having a thickness of 200 nm and a silicon oxide film 125b having a thickness of 700 nm are stacked in this order is formed. Here, after the silicon nitride film 125a is formed using SiH 4 and NH 3 as source gases by plasma CVD, the silicon oxide film 125b is continuously formed using TEOS and O 2 as raw materials. The material and configuration of the interlayer insulating film 126 are not limited to the above, and may be formed using an insulating film containing other silicon, or may have a single layer or a stacked structure. Alternatively, an organic insulating film such as acrylic may be provided over an insulating film containing silicon.

  After the formation of the interlayer insulating film 126, it is preferable to perform a process of hydrogenating the semiconductor layers 107n, 107p, and 107g by performing a heat treatment at a temperature of 300 to 500 ° C. for about 30 minutes to 4 hours. In the hydrogenation process, hydrogen atoms are supplied to the interface between the active region of the semiconductor layer and the gate insulating film, and the dangling bonds that degrade the TFT characteristics are terminated to be deactivated. In this embodiment, heat treatment is performed for 1 hour at a temperature of 410 ° C. in a nitrogen atmosphere containing about 3% hydrogen. If the amount of hydrogen contained in the interlayer insulating film 126 (especially the silicon nitride film 125) is sufficient, the effect of hydrogenation can be obtained even if heat treatment is performed in a nitrogen atmosphere. Alternatively, plasma hydrogenation may be performed using hydrogen excited by plasma.

  The electrode and wiring 127 of each TFT can be formed by forming a contact hole in the interlayer insulating film 126 and then depositing a metal material inside the contact hole and on the interlayer insulating film 126. In this embodiment, the electrodes and the wiring 127 are formed by a two-layer film made of a titanium nitride film and an aluminum film. The titanium nitride film is provided as a barrier film for preventing aluminum from diffusing into the semiconductor layer. At this time, the drain electrode of the pixel TFT is connected to a pixel electrode made of a transparent conductive film such as ITO. The other electrode (source electrode) constitutes a source bus line, and a video signal is supplied through this source bus line, and a necessary charge is written to the pixel electrode based on the gate signal of the gate bus line.

  Finally, when annealing is performed at a temperature of 350 ° C. for 1 hour, an N-channel thin film transistor 128, a P-channel thin film transistor 129, and a pixel thin film transistor 130 are completed as shown in FIG. Further, if necessary, a contact hole may be provided also on the gate electrodes 110n and 110p, and a desired electrode and the gate electrodes 110n and 110p may be connected through the wiring 127. For the purpose of protecting the TFT, a protective film made of a silicon nitride film or the like may be provided on each TFT.

The characteristics of each TFT manufactured by the above method will be described. The N-channel thin film transistor 128 has a high field effect mobility of 250 to 300 cm 2 / Vs, and the P-channel thin film transistor 129 has a high field effect mobility of 120 to 150 cm 2 / Vs. The threshold voltage of the N-channel thin film transistor 128 is about 1V, and the threshold voltage of the P-channel thin film transistor 129 is about −1.5V. Thus, these TFTs exhibit very good characteristics. On the other hand, in the pixel thin film transistor 130, there is no abnormal increase in leakage current at the time of TFT off operation, which is frequently seen in the conventional example. A very low leakage current value of several pA or less is stably shown. This value is completely different from that of a conventional TFT manufactured without using a catalyst element, and the manufacturing yield can be greatly improved. Further, even when a durability test by repeated measurement or bias or temperature stress is performed, the characteristics are hardly deteriorated, and the reliability is very high as compared with the conventional TFT.

  When an inverter chain, a ring oscillator, or the like on a driver is formed using a CMOS structure circuit in which the N-channel type thin film transistor 134 and the P-channel type thin film transistor 135 which are manufactured by the above method are complementarily formed, a signal is generated more than a conventional CMOS structure circuit. Low delay, high reliability, and stable circuit characteristics. In addition, when each TFT manufactured by the above method is applied to a liquid crystal display panel, display unevenness is smaller than that of a liquid crystal display panel using a TFT manufactured by a conventional method, pixel defects due to TFT leakage are extremely small, and a high contrast ratio is high. Is obtained.

(Second Embodiment)
A second embodiment according to the present invention will be described with reference to FIGS. In this embodiment, a circuit having a CMOS structure in which an N-channel TFT and a P-channel TFT are configured to be complementary is formed on a glass substrate.

  As shown in FIG. 6A, the first base film 202 made of a silicon oxynitride film and the silicon oxide film are formed on the surface of the glass substrate 201 on which the TFT is formed, by the same method as in the first embodiment. A second base film 203 is sequentially formed, and then an a-Si film 204 having a thickness of, for example, 50 nm is formed. Next, a small amount of nickel 205 is added to the surface of the a-Si film 204 by the same method as in the first embodiment.

  Subsequently, a first heat treatment is performed, and the a-Si film 204 is crystallized in a solid state using the nickel 205 added to the a-Si film 204 as a catalyst to obtain a crystalline silicon film 204a. Then, as shown in FIG. 6B, the crystallinity of the crystalline silicon film 204a is improved by irradiating the laser beam 206 by the same method as in the first embodiment, and a higher quality crystalline material is obtained. A silicon film 204b is obtained.

  Thereafter, unnecessary portions of the crystalline silicon film 204b are removed, and element isolation is performed. By this step, as shown in FIG. 6C, island-like crystalline silicon layers (semiconductor layers) 207n and 207p, which will be semiconductor layers of N-channel TFTs and P-channel TFTs later, are formed. Here, p-type is applied to the entire surface of the semiconductor layers 207n and 207p of the N-channel TFT and the P-channel TFT or only to the semiconductor layer 207n of the N-channel TFT in order to control the threshold voltage. An impurity element (such as B) may be added at a low concentration.

  Next, an insulating film 209a and an insulating film 209b are formed in this order so as to cover the semiconductor layers 207n and 207p of the TFT in the same manner as in the first embodiment described above, and a laminated insulating film 208 having a two-layer structure is formed. To do. Here, a silicon oxide film with a thickness of 50 nm is used as the insulating film 209a, and a silicon nitride film with a thickness of 50 nm is used as the insulating film 209b. Therefore, the total thickness of the laminated insulating film 208 in this embodiment is 100 nm. Note that the thickness of each insulating film included in the stacked insulating film 208 is not limited to the above, and can be determined as appropriate.

  Subsequently, a refractory metal is deposited by a sputtering method to form a conductive film by a method similar to the method described with reference to FIG. Gate electrodes 210n and 210p as shown are formed. In the present embodiment, tungsten (W) is used as the refractory metal, and the gate electrodes 210n and 210p having a thickness of 300 to 600 nm, for example, 450 nm are formed.

  Next, an n-type impurity (phosphorus) 211 is implanted into the semiconductor layers 207n and 207p at a low concentration by ion doping using the gate electrodes 210n and 210p as a mask. Thereby, phosphorus 211 is implanted at a low concentration into regions 212n and 212p of semiconductor layers 207n and 207p that are not covered with gate electrodes 210n and 210p. The regions of the semiconductor layers 207n and 207p that are covered with the gate electrode and are not implanted with phosphorus at a low concentration are channel regions 213n and 213p in the later N-channel TFT and P-channel TFT.

  Next, as shown in FIG. 6E, a resist mask 214 made of a photoresist is formed so as to cover the gate electrode 210n of the N-channel TFT and to expose the outer edge portion of the semiconductor layer 207n. At this time, no mask is provided above the semiconductor layer 207p of the P-channel TFT, and the entire TFT is exposed. Thereafter, in the same manner as described with reference to FIG. 4C, the resist mask 214n and the gate electrode 210p of the P-channel TFT are masked to form an upper silicon nitride film in the stacked insulating film 208. Only 209b is etched. As a result, second insulating films 217n and 217p, which are upper layers of the gate insulating film in each TFT, are obtained from the silicon nitride film 209b. In this etching process, the lower silicon oxide film 209a functions as an etch stopper for etching, and therefore remains almost unetched. Thereby, gate insulating films 208n and 208p composed of the second insulating films 217n and 217p and the silicon oxide film (first insulating film) 209a are obtained.

Subsequently, as shown in FIG. 7A, using the resist mask 214 used in the etching step as it is, impurities (boron) 215 imparting p-type to each of the semiconductor layers 207n and 207p are ion-doped. inject. Boron doping uses diborane (B 2 H 6 ) as a doping gas, an acceleration voltage of 30 kV to 70 kV, for example 55 kV, and a dose of 1 × 10 15 to 1 × 10 16 cm −2 , for example 5 × 10 16. Performed under conditions of cm −2 . In this embodiment, since the silicon nitride film 209b is etched before this doping step, boron is doped through only the silicon oxide film 209a in this doping step. Therefore, the accelerating voltage in this step is set lower than the accelerating voltage in the doping step (FIG. 4B) of the first embodiment in which doping is performed through two layers of the silicon nitride film and the silicon oxide film.

  By the p-type impurity doping step, boron is implanted at a high concentration into the region 216n exposed from the mask 214 in the semiconductor layer 207n of the N-channel TFT, and the gate electrode 210p in the semiconductor layer 207p of the P-channel TFT. Boron 215 is implanted at a high concentration into the region 216p other than the covered channel region 213p. As a result, in the region 216p, the high-concentration p-type impurity (boron) inverts the n-type impurity phosphorus implanted at a low concentration in the previous step, so that the conductivity type becomes p-type.

  Next, after removing the resist mask 214, new doping masks 218n and 218p are formed of photoresist as shown in FIG. The doping mask 218n is provided so as to greatly cover the gate electrode 210n of the N-channel TFT, and the doping mask 218p further covers the gate electrode 210p of the P-channel TFT more than once, and the outer edge of the semiconductor layer 207p. It is provided so that a part may be exposed.

  Thereafter, n-type impurities (phosphorus) 219 are implanted into the semiconductor layers 207n and 207p by ion doping using the resist masks 218n and 218p as masks. By this n-type impurity doping step, phosphorus is implanted at a high concentration into the regions exposed from the resist masks 218n and 218p in the semiconductor layers 207n and 207p, thereby forming high-concentration n-type impurity regions.

  By the n-type impurity doping step, the region 220 of the N-channel TFT semiconductor layer 207n that is not covered with the gate electrode 210n but is covered with the resist mask 218n and is not doped with high-concentration phosphorus is low. It becomes an LDD region in which phosphorus is implanted at a concentration. When the LDD region is formed, it is possible to suppress a leakage current particularly during an off operation and to improve reliability against hot carrier deterioration and the like. Further, as described above, the region covered with the gate electrode 210n in the semiconductor layer 207n becomes the channel region 213n. Further, a region of the semiconductor layer 207n that is not covered with the resist mask 218n but is covered with the gate insulating film upper layer (first insulating film) 209a becomes a source and drain region 222, and an outer edge portion (first insulating layer) of the semiconductor layer 207n. The region not covered with the film 209a is a gettering region 223n doped with high-concentration boron.

  Similarly, in the P-channel TFT semiconductor layer 207p, a region 221 that is not covered with the gate electrode 210p but covered with the resist mask 218p and not doped with high-concentration phosphorus is a region into which only boron is implanted. The rest are the source and drain regions of the P-channel TFT. Further, in the semiconductor layer 207p, a region 223p exposed from the resist mask 218p and implanted with phosphorus at a high concentration becomes a gettering region.

  As described above, in the step of doping high-concentration phosphorus, phosphorus is doped through the gate insulating films 208n and 208p into regions of the semiconductor layers 207n and 207p that are not covered with the masks 218p and 218g. At this time, as described in the first embodiment, the gate insulating film is doped through two layers of the second insulating film (silicon nitride film) and the first insulating film (silicon oxide film), or the gate. Depending on whether the insulating film is doped only through the first insulating film (silicon oxide film), it is possible to form regions having different impurity concentrations and the like by the same doping process, depending on the doping state of phosphorus. become.

  Next, after removing the doping masks 218n and 218p, second heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere. In this heat treatment step, as shown in FIG. 7C, the catalytic element (nickel) present in the active regions of the respective semiconductor layers 207n and 207p is converted into getters formed outside the source and drain regions 222 and 221. It can be moved to the ring regions 223n and 223p.

  In the gettering regions 223n and 223p, phosphorus and boron are contained at a high concentration, so that the solid solubility with respect to nickel is high, and segregation sites with respect to nickel are easily formed. Further, since the upper gate insulating film is thinned, it becomes amorphous during the above-described doping, and the free energy for nickel is reduced. For this reason, crystal defects and dangling bonds (dangling bonds) also function as nickel segregation sites. As a result, the gettering effect in the gettering regions 223n and 223p is synergistically enhanced.

  Therefore, nickel existing in the channel region 213n and the source and drain regions 222n in the semiconductor layer 207n of the N-channel TFT is transferred from the channel region 213n to the source and drain regions 212n and the gettering by the second heat treatment. The region 223n can be moved in a direction indicated by an arrow 224 in FIG. Similarly, also in the semiconductor layer 207p of the P-channel TFT, the gettering region 223p formed outside the source and drain regions has a very high gettering capability like the gettering region 223n of the N-channel TFT. Then, nickel existing in the channel region 213p and the source and drain regions 221 is moved in the direction indicated by the arrow 224 from the channel region 213p to the source and drain regions 221 and the gettering region 223p.

  This heat treatment process activates the n-type impurity (phosphorus) doped in the source and drain regions 222 and the LDD region 220, and p-type doping in the source and drain regions 221 of the P-channel TFT. Type impurities (boron) are also activated. However, in the gettering regions 223n and 223p, since the crystal is almost amorphous, the crystal is not recovered by the heat treatment for gettering, and the amorphous component is held as it is. Although the resistance of these gettering regions is extremely high, it is formed as a region different from the source region or the drain region so as not to hinder the movement of carriers as a TFT. The characteristic is not deteriorated.

  Through the above steps, the catalyst element remaining in the channel formation region of the TFT semiconductor layer and the junction between the channel formation region and the source region or drain region can be gettered, and the generation of leakage current due to segregation of the catalyst element is suppressed. be able to. In addition, since the gettering region is formed in a region different from the source region or the drain region in the active region of the TFT, the resistance increases in the source region or the drain region of the TFT due to the amorphousization of the gettering region. The problem can be solved.

  Next, as illustrated in FIG. 7D, an interlayer insulating film 226, electrodes, and wirings 227 are formed. The interlayer insulating film 226 can be formed using a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film. In the present embodiment, as in the first embodiment, an interlayer insulating film 226 having a two-layer structure in which a silicon nitride film 225a having a thickness of 200 nm and a silicon oxide film 225b having a thickness of 700 nm are stacked in this order is formed. .

  After forming the interlayer insulating film 226, it is preferable to perform a step of hydrogenating the semiconductor layers 207n and 207p by performing heat treatment at a temperature of 300 to 500 ° C. for about 30 minutes to 4 hours. In the hydrogenation process, hydrogen atoms are supplied to the interface between the active region of the semiconductor layer and the gate insulating film, and the dangling bonds that degrade the TFT characteristics are terminated to be deactivated. In this embodiment, heat treatment is performed for 1 hour at a temperature of 410 ° C. in a nitrogen atmosphere containing about 3% hydrogen. If the amount of hydrogen contained in the interlayer insulating film 226 (particularly the silicon nitride film 225) is sufficient, the effect of hydrogenation can be obtained even if heat treatment is performed in a nitrogen atmosphere. Alternatively, plasma hydrogenation may be performed using hydrogen excited by plasma.

  The electrode and wiring 227 of each TFT are formed by forming a contact hole in the interlayer insulating film 226 and then forming the electrode and wiring 227 with a two-layer film composed of a titanium nitride film and an aluminum film. The titanium nitride film is provided as a barrier film for preventing aluminum from diffusing into the semiconductor layer.

  Finally, when annealing is performed at a temperature of 350 ° C. for 1 hour, an N-channel thin film transistor 228 and a P-channel thin film transistor 229 are completed as shown in FIG. 7D. Further, if necessary, a contact hole may be provided also on the gate electrodes 210n and 210p, and a desired electrode and the gate electrodes 210n and 210p may be connected through the wiring 227. For the purpose of protecting the TFT, a protective film made of a silicon nitride film or the like may be provided on each TFT.

  The field effect mobility and the threshold voltage of each TFT manufactured by the above method show good characteristics similar to those of each TFT manufactured by the method of the first embodiment.

  In the first embodiment and the second embodiment, the gettering region may be disposed in a region other than the active region in the semiconductor layer. Hereinafter, an example of arrangement of gettering regions in the TFT semiconductor layer will be described with reference to plan views shown in FIGS.

  Various shapes of gettering regions can be formed in the semiconductor layers of the N-channel TFT, the P-channel TFT, and the pixel TFT in the first and second embodiments. Further, the areas of the gettering region in the semiconductor layer of the N-channel TFT and the gettering region in the semiconductor layer of the P-channel TFT are made approximately equal, and the distance from the gettering region to the channel region is made approximately equal. The efficiency of gettering with respect to the catalytic element of the channel type TFT and the P channel type TFT can be more reliably aligned.

  Note that to make the area of the gettering region in the semiconductor layer of the N-channel TFT and the gettering region in the semiconductor layer of the P-channel TFT approximately equal to each other, the width of the semiconductor layer (channel region) in each TFT is W, When the area S of the gettering region is taken, the ratio S / W of the width W of the semiconductor layer (channel region) and the area S of the gettering region is made substantially equal in the N-channel TFT and the P-channel TFT.

  8A to 8D are plan views illustrating the configuration of the semiconductor layer 30 and the gate electrode 35. In these drawings, the same components are denoted by the same reference numerals. The semiconductor layer 30 has a channel formation region formed in a region overlapping with the gate electrode 35, source and drain regions 31 and 32 on both sides of the channel formation region, and a gettering region. The source and drain regions 31 and 32 have contact portions 36 and 37, respectively. In this specification, a portion where a wiring for electrically connecting each TFT is connected to a semiconductor layer is referred to as a contact portion.

  In the structure shown in FIG. 8A, the gettering regions 33a and 34a are arranged in a rectangular shape extending in a direction parallel to the gate electrode 35 at a position away from the channel formation region (outer edge portion of the semiconductor layer). That is, the long side of the rectangle is parallel to the gate electrode. In addition, the rectangular corner portion is arranged so as to hang over the corner portion of the semiconductor layer 30.

  In the structure shown in FIG. 8B, the gettering regions 33 b and 34 b are rectangular shapes extending in a direction perpendicular to the gate electrode 35 at positions away from the channel formation region below the gate electrode 35 (outer edge portion of the semiconductor layer). Arranged. In addition, the rectangular corner portion is arranged so as to hang over the corner portion of the semiconductor layer 30.

  In the configuration shown in FIG. 8C, the gettering regions 33 c and 34 c are rectangular shapes extending in a direction parallel to the gate electrode 35 at positions away from the channel formation region below the gate electrode 35 (outer edge portion of the semiconductor layer). And a complicated shape formed by combining the gate electrode 35 and a rectangle extending in the vertical direction. The corner portion of this shape is arranged so as to hang over the corner portion of the semiconductor layer 30. In this case, since the area of the gettering region can be made larger than in the configuration of FIG. 8A or FIG. 8B, the gettering efficiency for the catalytic element can be further increased.

  In any of the configurations shown in FIGS. 8A to 8C, the gettering region is disposed at a position where the current flowing between the contact portions formed in the source region or the drain regions 31 and 32 is not hindered. ing.

  For example, the gettering regions 33 a and 34 a shown in FIG. 8A do not hinder current flowing between the contact portion 36 formed in the source region 31 and the contact portion 37 formed in the drain region 32. Placed in position. Similarly, the gettering regions 33b and 34b shown in FIG. 8B do not hinder the current flowing between the contact portion 36 connected to the source region 31 and the contact portion 37 formed in the drain region 32. Placed in position. Further, the gettering regions 33c and 34c shown in FIG. 8C do not hinder the current flowing between the contact portion 36 formed in the source region 31 and the contact portion 37 formed in the drain region 32. Is arranged.

  The configuration shown in FIG. 8D is basically the same as the configuration shown in FIG. 8C, but differs in that the gettering regions 33d and 34d are applied to part of the contact portions 36 and 37. Yes. Thereby, the area of the gettering regions 33d and 34d can be further expanded, and the gettering efficiency of the gettering regions 33d and 34d can be improved. Basically, there is no problem even if the gettering regions 33d and 34d cover a part of the contact portions 36 and 37, but the area where the gettering region and the contact portion overlap is at most half or less of the contact portions 36 and 37. It is necessary to pay attention to. Accordingly, the design distance between the contact portions 36 and 37 and the gettering regions 33d and 34d is set to a suitable design distance in consideration of the alignment accuracy of the exposure apparatus used in the photolithography process corresponding to each region formation. It is necessary to decide.

  In addition, the structure of this invention is not limited to the structure shown to FIG. 8 (A)-(D). The gettering region can be arranged at any position as long as it does not affect (does not inhibit) the current flowing between the source region and the drain region.

  FIG. 9A illustrates the configuration of the semiconductor layer 30 and the gate electrode 35 in the case where a plurality of gate electrodes 35 cross the semiconductor layer 30 and a plurality of channel formation regions are formed in the semiconductor layer 30. FIG. The semiconductor layer 30 has a plurality of channel forming regions formed under the gate electrode 35, source and drain regions 31, 32 on both sides thereof, and gettering regions 33e, 34e, 38e. The gettering regions 33e and 34e are arranged on the outer edge portion of the semiconductor layer 30 and have the same shape as the gettering regions 33a to 33d and 34a to 34d shown in FIGS. Yes. Although the gettering regions 33e and 34e may cover a part of the contact portions 36 and 37, basically, the area where the gettering region and the contact portion overlap is at most less than half the area of the contact portions 36 and 37. Keep in mind that on the other hand. The gettering region 38e is formed between the source and region 31 (or drain region 32) located between the plurality of gate electrodes 35. The gettering region 38e is also arranged so as not to hinder the flow of current. Preferably, they are arranged so as not to overlap with contact portions 39 formed between gate electrodes 35.

  FIG. 9B is also a plan view showing a configuration in the case where a plurality of gate electrodes 35 cross the semiconductor layer 30 and a plurality of channel formation regions are formed in the semiconductor layer 30. In the structure shown in FIG. 9B, two TFTs are connected in series while sharing the semiconductor layer 30, and the connecting portion does not have a contact portion. That is, there is no need to take out an electrical signal from the connecting portion. The TFT having such a configuration is actually used in a circuit such as a clocked inverter or a latch circuit. The semiconductor layer 30 has a plurality of channel formation regions formed below the gate electrode 35, source and drain regions 31, 32 on both sides thereof, and gettering regions 33f, 34f, 38f. The gettering regions 33f and 34f are arranged on the outer edge portion of the semiconductor layer 30 and have the same shape as the gettering regions 33a to 33d and 34a to 34d shown in FIGS. Yes. On the other hand, the gettering region 38f is disposed between the source region 31 (or the drain region 32) formed between the plurality of gate electrodes 35. The gettering region 38f is arranged at a position where the current flowing from the contact portion 36 to the contact portion 37 is not hindered at least in the connecting portion.

  The shape of the TFT semiconductor layer 30 differs depending on the amount of current required for the TFT. As shown in FIGS. 8 and 9, the width of the channel region is narrower than that of the source and drain regions, and the wedge shape is obtained when the source and drain regions and the channel region have the same width. In either case, the present invention can be similarly applied.

In addition, no matter which shape of the gettering region is applied, the catalytic element moves to the gettering region due to the heat treatment for gettering. The concentration is typically 5 × 10 18 / cm 3 or more.

(Third embodiment)
A third embodiment of the present invention will be described with reference to FIG. In this embodiment, the amorphous semiconductor film is crystallized by a method different from the method described in the first and second embodiments.

  First, as in the first and second embodiments, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like is formed on a substrate (a glass substrate in this embodiment) 401 in order to prevent impurity diffusion from the substrate. Forms a basement film. In this embodiment, a silicon nitride film is formed as the lower first base film 402, and a silicon oxide film is formed thereon as the second base film 403. Next, an amorphous semiconductor film (a-Si film) 404 having a thickness of 30 to 80 nm is formed by the same method as in the first and second embodiments. The base insulating films 402 and 403 and the a-Si film 404 may be continuously formed without being released to the atmosphere.

  Next, a mask insulating film (thickness: about 200 nm) 405 formed from a silicon oxide film is formed. As shown in FIG. 10A, the mask insulating film 405 has an opening 400 for adding a catalytic element to the a-Si film 404.

  Next, as shown in FIG. 10B, an aqueous solution (nickel acetate aqueous solution) containing 100 ppm of the catalytic element (nickel in this embodiment) in terms of weight is applied by a spin coating method to form the catalytic element layer 406. To do. At this time, in the opening 400 of the mask insulating film 405, the catalytic element layer 406 selectively contacts the a-Si film 404, and a catalytic element addition region 400s is formed.

  In this embodiment, nickel is added using a spin coating method, but a thin film (nickel film in this embodiment) formed from a catalytic element is formed on the a-Si film 404 by vapor deposition or sputtering. Then, nickel may be added.

  Next, heat treatment is performed at 500 to 650 ° C. (preferably 550 to 600 ° C.) for 6 to 20 hours (preferably 8 to 15 hours). In this embodiment, a heat treatment is performed at 570 ° C. for 14 hours. As a result, as shown in FIG. 10C, crystal nuclei are generated in the catalytic element addition region 400s, and the a-Si film 404 in the catalytic element addition region 400s is first crystallized to become a crystallization region 404a. Furthermore, crystallization proceeds in a direction parallel to the substrate 401 (direction indicated by an arrow 407) starting from the crystallization region 404a, and a crystalline silicon film 404b having a uniform macroscopic crystal growth direction is formed. At this time, the nickel 406 existing on the mask 405 is blocked by the mask film 405 and does not reach the underlying a-Si film 404. Therefore, the a-Si film 404 is crystallized only by nickel introduced in the catalytic element addition region 400s. A region where the lateral crystal growth does not reach remains as an amorphous region 404c. However, depending on the layout, a boundary may be generated by colliding with a crystal growth region in the lateral direction from an adjacent opening, and in this case, it is not an amorphous region.

  After removing the silicon oxide film 405 used as a mask, as shown in FIG. 10D, the crystalline silicon film 404b is irradiated with a laser beam 408, and the crystal is crystallized as in the first and second embodiments. Sexual improvement may be made. Thereby, the crystalline silicon film 404b obtained by the crystal growth in the lateral direction is further improved in quality and becomes a crystalline silicon film 404d.

  Subsequently, as shown in FIG. 10E, the crystalline silicon film 404d in the region where the crystal is grown in the lateral direction is etched into a predetermined shape, thereby forming a semiconductor layer 409 of the later TFT.

  The crystallization method in this embodiment can be applied to the crystallization process in the first and second embodiments. As a result, a high-performance TFT having a high current driving capability can be realized.

(Fourth embodiment)
The semiconductor device of this embodiment is an active matrix substrate. FIGS. 11A and 11B are block diagrams of the active matrix substrate of this embodiment.

  FIG. 11A shows a circuit configuration for performing analog driving. The semiconductor device of this embodiment includes a source side drive circuit 50, a pixel unit 51, and a gate side drive circuit 52. Note that in this specification, a drive circuit refers to a generic name including a source side processing circuit and a gate side drive circuit.

  The source side driving circuit 50 includes a shift register 50a, a buffer 50b, and a sampling circuit (transfer gate) 50c. Further, the gate side driving circuit 52 is provided with a shift register 52a, a level shifter 52b, and a buffer 52c. Further, if necessary, a level shifter circuit may be provided between the sampling circuit and the shift register.

  In the present embodiment, the pixel unit 51 includes a plurality of pixels, and each of the plurality of pixels includes a TFT element.

  Although not shown, a gate side drive circuit may be further provided on the opposite side of the gate side drive circuit 22 with the pixel portion 51 interposed therebetween.

  FIG. 11B shows a circuit configuration for performing digital driving. The semiconductor device of this embodiment includes a source side drive circuit 53, a pixel portion 54, and a gate side drive circuit 55. In the case of digital driving, as shown in FIG. 11B, a latch (A) 53b and a latch (B) 53c may be provided instead of the sampling circuit. The source side driving circuit 53 includes a shift register 53a, a latch (A) 53b, a latch (B) 53c, a D / A converter 53d, and a buffer 53e. The gate side driving circuit 55 includes a shift register 55a, a level shifter 55b, and a buffer 55c. If necessary, a level shifter circuit may be provided between the latch (B) 53c and the D / A converter 53d.

  In addition, the said structure is realizable according to the manufacturing process shown in above-mentioned Embodiment 1-3. In this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of the present invention, a memory and a microprocessor can be formed.

(Fifth embodiment)
The semiconductor device of this embodiment is an active matrix type liquid crystal display device or organic EL display device using the CMOS circuit or pixel portion formed in the above-described embodiment, and all electric appliances having such a display device as a display portion. It is.

  Such electric appliances include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Is mentioned.

  In this embodiment, a crystalline semiconductor film having good crystallinity using a catalyst element can be formed, and the catalyst element can be sufficiently gettered. In addition, a structure can be easily made according to required characteristics and purposes by using an N-channel TFT and a P-channel TFT. Therefore, a CMOS circuit in which the hot carrier resistance of the N-channel TFT is increased and the parasitic capacitance of the P-channel TFT is suppressed can be obtained. As a result, both the characteristics of the N-channel TFT and the P-channel TFT can be improved, so that a good CMOS driving circuit having a highly reliable and stable circuit characteristic can be realized. Further, even in a pixel switching TFT in which a leakage current during an off operation is a problem, a TFT in a sampling circuit of an analog switch unit, etc., generation of a leakage current that is considered to be due to segregation of a catalytic element can be sufficiently suppressed. As a result, a good display without display unevenness is possible. In addition, since the display is good without display unevenness, it is not necessary to use a light source more than necessary, and wasteful power consumption can be reduced. Therefore, an electric appliance (a mobile phone, a portable book, a display) that can reduce power consumption can be realized.

  As described above, the scope of application of the present invention is extremely wide and can be applied to electric appliances in various fields. Moreover, the electric appliance of 5th Embodiment is realizable using the display apparatus produced combining the 1st-4th embodiment.

  As mentioned above, although embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, Various deformation | transformation based on the technical idea of this invention is possible.

  For example, in addition to the pure silicon film shown in the above-described embodiment, a mixed film of germanium and silicon (silicon / germanium film) or a pure germanium film can be used as the semiconductor film targeted by the present invention.

In addition, as a method of introducing nickel, a method of applying a solution in which a nickel salt is dissolved on the surface of the amorphous silicon film was adopted, but before the amorphous silicon film was formed, nickel was introduced on the surface of the base film, Alternatively, nickel may be diffused from the lower layer of the amorphous silicon film to cause crystal growth. Various other methods can be used for introducing nickel. For example, there is a method in which an SOG (spin on glass) material is used as a solvent for dissolving a nickel salt and is diffused from an SiO 2 film. Further, a method of forming a thin film by a sputtering method, a vapor deposition method, a plating method, a method of directly introducing by an ion doping method, or the like can be used.

  Furthermore, in the above-described embodiment, phosphorus is used in the gettering step, but arsenic and antimony may be used in addition to that.

  According to the present invention, a catalytic element remaining in an active region of a crystalline semiconductor film having a good crystallinity manufactured using a catalytic element, particularly a channel forming region or a junction between a channel forming region and a source region or a drain region A sufficiently reduced semiconductor device is provided.

  In particular, in the N-channel TFT, the gate insulating film is partially thinned or removed, so that the doping conditions of the n-type impurity element for the source and drain regions and the gettering region can be optimized. Therefore, the gettering capability of the gettering region can be improved while suppressing the increase in resistance of the source and drain regions.

  Further, when applied to a semiconductor device including an N-channel TFT and a P-channel TFT, it is advantageous because the structure of each TFT can be changed according to required characteristics.

  Furthermore, according to the present invention, the semiconductor device can be manufactured by a simple process equivalent to the conventional one without adding a process.

  If a TFT having an active region sufficiently gettered according to the present invention is used, a high-performance semiconductor device having stable characteristics with reduced leakage current, high reliability and little characteristic variation, and integration High-performance high-performance semiconductor devices can be realized. In addition, the manufacturing process of such a high-performance semiconductor element can be simplified and the manufacturing cost can be reduced. Furthermore, the yield rate can be greatly improved in the manufacturing process.

  The present invention can be applied to devices such as an active matrix liquid crystal display device, an organic EL display device, a contact image sensor, and a three-dimensional IC, and an electronic device including such a device. When the present invention is applied to an active matrix substrate and a liquid crystal display device using the same, the switching characteristics of the pixel switching TFT required for the active matrix substrate and the high performance required for the TFT constituting the peripheral drive circuit section are improved.・ We can satisfy high integration at the same time. Therefore, when the present invention is applied to a driver monolithic active matrix substrate in which the active matrix portion and the peripheral drive circuit portion are formed on the same substrate, it is particularly advantageous because the module can be made compact, high performance and low cost. It is.

It is sectional drawing which shows typically the structure of TFT in preferable embodiment by this invention. (A)-(C) are process cross-sectional schematic diagrams for demonstrating the manufacturing method of TFT in 1st Embodiment by this invention. (A)-(C) are process cross-sectional schematic diagrams for demonstrating the manufacturing method of TFT in 1st Embodiment by this invention. (A)-(C) are process cross-sectional schematic diagrams for demonstrating the manufacturing method of TFT in 1st Embodiment by this invention. (A)-(C) are process cross-sectional schematic diagrams for demonstrating the manufacturing method of TFT in 1st Embodiment by this invention. (A)-(E) are process cross-sectional schematic diagrams for demonstrating the manufacturing method of TFT in 2nd Embodiment by this invention. (A)-(D) are process cross-sectional schematic diagrams for demonstrating the manufacturing method of TFT in 2nd Embodiment by this invention. (A)-(D) are top views which show the example of arrangement | positioning of the gettering area | region in 1st and 2nd embodiment by this invention. (A) And (B) is a top view which shows the example of arrangement | positioning of the gettering area | region in 1st and 2nd embodiment by this invention. (A)-(E) are process cross-sectional schematic diagrams for demonstrating the manufacturing method of TFT in 3rd Embodiment by this invention. (A) And (B) is a block diagram of the active matrix substrate of 4th Embodiment by this invention. It is a graph which shows the density | concentration profile of the n-type impurity doped by the silicon oxide film. (A) is a figure which shows a crystal growth, and (B) is a figure which shows a <111> crystal zone plane, when adding a catalytic element to an amorphous semiconductor film and crystallizing, (C) Is a diagram showing a standard triangle of crystal orientation. (A) And (B) is a figure which shows the surface orientation distribution of the crystalline semiconductor film obtained by utilizing a catalyst element, (C) is a figure which shows the standard triangle of a crystal orientation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 3 Gate insulating film 3a 1st insulating film 3b 2nd insulating film 5 Gate electrode 7 Channel region 9 Source region and drain region 10 Thin film transistor 11 Gettering region 13 Semiconductor layer

Claims (32)

  1. A method of manufacturing a semiconductor device including a thin film transistor,
    Preparing an amorphous semiconductor film to which a catalytic element for promoting crystallization is added at least in part;
    Performing a first heat treatment on the amorphous semiconductor film to crystallize at least a part of the amorphous semiconductor film to obtain a crystalline semiconductor film including a crystalline region;
    Forming an island-like semiconductor layer having a crystalline region by patterning the crystalline semiconductor film;
    The island-shaped semiconductor layer, and the lower insulating film, in contact with the lower insulating film, by forming the different upper insulating film of the composition or density and the lower insulating film in this order, wherein the lower and upper insulating film Forming a laminated insulating film including:
    Among the upper insulating film, Ri by the removing the portion located on the region to be the gate Ttaringu region of the island-shaped semiconductor layer is formed from the first insulating film and an upper insulating film formed from the lower insulating film a step of second insulating and a film, to form the thin gate insulating film than the region to be the source and drain regions over the area where the gettering region that,
    Forming a gettering region by adding a gettering element having a gettering capability to at least a region to be the gettering region of the island-like semiconductor layer through the gate insulating film ;
    Including performing a second heat treatment on the island-shaped semiconductor layer to move at least a part of the catalytic element in the island-shaped semiconductor layer to the gettering region ,
    The method of manufacturing a semiconductor device , wherein the amorphous semiconductor film is an amorphous silicon film or an amorphous silicon / germanium film, and the catalytic element is nickel .
  2. Wherein among the upper insulating film, the step of divided portions located on the region to be the least gettering region of the island-shaped semiconductor layer, a semiconductor device according to claim 1 carried out the lower insulating film as an etching stopper Manufacturing method.
  3. In a region to be a source and drain region of the previous SL island-shaped semiconductor layer, further comprising a step (A) adding an impurity element imparting impurity element or a p-type imparting n-type through the gate insulating film,
    The step of adding a gettering element having a gettering capability to at least a region to be the gettering region of the island-shaped semiconductor layer includes the step of insulating the gate insulating region into the region to be the gettering region of the island-shaped semiconductor layer. Adding the impurity element imparting the n-type or the impurity element imparting the p-type as the gettering element via the film,
    The impurity element imparting n-type is phosphorus, the impurity element imparting the p-type is boron, the step (A) and (B), the semiconductor device according to claim 1 or 2 are performed simultaneously Manufacturing method.
  4. A method of manufacturing a semiconductor device including an N-channel thin film transistor and a P-channel thin film transistor,
    Preparing an amorphous semiconductor film to which a catalytic element for promoting crystallization is added at least in part;
    Performing a first heat treatment on the amorphous semiconductor film to crystallize at least a part of the amorphous semiconductor film to obtain a crystalline semiconductor film including a crystalline region;
    Forming a plurality of island-like semiconductor layers each having a crystalline region by patterning the crystalline semiconductor film;
    The lower insulating film and the upper insulating film are formed in this order by forming a lower insulating film on the island-shaped semiconductor layer and an upper insulating film in contact with the lower insulating film and having a different composition or density in this order. Forming a laminated insulating film;
    Forming a gate electrode on the laminated insulating film;
    Of the island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor, a region serving as a gettering region and the entire island-shaped semiconductor layer serving as an active layer of the P-channel thin film transistor are exposed, and the N-channel thin film transistor Forming a first mask that covers a region to be a source region and a drain region and a gate electrode of the N-channel thin film transistor;
    Using the first mask and the gate electrode of the P-channel thin film transistor as a mask, doping the impurity element imparting p-type through the stacked insulating film to the semiconductor layer in the exposed region When,
    Wherein among the upper insulating film, the Rukoto to be removed by dividing the region are exposed from the gate electrode of said first mask and said P-channel thin film transistor, the first insulating film and an upper insulating formed from lower insulating film Forming a gate insulating film including a second insulating film formed from the film;
    Exposing the entire island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor and a region serving as a gettering region of the island-shaped semiconductor layer serving as an active layer of the P-channel thin film transistor; Forming a second mask covering a region to be a drain region and the gate electrode of a P-channel thin film transistor;
    An island which becomes an active layer of the N-channel thin film transistor is formed by doping an impurity element imparting n-type through a gate insulating film into a region exposed from the second mask in the island-shaped semiconductor layer. A source region and a drain region in the N-channel thin film transistor are formed in the N-shaped semiconductor layer, and each of the N-channel and P-channel thin film transistors is formed in an island-shaped semiconductor layer serving as an active layer of the N-channel and P-channel thin film transistors. Forming a gettering region in
    Performing a second heat treatment to move at least a part of the catalytic element in the island-like semiconductor layer to the gettering region ,
    The amorphous semiconductor film is an amorphous silicon film or an amorphous silicon / germanium film, the catalytic element is nickel, the impurity element imparting n-type is phosphorus, and the p-type is imparted. manufacturing method of the impurity element to a semiconductor device Ru boron der.
  5. A method of manufacturing a semiconductor device including an N-channel thin film transistor and a P-channel thin film transistor,
    Preparing an amorphous semiconductor film to which a catalytic element for promoting crystallization is added at least in part;
    Performing a first heat treatment on the amorphous semiconductor film to crystallize at least a part of the amorphous semiconductor film to obtain a crystalline semiconductor film including a crystalline region;
    Forming a plurality of island-like semiconductor layers each having a crystalline region by patterning the crystalline semiconductor film;
    A lower insulating film on the island-shaped semiconductor layer, in contact with the lower insulating film, different and upper insulating film compositions or density and the lower insulating film by forming in this order, including the lower and the upper insulating film Forming a laminated insulating film;
    Forming a gate electrode on the laminated insulating film;
    Of the island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor, a region serving as a gettering region and the entire island-shaped semiconductor layer serving as an active layer of the P-channel thin film transistor are exposed, and the N-channel thin film transistor Forming a first mask that covers a region to be a source region and a drain region and a gate electrode of the N-channel thin film transistor;
    Wherein among the upper insulating film, the Rukoto to be removed by dividing the region are exposed from the gate electrode of said first mask and P-channel thin film transistor, the first insulating film and an upper insulating film formed from the lower insulating film Forming a gate insulating film including a second insulating film formed from:
    Doping the island-like semiconductor layer with an impurity element imparting p-type through the first insulating film using the first mask and the gate electrode of the P-channel thin film transistor as a mask;
    Exposing the entire island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor and a region serving as a gettering region of the island-shaped semiconductor layer serving as an active layer of the P-channel thin film transistor; Forming a second mask covering a region to be a drain region and the gate electrode of a P-channel thin film transistor;
    An island which becomes an active layer of the N-channel thin film transistor is formed by doping an impurity element imparting n-type through a gate insulating film into a region exposed from the second mask in the island-shaped semiconductor layer. A source region and a drain region in the N-channel thin film transistor are formed in the N-shaped semiconductor layer, and each of the N-channel and P-channel thin film transistors is formed in an island-shaped semiconductor layer serving as an active layer of the N-channel and P-channel thin film transistors. Forming a gettering region in
    And performing a second heat treatment to move at least a part of the catalytic element in the island-shaped semiconductor layer to the gettering region ,
    The amorphous semiconductor film is an amorphous silicon film or an amorphous silicon / germanium film, the catalytic element is nickel, the impurity element imparting n-type is phosphorus, and the p-type is imparted. manufacturing method of the impurity element to a semiconductor device Ru boron der.
  6. A method of manufacturing a semiconductor device including an N-channel thin film transistor and a P-channel thin film transistor,
    Preparing an amorphous semiconductor film to which a catalytic element for promoting crystallization is added at least in part;
    Performing a first heat treatment on the amorphous semiconductor film to crystallize at least a part of the amorphous semiconductor film to obtain a crystalline semiconductor film including a crystalline region;
    Forming a plurality of island-like semiconductor layers each having a crystalline region by patterning the crystalline semiconductor film;
    A lower insulating film on the island-shaped semiconductor layer, in contact with the lower insulating film, different and upper insulating film compositions or density and the lower insulating film by forming in this order, including the lower and the upper insulating film Forming a laminated insulating film;
    Forming a gate electrode on the laminated insulating film;
    Of the island-shaped semiconductor layer serving as the active layer of the N-channel thin film transistor, the region serving as the gettering region and the whole of the island-shaped semiconductor layer serving as the active layer of the P-channel thin film transistor are exposed. Forming a first mask that covers a region to be a source region and a drain region and a gate electrode of the N-channel thin film transistor;
    Using the first mask and the gate electrode of the P-channel thin film transistor as a mask, doping an impurity element imparting p-type to the island-like semiconductor layer through the stacked insulating film;
    Wherein among the upper insulating film, the Rukoto to be removed by dividing the region are exposed from the gate electrode of said first mask and said P-channel thin film transistor, the first insulating film and an upper insulating formed from lower insulating film Forming a gate insulating film including a second insulating film formed from the film;
    Of the island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor, a region serving as a source region, a drain region, and a gettering region, and of the island-shaped semiconductor layer serving as an active layer of the P-channel thin film transistor, A region that becomes an LDD region of the N-channel thin film transistor, a region that becomes a source and drain region of the P-channel thin film transistor, and a second electrode that covers the gate electrode of the P-channel thin film transistor. Forming a mask;
    An island which becomes an active layer of the N-channel thin film transistor is formed by doping an impurity element imparting n-type through a gate insulating film into a region exposed from the second mask in the island-shaped semiconductor layer. A source region and a drain region in the N-channel thin film transistor are formed in the N-shaped semiconductor layer, and each of the N-channel and P-channel thin film transistors is formed in an island-shaped semiconductor layer serving as an active layer of the N-channel and P-channel thin film transistors. Forming a gettering region in
    Performing a second heat treatment to move at least a part of the catalytic element in the island-like semiconductor layer to the gettering region ,
    The amorphous semiconductor film is an amorphous silicon film or an amorphous silicon / germanium film, the catalytic element is nickel, the impurity element imparting n-type is phosphorus, and the p-type is imparted. manufacturing method of the impurity element to a semiconductor device Ru boron der.
  7. A method of manufacturing a semiconductor device including an N-channel thin film transistor and a P-channel thin film transistor,
    Preparing an amorphous semiconductor film to which a catalytic element for promoting crystallization is added at least in part;
    Performing a first heat treatment on the amorphous semiconductor film to crystallize at least a part of the amorphous semiconductor film to obtain a crystalline semiconductor film including a crystalline region;
    Forming a plurality of island-like semiconductor layers each having a crystalline region by patterning the crystalline semiconductor film;
    A lower insulating film on the island-shaped semiconductor layer, in contact with the lower insulating film, different and upper insulating film compositions or density and the lower insulating film by forming in this order, including the lower and the upper insulating film Forming a laminated insulating film;
    Forming a gate electrode on the laminated insulating film;
    Of the island-shaped semiconductor layer serving as the active layer of the N-channel thin film transistor, the region serving as the gettering region and the whole of the island-shaped semiconductor layer serving as the active layer of the P-channel thin film transistor are exposed. Forming a first mask that covers a region to be a source region and a drain region and a gate electrode of the N-channel thin film transistor;
    Wherein among the upper insulating film, the Rukoto to be removed by dividing the region are exposed from the gate electrode of said first mask and said P-channel thin film transistor, the first insulating film and an upper insulating formed from lower insulating film Forming a gate insulating film including a second insulating film formed from the film;
    Doping the island-like semiconductor layer with an impurity element imparting p-type through the first insulating film using the first mask and the gate electrode of the P-channel thin film transistor as a mask;
    Of the island-shaped semiconductor layer serving as an active layer of the N-channel thin film transistor, a region serving as a source region, a drain region, and a gettering region, and of the island-shaped semiconductor layer serving as an active layer of the P-channel thin film transistor, A region that becomes an LDD region of the N-channel thin film transistor, a region that becomes a source and drain region of the P-channel thin film transistor, and a second electrode that covers the gate electrode of the P-channel thin film transistor. Forming a mask;
    An island which becomes an active layer of the N-channel thin film transistor is formed by doping an impurity element imparting n-type through a gate insulating film into a region exposed from the second mask in the island-shaped semiconductor layer. A source region and a drain region in the N-channel thin film transistor are formed in the N-shaped semiconductor layer, and each of the N-channel and P-channel thin film transistors is formed in an island-shaped semiconductor layer serving as an active layer of the N-channel and P-channel thin film transistors. Forming a gettering region in
    Performing a second heat treatment to move at least a part of the catalytic element in the island-like semiconductor layer to the gettering region ,
    The amorphous semiconductor film is an amorphous silicon film or an amorphous silicon / germanium film, the catalytic element is nickel, the impurity element imparting n-type is phosphorus, and the p-type is imparted. manufacturing method of the impurity element to a semiconductor device Ru boron der.
  8. The gate forming an insulating film, the upper layer with respect to the insulating film by etching conditions such as the etching rate greater than the etching rate for the lower insulating film, according to claim 4 to 7 comprising the step of etching the upper insulating film A method for manufacturing a semiconductor device according to any one of the above.
  9. The method for manufacturing a semiconductor device according to any one of claims 4 to 8 including the step of etching the upper insulating film by using the lower insulating film as an etching stopper film for forming the gate insulating film.
  10. The step of forming the multilayer insulating film, forming a lower insulating film mainly containing silicon oxide, one of claims 4 and a step of forming an upper insulating film mainly containing silicon nitride 9 A method for manufacturing the semiconductor device according to claim 1.
  11. The step of forming the multilayer insulating film, after forming the lower insulating film, manufacturing a semiconductor device according to any one of claims 4 to 10 comprising the step of forming the upper insulating film without exposure to the atmosphere Method.
  12. The steps of forming a source region and a drain region in the N-channel type thin film transistor and forming a gettering region in each of the N-channel type and P-channel type thin film transistors include an island-shaped semiconductor that becomes an active layer of the N-channel type thin film transistor Compared to the regions that become the source region and the drain region in the layer, in the island-shaped semiconductor layer that becomes the active layer of the N-channel and P-channel thin film transistors, the region that becomes the gettering region is more susceptible to crystal breakdown. the method of manufacturing a semiconductor device according to any one of claims 4 to 11, comprising the step of doping the impurity element imparting the n-type at amorphization is susceptible doping conditions.
  13. The steps of forming a source region and a drain region in the N-channel type thin film transistor and forming a gettering region in each of the N-channel type and P-channel type thin film transistors are compared with the source region and the drain region of the N-channel type thin film transistor. In the gettering region of the N-channel and P-channel thin film transistors, the ratio Pa / Pc between the TO phonon peak Pa of the amorphous semiconductor and the TO phonon peak Pc of the crystalline semiconductor in the Raman spectrum is increased. a source region and a drain region in the N-channel thin film transistor, claim 4 to 12 is a step of forming a gettering region in each of said N-channel and P-channel thin film transistor The method of manufacturing a semiconductor device according.
  14. Even after the second heat treatment step, in the gettering region of the N-channel and P-channel thin film transistors, the amorphous semiconductor TO of the Raman spectrum is compared with the source and drain regions of the N-channel thin film transistor. The method for manufacturing a semiconductor device according to claim 13 , wherein a state in which a ratio Pa / Pc between the phonon peak Pa and the TO phonon peak Pc of the crystalline semiconductor is large is maintained.
  15. The gettering region, method of manufacturing a semiconductor device according to any one of claims 1 to 14 in which electrons or holes of the island-like semiconductor layer is formed in a region other than the region to be moved.
  16. The gettering region, the contact with the source region or the drain region, a method of manufacturing a semiconductor device according to any of claims 1 to 15 which is formed so as not to contact with said channel area.
  17. After the second heat treatment step, according to any one of further comprising claim 1 forming an electrically connected to the wiring to the contact portion 16, including at least a portion of the source region or the drain region Semiconductor device manufacturing method.
  18. By the second heat treatment step, among the island-shaped semiconductor layer, the activation of the impurity element imparting impurity element contact and p-type which imparts the n-type doped with at least the source region and the drain region the method of manufacturing a semiconductor device according to any one of claims 4 14.
  19. The step of preparing an amorphous semiconductor film to which at least a part of the catalyst element for promoting crystallization is added,
    Forming a mask having an opening on the amorphous semiconductor film;
    The method of manufacturing a semiconductor device according to any of claims 1 18, including the step of adding the catalyst element to a selected region of the amorphous semiconductor film through the opening.
  20. Wherein after the first heat treatment step, a method of manufacturing a semiconductor device according to any one of the semiconductor film from further comprising claim 1 the step of irradiating a laser beam to 19.
  21. A semiconductor device manufactured by the method according to claim 1 and including at least one thin film transistor,
    The at least one thin film transistor comprises:
    A semiconductor layer formed of the island-like semiconductor layer and having a crystalline region including a channel region, a source region, and a drain region;
    At least the channel region of the semiconductor layer, and the gate insulating film formed on said source region and said drain region,
    A gate electrode formed to face the channel region through the gate insulating film,
    The semiconductor layer contains the catalytic element,
    The gettering region, the channel region, viewed including the catalyst element at a higher concentration than the source region and the drain region,
    At least the channel region, a portion located in said source region and said drain region of said gate insulating film includes a first insulating film formed in contact with the first insulating film on the first insulating film, It is composed of two or more insulating films including the first insulating film and the second insulating film having a different composition or density ,
    Portion positioned on the gettering region of the gate insulating film includes a first insulating film, and a semiconductor device which does not include the second insulating film.
  22. The first insulating film and the second insulating film, respectively, are formed of silicon oxide or silicon nitride, wherein said first composition ratio of silicon in the insulating film and the second insulating film are different claim 21 Semiconductor device.
  23. 23. The semiconductor device according to claim 21 , wherein the first insulating film contains silicon oxide as a main component, and the second insulating film contains silicon nitride as a main component.
  24. The gettering region, the semiconductor device according to any one of the at least one charge electrons or holes during the operation of the thin film transistor is formed in a region other than the region that moves in claim 21 to 23 among the semiconductor layer.
  25. The gettering region, the semiconductor device according to any of claims 21 24 in which is formed so as not to contact with at least the channel region.
  26. Wherein in the gettering region, the source and drain regions, and than the previous SL channel region, the semiconductor device according to claim 21 a small percentage of the proportion of the amorphous component more crystalline components 25 .
  27. 27. The semiconductor device according to claim 21, wherein the gettering region includes phosphorus and boron .
  28. At least the channel region in the semiconductor layer, <111> crystal zone planes of the crystal is mainly composed of a region oriented semiconductor device according to any of claims 21 27.
  29. Wherein at least the channel region in the semiconductor layer has a plurality of crystalline domains, domain diameter of the crystalline domain is 2μm or more 10μm or less, the semiconductor device according to any of claims 21 28.
  30. Wherein the gate electrode, W, Ta, Ti, a semiconductor device according to any one of element selected from Mo or claim 21, which is formed from one or more of the alloy material of the element, 29.
  31. Wherein the channel region of the semiconductor layer and between the source and drain regions, the semiconductor device according to yet claim 21 30 having a low concentration impurity region.
  32. A semiconductor device manufactured by the method according to claim 4 and comprising an N-channel thin film transistor and a P-channel thin film transistor,
    The N-channel thin film transistor and the P-channel thin film transistor are respectively
    A semiconductor layer having a crystalline region including a channel region, a source region and a drain region;
    The gate insulating film formed on at least the channel region, the source region, and the drain region of the semiconductor layer;
    The gate electrode formed to face the channel region through the gate insulating film, the semiconductor layer includes the catalytic element ,
    The semiconductor layer of the N-channel thin film transistor is formed from the island-shaped semiconductor layer that becomes an active layer of the N-channel thin film transistor, and the semiconductor layer of the P-channel thin film transistor is an active layer of the P-channel thin film transistor. Formed from the island-like semiconductor layer to be a layer,
    In the N-channel thin film transistor,
    The gettering region, the channel region, viewed including the catalyst element at a higher concentration than the source region and the drain region,
    Of the gate insulating film, at least portions located on the channel region, the source region, and the drain region are formed on the first insulating film and on the first insulating film in contact with the first insulating film, It is composed of two or more insulating films including the first insulating film and the second insulating film having a different composition or density ,
    A portion of the gate insulating film located on the gettering region includes the first insulating film and does not include the second insulating film,
    In the P-channel type thin film transistor,
    The gettering region includes the catalytic element at a higher concentration than the channel region, the source region, and the drain region,
    At least a portion of the gate insulating film located on the channel region is formed on the first insulating film and on the first insulating film in contact with the first insulating film. It is composed of two or more insulating films including the second insulating film having different densities,
    A portion of the gate insulating film located on the source region, the drain region, and the gettering region includes the first insulating film and does not include the second insulating film .
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