JP2007233415A - Semiconductor integrated circuit device for driving display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce EMI and current consumption in internal wiring after input of display data to a data driver. <P>SOLUTION: A data driver 4 includes a receiver 10 for receiving display data input from the outside of a chip, a data fetching circuit 30 for fetching the display data output from the receiver 10, and a latch 40 for storing display data output from the data fetching circuit 30. The data fetching circuit 30 has internal wiring 31 for transferring display data output from the receiver 10, a data inversion circuit 33 for inverting the logical level of display data transferred by the internal wiring 31, in response to a data inversion signal, and a data register 34 for storing the inverted display data output from the data inversion circuit 33. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device for driving a display panel.

  As a dot-matrix display device, the liquid crystal display device is used in various devices such as personal computers because of its thinness, light weight, and low power, and it is particularly useful for controlling image quality with high definition. Display devices dominate.

A liquid crystal display module of a liquid crystal display device includes a liquid crystal panel (LCD panel), a control circuit (hereinafter referred to as a controller) composed of a semiconductor integrated circuit device (hereinafter referred to as IC), and a scanning side drive circuit (hereinafter referred to as scanning) composed of an IC. And a data side driving circuit (hereinafter referred to as a data driver). The transfer speed of display data has been increased due to the high definition and large size of the liquid crystal panel. As the display data transfer rate increases, the frequency per unit time at which the clock signal and display data are inverted increases. As a result, when the clock signal or display data is a binary voltage signal (hereinafter referred to as a CMOS signal) whose amplitude changes (inverts) between the power supply voltage ("H" level) and the ground ("L" level). , there is a problem that EMI (E lectro M agnetic I nterference ) noise and current consumption increases in the wiring between the controller and the data driver clock signal and the display data is transferred.

  As one method for solving this problem, the logic of the display data composed of CMOS signals is primarily inverted by the data primary inversion circuit of the transfer source in accordance with the data inversion signal INV to reduce the inversion frequency in the entire transfer wiring. Then, a secondary inversion method is used to restore the original logic in the data secondary inversion circuit of the transfer destination (see, for example, Patent Document 1). In this method, for example, when transferring display data composed of CMOS signals with an 18-bit width of 6 bits × 3 dots (R, G, B), the transfer source controller performs transfer for each bit of 18-bit display data. When a change that logically inverts from “H” level to “L” level or “L” level to “H” level before and after is detected and the number of changed bits is, for example, 13 bits, which is more than half of 18 bits, data The inversion signal INV = “H” level is generated. Then, with this data inversion signal INV, the 18-bit data primary inversion circuit provided near the output terminal in the controller inverts the 18-bit logic. As a result, in the 18-bit width transfer wiring, 13 bits out of 18 bits are not inverted, and only 5 bits are inverted, so that the frequency of inversion can be reduced and EMI noise and current consumption can be reduced. Then, in order to restore the display data of 18-bit width to the original logic, an 18-bit data secondary inversion circuit provided near the input terminal in the transfer destination data driver is inverted again to 18-bit logic. .

As another method for solving the above problem, an interface using a small amplitude differential signal transmission system is used. As a typical example, an interface by RSDS (reduced swing differential signaling) (hereinafter referred to as RSDS interface) (see Patent Document 2) is used.
Japanese Patent Laying-Open No. 2003-84726 (FIG. 9) Japanese Patent No. 3285332

  However, as the image quality of liquid crystal panels is further increased in definition and size, and the number of pixels increases to SXGA (1280 × 1024 pixels) and UXGA (1600 × 1200 pixels), the above two solutions are used. However, the problem of increased current consumption has arisen. That is, both methods can reduce the EMI noise and current consumption in the wiring between the ICs, but the problem arises that the EMI noise and current consumption in the internal wiring after the display data is input to the data driver increases. I came.

The display panel driving semiconductor integrated circuit device of the present invention includes a receiving unit that receives display data input from the outside of the chip, a data capturing circuit that captures display data output from the receiving unit, and a data capturing circuit that outputs the data. A display panel driving semiconductor integrated circuit device comprising a latch for storing display data.
The data capturing circuit includes an internal wiring for transferring display data output from the receiving unit, a data inversion circuit for inverting the logic level of display data transferred by the internal wiring in response to a data inversion signal, A data register for storing the inverted display data output from the data inverting circuit.

  According to the present invention, EMI noise and current consumption due to internal wiring after display data is input to the semiconductor integrated circuit device can be reduced.

In order to clarify the CMOS signal and the RSDS signal, the display data and the timing signal used in the following description are defined below.
(1) Display data DATA: CMOS signal or RSDS signal not classified (2) Display data DA: CMOS signal (3) Display data D00 to D05, D10 to D15, D20 to D25: CMOS signal (4) Display data DN / DP: RSDS signal (5) Display data D00N / D00P to D02N / D02P, D10N / D10P to D12N / D12P, D20N / D20P to D22N / D22P: RSDS signal (6) Clock signal CLK: No distinction between CMOS signal and RSDS signal (7) Clock signal CK: CMOS signal (8) Clock signal CKN / CKP: RSDS signal (9) Start signal STH, latch signal STB, data inversion signal INV: CMOS signal

  The liquid crystal display module of the liquid crystal display device according to the present invention will be described below with reference to the drawings. As shown in FIG. 1, the liquid crystal display module of the liquid crystal display device includes a liquid crystal panel 1, a controller 2, a scan driver 3, and a data driver 4. Although the liquid crystal panel 1 is not shown in detail, for example, in the case of a transmission type, a semiconductor substrate on which transparent pixel electrodes and thin film transistors (TFTs) are arranged, a counter substrate on which one transparent electrode is formed on the entire surface, and these It consists of a structure in which liquid crystal is sealed between two substrates facing each other. A predetermined voltage is applied to each pixel electrode by controlling a TFT having a switching function, and between each pixel electrode and the opposite substrate electrode. An image is displayed by changing the transmittance of the liquid crystal according to the potential difference. The liquid crystal panel 1 may be of a reflective type, and in this case, a function of reflecting light is imparted to one of the two substrates, and an image is displayed by changing the reflectance of the liquid crystal. On the semiconductor substrate, a scanning line for sending a TFT switching control signal (scanning signal) and a data line for sending a gradation voltage to be applied to each pixel electrode are wired. Hereinafter, when the resolution of the liquid crystal panel 1 is SXGA (1280 × 1024 pixels: one pixel is composed of 3 dots of R, G, and B) and 262144 color display (each of R, G, and B is composed of 64 gradations) Will be described as an example.

  1024 scanning lines of the liquid crystal panel 1 are arranged corresponding to 1024 pixels in the vertical direction. In addition, since one pixel is composed of three dots of R, G, and B, 1280 × 3 = 3840 data lines are arranged corresponding to 1280 pixels in the horizontal direction. Four scanning drivers 3 are arranged in such a manner that 256 are shared by one for 1024 gate lines. Ten (4-1, 4-2,..., 4-10) data drivers 4 are arranged so that 384 are shared by one for 3840 data lines.

  Display data and timing signals are transferred to the controller 2 from a PC (personal computer) 5 via, for example, an LVDS (low voltage differential signaling) interface. A clock signal or the like is transferred from the controller 2 to the scan driver 3 in parallel to each scan driver 3, and a vertical synchronization start signal STV is transferred to the first-stage scan driver 3, and the cascade-connected second and subsequent stages are scanned. The data is sequentially transferred to the driver 3. A horizontal synchronization start signal STH and a latch signal STB made of a CMOS signal are transferred from the controller 2 to the first stage data driver 4-1 via a CMOS interface, and display data DN / DP and a clock signal CKN made of an RSDS signal are transferred. / CKP is transferred via the RSDS interface. To the second and subsequent data drivers 4-2, 4-3,..., 4-10 cascaded from the first stage data driver 4-1, display data DA consisting of CMOS signals, a clock signal CK, a start signal STH, The latch signal STB and the data inversion signal INV are sequentially transferred via the CMOS interface. The data inversion signal INV is generated based on the number of changed bits by detecting a logical inversion before and after each bit of the display data DA in the first-stage data driver 4-1.

  A pulsed scanning signal is sent line by line from the scanning driver 3 to each scanning line of the liquid crystal panel 1. All the TFTs connected to the scanning line to which the pulse is applied are turned on. At that time, the gradation voltage is supplied from each data driver 4 to the data line of the liquid crystal panel 1 and applied to the pixel electrode through the turned-on TFT. The When the TFT connected to the scanning line to which no pulse is applied changes to the OFF state, the potential difference between the pixel electrode and the counter substrate electrode is maintained until the next gradation voltage is applied to the pixel electrode. A pulse is sequentially applied to all the scanning lines, whereby a predetermined gradation voltage is applied to all the pixel electrodes, and an image can be displayed by rewriting the gradation voltage in a frame period. .

  The data driver 4 according to an embodiment of the present invention will be described below with reference to FIG. The data driver 4 receives R, G, B 6-bit display data for 64 gradations of R, G, B corresponding to 384 data lines, respectively. It has a 384 output configuration in which one gradation voltage corresponding to the logic of the display data is output. As a specific circuit configuration, the receiver 10 constituting the interface circuit for inter-chip data transfer and the digital display data DA are serial / parallel converted to an analog gradation voltage corresponding to the logic of the display data DA. A shift register 20, a data capturing circuit 30, a latch 40, a level shifter 50, a digital-analog conversion circuit (hereinafter referred to as a D / A converter) 60, and a voltage follower output circuit 70 that constitute a circuit for conversion are included. The data driver 4 has a power supply circuit for operating the above circuits, but illustration and description thereof are omitted.

  2 will be described as input terminals of the data driver 4. FIG. The ISTH terminal is an input terminal for the start signal STH, and the start signal STH is input to the shift register 20. The ISTB terminal is an input terminal for the latch signal STB, and the latch signal STB is input to the latch 40 and the voltage follower output circuit 70. The IFM terminal is a terminal for selecting a CMOS or RSDS interface mode. A fixed potential of “H” level or “L” level is supplied to the IFM terminal as an interface mode selection signal, and the potential is input to the receiver 10. The ICKP / ICK terminal and the ICKN / IINV terminal are input terminals for the clock signal CKN / CKP when the IFM terminal = “H” level, and the ICKP / ICK terminal is the clock signal CK when the IFM terminal = “L” level. And the ICKN / IINV terminal are input terminals for the data inversion signal INV. The clock signals CKN / CKP and CK and the data inversion signal INV are input to the receiver 10, respectively. ID00N / ID00-ID02P / ID05 terminal, ID10N / ID10-ID12P / ID15 terminal, ID20N / ID20-ID22P / ID25 terminal are gradation display 6 bits × R, G, B3 dots (1 pixel) = 18 bits width When the display data DATA is an input terminal and the IFM terminal is at "H" level, display data D00N / D00P-D02N / D02P, D10N / D10P-D12N / D12P, D20N / D20P-D22N / D22P (hereinafter, referred to as RSDS signals) DN / DP) and input terminals for display data D00-D05, D10-D15, D20-D25 (hereinafter referred to as DA) consisting of CMOS signals when the IFM terminal is at "L" level. Each of the display data DATA is input to the receiver 10.

  Each terminal shown in FIG. 2 will be described as an output terminal of the data driver 4. The OSTH terminal is an output terminal of the start signal STH, and the start signal STH is output from the shift register 20. The OCK terminal is an output terminal of the clock signal CK, and the clock signal CK is output from the shift register 20. The OSTB terminal is an output terminal of the latch signal STB, and the latch signal STB is output from the latch 40. The OINV terminal is an output terminal for the data inversion signal INV, and the data inversion signal INV is output from the data fetch circuit 30. Terminals OD00 to OD05, OD10 to OD15, and OD20 to OD25 are display data DA output terminals. Each display data DA is output from the data fetch circuit 30.

  The receiver 10 constituting the interface circuit for interchip data transfer will be described. The receiver 10 receives the clock signal CLK and display data DATA that are RSDS signals or CMOS signals, and outputs the clock signal CK and display data DA that are CMOS signals to the internal shift register 20 and the data fetch circuit 30. As shown in FIG. 3, the receiver 10 bypasses the RSDS receiver 11a to which the clock signal CKN / CKP is input, the RSDS receiver 11b to which the display data DN / DP is input, the clock signal CK and the data inversion signal INV. Bypass circuit 12a, display circuit DA bypass circuit 12b, RSDS receiver 11a output frequency divider circuit 13a, RSDS receiver 11b output frequency divider circuit 13b, data inversion signal generation circuit 14, and data 1 It has a next inversion circuit 15, a selector 16a for the clock signal CK, a selector 16b for the data inversion signal INV, and a selector 16c for the display data DA.

  When the IFM terminal = “H” level, each RSDS receiver 11a, 11b is in an operation state in which the internal bias signal is turned on and the clock signal CKN / CKP and the display data DN / DP can be received. At the L "level, the internal bias signal is turned off to make it inoperative and reduce current consumption.

  Each of the bypass circuits 12a and 12b includes, for example, two OR circuits as shown in FIG. 4, and bypasses the clock signal CK, the data inversion signal INV, and the display data DA when the IFM terminal = “L” level. When the IFM terminal = “H” level, bypass of the CMOS signal is prohibited.

  The frequency dividing circuit 13a divides the clock signal CK output from the RSDS receiver 11a by 2, and outputs the result by a single line. Each frequency dividing circuit 13b divides display data D00-D01, D02-D03,..., D24-D25, which are output from each RSDS receiver 11b and time-multiplexed 2-bit display data into the same wiring by two. The data is divided into bit data D00, D01,..., D24, D25 and output on two lines.

  The data inversion signal generation circuit 14 includes a data inversion detection circuit 17, a first determination circuit 18, and a second determination circuit 19. Since the data inversion detection circuit 17 corresponds to each 6-bit display data DA of R, G, and B, there are three data inversion detection circuits 17. Each data inversion detection circuit 17 detects a change before and after each of the 6 bits, as shown in FIG. It consists of an EXOR circuit that outputs an exclusive OR of outputs. The EXOR circuit outputs an “L” level for a bit that does not change before and after, and outputs an “H” for a bit that has a change. Display data DA is output from the second-stage flip-flop. Three first determination circuits 18 are provided to correspond to each data inversion detection circuit 17. When the IFM terminal = “H” level, the first determination circuit 18 is in an operation state that allows determination, and when the IFM terminal = “L” level. In the non-operating state, current consumption is reduced. Each first determination circuit 18 detects the number of bits that have changed among the 6 bits, and outputs an “H” level if, for example, 4 bits or more. The second determination circuit 19 detects the number of outputs of “H” level among the outputs of the three first determination circuits 18, and outputs “H” when the number of outputs is two or more. The output of the second determination circuit 19 becomes the data inversion signal INV.

  The data primary inversion circuit 15 includes an EXOR circuit, and controls the inversion of the display data DA from the data inversion signal generation circuit 14 by the data inversion signal INV from the data inversion signal generation circuit 14 when the IFM terminal = “H” level. To do.

  The selector 16a selectively outputs the clock signal CK from the frequency divider circuit 13a when the IFM terminal = “H” level, and selectively outputs the clock signal CK from the bypass circuit 12a when the IFM terminal = “L” level. . The selector 16b selectively outputs the data inversion signal INV from the data inversion signal generation circuit 14 when the IFM terminal = “H” level, and the data inversion signal INV from the bypass circuit 12a when the IFM terminal = “L” level. Is selected and output. When the IFM terminal = “H” level, the selector 16c selectively outputs the display data D00-D01, D02-D03,..., D24-D25 from the data primary inversion circuit 15, and the IFM terminal = “L” level. At this time, the display data D00-D01, D02-D03,..., D24-D25 from the bypass circuit 12b are selectively output.

  The operation of the receiver 10 when the IFM terminal = “H” level will be described. The RSDS receivers 11a and 11b are in an operating state, and the bypass circuits 12a and 12b are prohibited from bypassing CMOS signals. The selector 16a selects the frequency divider 13a output, the selector 16b selects the data inversion signal generation circuit 14 output, and the selector 16c selects the data primary inversion circuit 15 output. With these operations, the receiver 10 functions as an RSDS receiver as shown in FIG. Therefore, at this time, when the clock signal CKN / CKP and the display data DN / DP are input to the receiver 10, each RSDS receiver 11a, 11b receives them, and from the receiver 10, the clock signal from the frequency dividing circuit 13a. CK is output and display data DA from the data primary inversion circuit 15 is output.

  Next, the operation of the receiver 10 when the IFM terminal = “L” level will be described. The RSDS receivers 11a and 11b are deactivated, and the bypass circuits 12a and 12b bypass the clock signal CK, the data inversion signal INV, and the display data DA. The selector 16a selects the clock signal output of the bypass circuit 12a, the selector 16b selects the data inversion signal output of the bypass circuit 12a, and the selector 16c selects the output of the bypass circuit 12b. By these operations, as shown in FIG. 7, the receiver 10 functions as a CMOS receiver. Therefore, at this time, when the clock signal CK, the data inversion signal INV, and the display data DA are input to the receiver 10, each bypass circuit 12a, 12b bypasses the CMOS signal, and from the receiver 10, the bypass circuit 12a Clock signal CK and data inversion signal INV are output, and display data DA from the bypass circuit 12b is output.

  Returning to FIG. 2, the shift register 20, the data capture circuit 30, the latch 40, the level shifter 50, the D / A converter 60, and the voltage follower output circuit 70 will be described. The shift register 20 consists of 128 bits corresponding to 384 data lines (one bit is assigned to three data lines R, G, and B), and one of the plurality of scanning lines of the liquid crystal panel 1 is assigned to one scanning line. For each horizontal period to be scanned, the “H” level of the start signal STH is read at the timing of the front edge and the rear edge of the clock signal CK, and the control signals C1, C2,. Supply to the capture circuit 30.

  As shown in FIG. 8, the data capturing circuit 30 includes an internal wiring 31 for display data DA, an internal wiring 32 for a data inversion signal INV, a data secondary inversion circuit 33, and a data register 34. The internal wiring 31 connects the display data DA output terminal of the receiver 10 and the OD00-OD05, OD10-OD15, and OD20-OD25 terminals. The internal wiring 32 connects the data inversion signal INV output terminal of the receiver 10 and the OINV terminal. The data secondary inversion circuit 33 is composed of an EXOR circuit of 6 bits × 3 dots (R, G, B), 18 bits wide × 128 bits, corresponding to 384 data lines. The display data DA is input from the internal wiring 31 to one input terminal of the EXOR circuit, and the data inversion signal INV is input from the internal wiring 32 to the other input terminal of the EXOR circuit. The data register 34 is supplied from the data secondary inversion circuit 33 in an 18-bit width × 128 bits of 6 bits × 3 dots (R, G, B) every horizontal period corresponding to 384 data lines. Display data DA for one scanning line is captured at the timing of the trailing edge of the control signals C1, C2,.

  The latch 40 holds the display data DA fetched in the data register 34 every horizontal period at the timing of the front edge of the latch signal STB and supplies it to the level shifter 50 at a time. The level shifter 50 increases the voltage level of the display data DA from the latch 40 and supplies it to the D / A converter 60. In accordance with the display data DA from the level shifter 50, the D / A converter 60 has 1 corresponding to the logic of the display data DA out of 64 gradations for each 6-bit display data DA corresponding to each of the 384 data lines. Two gradation voltages are supplied to the voltage follower output circuit 70. The voltage follower output circuit 70 outputs the grayscale voltage from the D / A converter 60 as outputs S1 to S384 at the timing of the trailing edge of the latch signal STB with enhanced driving capability.

  For transferring various signals between the controller 2 and the data driver 4 and between the data drivers 4 of the liquid crystal display module shown in FIG. 1, the controller 2, the data driver 4, and various signal lines from the controller 2 to the data driver 4 are connected. This will be described with reference to FIG. The start signal STH and the latch signal STB are transferred as CMOS signals from the controller 2 to the data driver 4-1, and cascaded from the data driver 4-1 to the data drivers 4-2, 4-3,. Are transferred sequentially.

  The transfer of the clock signal CLK, the display data DATA, and the data inversion signal INV will be described. The potential level of the IFM terminal of the data driver 4-1 is set to "H" level, and the potential level of the IFM terminal of the data drivers 4-2, 4-3, ..., 4-10 is set to "L" level. . As a result, the RSDS receivers 11a and 11b of the data driver 4-1 are activated, and the receiver 10 of the data driver 4-1 functions as an RSDS receiver as shown in FIG. And the receiver 10 of the data driver 4-1 constitute an RSDS interface. Accordingly, the clock signal CKN / CKP and the display data DN / DP are transferred from the controller 2 to the data driver 4-1 via the RSDS interface.

  In the data driver 4-1, the clock signal CKN / CKP is converted into the clock signal CK by the receiver 10 and transferred to the OCK terminal via the shift register 20. The display data DN / DP is converted into display data DA by the receiver 10. The data inversion signal generation circuit 14 of the receiver 10 detects inversion before and after each bit of the display data DA and generates a data inversion signal INV corresponding to the number of inversion bits. The display data DA is subjected to primary inversion control in accordance with the data inversion signal INV by the data primary inversion circuit 15 of the receiver 10 and transferred to the data capturing circuit 30 together with the data inversion signal INV. The display data DA and the data inversion signal INV transferred to the data capturing circuit 30 are transferred to the OD00-OD05, OD10-OD15, OD20-OD25 and OINV terminals via the internal wirings 31 and 32, and the data 2 It is transferred to the next inversion circuit 33. The display data DA is subjected to secondary inversion control in accordance with the data inversion signal INV by the data secondary inversion circuit 33 and transferred to the data register 34. At this time, the display data DA is subjected to secondary inversion control in accordance with the data inversion signal INV immediately before being input to the data register 34, so that the inversion frequency of the display data DA in the internal wiring 31 is reduced and the internal wiring 31. EMI noise and current consumption can be reduced.

  As shown in FIG. 7, the receiver 10 of the data driver 4-2 functions as a CMOS receiver as each RSDS receiver 11a, 11b of the data driver 4-2 becomes inoperative and is bypassed. Accordingly, the clock signal CK, the data inversion signal INV, and the display data DA are transferred from the data driver 4-1 to the data driver 4-2. In the data driver 4-2, the clock signal CK is transferred to the OCK terminal via the shift register 20. The display data DA is transferred to the data fetch circuit 30 together with the data inversion signal INV. The display data DA and the data inversion signal INV transferred to the data capturing circuit 30 are transferred to the OD00-OD05, OD10-OD15, OD20-OD25 terminals and the OINV terminal as well as the data 2 similarly to the data driver 4-1. It is transferred to the next inversion circuit 33. The display data DA is transferred to the data register 34 in the same manner as the data driver 4-1, so that EMI noise and current consumption in the internal wiring 31 can be reduced.

  The third and subsequent data drivers 4-3,..., 4-10 function in the same manner as the data driver 4-2, and the clock signal CK and the display data DA are data drivers 4-3,. Are sequentially transferred through the CMOS interface circuit. Further, since the RSDS receivers 11a and 11b of the data drivers 4-2, 4-3,..., 4-10 on and after the second stage are in an inoperative state, current consumption at these receivers can be reduced.

  Next, a timing operation until the display data DATA for the data driver 4-3 is input to the data driver 4-1 and transferred to the data driver 4-3 will be described with reference to FIG. For example, a clock signal CKN / CKP is input to the data driver 4-1 as a 75 MHz RSDS signal at the timing shown in FIG. 10A, and the display data DN / DP is displayed in synchronization with the clock signal CKN / CKP. It is input at the timing shown in FIG. Corresponding to the 259th clock signal CKN / CKP shown in FIG. 10A, the display data DN / DP for the outputs S1 to S3 of the data driver 4-3 shown in FIG. , Corresponding to the 260th clock signal CKN / CKP, the display data DN / DP for the outputs S4 to S6 of the data driver 4-3 are input. Further, the start signal STH1 is input to the data driver 4-1 at a timing earlier than the drawing, and in FIG. 10B, the ISTH terminal is at the “L” level.

The clock signal CKN / CKP is divided by 2 by the receiver 10 in the data driver 4-1 to become a 37.5 MHz clock signal CK 1 (not shown), transferred in the data driver 4-1, and used as the clock signal CK 2. As shown in FIG. 10D, the clock signal CKN / CKP is input to the data driver 4-2 with a delay of t = t _P1 (for example, t _P1 = 15 ns). The display data DN / DP is divided by 2 by the receiver 10 in the data driver 4-1, and becomes display data D00-D05, D10-D15, D20-D25 (not shown) of 37.5 MHz. As shown in FIG. 10 (f), the data driver 4-2 is delayed by a delay of t = t _PLH2 (t _PHL2 ) (for example, t _PLH2 , t _PHL2 = −3 to +1 ns) from the clock signal CK2. Is input. Corresponding to the 2-1st clock signal CK2 shown in FIG. 10D, the display data DA for the outputs S1 to S3 and S4 to S6 of the data driver 4-3 shown in FIG. Similarly, the display data DA for the outputs S7 to S9 and S10 to S12 of the data driver 4-3 is input corresponding to the 2-2nd clock signal CK2. Further, the start signal STH1 is transferred through the data driver 4-1, and is input to the data driver 4-2 as the start signal STH2 at a timing earlier than shown in the figure. In FIG. 10E, the ISTH terminal is “L” level.

The clock signal CK2 is transferred in the data driver 4-2, and the clock signal CK3 is data with a delay of t = t _P2 (for example, t _P2 = 15 ns) from the clock signal CK2, as shown in FIG. Input to the driver 4-3. The start signal STH2 is transferred through the data driver 4-2, and is used as the start signal STH3. The leading edge of the delay of t = tPLH1 (for example, tPLH1 = −3 to +1 ns) from the trailing edge of the 3-1st clock signal CK3. The delay time t = tPHL1 (for example, tPHL1 = −3 to +1 ns) is input from the rear edge of the 3-2nd clock signal CK3. The display data DA is transferred in the data driver 4-2 and is input to the data driver 4-3 with a delay of t = t _PLH2 (t _PHL2 ) from the clock signal CK 3 as shown in FIG. 10 (i). Corresponding to the 3-3rd clock signal CK3 shown in FIG. 10G, the display data DA for the outputs S1 to S3 and S4 to S6 of the data driver 4-3 shown in FIG. Similarly, display data DA for the outputs S7 to S9 and S10 to S12 of the data driver 4-3 is input corresponding to the 3-4th clock signal CK3.

  As described above, in the data driver 4-1, to which the display data DN / DP including the RSDS signal is input, the display data DN / DP is converted into the display data DA including the CMOS signal by the receiver 10. Then, the data inversion signal INV is generated by the internal receiver 10, and the display data DA converted into the CMOS signal is subjected to primary inversion control according to the data inversion signal INV and then transferred to the data fetch circuit 30. . The display data DA subjected to primary inversion control is subjected to secondary inversion control according to the data inversion signal INV immediately before being transferred to the internal register 31 and input to the data register 34 in order to return to the original logic. . Thereby, the inversion frequency of the display data DA in the internal wiring 31 is reduced, and EMI noise and current consumption in the internal wiring 31 can be reduced.

  In the data drivers 4-2, 4-3,..., 4-10 to which display data DA composed of CMOS signals is input, the display data DA subjected to the primary inversion control by the data driver 4-1 is directly passed through the receiver 10. The data is transferred to the data capturing circuit 30. The display data DA transferred to the data fetch circuit 30 is transferred to the internal wiring 31 and immediately before being input to the data register 34, the data inversion signal generated by the data driver 4-1 to restore the original logic. Secondary inversion control according to INV is performed. Thereby, also in the data drivers 4-2, 4-3,..., 4-10, the inversion frequency of the display data DA in the internal wiring 31 is reduced, and EMI noise and current consumption in the internal wiring 31 can be reduced.

  Next, a second example of the liquid crystal display device according to the present invention will be described with reference to FIG. In addition, the same code | symbol is attached | subjected about the same thing as FIG. 1, and the description is abbreviate | omitted. 1 differs from the liquid crystal display device of FIG. 1 in that it has a controller 102 and a data driver 104 instead of the controller 2 and the data driver 4, and the controller 102 to the first stage data driver 104-1 have a small amplitude differential signal system. Instead of the RSDS interface, the display data DN / DP and the clock signal CKN / CKP consisting of a min-LVDS signal are transferred using a min-LVDS (registered trademark of TEXAS INSTRUMENTS) system as an interface. . The data driver 104 can use the same circuit configuration as that of the data driver 4 shown in FIG. 2 except that a min-LVDS receiver is used instead of the RSDS receivers 11a and 11b of the receiver 10. This is the same, and illustration and description are omitted.

Next, a third example of the liquid crystal display device according to the present invention will be described with reference to FIG. In addition, the same code | symbol is attached | subjected about the same thing as FIG. 1, and the description is abbreviate | omitted. A difference from the liquid crystal display device of FIG. 1 is that the controller 202 and the data driver 204 are provided instead of the controller 2 and the data driver 4, and the first-stage data driver 204-1 from the controller 202 has a small amplitude differential signal system. as an interface, instead of the RSDS interface, CMADS: scheme the display data DN / DP and clock signal consisting CMADS signal using the interface (C urrent M ode a dvanced D ifferential S ignaling NEC trademark of (Ltd.)) CKN / CKP is transferred. The data driver 204 can use the same circuit configuration as that of the data driver 4 shown in FIG. 2 except that a CMADS receiver is used instead of the RSDS receivers 11a and 11b of the receiver 10. Therefore, illustration and description are omitted.

  In the first to third embodiments, as a data driver, the display data input can be switched between one small amplitude differential signal input of the RSDS signal, min-LVDS or CMADS signal and the CMOS signal input. However, the present invention is not limited to this, and only one of RSDS signal, min-LVDS, or CMADS signal can be input, or only a CMOS signal can be input. In the case of a data driver that can input only one of the RSDS signal, min-LVDS, or CMADS signal, the data driver is the same as the equivalent circuit when the IFM of the receiver 10 shown in FIG. 6 is “H”. What is necessary is just to set it as the circuit structure which has an inversion signal generation circuit and a data primary inversion circuit. In the case of a data driver capable of inputting only a CMOS signal, the generation of the data inversion signal INV and the data primary inversion control are performed similarly to the equivalent circuit when the receiver of the data driver is IFM = “L” of the receiver 10 shown in FIG. What is necessary is just to set it as the circuit structure which has the input terminal of the data inversion signal INV performed outside a data driver for data secondary inversion control. In this case, the generation of the data inversion signal INV and the data primary inversion control may be performed by the controller. In a liquid crystal display device using a data driver capable of inputting only one of the RSDS signal, min-LVDS or CMADS signal or a data driver capable of inputting only a CMOS signal, not only the above-mentioned inter-chip data transfer system but also a controller. The display data can be transferred to each data driver in parallel. Further, instead of the RSDS signal, min-LVDS, and CMADS signal, other small amplitude differential signals can be applied. Although the liquid crystal display device has been described as an example, the present invention is not limited to this, and the present invention can also be used for other display devices in which display data is transferred through an internal wiring and taken into a data register. Furthermore, the present invention is not limited to a display device, and can be used for other electronic devices in which data is transferred through an internal wiring and taken into a data register.

1 is a block diagram showing a schematic configuration of a liquid crystal display module of a liquid crystal display device according to the present invention. The block diagram which shows schematic structure of the data driver 4 of one Embodiment of this invention. The circuit diagram which shows the receiver 10 used for the data driver 4 shown in FIG. The circuit diagram which shows the bypass circuit 12 used for the receiver 10 shown in FIG. FIG. 4 is a circuit diagram showing a data inversion signal generation circuit 14 used in the receiver 10 shown in FIG. 3. The figure which shows the operation state when IFM = "H" of the receiver 10 shown in FIG. The figure which shows the operation state when IFM = "L" of the receiver 10 shown in FIG. FIG. 3 is a circuit diagram showing a data capturing circuit 30 used in the data driver 4 shown in FIG. 2. FIG. 2 is a diagram for explaining transfer of various signals between a controller 2 and a data driver 4 shown in FIG. 1. 10 is a timing chart for explaining interchip transfer of a clock signal and display data between the data drivers shown in FIG. The block diagram which shows schematic structure of the liquid crystal display module of the 2nd example of the liquid crystal display device which concerns on this invention. The block diagram which shows schematic structure of the liquid crystal display module of the 3rd example of the liquid crystal display device which concerns on this invention.

Explanation of symbols

1 Liquid crystal panel 2, 102, 202 Controller (control circuit)
4, 104, 204 Data driver (data side drive circuit)
10 Receiver (Receiver)
11a, 11b RSDS receiver 12a, 12b Bypass circuit 13a, 13b Frequency dividing circuit 14 Data inversion signal generation circuit 15 Data primary inversion circuit 16a, 16b, 16c Selector 17 Data inversion detection circuit 18 First determination circuit 19 Second determination circuit 30 Data capture circuit 31 Internal wiring 33 Data secondary inversion circuit 34 Data register 40 Latch

Claims (4)

A display panel comprising: a receiving unit that receives display data input from outside the chip; a data capturing circuit that captures display data output from the receiving unit; and a latch that stores display data output from the data capturing circuit A semiconductor integrated circuit device for driving,
The data capturing circuit includes an internal wiring for transferring display data output from the receiving unit, a data inversion circuit for inverting the logic level of display data transferred by the internal wiring in response to a data inversion signal, And a data register for storing the inverted display data output from the data inversion circuit. The internal lines are divided into first, second and third groups;
The data inversion circuit includes at least first to sixth EXOR circuits,
The first and fourth EXOR circuits receive display data and the data inversion signal transferred by the internal wiring of the first group, and the second and fifth EXOR circuits receive the second group. The display data transferred by the internal wiring and the data inversion signal are input, and the third and sixth EXOR circuits receive the display data and the data inversion signal transferred by the internal wiring of the third group. Enter
The data register latches the outputs of the first to third EXOR circuits in response to a first control signal, and the outputs of the fourth to sixth EXOR circuits in response to a second control signal. 2. A semiconductor integrated circuit device for driving a display panel according to claim 1, wherein the semiconductor integrated circuit device is latched.   The reception unit includes at least one reception circuit that receives a differential signal as the display data, a data inversion signal generation circuit that generates the data inversion signal by comparing display data before and after being output from the reception circuit, 3. A semiconductor integrated circuit device for driving a display panel according to claim 2, further comprising a second data inversion circuit for inverting the logic level of display data output from the receiving circuit in response to the data inversion signal. .   The receiver includes a first bypass circuit that bypasses a signal input from the outside of the chip as the data inversion signal and transfers the signal to the data capturing circuit when activated, and an outside of the chip as the display data 3. A semiconductor integrated circuit device for driving a display panel according to claim 2, further comprising: a second bypass circuit that bypasses the CMOS signal input from the input circuit when the CMOS signal is activated and transfers the CMOS signal to the data fetch circuit. .

Images