KR100405024B1 - Liquid Crystal Display Apparatus with 2 Port REV Device and Driving Method Thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a two-port data polarity inverter for reducing current consumption and improving EMI characteristics by reducing data transition in half and a driving method thereof.

A liquid crystal display device according to the present invention comprises: a liquid crystal panel for displaying an image corresponding to a video signal; A system driver for generating a control signal and a compressed data signal; A timing controller for generating and outputting timing signals for driving signals input from a system driver to the liquid crystal panel; A gate driver and a data driver which receive the timing signal from a timing controller and display an image on the liquid crystal panel in response to the data; A data alignment unit for causing the timing controller to supply the data signal to the data driver, a timing control signal generation unit for inputting a control signal to supply the timing signal to the gate driver and the data driver, and a control signal A polarity control signal generator for inputting the polarity control signal to the gate driver and the data driver; The polarity control signal generation unit checks whether the polarity of the liquid crystal is reversed and inverts the polarity corresponding thereto, and the first data polarity inversion driver which checks the data transition of odd-numbered data and inverts the polarity of the data accordingly. And a second data polarity inversion driving unit which checks the data transition of the even-numbered data and inverts the polarity of the data accordingly.

According to the present invention, by using a 2-port REV signal that checks and inverts each data transition of even-numbered and odd-numbered data, current consumption and EMI can be reduced in a high resolution model.

Description

Liquid Crystal Display Apparatus with 2 Port REV Device and Driving Method Thereof}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display having a two-port data selector for reducing current consumption and reducing EMI by reducing data transition in half, and a driving method thereof.

In general, a liquid crystal display (LCD) displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. An active matrix liquid crystal display device in which switching elements are formed for each liquid crystal cell is suitable for displaying moving images. As a switching element used in an active matrix liquid crystal display device, a thin film transistor (hereinafter, referred to as TFT) is mainly used. Such active matrix type liquid crystal display devices can be miniaturized compared to CRTs, and can be used not only for personal computers and notebook computers, but also for office automation devices such as photocopiers, mobile devices such as cell phones and pagers. It is widely used.

As shown in FIG. 1, a driving device of a liquid crystal display device includes a system driver 1 for converting an analog signal into digital video data, and a data driver for supplying a data signal to data lines DL of the liquid crystal panel 6. 3), a gate driver 5 for sequentially driving the gate lines GL of the liquid crystal panel 6, a timing controller 2 for controlling the data driver 3 and the gate driver 5; A gamma voltage generator 4 for supplying gamma voltage to the data driver 3 is provided.

Liquid crystal is injected between the two glass substrates, and the liquid crystal panel 6 is formed such that the gate lines GL and the data lines DL are orthogonal to each other on the lower glass substrate. A TFT for selectively supplying an image input from the data lines DL to the liquid crystal cell Clc is formed at the intersection of the gate lines GL and the data lines DL. For this purpose, the TFT has a gate terminal connected to the gate line GL, and a source terminal connected to the data line DL. The drain terminal of the TFT is connected to the pixel electrode of the liquid crystal cell Clc.

The system driver 1 converts an analog input video signal into a digital video signal suitable for the liquid crystal panel 6 and detects a synchronization signal included in the video signal. A low voltage differential signal (LVDS) interface and a TTL interface are mainly used for data and control signal transmission of the system driver 1. In addition, these interface functions are collected and used together with the timing controller 2 in a single chip. The LVDS compresses several pieces of data in one line and is input to the timing controller 2. In each line where data is transmitted, an electric field is formed that is induced by the flow of current, and the radiation of the electric field causes noise in signals transmitted to adjacent lines, causing electromagnetic waves (EMI) to interfere with the normal operation of the component. . This electromagnetic wave phenomenon lowers the voltage of the data signal. In order to solve the electromagnetic wave phenomenon, a method of transmitting a differential signal has been proposed, and a differential signal is a signal having a relationship as shown in FIG. 2 having the same amplitude and opposite phase. When adjacent lines are used to transmit positive and negative signals S + and S- at the same time, the electric field generated in each adjacent line is extinguished by interaction. Specifically, when the positive signal S + is converted from the low level to the high level, the negative signal S− is converted from the high level to the low level. At this time, the directions of the currents flowing in the two lines are opposite to each other, and the electric field is canceled by forming the opposite direction of the electric field by the Fleming law. The offset of the electric field is minimized by the offset electric field. Accordingly, the data signal can be supplied to the timing controller 2 at the original voltage.

The timing controller 2 supplies the data signals of red (R), green (G), and blue (B) from the system driver 1 to the column driver 3. In addition, the timing controller 2 generates the dot clock Dclk and the gate start pulse GSP using the horizontal / vertical synchronization signals H and V input from the system driver 1 to generate the data driver 3 and the data driver 3. The gate driver 5 is timing controlled. The dot clock Dclk is supplied to the data driver 3, and the gate start pulse GSP is supplied to the gate driver 5.

The gate driver 5 shifts the shift register to sequentially generate the scan pulse in response to the gate start pulse GSP input from the timing controller 2, and shifts the voltage of the scan pulse to a level suitable for driving the liquid crystal cell. Level shifter or the like. In response to the scan pulse input from the gate driver 5, video data on the data line DL is supplied to the pixel electrode of the liquid crystal cell Clc by the TFT.

The dot clock Dclk is input to the data driver 3 together with data signals of red (R), green (G), and blue (B) from the timing controller 2. The data driver 3 latches the red (R), green (G), and blue (B) digital video data in synchronization with the dot clock Dclk, and then corrects the latched data in accordance with the gamma voltage Vγ. Done. The data driver 3 converts the data corrected by the gamma voltage Vγ into analog data and supplies the data lines DL by one line.

The gamma voltage generator 4 generates a gamma voltage Vγ corresponding to the gray scale value of the data in consideration of the electrical and optical characteristics of the liquid crystal panel. This gamma voltage Vγ is a voltage divided by the gamma voltage generator 4 corresponding to the gradation level. Therefore, the gamma voltage Vγ generated from the gamma voltage generator 4 is set to have a different voltage size in response to the gray level value selected in the expressible range.

3 illustrates the timing controller of FIG. 1 in detail.

Referring to FIG. 3, the timing controller 2 generates predetermined signals for driving the liquid crystal display using the LVDS, vertical and horizontal synchronization signals H and V input from the system driver 1.

The LVDS supplies a data signal of red (R), green (G), and blue (B) to the data driver 3 through the data sorting unit 12.

The vertical and horizontal synchronization signals H and V supply timing control signals to the data driver 3 and the gate driver 5 through the timing control signal generator 14.

The control signals necessary for the data driver 3 among these timing control signals include a source sampling clock ("SSC"), a source output enable ("SOE"), Source Start Pulse (hereinafter referred to as "SSP").

Control signals required for the gate driver 5 include a gate shift clock (hereinafter referred to as "GSC"), a gate output enable (hereinafter referred to as "GOE"), and a gate start pulse (gate start). Pulse: hereinafter referred to as "GSP").

The horizontal and vertical synchronization signals H and V supply the polarity control signal to the data driver 3 and the gate driver 5 through the polarity control signal generator 16.

The polarity control signals include liquid crystal polarity inversion (hereinafter referred to as "POL") and data polarity inversion (hereinafter referred to as "REV").

The liquid crystal display device supplies data signals and control signals from the system driver 1 to the data driver 3 and the gate driver 5 through the timing controller 2.

4A is a view showing in detail the REV transmitter in the timing controller 2 according to the prior art.

Referring to FIG. 4A, the REV transmitter includes a data transition checker 30 that checks a data transition, and an REV signal adder 32 that determines an output level by determining the number of signals whose polarity of data changes according to the data transition. And a REV signal output section 34 for receiving a signal from the data transition check section 30 and the REV signal summing section 32 to generate a signal for inverting the output data.

The data transition checker 30 is composed of two flip-flops 36 and 38 and an exclusive OR (40) gate. The data transition checker 30 compares the current data flip-flop 36 with the previous data flip-flop 38 to check the change of the high 1 and the low 0 of the data. If there is each data transition, the output of the data transition checker 30 is output high (1), and if there is no transition, output is low (0). At this time, the data are sequentially compared regardless of the even number (EVEN) and the odd number (ODD).

The REV signal adder 32 adds the number of data having data transitions through the data transition checker 30 to 36 even and odd data of each of R, G, and B data. 42, 44). At this time, it is checked through the Majority Detector 46 whether the number of output cuts 1 when there is a data transition exceeds 18, which is half of the total number of R, G, and B data. If the number of the high (1) outputs with data transitions by the majority detector 46 exceeds 18, which is half of 36 bits, the REV is high (1) and the number of high (1) is 18 or less. REV is output low (0).

The REV signal output unit 34 outputs a signal for inverting the output data when the output REV of the REV signal adder 32 is high (1) using a 2x1 multiplexer 48, 50. . That is, the REV signal output unit 34 inverts the output data to reduce the amount of data transition when the number of data transitions is more than half so that the output data is shifted by only {36- (data transition amount of 18 or more)}. Sends data polarity inversion signal.

Thus, in the low (0) state, the input data is recognized as it is, and in the high (1) state, the REV signal for inverting and recognizing the input data is input to the data driver 3.

4B is a diagram schematically illustrating a REV receiver in a data driver.

Referring to FIG. 4B, the REV receiver 35 includes 2 × 1 multiplexers 48 and 50. Thus, the input side of the multiplexer is connected such that the signal output through the multiplexer (48, 50) of the REV signal output unit 34 in FIG. 4A is input as it is, and the other side is the REV signal output unit ( The signal from 34 is inverted and inputted. REV signals input to the multiplexers 48 and 50 are selected from the normal and inverted signals by the high (1) and low (0) signals from the majority detector 46 of the REV signal summing unit 32, thereby providing data drivers. It is input to the latch circuit constituting (3) to invert the R, G, and B data polarities.

5 is a view briefly showing a REV driving method according to the prior art.

Referring to FIG. 5, the number of data transitions is reduced by comparing current clock data with previous clock data in 36 bits of even and odd data. That is, the clock data CLK 1 is compared with the clock data CLK 2 to check whether the data is transitioned.

This driving method compares the transitions before and after 36-bit data coming into the liquid crystal module from the system as a single port, and inverts when the value is greater than or equal to 18 bits by the majority detector 46 and exports the existing data when the value is less. Since the REV is selected in response to the data transition of, a large current consumption and a lot of electromagnetic waves are generated.

Accordingly, an object of the present invention is to provide a liquid crystal display device having a two-port data polarity inverter that reduces current consumption and improves electromagnetic interference (EMI) by reducing data transition by half using two-port REV in a timing controller driving method. It is to provide a driving method.

1 is a block diagram of a general liquid crystal display device.

FIG. 2 is a diagram illustrating a change amount of a gate high voltage and a common voltage with time applied to the thin film transistor illustrated in FIG. 1.

FIG. 3 is a detailed view of the timing controller in FIG. 1. FIG.

4A is a detailed view of a REV transmitter in a timing controller 2 according to the prior art.

FIG. 4B is a detailed view of a REV receiver in a data driver according to the REV transmitter in FIG. 4A; FIG.

5 is a view simply showing a REV driving method according to the prior art.

6 is a block diagram showing a liquid crystal display device according to the present invention;

7 is a detailed view of the timing controller shown in FIG. 6;

8A is a detailed view of a REV transmitter in a timing controller according to the first embodiment of the present invention.

FIG. 8B is a detailed view of the REV receiver in the data driver according to the REV transmitter in FIG. 8A; FIG.

FIG. 9 is a view simply showing a REV driving method according to the present invention shown in FIG.

10 shows the "H" pattern used in the EMI test.

Fig. 11 is a diagram showing an output state of data when REV is Off.

12 is a view showing a comparison of the data output form when using a one-port REV signal according to the prior art.

13 is a view showing a comparison of the data output form when using the two-port REV signal according to the present invention.

14A is a detailed view of a REV transmitter in a timing controller according to a second embodiment of the present invention.

FIG. 14B is a detailed view of a REV receiver in a data driver according to the REV transmitter in FIG. 14A; FIG.

In order to achieve the above object, a driving device of a liquid crystal display device having a two-port data polarity inverter according to the present invention includes a liquid crystal panel for displaying an image corresponding to a video signal; A system driver for generating a control signal and a compressed data signal; A timing controller for generating and outputting timing signals for driving signals input from the system driver to the liquid crystal panel; A gate driver and a data driver configured to receive the timing signal from the timing controller and display an image on the liquid crystal panel in response to the data; A data alignment unit for causing the timing controller to supply the data signal to the data driver, a timing control signal generator for inputting the control signal to supply the timing signal to the gate driver and the data driver, and the control A polarity control signal generator for inputting a signal to supply a polarity control signal to the gate driver and the data driver; The polarity control signal generation unit checks whether the polarity of the liquid crystal is reversed and inverts the polarity corresponding thereto, and the first data polarity inversion that checks the data transition of the odd-numbered data and inverts the polarity of the data accordingly. And a second data polarity inversion driver which checks the data transition of the even-numbered data and inverts the polarity of the data correspondingly.

In this case, the first data polarity inversion driving unit is configured to determine an output level by identifying a first data transition unit for checking data transitions of the odd-numbered data and the number of signals whose polarity of data changes according to the data transitions. And a first data polarity inversion signal output section for receiving a signal from the first data transition check section and the first data polarity inversion signal adder and outputting a signal for inverting output data. Features.

The second data polarity inversion driving unit includes a second data transition unit for checking data transitions of the even-numbered data, and second data for determining an output level by grasping the number of signals whose polarities of the data change according to the data transitions. And a second data polarity inversion signal output unit configured to receive a signal from the second data transition check unit and the second data polarity inversion signal adder and output a signal for inverting output data. do.

A method of driving a liquid crystal display device having a two-port data polarity invertor according to the present invention is a liquid crystal display having first and second data polarity inversion driving units, and inputs odd-numbered data bits to the first data polarity inversion driving unit. Comparing the data transitions so that the polarities of the odd-numbered data are reversed, and inputting even-numbered data bits to the second data polarity inversion driving unit and comparing the data transitions so that the polarities of the even-numbered datas are reversed. Characterized in that it comprises a step.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device having a two-port data polarity inverter, comprising: a liquid crystal display device having first and second data polarity inversion drivers, wherein the data bits input to the polarity inversion driver are divided in half. Dividing into first and second data bits, inputting first data bits to the first data polarity inversion driving unit and comparing the data transitions thereof to invert the polarity of the first data, and the second data polarity. And inputting second data bits to the inversion driver and comparing the data transitions thereof to invert the polarity of the second data.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 6 to 14B.

6 is a block diagram illustrating a liquid crystal display according to the present invention.

Referring to FIG. 6, a driving apparatus of a liquid crystal display according to the present invention includes a system driver 51 for converting an analog signal into digital video data and a data signal on data lines DL of the liquid crystal panel 56. A data driver 53 for supplying, a gate driver 55 for driving the gate lines GL of the liquid crystal panel 56 sequentially, and a data driver 53 and a gate driver 55 for controlling the data driver 53 and the gate driver 55. A timing controller 52 and a gamma voltage generator 54 for supplying a gamma voltage to the data driver 53 are provided.

Liquid crystal is injected between the two glass substrates, and the liquid crystal panel 56 is formed such that the gate lines GL and the data lines DL are orthogonal to each other on the lower glass substrate. A TFT for selectively supplying an image input from the data lines DL to the liquid crystal cell Clc is formed at the intersection of the gate lines GL and the data lines DL. To this end, the TFT has a gate terminal connected to the gate line GL, and a source terminal connected to the data line DL. The drain terminal of the TFT is connected to the pixel electrode of the liquid crystal cell Clc.

The system driver 51 converts the analog input video signal into a digital video signal suitable for the liquid crystal panel 56 and detects a synchronization signal included in the video signal. The LVDS (Low Voltage Differential Signal) interface and the TTL interface are mainly used for data and control signal transmission of the system driver 51. In addition, these interface functions are collected and used together with the timing controller 52 in a single chip. The LVDS compresses several pieces of data in one line and inputs the timing controller 52.

The timing controller 52 supplies the red (R), green (G), and blue (B) data signals from the system driver 51 to the data driver 53. In addition, the timing controller 52 generates the dot clock Dclk and the gate start pulse GSP by using the horizontal / vertical synchronization signals H and V input from the system driver 1 to generate the data driver 53 and the data driver 53. The timing of the gate driver 55 is controlled. The dot clock Dclk is supplied to the data driver 53, and the gate start pulse GSP is supplied to the gate driver 55.

The gate driver 55 shifts the shift register to sequentially generate the scan pulse in response to the gate start pulse GSP input from the timing controller 52, and shifts the voltage of the scan pulse to a level suitable for driving the liquid crystal cell. Level shifter or the like. In response to the scan pulse input from the gate driver 55, video data on the data line DL is supplied to the pixel electrode of the liquid crystal cell Clc by the TFT.

The dot driver Dclk is input to the data driver 53 together with data signals of red (R), green (G), and blue (B) from the timing controller 52. The data driver 53 latches the red (R), green (G), and blue (B) digital video data in synchronization with the dot clock Dclk, and then corrects the latched data in accordance with the gamma voltage Vγ. Done. The data driver 53 converts the data corrected by the gamma voltage Vγ into analog data and supplies the data lines DL by one line.

The gamma voltage generator 54 generates a gamma voltage Vγ corresponding to the gray scale value of the data in consideration of the electrical and optical characteristics of the liquid crystal panel. The gamma voltage Vγ is a voltage divided by the gamma voltage generator 54 corresponding to the gradation level. Therefore, the gamma voltage Vγ generated from the gamma voltage generator 54 is set to have a different voltage size in response to the gray level value selected in the expressible range.

7 illustrates a timing controller according to the present invention in detail.

Referring to FIG. 7, the timing controller 52 generates predetermined signals for driving the liquid crystal display using the LVDS, vertical and horizontal synchronization signals H and V input from the system driver 51.

The LVDS supplies data signals of red (R), green (G), and blue (B) to the data driver 53 through the data alignment unit 62.

The vertical and horizontal synchronization signals H and V supply timing control signals to the data driver 53 and the gate driver 55 through the timing control signal generator 64.

Among the timing control signals, control signals required for the data driver 53 include SSC, SOE, and SSP.

Control signals required for the gate driver 55 include GSC, GOE, and GSP.

The horizontal and vertical synchronization signals H and V supply the polarity control signal to the data driver 53 and the gate driver 55 through the polarity control signal generator 66.

Polar control signals include POL, REV 1, and REV 2. In this case, REV 1 determines whether to reverse polarity through the data transition of current data and previous data in even-numbered data, and REV 2 determines polarity-reversal through data transition of current data and previous data in odd-numbered data. Is to decide.

The liquid crystal display device supplies data signals and control signals from the system driver 51 to the data driver 53 and the gate driver 55 through the timing controller 52.

8A is a diagram illustrating in detail a REV transmitter in a timing controller according to a first embodiment of the present invention.

Referring to FIG. 8A, the REV transmitter transmits a polarity control signal by checking a data transition of odd-numbered data and outputs a polarity control signal by checking a data transition of even-numbered data. 2 drive part 80 is provided.

First, the REV 1 driver 70 determines the output level by identifying a first data transition checker 72 that checks data transitions of odd-numbered data, and the number of signals whose polarities of data change according to the data transitions. A first signal adding section 74, a first data transition checking section 72, and a REV 1 signal output section 76 for receiving a signal from the REV 1 signal adding section 74 and outputting a signal for inverting the output data. do.

The first data transition check unit 72 is composed of two flip-flops 71 and 73 and an exclusive OR gate 75. The first data transition checker 72 compares each data input to the current data flip-flop 71 and the previous data flip-flop 73 and checks the change of the high 1 and the low 0 of the data. If there is a data transition, the output of the first data transition check unit 72 is high (1), and if there is no transition, it is output low (0). At this time, the data are compared sequentially regardless of the even and odd numbers.

The REV 1 signal adder 74 adds the number of data having data transitions through the first data transition checker 72 for each of the odd (odd) -th data of each of R, G, and B, respectively. , 77). At this time, it is checked whether the number of the high (1) outputs when there is a data transition exceeds 9, which is half of the total number of odd R, G, and B data. If the number of highs (1) exceeds 9, REV1 is high (1), and if it is 9 or less, it is low (0).

The REV 1 signal output unit 76 uses a 2x1 multiplexer 79 to output a signal for inverting the output data when the output REV of the REV 1 signal adder 74 is high (1). 53). That is, to reduce the amount of transition when the number of data transitions exceeds half (9), the REV 1 signal output unit 76 inverts the output data and outputs only {18- (number of data transitions of 9 or more)}. Make a transition.

As a result, when the REV 1 signal is in the low (0) state, the input data is recognized as it is, and when the high (1) signal is input to the data driver 53 to invert the recognition of the input data.

The REV 2 driver 80 checks the data transitions of even-numbered data, and the REV 2 signal for determining an output level by grasping the number of signals whose polarity of data changes according to the data transitions. An adder 84, a second data transition checker 82, and a REV 2 signal adder 84 receive a signal and output a signal for inverting output data.

The second data transition checker 82 is composed of two flip-flops 81 and 83 and an XOR gate 85. The second data transition checker 82 compares each data input to the current data flip-flop 81 and the previous data flip-flop 83 and checks the change of the high 1 and the low 0 of the data. If there is a data transition, the output of the second data transition checker 82 is high (1), and if there is no transition, it is output low (0). At this time, the data are compared sequentially regardless of the even and odd numbers.

The REV 2 signal adder 84 adds the number of data having data transitions through the second data transition checker 82 for each of the 18th even data of each of R, G, and B. , 87). At this time, it is checked whether the number of the high (1) outputs when there is a data transition exceeds 9, which is half of the total number of R, G, and B data. If the number of highs (1) exceeds 9, REV 2 is high (1), and if it is 9 or less, it is low (0).

The REV 2 signal output unit 86 uses a 2x1 multiplexer 89 to output a signal for inverting the output data when the output REV 2 of the REV signal adding unit 84 is high (1). 53). In other words, when the number of data transitions exceeds half (9), the output data is inverted to reduce the amount of transitions so that the output data is shifted by only {18- (number of data transitions of 9 or more)}. .

As a result, when the REV 2 signal is in the low (0) state, the input data is recognized as it is, and in the case of the high (1), the signal to invert the input data to be recognized is input to the data driver 53.

FIG. 8B is a detailed view illustrating a REV receiver in a data driver according to the REV transmitter of FIG. 8A.

Referring to FIG. 8B, the REV receivers 90 and 92 include 2x1 multiplexers 79 'and 89'. Thus, one side of the input side of the multiplexers 79 'and 89' is connected so that the signal output through the multiplexers 79 'and 89' of the REV signal output units 76 and 86 in FIG. 8A is input as it is. The other side is connected to invert the signal from the REV signal output units 76 and 86 in FIG. 8A. REV signals input to the multiplexers 79 and 89 are divided by the high and low signals from the majority detectors 78 and 88 of the REV signal adders 74 and 84, thereby suppressing the normal and inverted signals. Selected and input to the latch circuit constituting the data driver 53 to reverse the polarity of the R, G, B data.

FIG. 9 is a diagram briefly showing a method of driving a REV according to the present invention shown in FIG. 8.

Referring to FIG. 9, the driving method according to the present invention divides the even-numbered data and the odd-numbered data and compares each data.

Here, A compares the even-numbered first clock data and the second clock data, and B represents the comparison of the odd-numbered first clock data and the second clock data.

As a result, by using the REVs 1 and 2 shown in FIG. 8, 18 bits of data can be compared to further reduce the probability of checking the data transition.

This can be predicted through the " H " display state and the output form of the EMI pattern shown in Figs.

FIG. 10 is a diagram illustrating a "H" pattern used for an EMI test. FIG.

Referring to FIG. 10, the region in which the "H" pattern is shown includes a first column (I) of two columns in which all cells display a gray form in a horizontal direction, and three columns in which gray and white patterns alternate between two cells. It consists of a 2nd form (II) and the 3rd form (III) of one row corresponding to the column comprised in the form of the white bar among the "H" patterns.

The worst form of EMI is the third form, and the effects thereof are as follows.

11 to 13 are diagrams illustrating data transitions in each cell based on the third aspect of FIG. 10.

First, FIG. 11 is a diagram illustrating an output state of data when REV is Off. In this case, the gray pattern is "1" and the white pattern is "0" based on the left side.

When even-numbered data and odd-numbered data are divided and sequentially input to the Dn cell, data output appears as shown in FIG. 11. This may be represented as an output waveform having a frequency of about 16 MHz through the data transition form.

12 is a view showing a comparison of the data output form when using a one-port REV signal according to the prior art.

Referring to FIG. 12, it can be seen that data transition is reduced rather than when the REV signal shown in FIG. 11 is turned off. This may result in an output waveform of 4 MHz lower than the data output of FIG. 11 of 16 MHz.

13 is a view showing a comparison of the data output form when using the two-port REV signal according to the present invention.

Referring to FIG. 13, even-numbered data and odd-numbered data are distinguished by using the REV generator shown in FIG. 8, and the transition of each of these data is compared.

As shown in FIG. 13, it can be seen that the form of the data output by comparing the transition of each data has no change in data. This is represented by a DC output waveform. This greatly reduces EMI characteristics and current consumption.

FIG. 14A is a diagram illustrating in detail a REV transmitter in a timing controller according to a second embodiment of the present invention, in which data inputted to the timing controller is divided into N blocks and inputted thereto, and then data polarity inversion is shown. In particular, here, the driving is performed by dividing all data bits into two.

Referring to FIG. 14A, the REV transmitter divides data into two bits and checks the data transition of the first output data to output the polarity control signal, and the REV 1 driver 100 checks the data transition of the second output data. REV 2 driver 110 for outputting a polarity control signal.

First, the REV 1 driver 100 determines the output level by identifying a first data transition unit 102 that checks data transitions of first output data, and the number of signals whose polarities of data change according to the data transitions. A first signal adding section 104, a first data transition checking section 102, and a REV 1 signal output section 106 for receiving a signal from the REV 1 signal adding section 104 and outputting a signal for inverting the output data. do.

The first data transition check unit 102 is composed of two flip-flops 101 and 103 and an XOR 105 gate. The first data transition checker 102 compares each data input to the current data flip-flop 101 and the previous data flip-flop 103 to check the change of the high 1 and the low 0 of the data. If there is a data transition, the output of the first data transition checker 102 is high (1), and if there is no transition, it is output low (0). In this case, the data are sequentially compared regardless of the first data and the second data.

The REV 1 signal adder 104 adds the number of data having data transitions through the first data transition checker 102 for each of 18 pieces of first output data of R, G, and B respectively. To be added. At this time, it is checked whether the number of the high (1) output when there is a data transition exceeds 9, which is half of the total number of first R, G, and B data. If the number of highs (1) exceeds 9, REV 1 is high (1), and if it is 9 or less, it is low (0).

The REV 1 signal output section 106 uses a 2x1 multiplexer 109 to output a signal for inverting the output data when the output REV of the REV signal adding section 104 is high (1). Supplies). That is, to reduce the amount of transition when the number of data transitions exceeds half (9), the REV 1 signal output unit 106 inverts the output data and outputs only {18-(number of data transitions of 9 or more)}. Make a transition.

As a result, when the REV 1 signal is in the low (0) state, the input data is recognized as it is, and when the high (1) signal is input to the data driver 53 to invert the recognition of the input data.

The REV 2 driver 110 determines the output level by identifying the second data transition unit 112 that checks the data transition of the second output data, and the number of signals whose polarity of the data changes according to the data transition. And a REV 2 signal output unit 116 for receiving a signal from the data transition checker 112 and the REV 2 signal adder 114 and outputting a signal for inverting the output data.

The second data transition checker 112 includes two flip-flops 111 and 113 and an XOR 115 gate. The second data transition checker 112 compares each data input to the current data flip-flop 111 and the previous data flip-flop 113 to check the change of the high 1 and the low 0 of the data. If there is a data transition, the output of the second data transition checker 112 is high (1), and if there is no transition, it is output low (0). In this case, the data are sequentially compared regardless of the first data and the second data.

The REV 2 signal adder 114 adds the number of data having data transitions through the second data transition checker 112 for each of 18 pieces of second output data of R, G, and B respectively. To be added. At this time, it is checked whether the number of the high (1) outputs when there is a data transition exceeds 9, which is half of the total number of R, G, and B data. If the number of highs (1) exceeds 9, REV becomes high (1), and if it is 9 or less, it becomes low (0).

The REV 2 signal output unit 116 uses a 2x1 multiplexer 109 to output a signal for inverting the output data when the output REV 2 of the REV signal adder 114 is high (1). 53). In other words, if the number of data transitions exceeds half (9), the output data is inverted to reduce the amount of transitions so that the output data is shifted by only {18-(number of data transitions of 9 or more)}.

As a result, when the REV 2 signal is in the low (0) state, the input data is recognized as it is, and when the high (1) signal is input to the data driver 53 to invert the recognition of the input data.

FIG. 14B is a diagram illustrating in detail a REV receiver in a data driver according to the REV transmitter of FIG. 14A.

Referring to FIG. 14B, the REV receivers 120 and 122 include 2 × 1 multiplexers 109 and 119. Thus, one side of the input side of the multiplexers 109 and 119 is connected so that a signal output through the multiplexers 109 and 119 of the REV signal output units 106 and 116 in FIG. 14A is input as it is, and the other side is a REV in FIG. 14A. The signals from the signal output units 106 and 116 are inverted and connected to each other. REV signals input to the multiplexers 109 and 119 are selected by the high and low signals from the majority detectors 108 and 118 of the REV signal adder 104 and 114, and the normal and inverted signals are selected. It is input to the latch circuit constituting the data driver 53 to invert the R, G, and B data polarities.

As described above, the driving device of the liquid crystal display according to the present invention uses a two-port REV signal that checks and inverts each data transition of even-numbered and odd-numbered data, thereby reducing current consumption and EMI in a high resolution model. have. In addition, by dividing the data into N pieces, each data transition of the N pieces of data can be checked and inverted.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (17)

A liquid crystal panel which displays an image corresponding to the video signal; A system driver for generating a control signal and a compressed data signal; A timing controller which generates and outputs timing signals for driving the liquid crystal panel with signals input from the system driver; A gate driver and a data driver which receive the timing signal from the timing controller and display an image on the liquid crystal panel in response to the data signal; A data alignment unit for causing the timing controller to supply the data signal to the data driver, a timing control signal generator for inputting the control signal to supply the timing signal to the gate driver and the data driver, and the control A polarity control signal generator for inputting a signal to supply a polarity control signal to the gate driver and the data driver; The polarity control signal generation unit checks the polarity of the polarity of the liquid crystal and the liquid crystal polarity inversion driving unit for inverting the polarity corresponding thereto; A first data polarity inversion driver which checks a data transition of odd-numbered data and inverts the polarity of the data correspondingly; And a second data polarity inversion driver for checking the data transition of even-numbered data and inverting the polarity of the data corresponding thereto. The method of claim 1, The first data polarity inversion driving unit includes a first data transition checking unit for checking data transitions of the odd-numbered data; A first data polarity inversion signal summing unit for determining an output level by identifying the number of signals whose polarities of data change due to the data transition; And a first data polarity inversion signal output unit configured to receive a signal from the first data transition checker and the first data polarity inversion signal adder and output a signal for inverting output data. It has a liquid crystal display device. The method of claim 1, The second data polarity inversion driving unit includes a second data transition checking unit which checks data transitions of the even-numbered data; A second data polarity inversion signal summing unit for determining an output level by grasping the number of signals whose polarity of data changes according to the data transition; And a second data polarity inversion signal output unit configured to receive a signal from the second data transition check unit and the second data polarity inversion signal adder and output a signal for inverting output data. It has a liquid crystal display device. The method of claim 1, The timing control signal generator generates control signals such as a source sampling clock, a source output enable, a source start pulse, and a dot clock for the data driver. A liquid crystal display device having a two-port data polarity inverter characterized by being supplied. The method of claim 1, The timing control signal generator 2 supplies control signals such as a gate shift clock, a gate output enable, a gate start pulse, and the like for the gate driver. A liquid crystal display device having a port data polarity reverser. The method of claim 2 or 3, And the data transition checking unit includes two flip-flops and an exclusive logical sum gate for comparing current data with previous data and checking data transitions corresponding thereto. The method of claim 2 or 3, The data polarity inversion signal summing unit and a summer for summing the number of data having the data transition from the data transition unit; And a majority detector for checking whether the sum of the data numbers exceeds a reference value. The method of claim 2 or 3, And the data polarity inversion signal output section comprises a multiplexer for receiving the polarity inversion signal from the data polarity inversion signal summing section and inverting the output data. The method of claim 1, The polarity control signal generation unit checks the polarity of the polarity of the liquid crystal and the liquid crystal polarity inversion driving unit for inverting the polarity corresponding thereto; A first data polarity inversion driver for dividing the data bits into two to check the data transition of the first output data bit and inverting the polarity of the data corresponding thereto; And a second data polarity inversion driver for checking the data transition of the second output data bit and inverting the polarity of the data corresponding thereto. In a liquid crystal display device having a first and second data polarity inversion driving unit, Inputting odd-numbered data to the first data polarity inversion driving unit and comparing the data transitions thereof to invert the polarity of the odd-numbered data; And inputting even-numbered data to the second data polarity inversion driving unit and comparing the data transitions thereof so that the polarity of the even-numbered data is inverted. Way. The method of claim 10, Inverting the polarity of the odd-numbered data is Checking whether there is a data transition by comparing current odd data with previous odd data; Summing the number of data having the data transition; And inverting the data when the sum of the number of data exceeds a reference value. The method of claim 10, Inverting the polarity of the even-numbered data is Checking whether there is a data transition by comparing current even data with previous even data; Summing the number of data having the data transition; And inverting the data when the sum of the number of data exceeds a reference value. The method according to claim 11 or 12, And said reference value is nine. In the liquid crystal display device having the first and second data polarity inversion driving unit, Dividing data input to the polarity inversion driving unit into half and dividing the data into first and second data bits; Inputting first data to the first data polarity inversion driving unit and comparing the data transitions thereof to invert the polarity of the first data; And inputting second data to the second data polarity inversion driving unit and comparing the data transitions thereof to invert the polarity of the second data. Way. The method of claim 14, Inverting the polarity of the first data is Checking whether there is a data transition by comparing a current data bit and a previous data bit among the first data; Summing the number of data having the data transition; And inverting the data when the sum of the number of data exceeds a reference value. The method of claim 14, Inverting the polarity of the second data is Checking whether there is a data transition by comparing a current data bit and a previous data bit of the second data; Summing the number of data having the data transition; And inverting the data when the sum of the number of data exceeds a reference value. The method according to claim 15 or 16, And said reference value is nine.