JP2007227419A - Test system and manufacturing process of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance reliability of a semiconductor device by detecting a failure hard to detect through inspection of the electric characteristics, in a short time with high precision. <P>SOLUTION: A visual inspection system 3 performs visual inspection of individual semiconductor chips after a semiconductor device is formed. Subsequently in the wiring process, the visual inspection system 3 performs visual inspection every time when a wiring layer is formed by a wiring pattern. Thereafter, an insulation film is formed above an uppermost wiring layer, and the electric characteristics are inspected by means of a prober 2. A semiconductor chip judged rejectable through these visual inspection and electric characteristics inspection undergoes overlay processing at a test control unit 5, and a marker indicative of a rejectable product is put on the semiconductor chip by means of a concentration marker 6. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an inspection technique for a semiconductor integrated circuit device, and more particularly to a technique effective for preventing failure outflow in an electrical characteristic inspection of a semiconductor device.

  A probe test is widely known as a test for inspecting electrical characteristics of a semiconductor device. In this probe test, the electrical characteristics of the electronic device in each semiconductor chip formed on the semiconductor wafer are inspected to determine whether the semiconductor device is good or defective.

  However, the present inventors have found that the test technique based on the electrical characteristics of the semiconductor device as described above has the following problems.

  In other words, the probe test is intended for inspection of electrical characteristics in circuit blocks (circuit modules) formed on a semiconductor chip. Wire breakage caused by foreign matter, contact failure, etc. generated in wiring connecting circuit blocks. There is a problem that defects such as short circuit cannot be found.

  For this reason, there is a risk of causing a defect after shipment of the manufactured semiconductor device, and the reliability of the semiconductor device is lowered.

  In addition, in the probe test, it is possible to inspect the wiring that connects the circuit blocks, but in that case, the number of items associated with the inspection becomes enormous, which greatly increases the inspection time and cost. Will be unrealistic.

  An object of the present invention is to provide a technique capable of detecting a defect that is difficult to detect in an inspection of electrical characteristics in a short time and with high accuracy and improving the reliability of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The test system according to the present invention performs an appearance inspection of a semiconductor chip formed on a semiconductor wafer, determines whether the semiconductor chip is good or defective, and outputs the determination result, and an electrical characteristic of the semiconductor chip. In the appearance inspection, the electrical characteristics inspection device that performs the inspection, determines whether the semiconductor chip is good or bad, and outputs the determination result, the visual inspection device, and the determination result output from the electrical characteristic inspection device. An inspection control unit for determining a defective product by combining the defective semiconductor chip and the defective semiconductor chip in the electrical property inspection and outputting the determination result.

  In the test system of the present invention, the visual inspection device performs visual inspection every time a semiconductor wafer having at least an electronic device and a wiring layer with a wiring pattern are formed, and each semiconductor chip is checked for good / bad. The electrical characteristic inspection apparatus does not inspect the electrical characteristics of the semiconductor chip determined to be defective by the appearance inspection.

  Furthermore, the test system according to the present invention is connected to the inspection control unit, and puts a mark for distinguishing a defective semiconductor chip from a non-defective semiconductor chip based on a determination result output from the inspection control unit. It is equipped with a marker.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  The method of manufacturing a semiconductor device according to the present invention includes a step of performing an appearance inspection of a semiconductor wafer on which an electronic device is formed to determine whether each semiconductor chip is good or defective, and a wiring pattern on the semiconductor wafer on which the electronic device is formed. Each time a wiring layer is formed, a visual inspection is performed to determine whether each semiconductor chip is good or defective, and all the wiring layers are formed, and an electronic device on a semiconductor wafer in which a protective film is applied to the uppermost wiring layer. The method includes a step of inspecting electrical characteristics, and a step of processing a defective semiconductor chip as a defective product in an appearance inspection and an inspection of electrical characteristics.

  In the method of manufacturing a semiconductor device according to the present invention, in the step of inspecting the electrical characteristics, the electrical characteristics of the semiconductor chip determined to be defective by the appearance inspection are not inspected.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) It is possible to detect defects and defects of a semiconductor device efficiently and at low cost.

  (2) Moreover, the yield in semiconductor device manufacture can be improved.

  (3) Further, the reliability of the semiconductor device can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a block diagram showing a configuration of a test system according to an embodiment of the present invention, FIG. 2 is a flowchart of an inspection process by the test system of FIG. 1, and FIG. 3 is an external view provided in the test system of FIG. FIG. 4 is an explanatory view showing an example of appearance inspection by a visual inspection apparatus provided in the test system of FIG. 1, and FIG. FIG. 6 is an explanatory diagram showing an example of the processing result of the probe test by the prober provided in the test system, and FIG. 6 shows an example of the processing result by the overlay processing by the test control unit provided in the test system of FIG. FIG.

  In the present embodiment, the test system 1 inspects the electrical characteristics of each semiconductor chip CH (FIG. 4) formed on the semiconductor wafer. As shown in FIG. 1, the test system 1 includes a prober (electrical characteristic inspection device) 2, an appearance inspection device 3, a data server (inspection control unit) 4, a test control unit (inspection control unit) 5, and a concentration marker ( Marker) 6.

  The prober 2, the appearance inspection apparatus 3, the data server 4, and the test control unit 5 are connected to each other by a communication line 7 such as a LAN (Local Area Network).

  The prober 2 applies an electrical test to a circuit block (functional block) B (FIG. 3) formed on each semiconductor chip by applying a probe needle to a bonding pad formed on each semiconductor chip CH of the semiconductor wafer. Whether the chip CH is good or bad is determined, and the result is transmitted to the data server 4.

  The appearance inspection apparatus 3 optically reads the shape of the wiring pattern that connects the circuit blocks, whether there are any defects, scratches, or foreign matters, and performs pass / fail judgment by image processing. Send to.

  The data server 4 receives and stores the inspection results transmitted from the prober 2 and the appearance inspection apparatus 3. The test control unit 5 is, for example, a personal computer, and controls all of the test system 1 and superimposes defective semiconductor chips CH on the basis of inspection results stored in the data server 4. Do.

  The concentration marker 6 is connected to the test control unit 5, and based on the result of the overlay process by the test control unit 5, all of the defects in the probe test by the prober 2 and the appearance inspection by the appearance inspection apparatus 3 are detected. The semiconductor chip CH is detected, and the defective semiconductor chip CH is marked with ink or engraving to distinguish it from the non-defective semiconductor chip CH.

  Next, the inspection process by the test system 1 in the present embodiment will be described using the flowchart of FIG.

  First, each semiconductor chip CH on which a semiconductor device is formed is subjected to appearance inspection by the appearance inspection apparatus 3 (step S101). At this time, the inspection result by the appearance inspection apparatus 3 is transmitted to the data server 4 via the communication line 7.

  Subsequently, in the wiring process, a wiring pattern is formed in each semiconductor chip region of the semiconductor wafer (step S102). Thereafter, the appearance inspection by the appearance inspection apparatus 3 is performed again (step S103). The appearance inspection device 3 transmits the inspection result to the data server 4 via the communication line 7.

  Since the wiring process for forming the wiring pattern is usually formed of multiple wiring layers by repeated manufacturing processes, an appearance inspection by the appearance inspection apparatus 3 is performed each time each wiring layer is formed. For example, when the wiring layer is formed of three layers, three appearance inspections are performed.

  In addition, the appearance inspection by the appearance inspection apparatus 3 mainly inspects the inter-block wiring BH connecting each circuit block B formed in the semiconductor chip CH, for example, as shown in FIG.

  Thereafter, in the protective film application step, an insulating film for protecting the wiring layer is formed on the uppermost wiring layer (step S104), and an electrical property inspection (probe test) is performed by the prober 2 (step S105).

  In the process of step S105, only the semiconductor chips that are non-defective in the process of step S101 and the process of step S103 are inspected. The prober 2 transmits the inspection result to the data server 4 via the communication line 7 after the probe test is completed.

  Subsequently, the test control unit 5 superimposes the result of the appearance inspection and the result of the probe test stored in the data server 4 (step S106), and the semiconductor determined to be defective in the appearance inspection and the probe test. Chip CH is detected.

  Here, the superimposition processing based on the appearance inspection and the inspection result of the probe test will be described with reference to FIGS.

  FIG. 4 is an explanatory view showing a processing example of the inspection result of the appearance inspection (step S103) by the appearance inspection apparatus 3.

  As shown in the upper part of FIG. 4, the position of each semiconductor chip CH is assigned by the X coordinate and the Y coordinate. In FIG. 4, the semiconductor chip CH indicated by “/” indicates that the appearance inspection is a non-defective product, and the semiconductor chip CH indicated by “A” indicates that the appearance inspection is a defective product. .

  Further, the semiconductor chip CH shown in black indicates a semiconductor chip serving as a reference, and the semiconductor wafers are superimposed on the basis of the position of the semiconductor chip in the overlay process. Further, an unmarked semiconductor chip CH indicates that it is not subject to inspection.

  The inspection results shown in the upper part of FIG. 4 (the X-coordinate and Y-coordinate of each semiconductor chip, the determination result of good (/) defective (A)) are converted into, for example, text data as shown in the lower part of FIG. And transmitted to the data server 4.

  Next, FIG. 5 is an explanatory view showing a processing example of the inspection result of the probe test (step S105) by the prober 2.

  In the upper part of FIG. 5, the semiconductor chip CH indicated by “/” indicates that the probe test was a non-defective product, and the semiconductor chip CH indicated by “B” indicates that the probe test was a defective product. ing.

  Similarly to FIG. 4, the semiconductor chip CH shown in black indicates a reference semiconductor chip, and an unmarked semiconductor chip is not subject to inspection.

  The inspection results shown in the upper part of FIG. 5 (the X-coordinate and Y-coordinate of each semiconductor chip, the determination result of good (/) defective (B)) are converted into, for example, text data as shown in the lower part of FIG. And transmitted to the data server 4.

  In this case, as described above, since the probe test is not performed on the semiconductor chip CH ('B') that is defective in the appearance inspection, the test time of the probe test can be shortened.

  FIG. 6 is an explanatory diagram of a processing example showing a processing result by the overlay processing (step S106) by the test control unit 5.

  In the superimposing process of the test control unit 5, all the semiconductor chips CH that are defective in the appearance inspection and the probe test are determined based on the text data in FIG. 4 and the text data in FIG. It is detected as a defective semiconductor chip, and the other semiconductor chips CH are processed as non-defective products.

  For example, in the upper part of FIG. 6, the semiconductor chip CH indicated by “/” indicates that the appearance inspection and the probe test were non-defective products, and the semiconductor chip CH indicated by “C” is not acceptable in the appearance inspection. The non-defective product (A) and the defective product (B) in the probe test are superimposed.

  Similarly to FIGS. 4 and 5, the semiconductor chip CH shown in black indicates a reference semiconductor chip, and the unmarked semiconductor chip CH indicates that it is not subject to inspection.

  Then, as shown in the lower part of FIG. 6, the test control unit 5 uses the result of overlay processing (the X coordinate, Y coordinate, determination result of good (/) defect (C) of each semiconductor chip) as text data. Output to the concentration marker 6.

  The concentration marker 6 receives the text data output from the test control unit 5 and is a marking that identifies the defective semiconductor chip CH (the semiconductor chip indicated by “C” in FIG. 6) as defective. I do.

  Thereby, according to the present embodiment, by performing the probe test and the appearance inspection together, it is possible to efficiently eliminate defects and defects in the inter-block wiring BH that are difficult to inspect by the probe test, and to reduce the cost. Therefore, the yield in semiconductor device manufacturing can be improved.

  In addition, since the shipment of defective semiconductor devices can be prevented with high accuracy, the defect rate of the semiconductor devices can be reduced and the reliability can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above-described embodiment, an example in which an appearance inspection is performed after a probe test has been described. For example, a non-defective product can be obtained by performing an appearance inspection of a semiconductor wafer that has become a lot defect due to poor adjustment of a semiconductor manufacturing apparatus and performing overlay processing. The semiconductor chips may be selected.

  The present invention is suitable for a technique for improving the efficiency of electrical characteristic inspection in a semiconductor device.

It is a block diagram which shows the structure of the test system by one embodiment of this invention. It is a flowchart of the inspection process by the test system of FIG. It is explanatory drawing which shows the example of an external appearance test | inspection of the semiconductor chip by the external appearance inspection apparatus provided in the test system of FIG. It is explanatory drawing which showed the example of a process of the external appearance inspection result by the external appearance inspection apparatus provided in the test system of FIG. It is explanatory drawing which showed the example of a process of the test result of the probe test by the prober provided in the test system of FIG. It is explanatory drawing which showed the process example of the process result by the superimposition process by the test control part provided in the test system of FIG.

Explanation of symbols

1 Test system 2 Prober (Electrical characteristic inspection device)
3 Visual inspection device 4 Data server (inspection control unit)
5 Test controller (inspection controller)
6 Concentration marker (marker)
7 Communication line CH Semiconductor chip B Circuit block BH Inter-block wiring

Claims (5)

An appearance inspection device that performs an appearance inspection of the semiconductor chip formed on the semiconductor wafer, determines whether the semiconductor chip is good or defective, and outputs the determination result;
An electrical characteristic inspection device for inspecting electrical characteristics of the semiconductor chip, determining whether the semiconductor chip is good or defective, and outputting the determination result;
In response to the determination result output from the visual inspection apparatus and the electrical characteristic inspection apparatus, a defective product is formed by combining a semiconductor chip that has failed in the visual inspection with a semiconductor chip that has failed in the electrical characteristic inspection. And a test control unit that outputs a result of the determination. The test system according to claim 1,
The appearance inspection apparatus is
At least a semiconductor wafer on which an electronic device is formed and a wiring layer by a wiring pattern are inspected to determine whether each semiconductor chip is good or bad,
The electrical property inspection apparatus is:
A test system characterized by not inspecting electrical characteristics of a semiconductor chip determined to be defective by the appearance inspection. The test system according to claim 1 or 2,
A marker that is connected to the inspection control unit and attaches a mark for distinguishing a defective semiconductor chip from a non-defective semiconductor chip based on a determination result output from the inspection control unit is provided. Test system. A step of performing an appearance inspection of the semiconductor wafer on which the electronic device is formed, and determining whether each semiconductor chip is good or bad;
A step of performing an appearance inspection each time a wiring layer is formed by a wiring pattern on a semiconductor wafer on which the electronic device is formed, and determining whether each semiconductor chip is good or bad;
A step of inspecting electrical characteristics of an electronic device in the semiconductor wafer in which all wiring layers are formed and a protective film is applied to the uppermost wiring layer;
A method of manufacturing a semiconductor device, comprising: a step of processing a defective semiconductor chip as a defective product in the appearance inspection and the electrical characteristic inspection. In the manufacturing method of the semiconductor device according to claim 4,
In the step of inspecting the electrical characteristics,
A method of manufacturing a semiconductor device, comprising: not inspecting electrical characteristics of a semiconductor chip determined to be defective by the appearance inspection.

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