KR20080063609A - Monitoring method of semiconductor device - Google Patents

Abstract

A method for monitoring semiconductor devices is provided to enhance yields by performing improvement on a corresponding process when defects are detected. A component structure is formed on a semiconductor substrate. By inspecting the semiconductor substrate having components, wafer pattern maps(BL,M1,M2,M3) are formed. By applying current to the semiconductor substrate having the components, a current map is formed. Coordinates of defect die are detected from the wafer pattern maps and the current map. The component structure includes structures of gate lines, bit lines, metal lines formed on the semiconductor substrate.

Description

Monitoring method of semiconductor device

1 is a flowchart schematically illustrating a method for monitoring a semiconductor device of the present invention.

2 is a diagram illustrating a PWI wafer map according to an embodiment of the present invention.

3A and 3B are diagrams illustrating a method of analyzing the wafer map of FIG. 2.

4A to 4C are diagrams showing analysis results according to embodiments of the present invention.

 The present invention relates to a method for monitoring a semiconductor device, and more particularly, to a monitoring method capable of reducing defect analysis time by performing monitoring at each step of forming a thin film or wiring before completing a process of manufacturing a semiconductor device.

In manufacturing a semiconductor device, the process of finding a defect in the device is one of the very important factors. The monitoring of the device is usually carried out after the process of forming the device on the wafer and forming a plurality of metal wires is completed.

In addition, after forming a plurality of elements and wirings per die on the wafer, the die in which the defect occurs is monitored.

In order to monitor the occurrence of such defects, after completing the process of forming a semiconductor device, a surface analysis (FA) is performed. The cross-sectional analysis method takes a very long time since all processes for forming a semiconductor device are performed by removing one layer from the uppermost layer after completion of all processes.

The present invention generates a wafer map by monitoring the device at each process step without cross-sectional analysis, and compares or analyzes it with a reference wafer map to feed back to the process line where a defect occurs, thereby increasing process yield and reducing monitoring time. have.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for monitoring a semiconductor device, and forms a device structure on a semiconductor substrate. The semiconductor substrate on which the device is formed is inspected to form a wafer pattern map. The current map is applied to the semiconductor substrate on which the device is formed to form a current map. And a monitoring step of detecting coordinates of the defective die from the wafer pattern map and the current map.

The device structure includes structures of respective gates, bit lines, and metallizations formed on a semiconductor substrate.

The wafer pattern map is formed by performing a pattern wafer inspection (PWI) analysis, and the PWI analysis is a method of finding surface defects of a device. In addition, a current map is formed by performing DC fail analysis. In a DC fail analysis, a die whose current is measured from 0 to 4 mA is classified as a normal die, and a die whose current is measured as 5 to 20 mA is classified as a bad die.

Coordinates of the detected bad die are fed back to a previous process step to prevent reoccurrence of the bad die.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1 is a flowchart schematically illustrating a method for monitoring a semiconductor device of the present invention. The method of manufacturing a semiconductor device may be implemented in a wide variety of ways depending on the structure of the device, the materials used and the application. The method of manufacturing a semiconductor device shown in FIG. 1 is a very simplified flowchart and uses a flash memory device as an embodiment. What is important in the present invention is a monitoring step performed at each process step. That is, it should be noted that the semiconductor process order may vary depending on the device to be formed.

Specifically, the semiconductor substrate on which the device is to be formed is loaded into the semiconductor manufacturing apparatus (S1). A plurality of gates are formed on the semiconductor substrate (S2), and bit lines are formed (S3). The first analysis S4 is performed. The first analysis S4 is performed using DC fail analysis and pattern wafer inspection (PWI). First, DC fail analysis is performed for each die, and a map of wafers for bridge generation is obtained.

DC fail analysis is an analysis method for finding defects caused by bridges of wafers that have been processed. For example, each die may be determined to be a normal die if a die flows with a current of 4 to 4 mA, and a die die if a die having a high current of 5 to 20 mA flows. It should be noted that this is only an example, and may vary by manufacturing method, materials used, and manufacturing company. DC fail is mainly caused by the bridge between metal films, and this defect is a very large factor in lowering the yield of the device.

The PWI is an enlarged part of the wafer surface to identify dies with wiring defects or surface defects. A partial wafer map is derived from the PWI, and defect photos and locations are entered into each wafer map. The map obtained by DC fail analysis is matched with a map in which a current map is displayed and a defect map by PWI are matched with each other to find a portion where a defect has occurred, and perform analysis on it.

When matching and analyzing a map, comparing and contrasting with a reference map without defects can perform the analysis efficiently. After the analysis of the bit line, the first metal wire is formed (S5) by the following process. A second analysis (S6) of the first metal wiring is performed. The second analysis is also performed in the same manner as the first analysis S4. The second analysis S6 obtains information on the DC fail map and the PWI map and identifies the cause of the failure. A second metal wiring is formed (S7) and a third analysis (S8) is also performed to identify the cause of the failure of the second metal wiring. The nth metal wiring is formed (Sk) and the n + 1 analysis is performed (Sk + 1) to find the cause of the defect in all the process steps in order to identify the cause of the defect, and to find a solution for this. Although monitoring is preferably performed at each manufacturing step, monitoring may only be performed at desired stages.

As a method of monitoring a semiconductor memory device, mainly a surface analysis method has been used. However, since this method is performed after the semiconductor manufacturing process is completed on the wafer, defects must be monitored by removing each layer one by one. This leads to very poor time and monetary efficiency.

In the present invention, the occurrence of a defect can be found immediately by monitoring the layer immediately after the formation of each layer, and the recurrence of the defect is prevented by feeding back a solution to the process according to the cause of the defect. can do.

2 is a diagram illustrating a PWI wafer map according to an embodiment of the present invention. As a PWI map for each step of manufacturing a semiconductor memory device, a PWI map BL after forming a bit line, a PWI map M1 after forming a first metal wiring, and a second metal wiring after forming a second metal wiring An example of the PWI map M3 after the PWI map M2 and the third metal wiring is formed. Other defects occur depending on the manufacturing method, manufacturing equipment and the materials used.

As shown in the figure, after manufacturing the bit line, the PWI photograph BL shows that many defects have occurred in the entire wafer. The photo shows a wafer, which is composed of multiple dies. The points on each of the dies are process defects. In other words, the less wafers appearing in the PWI picture, the better the quality of the wafer. The wafer at this time refers to a wafer which has been subjected to each manufacturing process, that is, a gate forming process and a metal wiring forming process. Accordingly, as shown in the PWI measurement picture, the bit line manufacturing process needs to be improved in all processes. Therefore, on the example PWI photograph, the bit line manufacturing process and the second metal wiring manufacturing process are urgently improved, and the first metal wiring and the third metal wiring manufacturing process are in good condition. Therefore, it is possible to analyze the cause of the defect according to the PWI result and feed back a solution to the corresponding process to find an improvement in the region where the defect occurs frequently.

3A and 3B are diagrams illustrating a method of analyzing the wafer map of FIG. 2. In one embodiment, an analysis drawing after forming the first metal wiring is shown. Figure 3a is an analysis of the DC fail (fail), Figure 3b is an analysis of the PWI. DC fail analysis (Fig. 3a) is to find the defect between gate or metal wiring by measuring the current flowing through each die without applying external voltage to the wafer. do. For example, if the current value is measured from 0 to 4mA, the die is a good die, and if the current of 5 to 20mA is measured, the die is classified as a fail die. The amount of current is displayed for each die, and color of the bad die is distinguished from the normal die. PWI analysis of these wafers (FIG. 3B) shows the resulting die with defects.

Matching DC fail measurements (Fig. 3a) and PWI measurements (Fig. 3b) to the same size allows the location of bridges and faulty devices (or metallizations) to be located so that faulty process steps can be identified immediately. In other device fabrication, it is possible to prevent the occurrence of similar defects.

4A to 4C are diagrams showing analysis results according to embodiments of the present invention. 4A is an analysis photograph of FIG. 4B and FIG. 4C. That is, Figure 4a is a picture of matching the DC fail analysis picture and PWI measurement picture with each other to enlarge the defect generation area using a device such as SEM for the PWI picture (Fig. 4b, 4c) analyzed in each process step ( A) and analyze the cause of the defect therefrom. Matching these PWI pictures (FIGS. 4B, 4C) and DC fail pictures creates an analysis picture as shown in FIG. 4A. In response, the coordinates of the individual dies are fed back to the process step for improvement of each part. You will find.

Line-type defects in the PWI image are easy to detect because the defects of the metal lines occur differently from the defects of materials such as spot-type general devices and insulating films. In the detailed description of the present invention, the defect analysis is performed on the bit line and the metal wiring, but the defect analysis may be performed and feedback after the gate is formed.

As a result, monitoring after each process step is performed to find faults between bridges and wires, which makes it easy to find the defect area for the previous process step and prevent duplicate defects. have.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

According to an embodiment of the present invention, by monitoring the semiconductor device step by step, it is possible to reduce the time by not removing the layer of the completed device, and to improve the process as soon as a defect is found. The yield can be improved by preventing the regeneration of bad dies.

Claims (8)

Forming a device structure on the semiconductor substrate; Inspecting the semiconductor substrate on which the device is formed to form a wafer pattern map; Forming a current map by applying current to the semiconductor substrate on which the device is formed; And And a monitoring step of detecting coordinates of a defective die from the wafer pattern map and the current map. The method of claim 1, And the device structure comprises a structure of each of a gate, a bit line, and a metal wiring formed on the semiconductor substrate. The method of claim 1, The wafer pattern map is formed by performing a pattern wafer inspection (PWI) analysis. The method of claim 3, wherein The PWI analysis is a method for monitoring a semiconductor device to find the surface defects of the device. The method of claim 1, And the current map is formed by performing a DC fail analysis. The method of claim 5, wherein And a die whose current is measured as 0 to 4 mA in the DC fail analysis is classified as a normal die. The method of claim 5, wherein In the DC fail analysis, a die whose current is measured at 5 to 20 mA is classified as a bad die. The method of claim 1, And monitoring the coordinates of the detected defective die to a previous process step.

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