TW201535553A - Method of bitmap failure associated with physical coordinate - Google Patents

Abstract

A method of Bitmap failure associated with physical coordinate is provided. In the method, data of wafer mapping inspection are obtained first, wherein the data contains images of defects in a plurality of layers within a wafer and a plurality of physical coordinates of the defects. Thereafter, a detection of Bitmap failure is performed to obtain digital coordinates of failure bits within the wafer. The digital coordinates are converted to a plurality of physical locations, and then the physical locations are overlapped over the physical coordinates so as to obtain the correlation of the failure bits and the defects rapidly.

Description

Bit failure detection method combining physical coordinates

The present invention relates to a Failure Analysis Methodology, and in particular to a method for detecting a bit failure in combination with a physical coordinate.

As the line width of the IC process continues to shrink, precise control and monitoring of components is also more important. In view of nanometer generation semiconductor technology, it is necessary to accurately detect and analyze the component yield.

Current methods for wafer failure analysis (FA) include a technique called Bitmap failure, which yields failure bits and finds their physical location, and can be invalidated. The failure item is used to predict which layer of structure inside the wafer has failed.

However, because the cause of the bit failure is unknown, if you want to accurately obtain the cause of the bit failure, you must grind the entire wafer under test from the surface until the layer structure that may cause the bit failure, and then It was subjected to scanning electron microscopy (SEM) surface analysis. Therefore, the current bit failure analysis is time consuming.

The invention provides a bit failure detection method combining physical coordinates, which can greatly shorten the analysis time of bit failure.

The invention further provides a bit failure detection method combining physical coordinates, which can quickly obtain the physical position of the failure bit and the cause of failure.

The bit failure detection method of the present invention combined with the physical coordinates includes first obtaining a wafer alignment detection data. The wafer alignment detection data includes an image of a plurality of defects of each layer in a wafer and a plurality of physical coordinates of the defects in the wafer. In this method, a one-bit failure detection step is performed to obtain a digital coordinate of a plurality of failed bits in the wafer, and convert the digital coordinates to a plurality of physical positions of a line or a polygon. The physical location is then overlaid on the physical coordinates within the wafer to obtain the correlation between the failed bit and the defect.

In an embodiment of the invention, the method further includes obtaining a scanning electron microscope (SEM) of the defect according to the physical position of each of the failing bits corresponding to the physical coordinates in the wafer. The image is then determined based on the SEM image to cause the failure bit.

In an embodiment of the invention, the step of overlapping the physical location with the physical coordinates in the wafer includes classifying the failed bits according to different defects in the wafer alignment detection data.

Another bit failure detection method combining physical coordinates of the present invention includes performing a one-bit failure detection step to obtain a digital coordinate of all the failed bits in a wafer, and then converting the digital coordinates into a graphic GDS file coordinate or inspection result file coordinate. Then, the data of the graphic data system coordinate or the detection result coordinate is compared with the database file of the wafer to output a plurality of physical locations of the invalidation bit. By comparing the physical location with the detection result of the wafer, a defect corresponding to the failed bit can be obtained.

In another embodiment of the invention, the method further includes classifying the failed bits based on the obtained defects.

In another embodiment of the present invention, if the digital coordinate is converted into a detection result coordinate, the detection result coordinate is directly related to the defect Klarf map in the step of comparing the data and the database file. Compare.

In another embodiment of the present invention, if the digital coordinate is converted into a coordinate data system coordinate, the coordinates of the detected defective wafer map are converted into coordinates of the graphic data system file before comparing the data and the database file. .

In various embodiments of the present invention, the digit coordinates obtained by the bit failure detection step include failure of a plurality of bit lines and failure of a plurality of word lines.

In various embodiments of the invention, the failure of the bit line or the failure of the word line may include an open, a short, or a close.

In various embodiments of the invention, the locations of the defects include word lines, bit lines, polysilicon layers, or contact windows.

In various embodiments of the present invention, the method further includes comparing the number of failed bits and the total number of defects to obtain a probability of defect caused by the bit failure (also referred to as "the defect generated by the source layer affects the yield. proportion").

In various embodiments of the present invention, the method further includes obtaining repeated systematic defects by detecting the different crystal grains in the wafer.

Based on the above, the present invention can obtain analysis results of hundreds or even thousands of bit failures in a short time, and can obtain the source (layer) of word line failure by the ratio between the number of defects and the failure bit or The fatality rate of the defect type. Moreover, the present invention can directly obtain an image of a defect portion that causes a bit failure and determine the defect type by using the wafer image stored in the wafer inspection system.

The above described features and advantages of the invention will be apparent from the following description.

1 is a diagram showing a step of detecting a bit failure in combination with a physical coordinate in accordance with a first embodiment of the present invention.

Referring to FIG. 1, the method in this embodiment first performs step 100 to obtain a wafer mapping data. The so-called wafer alignment detection is performed by the inspection machine according to the wafer map and the actual wafer alignment, so that each die in the wafer can be detected immediately, and the die is The various defects in the wafer are marked with different color codes on the wafer map, as shown in Figure 2 (Figure 2 is shown in black and white but is actually color). The above images are generally obtained by scanning electron microscopy (SEM), so they can be archived and named after the grain position or defect type. In this embodiment, the wafer alignment detection material includes a defect image in each layer structure in a single wafer, and physical coordinates of each defect in the wafer. The portion of the defect described above is, for example, a structure in a wafer such as a word line, a bit line, a polysilicon layer, or a contact window.

Then, in step 110, a bitmap failure step is performed to obtain the digit coordinates of the above-mentioned in-wafer failure bits. The so-called bit failure detection technology is to use the detection instrument to measure the failed bits and output the result in digital coordinates. The digit coordinates resulting from the bit failure detection step described above may include different types of bit failures, such as failure of a bit line, failure of a word line, or failure caused by other lines. Moreover, the failure of a bit line or the failure of a word line can also be classified into failures caused by different causes, such as open, short or close.

Next, in step 120, the above-described digit coordinates are converted into physical positions of lines or polygons. Since the data obtained by the current bit failure detection step is a physical layout in which the failure bit is displayed in the form of a GDSII coordinate, the digital coordinate can be converted into a corresponding one by using a specific software or other suitable device in the detection instrument. The file of the physical coordinates of the wafer alignment detection to step 100.

Then, in step 130, the physical location is superimposed on the physical coordinates within the wafer to obtain an association between the failed bit and the defect. For example, after performing step 130, information including a defect ID, a coordinate value of x and y, a defect classification, a source layer, a corresponding SEM image (if any), and the like can be obtained. As described above, step 130 of the embodiment can further classify the invalid bits according to different defects in the wafer alignment detection data, and refer to the strip chart 3A obtained after classification, which shows 9 different defects. Types 301~309 and their corresponding numbers, and the number of all defects is 1647. If the distribution of different defects on the wafer is to be analyzed, the wafer map of FIG. 3B can be obtained by software inversion (FIG. 3B is shown in black and white but is actually colored).

In addition, since the physical position of each failure bit corresponds to the physical coordinates in the wafer, the SEM image of each defect can be obtained, and the cause of the failure bit can be determined according to the SEM image. The SEM image here is the image obtained when the wafer is aligned, so no extra time is required to obtain the image of these defects. Of course, the present invention is not limited thereto, as long as the physical position of the failure bit corresponds to the physical coordinates in the wafer, the position of the defect can be obtained, and then the signature and the failure bit are compared.

In addition, the method according to the first embodiment can also obtain the probability of defect caused by the bit failure by comparing the number of failed bits and the total number of defects (also referred to as "the defect caused by the source layer affects the yield ratio". (source killing ratio)"). In other words, when the wafer alignment detection data obtained in step 100 shows that there are a total of m defects, and the number of defects corresponding to the failure bit is n from step 130, it can be (n/m×100%). ) The probability of a defect due to a bit failure is obtained.

Moreover, since the first embodiment detects the entire wafer, repeated systematic defects can be obtained by the detection results of different dies in the wafer. For example, if the allowable error is set to 1 μm, a defect of ±1 μm at the same position of different crystal grains can be regarded as a repeating defect.

4 is a diagram showing a step of detecting a bit failure in combination with a physical coordinate in accordance with a second embodiment of the present invention.

Referring to FIG. 4, the method of this embodiment first performs a one-bit failure detection step in step 400 to obtain the digital coordinates of all the failed bits in a wafer. The digit coordinates obtained by the above-described bit failure detection step may include different types of bit failures, such as failure of a bit line, failure of a word line, or failure caused by other lines. Moreover, the failure of a bit line or the failure of a word line can also be classified into failures caused by different causes, such as open, short or close.

In step 410, the digit coordinates are converted into a GDS coordinate or an inspection result coordinate (such as a Klarf file coordinate). The GDS file is generally a circuit design file of the layout, so the physical coordinates of the wafer are attached. In addition, the results of current wafer inspection systems can also be converted to GDS coordinates via specific software. As for the detection result coordinates, for example, the result file (also referred to as Klarf) obtained by the KLA company's testing equipment. In detail, digital coordinates (such as the coordinates of a bitmap file) can be converted into physical GDS coordinates or Klarf coordinates.

Next, in step 420, the data of the graphic data system coordinate or the detection result coordinate is compared with the database file of the wafer to output the physical location of the invalid bit. Specifically, if it is converted to a Klarf coordinate in the previous step 410, it is directly compared with the defect Klarf map. In addition, if the previous step 410 is to convert to a GDS coordinate, the coordinates of the detected defective wafer map (Klarf coordinates) are first converted to GDS coordinates, and then the two are compared.

Then, in step 430, the defect corresponding to each failure bit is obtained by comparing the physical position and the inspection result file of the wafer. As shown in FIG. 5, the coordinates of the coordinates obtained after performing step 430 are shown. In FIG. 5, line 502 within coordinate 500 is the physical location of the failed bit converted to the GDS coordinate via step 410, and region 504 is the location of defect 506 corresponding to the failed bit obtained via step 403. Although FIG. 5 shows only one straight line 502 (ie, one failure bit), there are actually thousands or tens of thousands of failed bits in a single wafer, and the present invention is not limited thereto. Moreover, since the so-called "inspection result file" is a wafer inspection performed every step of the wafer process, such as wafer mapping, it is possible to obtain the actual The images of the layers of the wafer, so the corresponding scanning electron microscopy (SEM) image 6 can be found according to the coordinates of the region 504 of FIG. 5, and the cause of the failure bit (502) can be determined based on the SEM image. If no defects are found in the predicted SEM image of a certain layer, the defect can be found by examining the SEM image of the same position of the other layers.

Moreover, the failed bits can also be classified according to the obtained defects. For example, since the defect portion may be a word line, a bit line, a polysilicon layer, a contact window, or more, it is also possible to classify the measured failure bit into (1) because the word line The failure bit caused by its own defect, (2) the failure bit due to the defect of the bit line itself, (3) the failure bit due to the defect of the polysilicon layer (such as the gate structure), (4) because of the contact A failure bit caused by a defect in the window...etc.

In addition, in the second embodiment, the probability of defect caused by the bit failure can be obtained by comparing the number of failed bits and the total number of defects (also referred to as "the defect generated by the source layer affects the yield ratio ( Source killing ratio)"). In the second embodiment, repeated systematic defects can also be obtained by the detection results of different die IDs in the wafer.

In summary, the present invention can obtain analysis results of hundreds or even thousands of bit failures in a short time, and obtain the exact position of the defect relative to the failed bit, thereby facilitating detection of the failed bit and finding out The reason. The present invention can also derive the source (layer) lethality of word line failure by the ratio between the number of defects and the failure bit. Since the present invention uses the wafer image stored by the wafer inspection system, it is also possible to directly obtain an image of the defect portion that causes the bit to fail. Furthermore, repeated system defects can be achieved in accordance with the method of the present invention.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100~130, 400~430‧‧‧ steps
Type 301~309‧‧‧
500‧‧‧ coordinates
502‧‧‧ Straight line
504‧‧‧Area
506‧‧‧ Defects

1 is a diagram showing a step of detecting a bit failure in combination with a physical coordinate in accordance with a first embodiment of the present invention. Fig. 2 is a view showing the result of wafer alignment detection in the first embodiment. 3A is a bar graph of classifying failure bits according to wafer alignment detection data in the first embodiment. FIG. 3B is a wafer map obtained through FIG. 3A. 4 is a diagram showing a step of detecting a bit failure in combination with a physical coordinate in accordance with a second embodiment of the present invention. Figure 5 is a schematic view of the coordinates obtained in the second embodiment. Fig. 6 is an SEM image view of the defect position in Fig. 5.

100~130‧‧‧Steps

Claims (12)

A method for detecting a bit failure in combination with a physical coordinate, comprising: obtaining a wafer alignment detection material, wherein the wafer alignment detection material includes an image of a plurality of defects of each layer in a wafer and the defect a plurality of physical coordinates in the wafer; performing a one-bit failure detection step to obtain a digital coordinate of a plurality of failed bits in the wafer; converting the digital coordinates to a plurality of physical positions of a line or a polygon And overlaying the physical location with the physical coordinates within the wafer to obtain an association between the failed bit and the defect. The method for detecting a bit failure in combination with a physical coordinate according to claim 1, further comprising: obtaining, according to the physical position of each of the failed bits, the physical coordinates in the wafer a plurality of scanning electron microscopy (SEM) images of defects; and determining the cause of the failure bit based on the SEM image. The method for detecting a bit failure in combination with a physical coordinate according to claim 1, wherein the step of overlapping the physical location with the physical coordinates in the wafer comprises: detecting the wafer alignment according to the wafer The defective bits are classified by different defects in the data. A bit failure detection method combining physical coordinates includes: performing a one-bit failure detection step to obtain a digital coordinate of all failure bits in a wafer; converting the digital coordinates into a graphic data system a coordinate or a detection result coordinate; comparing a data of the graphic data system coordinate or the detection result coordinate with a database file of the wafer to output a plurality of physical locations of the invalid bit; A detection result file of the physical location and the wafer is obtained to obtain a plurality of defects corresponding to the invalidation bit. The method for detecting a bit failure in combination with a physical coordinate as described in claim 4, further comprising classifying the failed bit according to the defect. The method for detecting a bit failure in combination with a physical coordinate according to claim 4, wherein the digital coordinates are converted to the coordinates of the detection result, and the data and the database file are compared. In the step, the detection result coordinates are directly compared with the detection defect wafer map. The method for detecting a bit failure in combination with a physical coordinate according to claim 4, wherein the digital coordinates are converted to the coordinates of the graphic data system, and the data and the database file are compared. The step further includes: converting the coordinates of the detected defect wafer map into coordinates of a graphic data system file. The method for detecting a bit failure in combination with a physical coordinate according to claim 1 or 4, wherein the digit coordinates obtained by the bit failure detecting step include failure of a plurality of bit lines and a majority The invalidation of the word line. The method for detecting a bit failure in combination with a physical coordinate according to claim 8, wherein the failure of the bit line or the failure of the word line includes an open, a short or a path ( Close). The method for detecting a bit failure in combination with a physical coordinate according to claim 1 or 4, wherein the defect portion comprises a word line, a bit line, a polysilicon layer or a contact window. The method for detecting a bit failure in combination with a physical coordinate as described in claim 1 or 4 of the patent application further includes comparing the number of the failed bits and the total number of the defects to obtain a bit failure. The probability of a defect. The method for detecting a bit failure in combination with a physical coordinate as described in claim 1 or 4 of the patent application further includes repeating system defects by detecting the different crystal grains in the wafer.